WO2012001870A1 - Solid state imaging device - Google Patents

Solid state imaging device Download PDF

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Publication number
WO2012001870A1
WO2012001870A1 PCT/JP2011/002789 JP2011002789W WO2012001870A1 WO 2012001870 A1 WO2012001870 A1 WO 2012001870A1 JP 2011002789 W JP2011002789 W JP 2011002789W WO 2012001870 A1 WO2012001870 A1 WO 2012001870A1
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Prior art keywords
circuit
voltage
current
constant
band
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PCT/JP2011/002789
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French (fr)
Japanese (ja)
Inventor
洋 藤中
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パナソニック株式会社
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Publication of WO2012001870A1 publication Critical patent/WO2012001870A1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60Noise processing, e.g. detecting, correcting, reducing or removing noise
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/71Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75Circuitry for providing, modifying or processing image signals from the pixel array
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/76Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device having a function for achieving both high-speed startup, low noise, and high dynamic range.
  • Solid-state imaging devices that convert light into electrical signals are used in various devices such as digital video cameras, digital still cameras, and facsimiles.
  • a solid-state imaging device a CCD (Charge Coupled Device) image sensor and a CMOS (Complementary Metal-Oxide Semiconductor) image sensor are known.
  • CMOS image sensor As a conventional CMOS image sensor, a solid-state imaging device having a voltage conversion circuit that generates a voltage different from a power supply voltage and driving a pixel using a voltage generated by the voltage conversion circuit is known. Yes.
  • Patent Document 1 a configuration of a conventional solid-state imaging device described in Patent Document 1 including a booster circuit as a voltage conversion circuit will be described with reference to FIG.
  • FIG. 14 is a block diagram illustrating a configuration of a conventional solid-state imaging device 1000 disclosed in Patent Document 1.
  • FIG. 14 is a block diagram illustrating a configuration of a conventional solid-state imaging device 1000 disclosed in Patent Document 1.
  • FIG. 14 is a block diagram illustrating a configuration of a conventional solid-state imaging device 1000 disclosed in Patent Document 1.
  • the solid-state imaging device 1000 includes a pixel array 1010 in which a plurality of unit pixels 1003 including a light receiving element that outputs a signal corresponding to the amount of incident light is arranged in a two-dimensional matrix, and a pixel signal is output from each unit pixel 1003.
  • the unit pixel 1003 is a so-called four-transistor pixel cell, and includes a photodiode 1030, a transfer transistor 1031, a reset transistor 1032, a selection transistor 1033, and a reading transistor 1034.
  • the read transistor 1034 in each unit pixel 1003 forms a source follower circuit (hereinafter referred to as a pixel source follower) by a read current source 1050 provided for each pixel column.
  • a pixel source follower a source follower circuit
  • the solid-state imaging device 1000 further includes a booster circuit 1100, a vertical scanning unit 1040, a horizontal scanning unit 1060, a horizontal selection transistor 1061, an amplifier 1069, an AD conversion unit 1080, and a signal processing unit 1090.
  • the vertical scanning unit 1040 drives the transistors 1031 to 1033 in the selected row, thereby resetting the photodiode 1030 and reading out the pixel signal.
  • the read pixel signals are sequentially supplied to the amplifier 1069 via the horizontal signal line 1062 when the horizontal scanning unit 1060 selects the horizontal selection transistors 1061 in the column order.
  • the pixel signal read to the amplifier 1069 is AD-converted by the AD conversion unit 1080, subjected to signal processing by the signal processing unit 1090, and then output from the solid-state imaging device 1000 to the outside.
  • the booster circuit 1100 generates a boosted voltage higher than the input power supply voltage by a voltage conversion operation such as a charge pump, and supplies the boosted voltage to the vertical scanning unit 1040.
  • the vertical scanning unit 1040 drives the transfer transistor 1031, the reset transistor 1032, and the selection transistor 1033 through the transfer transistor control line 1041, the reset transistor control line 1042, and the selection transistor control line 1043, respectively, using the boosted voltage. To do.
  • the vertical scanning unit 1040 drives the transfer transistor 1031, the reset transistor 1032, and the selection transistor 1033 with the power supply voltage
  • the source potential of each transistor is suppressed to a voltage that is lower than the power supply voltage by the threshold voltage. Is done.
  • the readout amount of the photodiode charge by the transfer transistor, the source follower circuit operation range by the selection transistor, and the source follower circuit gate applied voltage by the reset transistor are suppressed.
  • the amount of signals that can be handled is reduced, so that the dynamic range is reduced.
  • each transistor operates using the source potential as the power supply voltage. It becomes possible. As a result, sufficient readout of the photodiode charge, output up to the power supply voltage of the source follower circuit, and application of the power supply voltage itself to the source follower circuit gate are possible, and the amount of signals that can be handled increases, so a high dynamic range Can be realized.
  • the solid-state imaging device 1000 requires a constant voltage or a constant current input, such as an input current to the read current source 1050 in FIG. 14 and a current source for an amplifier included in the reference voltage of the booster circuit 1100 and the like.
  • a constant voltage or a constant current input such as an input current to the read current source 1050 in FIG. 14 and a current source for an amplifier included in the reference voltage of the booster circuit 1100 and the like.
  • noise mixed in the reference voltage of the read current source 1050 affects all the columns in common and becomes so-called horizontal noise, so the influence on the image quality is very large.
  • a noise countermeasure for the amplifier current source included in the input voltage to the read current source 1050, the reference voltage of the booster circuit 1100, etc. a low-pass filter is provided and noise band is limited to output the noise. It is known that the constant voltage signal can be reduced in noise.
  • a high dynamic range can be achieved by using a booster circuit, and a low noise can be achieved by using a low-noise circuit including a low-pass filter.
  • the booster circuit is a circuit that requires time until the normal boosted voltage value is output after the booster circuit is started up, and the booster circuit reaches a level acceptable as the start-up time as the solid-state imaging device. It is necessary to shorten the startup time.
  • the use of a low noise circuit limits the bandwidth of the circuit itself and delays the supply of constant voltage and constant current due to the rise delay of the low pass filter. Therefore, for example, a booster circuit to which a constant voltage is input from a low noise circuit cannot operate normally until the constant voltage is normally input. Therefore, the start-up is further delayed as a price for reducing noise.
  • the larger the band is, the larger the capacity constituting the low-pass filter must be, and the start-up will be delayed.
  • the band limitation is performed to a lower frequency, that is, the cutoff frequency that determines the noise removal lower limit frequency of the low-pass filter is set to a lower frequency, thereby increasing the noise. It is necessary to reduce.
  • the startup delay of the booster circuit is steadily increasing.
  • it is possible to improve the driving capability and increase the starting speed by increasing the switch size of the booster circuit to reduce the resistance of the switch path or increasing the switching frequency.
  • lowering the resistance of the switch path increases the inrush current during switching, and increasing the switching frequency increases the switching frequency.
  • the switching noise itself generated by the booster circuit also increases, and the noise reduction effect of the low noise circuit is impaired.
  • a booster circuit is indispensable for realizing a high dynamic range, and it is impossible to select not to use a booster circuit.
  • the conventional solid-state imaging device has a problem that it is difficult to achieve both high-speed startup, low noise, and high dynamic range.
  • noise start-up time and dynamic range.
  • an object of the present invention is to provide a solid-state imaging device having a function of achieving both high-speed startup, low noise, and high dynamic range.
  • a solid-state imaging device includes a plurality of pixels that are arranged in a matrix and convert light into a signal voltage, and a vertical signal line provided for each pixel column.
  • a current source circuit that is provided for each pixel column and supplies a current for reading the signal voltage to the vertical signal line by being supplied with a first voltage; and a power supply voltage by being supplied with a second voltage.
  • Uses a voltage conversion circuit for generating different voltages drives the plurality of pixels in a row sequence using the voltage generated by the voltage conversion circuit, and connects the vertical signal line and the current source circuit from the pixels in the corresponding row.
  • a vertical scanning circuit that reads out the signal voltage via the first voltage circuit, a first constant voltage circuit that supplies the current source circuit with the first voltage from which a higher frequency component is removed than the second voltage, and the voltage conversion circuit.
  • the vertical scanning circuit can drive the driving voltage for driving each pixel not by the power supply voltage but by the voltage supplied by the voltage conversion circuit. Accordingly, the source potential of the transistor included in each pixel can be operated up to the power supply voltage without being suppressed to a voltage lower than the power supply voltage by the threshold voltage. As a result, since a pixel signal that sufficiently reflects the signal voltage can be output from each pixel, a high dynamic range can be achieved.
  • the second constant voltage circuit that outputs the second voltage including the high band has a large amount of noise because the band is not limited, but the startup time as the constant voltage circuit is fast.
  • the first constant voltage circuit that outputs the first voltage in the low band has a small amount of noise because the band is limited, but the start-up time is slow due to the resistors and capacitors that constitute the low-pass filter.
  • the generated voltage of the voltage conversion circuit is supplied for the purpose of logical operation as the switch voltage of the pixel transistor, so the contribution of noise of the generated voltage itself to the pixel output is low, so the reference voltage without band limitation Is not a big problem for the image quality.
  • noise mixed in the current source circuit for reading out the signal voltage of each pixel is largely propagated to the pixel output and greatly affects the image quality.
  • noise mixed in the reference voltage of the current source circuit affects all the columns in common, so that it becomes so-called horizontal noise, and the influence on the image quality is very large.
  • the noise amount of the reference voltage is suppressed and the noise of the pixel output is reduced.
  • the start-up delay of the constant voltage circuit itself increases due to the band limitation, so the delay before starting the signal voltage read operation increases, but the read operation must be started before the voltage conversion circuit starts up. For example, it does not affect the startup time of the solid-state imaging device.
  • the activation of the voltage conversion circuit and the first constant voltage circuit having a low bandwidth can be operated in parallel. Therefore, since the start time of the voltage conversion circuit can be used as the read operation start time, it is possible to perform sufficient band limitation on the first constant voltage circuit. Therefore, it is possible to realize low noise and high dynamic range without degrading the startup time as a solid-state imaging device.
  • the solid-state imaging device is further connected to the first capacitor element connected to the first constant voltage circuit and the second constant voltage circuit, and has a capacitance value different from that of the first capacitor element. 2 capacitive elements.
  • a low-pass filter having a different band characteristic is formed by a capacitor having a different capacitance value connected to the constant voltage circuit using the impedance of the constant voltage circuit as a resistor.
  • a resistance element can be dispensed with. Therefore, the band limitation degree of the output voltage of the first constant voltage circuit connected to the current source circuit and the band limitation degree of the output voltage of the second constant voltage circuit connected to the voltage conversion circuit are reduced by noise and It becomes possible to make it different according to the necessity of shortening the delay time.
  • the solid-state imaging device is further connected to the first filter circuit connected to the first constant voltage circuit and to the second constant voltage circuit, and has a higher pass band than the first filter circuit. And a second filter circuit.
  • the band restriction degree of the output voltage of the first constant voltage circuit connected to the current source circuit can be set higher than the band restriction degree of the output voltage of the second constant voltage circuit connected to the voltage conversion circuit. Therefore, it is possible to enhance noise removal in the current source circuit without deteriorating the delay time.
  • one of the first constant voltage circuit and the second constant voltage circuit is connected to a capacitive element, and the other of the first constant voltage circuit and the second constant voltage circuit is a capacitive element. May not be connected.
  • a filter circuit may be connected to the first constant voltage circuit, and a filter circuit may not be connected to the second constant voltage circuit.
  • first constant voltage circuit and the second constant voltage circuit are included in a third constant voltage circuit
  • the third constant voltage circuit includes components of the first constant voltage circuit and A part of the components of the second constant voltage circuit is shared, and the first voltage from the first constant voltage circuit and the second voltage from the second constant voltage circuit are independently output. May be.
  • the constant voltage to the voltage conversion circuit is output via the constant voltage circuit unit included in the third constant voltage circuit, and the constant voltage to the current source circuit is output from the constant voltage circuit unit included in the third constant voltage circuit. And output through a band limiting resistor. Therefore, it is possible to achieve both high-speed startup, low noise, and high dynamic range while realizing a reduction in circuit scale.
  • a solid-state imaging device includes a plurality of pixels arranged in a matrix and converting light into a signal voltage, and a plurality of pixels provided for each pixel column.
  • a voltage conversion circuit that generates a voltage different from the power supply voltage, and the plurality of pixels are driven in a row sequence using the voltage generated by the voltage conversion circuit, and the vertical signal lines and the pixels from the pixels in the corresponding row are driven.
  • a vertical scanning circuit that reads out the signal voltage via a current source circuit; a first constant current circuit that supplies the first current from which a high-frequency component is removed from the second current to the current source circuit; and the voltage In the conversion circuit, the first Characterized in that it comprises a second constant current circuit for supplying a current.
  • the second constant current circuit has a large amount of noise, but the startup time is fast.
  • the first constant current circuit has a small amount of noise but a low startup time. In this regard, since the contribution of noise generated by the voltage conversion circuit itself to the pixel output is low, even if a reference current that is not band-limited is supplied, it does not pose a significant problem in image quality.
  • noise mixed in the current source circuit for reading out the signal voltage of each pixel is largely propagated to the pixel output and greatly affects the image quality.
  • noise mixed in the reference current of the current source circuit affects all columns in common, so that it becomes so-called horizontal noise, and the influence on image quality is very large.
  • the startup delay of the constant current circuit itself increases, so the delay until the signal voltage read operation starts increases, but the read operation must be started before the voltage conversion circuit starts. For example, it does not affect the startup time of the solid-state imaging device.
  • the activation of the voltage conversion circuit and the first constant current circuit having a low bandwidth can be operated in parallel. Therefore, since the startup time of the voltage conversion circuit can be used for the read operation startup time, it is possible to perform sufficient band limitation on the first constant current circuit. Therefore, it is possible to realize low noise and high dynamic range without degrading the startup time as a solid-state imaging device.
  • a mirror circuit is configured to supply a reference current instead of a reference voltage to the current source circuits in each column.
  • the solid-state imaging device is further connected to the first capacitor element connected to the first constant current circuit and the second constant current circuit, and has a capacitance value different from that of the first capacitor element. 2 capacitive elements.
  • a low-pass filter having a different band characteristic is formed with a capacitor having a different capacitance value connected to the constant current circuit, using the impedance of the constant current circuit as a resistance.
  • a resistance element can be dispensed with. Accordingly, the band limitation degree of the output voltage of the first constant current circuit connected to the current source circuit and the band limitation degree of the output voltage of the second constant current circuit connected to the voltage conversion circuit are reduced by noise and It becomes possible to make it different according to the necessity of shortening the delay time.
  • the solid-state imaging device further includes a first filter circuit connected to the first constant current circuit, and a second pass filter connected to the second constant current circuit, and having a higher passband than the first filter circuit. And a second filter circuit.
  • the band limit degree of the output voltage of the first constant current circuit connected to the current source circuit can be set higher than the band limit degree of the output voltage of the second constant current circuit connected to the voltage conversion circuit. Therefore, it is possible to enhance noise removal in the current source circuit without deteriorating the delay time.
  • one of the first constant current circuit and the second constant current circuit is connected to a capacitor element, and the other of the first constant current circuit and the second constant current circuit is a capacitor element. May not be connected.
  • the band limitation degree of the output voltage of the first constant current circuit and the band limitation degree of the output voltage of the second constant current circuit are reduced by noise and the delay time is shortened. It becomes possible to make it different according to the necessity of conversion.
  • a filter circuit may be connected to the first constant current circuit, and a filter circuit may not be connected to the second constant current circuit.
  • At least one of the first constant current circuit and the second constant current circuit may be a constant current circuit that generates a current by dividing a voltage.
  • the first constant current circuit includes a fourth constant voltage circuit and a first voltage / current conversion circuit
  • the second constant current circuit includes the fourth constant voltage circuit and the second voltage.
  • the first constant current circuit and the second constant current circuit are included in a third constant current circuit, and the third constant current circuit includes the first constant current circuit.
  • the circuit and the second constant voltage circuit share the fourth constant voltage circuit, and the first constant current from the first constant current circuit and the second current from the second constant current circuit And may be output independently.
  • the constant current to the voltage conversion circuit is output via the third constant voltage circuit and the second voltage current conversion circuit
  • the constant current to the current source circuit is the third constant voltage circuit and the first voltage conversion circuit.
  • the output is made via a voltage-current conversion circuit. Therefore, it is possible to achieve both high-speed startup, low noise, and high dynamic range while realizing a reduction in circuit scale.
  • the solid-state imaging device is further connected to the third capacitor element connected to the first voltage-current converter circuit and to the second voltage-current converter circuit, and the capacitance value of the third capacitor element is A different fourth capacitor element may be provided.
  • a low-pass filter having a different band characteristic is formed by a capacitive element having a different capacitance value connected to the voltage-current converter circuit, using the impedance of the voltage-current converter circuit as a resistor.
  • a resistance element can be dispensed with. Therefore, the band limitation degree of the output voltage of the first voltage-current conversion circuit connected to the current source circuit and the band limitation degree of the output voltage of the second voltage-current conversion circuit connected to the voltage conversion circuit are expressed as noise. It becomes possible to make it different according to the necessity of removal and delay time shortening.
  • the solid-state imaging device further includes a third filter circuit connected to the first voltage-current conversion circuit and a second filter-current conversion circuit connected to the second voltage-current conversion circuit and having a higher pass than the third filter circuit. And a fourth filter circuit having a band.
  • the band limitation degree of the output current of the first voltage-current conversion circuit connected to the current source circuit is set higher than the band limitation degree of the output current of the second voltage-current conversion circuit connected to the voltage conversion circuit. it can. Therefore, it is possible to enhance noise removal in the current source circuit without deteriorating the delay time.
  • One of the first voltage-current conversion circuit and the second voltage-current conversion circuit is connected to a capacitive element, and the other of the first voltage-current conversion circuit and the second voltage-current conversion circuit. May not be connected to the capacitor.
  • the band limitation degree of the output current of the first voltage-current converter circuit and the band limit degree of the output current of the second voltage-current converter circuit are reduced with noise and delayed. It becomes possible to make it different according to the necessity of time reduction.
  • a filter circuit may be connected to the first voltage-current conversion circuit, and a filter circuit may not be connected to the second voltage-current conversion circuit.
  • a vertical scanning circuit drives each pixel with a voltage supplied from a voltage conversion circuit instead of a power supply voltage, and (2) a voltage having a high frequency component is converted into a voltage. Since the voltage supplied to the circuit and limited to the frequency component in the low band is supplied to the current source circuit, it is possible to achieve both low noise and high dynamic range without degrading the startup time as a solid-state imaging device. Is possible.
  • FIG. 1 is a block diagram showing a configuration of a solid-state imaging device 1 according to Embodiment 1 of the present invention.
  • FIG. 2 is a block diagram showing an example of the configuration of the unit pixel 5 and the vertical scanning circuit 40 included in the solid-state imaging device of the present invention.
  • FIG. 3 is a block diagram showing an example of the configuration of the column ADC 56 included in the solid-state imaging device of the present invention.
  • FIG. 4 is a block diagram illustrating an example of the configuration of the voltage conversion circuit 300 included in the solid-state imaging device of the present invention.
  • FIG. 5A is a block diagram illustrating an example of a configuration of the low-band constant voltage circuit 100 included in the solid-state imaging device 1 according to Embodiment 1 of the present invention.
  • FIG. 5B is a block diagram illustrating an example of a configuration of the high-band constant voltage circuit 200 included in the solid-state imaging device 1 according to Embodiment 1 of the present invention.
  • FIG. 6 is a block diagram showing a configuration of the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • FIG. 7A is a block diagram illustrating a first example of the configuration of the low-band constant current circuit 107 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • FIG. 7B is a block diagram illustrating a first example of the configuration of the high-band constant current circuit 207 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • FIG. 8A is a block diagram illustrating a second example of the configuration of the low-band constant current circuit 107 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • FIG. 8B is a block diagram illustrating a second example of the configuration of the high-band constant current circuit 207 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • FIG. 9A is a block diagram showing a third example of the configuration of the low-band constant current circuit 107 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • FIG. 8A is a block diagram illustrating a second example of the configuration of the low-band constant current circuit 107 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • FIG. 9B is a block diagram illustrating a third example of the configuration of the high-band constant current circuit 207 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • FIG. 10 is a block diagram showing a configuration of the solid-state imaging device 3 according to Embodiment 3 of the present invention.
  • FIG. 11 is a block diagram showing a configuration of a multiband constant voltage circuit 400 included in the solid-state imaging device 3 according to Embodiment 3 of the present invention.
  • FIG. 12 is a block diagram showing a configuration of the solid-state imaging device 4 according to Embodiment 4 of the present invention.
  • FIG. 10 is a block diagram showing a configuration of the solid-state imaging device 3 according to Embodiment 3 of the present invention.
  • FIG. 11 is a block diagram showing a configuration of a multiband constant voltage circuit 400 included in the solid-state imaging device 3 according to Embodiment 3 of the present invention.
  • FIG. 12 is a block diagram showing a configuration of
  • FIG. 13 is a block diagram showing a configuration of a multiband constant current circuit 407 included in the solid-state imaging device 4 according to Embodiment 4 of the present invention.
  • FIG. 14 is a block diagram illustrating a configuration of a conventional solid-state imaging device 1000 disclosed in Patent Document 1. In FIG.
  • the solid-state imaging device 1 includes a low-band constant voltage circuit that limits the band in order to reduce noise, and a high-band low-voltage circuit that does not limit the band for speeding up the start.
  • a low-band constant voltage circuit that limits the band in order to reduce noise
  • a high-band low-voltage circuit that does not limit the band for speeding up the start.
  • FIG. 1 is a block diagram showing a configuration of a solid-state imaging device 1 according to Embodiment 1 of the present invention.
  • the solid-state imaging device 1 illustrated in FIG. 1 includes a pixel array 10, a vertical scanning circuit 40, a plurality of transfer transistor control lines 41, a plurality of reset transistor control lines 42, a plurality of selection transistor control lines 43, A plurality of vertical signal lines 45, a plurality of read current sources 50, a plurality of column ADCs 56, a reference signal generator 57, a horizontal signal line 55, a horizontal scanning circuit 60, a plurality of horizontal control lines 65, and an output A circuit 67, a timing control unit 70, at least one high-band constant voltage circuit 200, at least one low-band constant voltage circuit 100, and a band limiting capacitor 101 for limiting the band of the low-band constant voltage circuit; And at least one voltage conversion circuit 300.
  • Each functional block shown in FIG. 1 is arranged on only one side when viewed from the pixel array 10, but may be arranged on both sides of the pixel array 10.
  • the pixel array 10 includes a plurality of unit pixels 5 arranged in a matrix, and the unit pixels 5 photoelectrically convert the received light into signal voltages.
  • the plurality of vertical signal lines 45 are provided corresponding to the columns of the unit pixels 5 and transmit the signal voltages output from the unit pixels 5 of the corresponding columns.
  • FIG. 2 is a block diagram showing an example of the configuration of the unit pixel 5 and the vertical scanning circuit 40 included in the solid-state imaging device of the present invention.
  • the unit pixel 5 is a so-called four-transistor unit pixel cell, and includes a photodiode 30, a transfer transistor 31, a reset transistor 32, a selection transistor 33, and a readout transistor 34 (hereinafter collectively referred to as a pixel transistor). It is a pixel provided.
  • the read transistor 34 is connected in common by a vertical signal line 45 provided for each column between a plurality of unit pixels arranged in the same column, and a read current source 50 which is a current source circuit provided for each pixel column.
  • a source follower circuit (hereinafter referred to as a pixel source follower) is constituted by the read transistor 34 in the row in which the selection transistor 33 is conducted.
  • the pixel signal is read out by the pixel source follower via the vertical signal line 45.
  • the 4-transistor type unit pixel 5 is illustrated, but the unit pixel 5 may be a so-called 3-transistor type unit pixel in which the selection transistor 33 does not exist, and a plurality of photodiodes.
  • 30 may be a unit pixel of a so-called multi-pixel 1 cell sharing the readout transistor 34.
  • Each transistor constituting the unit pixel 5 may be either an NMOS transistor or a PMOS transistor, and a plurality of vertical signal lines 45 may exist for one column.
  • the unit pixel 5 is not limited to the configuration shown in FIG. 2 as long as the signal voltage from the photodiode 30 can be output to the vertical signal line 45.
  • the vertical scanning circuit 40 includes a decoder 44 that determines which row of pixel signals to read based on information from the timing control unit 70, and a plurality of vertical drivers 47 that drive each pixel transistor in the pixel.
  • the vertical driver 47 has the same configuration as each pixel transistor. However, at least one vertical driver 47 supplies a boosted voltage only to the vertical driver 47 that drives the reset transistor control line 42. As long as the voltage from the voltage conversion circuit 300 is supplied to the driver 47, it does not depart from the object and scope of the present invention. Further, different voltages from a plurality of voltage conversion circuits 300 are supplied to one vertical driver 47, such as a boosted voltage as an H level and a negative stepped down voltage as an L level are supplied to the vertical driver 47. However, it does not depart from the object and scope of the present invention.
  • the vertical scanning circuit 40 sequentially activates the transfer transistor control line 41, the reset transistor control line 42, and the selection transistor control line 43 to sequentially select the rows of the unit pixels 5 and perform vertical scanning.
  • the signal voltage of the selected row is transmitted to the column ADC 56 via the pixel source follower for each column.
  • the reset transistor 32 is turned on by the reset transistor control line 42, whereby the gate voltage of the read transistor 34, that is, the so-called floating diffusion voltage is reset.
  • the selection transistor 33 is turned on by the selection transistor control line 43, and the voltage after resetting the floating diffusion portion is set as the reset level voltage Vrst of the unit pixel 5 in the m-th row through the readout transistor 34 and the vertical signal line 45. And supplied to the column ADC 56 at the subsequent stage for AD conversion.
  • the photodiode 30 accumulates charges obtained by photoelectrically converting light received during the exposure time.
  • the transfer transistor 31 is turned on in the unit pixel 5 in the m-th row by the transfer transistor control line 41, and the charge accumulated in the photodiode 30 is transferred to the floating diffusion portion.
  • the transferred charge is vertically transmitted through the read transistor 34 as a voltage (Vrst + Vsig) obtained by superimposing the voltage Vsig of the m-th row signal level corresponding to the amount of received light on the reset level voltage Vrst of the unit pixel 5 of the m-th row.
  • the signal is output to the signal line 45 and supplied to the subsequent column ADC 56 for AD conversion.
  • the signal level of the unit pixel 5 in the m-th row corresponding to the amount of received light can be obtained by a so-called double sampling operation that extracts a difference between signals generated as a result of two AD conversions.
  • the driving method of the unit pixel 5 described above is an example.
  • the object and scope of the present invention do not limit the processing of the pixel signal, but the reset level voltage Vrst of the m-th unit pixel 5 and the m-th row signal level voltage Vsig according to the m-th received light amount. Is not limited to the illustrated driving method. Further, there may be a driving method in which the column ADC 56 does not exist and the conversion is performed by a single ADC after horizontal selection as an analog signal as in the conventional solid-state imaging device illustrated in FIG.
  • the solid-state imaging device 1 shown in FIG. 1 no signal amplifying means is provided for the output of the unit pixel 5, but an AGC (Auto) is provided in the signal path from the output of the unit pixel 5 to the input of the column ADC 56.
  • a signal amplifying means such as Gain Control
  • a so-called column amplifier may be provided.
  • the signal level of the signal input to the column ADC 56 can be increased.
  • the input conversion S / N in AD conversion is improved, and the image quality of the solid-state imaging device 1 can be improved. it can.
  • the column amplifier a so-called single-ended inverter amplifier that drives a constant-current load with a source-grounded amplifier circuit is preferably used.
  • Amplifying means such as an amplifier circuit may be used. Further, a sample hold means for sample holding the signal input to the column ADC 56 may be provided. In the case where sample hold means for the signal input to the column ADC 56 is provided, it is possible to perform so-called pipeline operation in which the conversion operation of the column ADC 56 and the signal reading from the unit pixel 5 to the vertical signal line 45 are operated in parallel. As a result, the frame rate of the solid-state imaging device 1 can be improved.
  • FIG. 3 is a block diagram showing an example of the configuration of the column ADC 56 included in the solid-state imaging device of the present invention.
  • the column ADC 56 is provided corresponding to the vertical signal line 45, and converts the signal voltage transmitted through the corresponding vertical signal line 45 into a digital signal.
  • the reference signal generation unit 57 generates a common reference signal supplied to the column ADC 56 of each column.
  • the column ADC 56 is exemplified as a so-called single slope AD converter circuit, but other ADC methods such as successive approximation do not depart from the object and scope of the present invention.
  • the column ADC 56 in the present embodiment simultaneously converts a plurality of signal voltages output to the vertical signal lines 45 of each column into digital signals.
  • the column ADC 56 includes a voltage comparison unit 415, a count unit (counter) 416, and a memory unit 418, and a common reference signal from the reference signal generation unit 57 is input thereto.
  • the reference signal generator 57 generates a reference signal voltage (ramp waveform signal voltage) Vslope that gradually changes over time.
  • the reference signal voltage Vslope may be a smooth slope waveform or a stepped waveform, and the waveform is not particularly limited as long as the waveform changes with a certain slope.
  • the slope of the reference signal voltage Vslope may be either positive or negative.
  • the reference signal generation unit 57 can be configured by filtering the DAC output by giving a code value that increases or decreases to a DAC (digital analog converter), or by performing an integration operation using a capacitive element. This configuration is not particularly limited as long as it is a reference signal generation unit 57 that can generate a waveform that changes with a certain inclination.
  • the voltage comparison unit 415 compares the signal voltage output to the vertical signal line 45 and converted into a digital signal with the reference signal voltage Vslope that is input to the voltage comparison unit 415 and gradually changes.
  • the voltage comparison unit 415 is preferably composed of a differential comparator having a well-known offset cancellation function, but may be composed of a so-called chopper comparator or the like, and the signal voltage of the vertical signal line 45 and the reference.
  • the configuration is not particularly limited as long as the voltage comparison unit 415 can compare the signal voltage Vslope.
  • the counting unit 416 changes the time from when the voltage comparison unit 415 starts comparison until the comparison result of the voltage comparison unit 415 changes, that is, the magnitude relationship between the signal voltage of the vertical signal line 45 and the reference signal voltage Vslope.
  • a / D conversion is performed by counting the time until the output of the voltage comparison unit 415 is inverted. That is, the count unit 416 performs AD conversion by counting the input clock CLK from the start of comparison until the magnitude relationship between the signal voltage and the reference signal voltage Vslope changes.
  • the count unit 416 transmits the digital signal value (count value) to the memory unit 418, and the memory unit 418 stores the transmitted digital signal value.
  • This AD conversion is performed twice on the reset level voltage Vrst and the voltage (Vrst + Vsig) obtained by superimposing the reset level Vrst on the signal level voltage Vsig corresponding to the amount of received light.
  • the signal of the unit pixel 5 is obtained from the difference information. A level is obtained. This double sampling operation is not essential for the present invention, and even if AD conversion is performed only for the signal level Vsig, it does not depart from the object and scope of the present invention.
  • the horizontal scanning circuit 60 sequentially controls the horizontal control lines 65 based on information from the timing control unit 70. As a result, the digital signal value stored in the memory unit 418 for each column is read to the horizontal signal line 55 and supplied to the output circuit 67.
  • the output circuit 67 outputs the transmitted digital signal value to the outside.
  • a high-speed transmission circuit such as LVDS is preferably used as the output circuit 67, but the output method, circuit, and configuration of the output circuit 67 are not particularly limited as long as the output means can output a digital signal value. Further, the type of serial output and parallel output, the number of output ports, and the like are not particularly limited.
  • the feature of the solid-state imaging device 1 according to the present embodiment is that it includes at least one high-band constant voltage circuit 200, at least one low-band constant voltage circuit 100, and at least one voltage conversion circuit 300.
  • the vertical scanning circuit 40 can drive the gate drive HIGH levels of the transfer transistor 31, the reset transistor 32, and the selection transistor 33 with the boosted voltage supplied from the voltage conversion circuit 300 instead of the power supply voltage. . Therefore, the source potential of each transistor can be operated up to the power supply voltage without being suppressed to a voltage lower than the threshold voltage from the power supply voltage. As a result, sufficient readout of the photodiode charge, output up to the power supply voltage of the source follower circuit, and application of the power supply voltage itself to the source follower circuit gate become possible, and the amount of signals that can be handled increases, resulting in a high dynamic range. Is possible.
  • the vertical scanning circuit 40 can drive the gate drive LOW level of the transfer transistor 31, the reset transistor 32, and the selection transistor 33 with a negative step-down voltage supplied from the voltage conversion circuit 300, instead of the ground potential. . Therefore, the gate potential when each transistor is turned off becomes a negative step-down voltage, and the occurrence of off-leakage current in each pixel transistor is suppressed, and abnormalities such as scratches and floating as an image are suppressed, thereby achieving high image quality.
  • At least one voltage conversion circuit 300 to generate a boosted voltage higher than the power supply voltage or a negative stepped-down voltage, supply it to the vertical scanning circuit 40, and use it for driving the pixel transistor, high dynamics can be achieved. Range and high image quality are realized.
  • FIG. 4 is a block diagram showing an example of the configuration of the voltage conversion circuit 300 included in the solid-state imaging device of the present invention.
  • the voltage conversion circuit 300 shown in the figure is a so-called charge pump type booster circuit, and includes switches SW1 to SW4, a pump capacitor Cp, a smoothing capacitor Cout, a voltage dividing resistor R1 for detecting a generated voltage, and R2 and a comparison circuit 301 that detects the generated voltage and controls the boosting operation.
  • the voltage conversion circuit 300 repeats the operation of accumulating energy as a voltage in the pump capacitor Cp and the operation of transferring the energy to the smoothing capacitor Cout by the switching operation of the switches SW1 to SW4, thereby increasing the voltage higher than the power supply voltage. Is generated.
  • the switches SW1 and SW3 are turned on when energy is stored in the pump capacitor Cp, and the switches SW2 and SW4 are turned on when the energy is transferred to the smoothing capacitor Cout.
  • the comparison circuit 301 controls the switching operation so that the generated voltage becomes a desired voltage, and generates a desired voltage different from the power supply voltage.
  • the output of the comparison circuit 301 is inverted and the CLK input for switching operation is gated. Thereby, the switching operation is stopped, and the generated voltage becomes a desired voltage value.
  • the voltage conversion circuit 300 may be a step-up circuit or a negative step-down circuit, and may be a so-called charge pump type circuit or a switching regulator type circuit. Not deviate from.
  • the voltage conversion circuit 300 requires at least one of a reference voltage and a reference current.
  • the comparison circuit 301 requires a reference voltage for voltage comparison and a reference current for circuit operation of the comparison circuit.
  • 5A and 5B are block diagrams showing examples of configurations of the high-band constant voltage circuit 200 and the low-band constant voltage circuit 100 included in the solid-state imaging device 1 according to Embodiment 1 of the present invention, respectively.
  • the solid-state imaging device 1 includes at least one high-band constant voltage circuit 200 and at least one low-band constant voltage circuit 100.
  • the high band constant voltage circuit 200 is a second constant voltage circuit that outputs a second voltage with no band limitation to the output of a general band gap reference circuit (BGR in the figure) 105.
  • the low-band constant voltage circuit 100 performs band limitation by inserting a low-pass filter 103 including a band-limiting resistor 102 and a band-limiting capacitor 101 with respect to the output of a general band-gap reference circuit 105 to perform first band limitation. It is the 1st constant voltage circuit which outputs a voltage. Since the high-band constant voltage circuit 200 is not band-limited, the amount of noise is large, but the startup time as the constant-voltage circuit is fast. On the other hand, since the low-band constant voltage circuit 100 performs band limitation, the amount of noise is small and the low-band voltage circuit 100 can be used as a low-noise circuit. Time is slow.
  • the band limiting capacitor 101 it is preferable to use an external capacitor in order to greatly limit the band. However, it is not always necessary to use an external capacitor. The use of this capacity does not depart from the purpose and scope of the present invention.
  • the band gap reference circuit 105 is exemplified. However, if the voltage source circuit generates a voltage, the object and scope of the present invention are applicable to, for example, a voltage generation circuit using resistance voltage division. Not deviate from. Furthermore, in the present embodiment, an example in which the low-pass filter 103 that is the first filter circuit is connected only to the low-band constant voltage circuit 100 is illustrated. However, the high-band constant voltage circuit 200 is not affected by the startup time.
  • the band of the low pass filter connected to the low band constant voltage circuit 100 is set lower than the band of the low pass filter connected to the high band constant voltage circuit 200.
  • band limitation by another band limiting unit may be used.
  • a low-pass filter is not configured with a band-limiting resistor and a band-limiting capacitor, but even when only a capacitive element for band-limiting is connected, the circuit output impedance of the previous stage of the band-limiting capacitor is used as a resistor, Therefore, the same effect as in the present embodiment can be obtained, and a resistance element can be dispensed with. Even in this case, not only the first capacitive element is connected to the low-band constant voltage circuit 100 but also the first capacitive element and the capacitance value are connected to the high-band constant voltage circuit 200 within a range that does not affect the startup time. Even the configuration in which the second capacitive elements having different values are connected does not depart from the object and scope of the present invention.
  • the band of the low-pass filter composed of the first capacitor element is set lower than the band of the low-pass filter composed of the second capacitor element.
  • the number of voltage outputs is not limited, and there may be an arbitrary number of voltage outputs of 2 or more.
  • the voltage conversion circuit 300 requires a start-up time because it has a large capacity for smoothing and it is necessary to repeat the switching operation in order to perform the step-up or step-down operation.
  • the allowable time as the activation time varies depending on the application, such as several tens of ms to several hundred ms, but there is always a limitation of an allowable activation delay time. Since normal imaging cannot be performed until the voltage conversion circuit 300 is activated, the activation delay of the voltage conversion circuit 300 needs to be suppressed within a range that does not affect the above-described restriction.
  • the startup delay of the voltage conversion circuit 300 is determined by the time required for the step-up or step-down operation and the time until the reference voltage and the reference current are normally supplied.
  • the high-band constant voltage circuit 200 is used for supplying the reference voltage to the voltage conversion circuit 300, the start-up delay of the constant voltage circuit itself is small, and the start-up of the voltage conversion circuit 300 is low-band constant.
  • the speed is increased compared to the case where the voltage circuit 100 is used. Since the startup of the voltage conversion circuit 300 is speeded up, there is a margin in the startup time, so that the voltage conversion circuit 300 reduces the switch size, increases the resistance of the switch path, or decreases the switching frequency. Is also possible. In this case, the inrush current at the time of switching is reduced and the switching frequency is lowered, so that the switching noise itself generated by the booster circuit is also reduced, and the noise can be further reduced.
  • the generated voltage of the voltage conversion circuit 300 is supplied as a switch voltage of the pixel transistor for the purpose of logical operation, and the voltage conversion circuit 300 itself forms one band limit, so that noise of the generated voltage itself propagates to the pixel output. Since the degree of contribution is low, supplying a reference voltage and a reference current that are not band-limited does not pose a major problem in image quality.
  • the noise mixed in the pixel source follower composed of the read current source 50 and the read transistor 34 is largely propagated to the pixel output and greatly affects the image quality.
  • noise mixed in the reference voltage of the read current source 50 affects all the columns in common, so that it becomes so-called horizontal noise, and the influence on the image quality is very large. Therefore, the reference voltage to the read current source 50 needs to greatly limit noise.
  • the low-band constant voltage circuit 100 by using the low-band constant voltage circuit 100 to supply the reference voltage to the read current source 50, the amount of noise of the reference voltage is suppressed, and the noise of the pixel output is reduced.
  • the startup delay of the constant voltage circuit itself is large and the delay until the operation of the pixel source follower is increased.
  • the pixel source follower has been started up before the voltage conversion circuit 300 is started up. For example, it does not affect the startup time of the solid-state imaging device 1.
  • the activation of the voltage conversion circuit 300 and the low-band constant voltage circuit 100 can be operated in parallel.
  • the start time of the voltage conversion circuit 300 and the same start time such as several tens ms to several hundred ms can be given to the pixel source follower, so that sufficient band limitation is performed on the low band constant voltage circuit 100. It becomes possible. Therefore, noise can be greatly reduced without degrading the startup time of the solid-state imaging device 1.
  • the solid-state imaging device 1 includes at least one high-band constant voltage circuit 200 and converts at least the voltage conversion circuit 300 using the second voltage generated by the high-band constant voltage circuit 200. Used in.
  • the solid-state imaging device 1 includes at least one low-band constant voltage circuit 100 and uses at least the read current source 50 with the first voltage generated by the low-band constant voltage circuit 100.
  • the solid-state imaging device 2 according to the present embodiment is different from the solid-state imaging device 1 according to the first embodiment in that a low-band constant current circuit and a high-band constant voltage circuit are used instead of the low-band constant voltage circuit and the high-band constant voltage circuit. Use of the current circuit is different. Further, the difference is that the gate input to the read current source 50 which is a current source circuit is not a reference voltage, the read current source 50 forms a mirror circuit, and the reference current becomes an input to the read current source 50.
  • FIG. 6 is a block diagram showing a configuration of the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • 7A and 7B are block diagrams showing first examples of the configurations of the low-band constant current circuit 107 and the high-band constant current circuit 207, respectively, included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. It is. In addition, the same code
  • the solid-state imaging device 2 has the same configuration as that of the solid-state imaging device 1 according to the first embodiment, except for the input unit to the low-band constant current circuit 107, the high-band constant current circuit 207, and the readout current source 50. .
  • the high-band constant current circuit 207 outputs the current obtained by the VI conversion circuit 500 as the second current without band limitation with respect to the output of the general bandgap reference circuit 105. It is a constant current circuit.
  • the low-band constant current circuit 107 limits the band obtained by the VI conversion circuit 500 to the output of the general band gap reference circuit 105 by the band-limiting capacitor 101 and outputs it as the first current.
  • the first constant current circuit Note that the connection method between the VI conversion circuit 500 and the band limiting capacitor 101 exemplified in this embodiment is an example, and the configuration of the VI conversion circuit 500 is not limited as long as the circuit has a VI conversion function. For example, a simple source grounding circuit may be used.
  • the band limiting method of the VI conversion circuit is not limited.
  • the filter circuit may be configured or connected in the VI conversion circuit instead of the connection of the band limiting capacitor.
  • the number of current outputs is not limited, and there may be an arbitrary number of current outputs of two or more.
  • the high-band constant current circuit 207 has a large amount of noise because the band is not limited, but the startup time as a constant-current circuit is fast.
  • the low-band constant current circuit 107 since the low-band constant current circuit 107 performs band limitation, the amount of noise is small, and the low-band constant current circuit 107 can be used as a low-noise circuit. Is slow.
  • the band limiting capacitor 101 it is preferable to use an external capacitor in order to greatly limit the band. However, it is not always necessary to use an external capacitor. The use of this capacity does not depart from the purpose and scope of the present invention.
  • the band gap circuit is exemplified as the previous stage of the VI conversion circuit.
  • the present invention is applicable to a voltage generation circuit that generates a voltage, for example, a voltage generation circuit using resistance voltage division. Does not deviate from the purpose and scope of In the present embodiment, an example in which the band limiting capacitor 101 as the first capacitor is connected only to the low-band constant current circuit 107 is illustrated. However, the high-band constant current circuit 207 is not affected by the start-up time.
  • the band limiting capacity connected to the low band constant current circuit 107 is set larger than the band limiting capacity connected to the high band constant current circuit 207. Even when the band is limited by configuring or connecting the filter circuit in the VI conversion circuit, not only the first filter circuit is connected to the low-band constant current circuit 107 but also the start-up time is not affected.
  • a second filter circuit may be connected to the high-band constant current circuit 207 in the range. Also in this case, the band limiting capacity connected to the low band constant current circuit 107 is set larger than the band limiting capacity connected to the high band constant current circuit 207.
  • FIGS. 8A and 8B are block diagrams illustrating a second example of the configuration of the low-band constant current circuit 107 and the high-band constant current circuit 207, respectively, included in the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • the high-band constant current circuit 207 and the low-band constant current circuit 107 do not use the band gap reference circuit 105 and the VI conversion circuit 500, but a voltage dividing circuit 701 as illustrated in FIGS. 8A and 8B. Even if the current is generated by dividing the power supply voltage by using, it does not depart from the present invention.
  • the low-band constant current circuit 107 can be configured by the band-limiting capacitor 705.
  • band limiting capacitor 705 an example in which the band is limited by the band limiting capacitor 705 is illustrated, but band limiting may be performed by another means such as inserting a filter circuit in the gate voltage. If the band is higher than that of the low-band constant current circuit 107, the present invention does not depart from the present invention even if the band is limited.
  • FIGS. 9A and 9B are block diagrams showing a third example of the configuration of the low-band constant current circuit 107 and the high-band constant current circuit 207, respectively, included in the solid-state imaging device 2 according to Embodiment 2 of the present invention.
  • . 8A and 8B exemplify the example in which the voltage is divided by the resistor and the MOS transistor, but the voltage dividing circuit does not depart from the present invention as long as the requirement of current generation by dividing the fixed voltage is satisfied.
  • voltage is divided by other means such as dividing by two MOS transistors connected in series, and a current is generated from a fixed voltage such as a power supply voltage.
  • a fixed voltage such as a power supply voltage
  • the voltage conversion circuit 300 requires a startup time, and normal imaging cannot be performed until the voltage conversion circuit 300 is started. Therefore, the startup delay of the voltage conversion circuit 300 is the startup of the solid-state imaging device 2. It is necessary to limit to a range that does not affect the time constraint.
  • the high-band constant current circuit 207 is used for supplying the reference current to the voltage conversion circuit 300, the start-up delay of the constant-current circuit itself is small, and the start-up of the voltage conversion circuit 300 is performed by the low-band constant current circuit. Compared with the case of using 107, the speed is increased. As described above, since the startup of the voltage conversion circuit 300 is accelerated, it is possible to reduce the inrush current at the time of switching and to reduce the switching frequency, and to reduce the switching noise itself generated by the booster circuit. Noise can be reduced.
  • the generated voltage of the voltage conversion circuit 300 is not a big problem even if a reference voltage and a reference current that are not band-limited are supplied, but noise mixed in the pixel source follower is not output to the pixel output. Propagation greatly affects the image quality.
  • the noise amount of the reference current is suppressed and the noise of the pixel output is reduced.
  • the startup delay of the constant current circuit itself is large, and the delay until the operation of the pixel source follower is large.
  • the activation of the voltage conversion circuit 300 and the low-band constant current circuit 107 can be operated in parallel, and the activation time such as several tens ms to several hundreds ms, which is the same as the activation time of the voltage conversion circuit 300, is set as the pixel source follower. Can be given to. Therefore, sufficient band limitation can be performed on the low-band constant current circuit 107, and noise can be greatly reduced without deteriorating the startup time of the solid-state imaging device 2.
  • the solid-state imaging device 2 includes at least one high-band constant current circuit 207, and at least the voltage conversion circuit 300 converts the second current generated by the high-band constant current circuit 207. Used in.
  • the solid-state imaging device 2 includes at least one low-band constant current circuit 107 and uses at least the read current source 50 the first current generated by the low-band constant current circuit 107. As a result, it is possible to achieve both a start-up time as the solid-state imaging device 2 and a low noise and high dynamic range.
  • the pixel output when the source potential of the read current source 50 fluctuates due to noise or the like can be obtained. Noise propagation is suppressed.
  • the solid-state imaging device 3 according to the present embodiment uses a multi-band constant voltage circuit 400 instead of the low-band constant voltage circuit and the high-band constant voltage circuit with respect to the solid-state imaging device 1 according to the first embodiment. It is different in point.
  • FIG. 10 is a block diagram showing a configuration of the solid-state imaging device 3 according to Embodiment 3 of the present invention.
  • FIG. 11 is a block diagram showing a configuration of a multiband constant voltage circuit 400 included in the solid-state imaging device 3 according to Embodiment 3 of the present invention.
  • symbol is attached
  • the solid-state imaging device 3 has the same configuration as the solid-state imaging device 1 according to Embodiment 1 except for the multiband constant voltage circuit 400.
  • the multi-band constant voltage circuit 400 includes a high-band constant voltage output that is output without band limitation, a band-limiting resistor 102, and a band-limiting capacitor with respect to a single output of a general band gap reference circuit 105.
  • the third constant voltage circuit includes a low-band constant voltage output that is band-limited by inserting a low-pass filter 103 by 101. That is, the multi-band constant voltage circuit 400 includes a low-band constant voltage circuit 100 that is a first constant voltage circuit and a high-band constant voltage circuit 200 that is a second constant voltage circuit. Part of the components and the components of the high-band constant voltage circuit 200 are shared, and the constant voltage from the low-band constant voltage circuit and the constant voltage from the high-band constant voltage circuit are output independently.
  • the band gap circuit is exemplified.
  • the voltage source circuit generates voltage
  • a voltage generation circuit using resistance voltage division does not depart from the object and scope of the present invention.
  • the number of voltage outputs is not limited, and there may be an arbitrary number of voltage outputs of two or more.
  • the high-band constant voltage output has a large amount of noise because the band is not limited, but the startup time as a constant-voltage circuit is fast.
  • the low-band constant voltage output is band-limited, so the amount of noise is small and can be used as a low-noise circuit. Time is slow.
  • the band limiting capacitor 101 it is preferable to use an external capacitor in order to greatly limit the band.
  • an external capacitor it is not always necessary to use an external capacitor.
  • the use of this capacity does not depart from the purpose and scope of the present invention.
  • the low-pass filter which is the first filter circuit
  • the second high-band constant voltage output is not affected by the start-up time.
  • a low-pass filter which is a filter circuit
  • the band of the low-pass filter connected to the low-band constant voltage output is set lower than the band of the low-pass filter connected to the high-band constant voltage output.
  • a low-pass filter is not configured with a band-limiting resistor and a band-limiting capacitor, but even when only a capacitive element for band-limiting is connected, the circuit output impedance of the previous stage of the band-limiting capacitor is used as a resistor, Therefore, the same effect as in the present embodiment can be obtained, and a resistance element can be dispensed with.
  • the multi-band constant voltage circuit 400 exemplified in this embodiment is an example, and if a constant voltage output of a plurality of bands is generated from a single constant voltage circuit, the detailed circuit is not limited.
  • the voltage conversion circuit 300 requires a startup time, and normal imaging cannot be performed until the voltage conversion circuit 300 is started. Therefore, the startup delay of the voltage conversion circuit 300 is the startup of the solid-state imaging device 3. It is necessary to limit to a range that does not affect the time constraint.
  • the high-band constant voltage output of the multi-band constant voltage circuit 400 is used to supply the reference voltage to the voltage conversion circuit 300, the start-up delay of the constant voltage circuit itself is small, and the start-up of the voltage conversion circuit 300 is Compared with the case where a low-band voltage output is used, the speed is increased.
  • the startup of the voltage conversion circuit 300 is accelerated, it is possible to reduce the inrush current at the time of switching and to reduce the switching frequency, and to reduce the switching noise itself generated by the booster circuit. Noise can be reduced.
  • the generated voltage of the voltage conversion circuit 300 is not a big problem even if a reference voltage and a reference current that are not band-limited are supplied, but noise mixed in the pixel source follower is not output to the pixel output. Propagation greatly affects the image quality.
  • the start-up delay of the constant voltage circuit itself is large, and the delay until the operation of the pixel source follower is large.
  • the start-up of the voltage conversion circuit 300 and the low-band constant-voltage output can be performed in parallel, and the start-up time such as several tens to several hundreds of ms that is the same as the start-up time of the voltage conversion circuit 300 Can be given to. Therefore, sufficient band limitation can be performed on the low-band constant voltage output, and noise can be greatly reduced without degrading the startup time as the solid-state imaging device 3.
  • the solid-state imaging device 3 includes the multi-band constant voltage circuit 400, and at least the high-band constant voltage that is the second voltage generated by the multi-band constant voltage circuit 400 is at least a voltage. Used in the conversion circuit 300.
  • the solid-state imaging device 3 uses at least the read current source 50 with the low-band constant voltage that is the first voltage generated by the multi-band constant voltage circuit 400. As a result, it is possible to achieve both a start-up time as the solid-state imaging device 3 and a low noise and high dynamic range.
  • the solid-state imaging device 4 uses a multi-band constant current circuit 407 instead of the low-band constant current circuit and the high-band constant current circuit with respect to the solid-state imaging device 2 according to the second embodiment. It is different in that. Also, the gate input to the read current source 50 is not a reference voltage, the read current source 50 forms a mirror circuit, and the reference current becomes an input to the read current source 50.
  • FIG. 12 is a block diagram showing a configuration of the solid-state imaging device 4 according to Embodiment 4 of the present invention.
  • FIG. 13 is a block diagram showing a configuration of a multiband constant current circuit 407 included in the solid-state imaging device 4 according to Embodiment 4 of the present invention.
  • the same elements as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted here.
  • the solid-state imaging device 4 has the same configuration as the solid-state imaging device 2 according to the second embodiment except for the multi-band constant current circuit 407.
  • the multi-band constant current circuit 407 is a VI conversion circuit that is a second voltage-current conversion circuit for a single output of a general bandgap reference circuit 105 that is a fourth constant voltage circuit. 500, a high-band constant current output in which the current obtained by 500 is output without band limitation, and a low-band constant current in which the current obtained by the VI conversion circuit 500, which is the first voltage-current conversion circuit, is band-limited by the band-limiting capacitor 101. And a third constant current circuit having an output. That is, the multi-band constant current circuit 407 includes a low-band constant current circuit 107 that is a first constant current circuit and a high-band constant current circuit 207 that is a second constant current circuit.
  • the band gap reference circuit 105 which is a common component with the high-band constant current circuit 207 is shared, and the constant current from the low-band constant current circuit and the constant current from the high-band constant current circuit are output independently.
  • the connection method between the VI conversion circuit 500 and the band limiting capacitor 101 exemplified in this embodiment is an example, and the configuration of the VI conversion circuit 500 is not limited as long as the circuit has a VI conversion function. For example, a simple source grounding circuit may be used. Further, if the band of the output current of the VI conversion circuit 500 is limited, the band limiting method of the VI conversion circuit is not limited.
  • the filter circuit may be configured or connected in the VI conversion circuit instead of the connection of the band limiting capacitor. Further, the number of current outputs is not limited, and there may be an arbitrary number of current outputs of two or more.
  • the high-band constant current output has a large amount of noise because the band is not limited, but the startup time as a constant-current circuit is fast.
  • the low-band constant current output is band-limited, so the amount of noise is small and can be used as a low-noise circuit.
  • the startup time as a constant-current circuit is Slow.
  • the band limiting capacitor 101 it is preferable to use an external capacitor in order to greatly limit the band. However, it is not always necessary to use an external capacitor. The use of this capacity does not depart from the purpose and scope of the present invention.
  • the band gap circuit is exemplified. However, as long as the voltage source circuit generates voltage, for example, a voltage generation circuit using resistance voltage division does not depart from the object and scope of the present invention. .
  • the example in which the band limiting capacitor, which is the third capacitor element is connected only to the VI conversion circuit that outputs the low-band constant current output. However, the high-band constant current is not affected by the start-up time.
  • the band limiting capacity connected to the VI conversion circuit that outputs the low-band constant current output is set to be larger than the band limiting capacity connected to the VI conversion circuit that outputs the high-band constant current output.
  • the band is limited by configuring or connecting the filter circuit in the VI conversion circuit, not only the third filter circuit is connected to the VI conversion circuit that outputs a low-band constant current output, but also the startup.
  • a fourth filter circuit may be connected to a VI conversion circuit that outputs a high-band constant current output within a range that does not affect time. Also in this case, the low-band constant current output band is set lower than the high-band constant current output band.
  • the voltage conversion circuit 300 requires a start-up time, and normal imaging cannot be performed until the voltage conversion circuit 300 is started. Therefore, the start-up delay of the voltage conversion circuit 300 is the start-up of the solid-state imaging device 4. It is necessary to limit to a range that does not affect the time constraint.
  • the high-band constant current output of the multi-band constant current circuit 407 is used to supply the reference current to the voltage conversion circuit 300, the start-up delay of the constant current circuit itself is small, and the start-up of the voltage conversion circuit 300 is Compared with the case where a low-band constant current output is used, the speed is increased.
  • the startup of the voltage conversion circuit 300 is accelerated, it is possible to reduce the inrush current at the time of switching and to reduce the switching frequency, and to reduce the switching noise itself generated by the booster circuit. Noise can be reduced.
  • the generated voltage of the voltage conversion circuit 300 is not a big problem even if a reference voltage and a reference current that are not band-limited are supplied, but noise mixed in the pixel source follower is not output to the pixel output. Propagation greatly affects the image quality.
  • the amount of noise of the reference current is suppressed, and the noise of the pixel output is reduced.
  • the startup delay of the constant current circuit itself is large, and the delay until the operation of the pixel source follower is large.
  • the startup of the voltage conversion circuit 300 and the low-band constant current output can be operated in parallel. Can be given. Therefore, sufficient band limitation can be performed on the low-band constant current output, and noise can be greatly reduced without degrading the startup time as the solid-state imaging device 4.
  • the solid-state imaging device 4 includes the multi-band constant current circuit 407, and at least the high-band constant current that is the second current generated by the multi-band constant current circuit 407 is at least a voltage. Used in the conversion circuit 300. Further, the solid-state imaging device 4 uses the low-band constant current that is the first current generated by the multi-band constant voltage circuit 400 for at least the read current source 50. As a result, it is possible to achieve both a start-up time as the solid-state imaging device 4 and a reduction in noise and a high dynamic range.
  • the pixel output when the source potential of the read current source 50 fluctuates due to noise or the like can be obtained. Noise propagation is suppressed.
  • the solid-state imaging device according to the present invention is not limited to the above-described embodiments.
  • each unit pixel 5 has a structure having one photodiode, a transfer transistor, a floating diffusion, a reset transistor, and an amplification transistor, so-called one-pixel one-cell structure.
  • the solid-state imaging device of the present invention includes a plurality of photodiodes in addition to the one-pixel / one-cell structure, and further shares any one or all of the floating diffusion, the reset transistor, and the amplification transistor in the unit cell.
  • a structure, a so-called multi-pixel 1-cell structure can be used.
  • the solid-state imaging devices 1 to 4 of the present invention may have a structure in which the photodiode is formed on the surface of the semiconductor substrate, that is, on the same side as the surface on which the gate terminal and the wiring of the transistor are formed.
  • a so-called back-illuminated image sensor (back-illuminated solid-state imaging device) structure in which the photodiode is formed on the back surface side of the semiconductor substrate, that is, the surface on which the gate terminal and wiring of the transistor are formed. You can also.
  • the solid-state imaging device is useful as a digital still camera, a digital video camera, and the like that require high image quality such as high-speed startup, low noise, and high dynamic range.
  • Solid-state imaging device 5 1003 Unit pixel 10, 1010 Pixel array 30, 1030 Photodiode 31, 1031 Transfer transistor 32, 1032 Reset transistor 33, 1033 Select transistor 34, 1034 Read transistor 40 Vertical scan Circuit 41, 1041 Transfer transistor control line 42, 1042 Reset transistor control line 43, 1043 Selection transistor control line 44 Decoder 45, 1045 Vertical signal line 47 Vertical driver 50, 1050 Read current source 55, 1062 Horizontal signal line 56 Column ADC 57 Reference signal generation unit 60 Horizontal scanning circuit 61, 1061 Horizontal selection transistor 65 Horizontal control line 67 Output circuit 70 Timing control unit 100 Low-band constant voltage circuit 101, 705, 706 Band-limiting capacitor 102 Band-limiting resistor 103 Low-pass filter 105 Band gap Reference circuit 107 Low-band constant current circuit 200 High-band constant voltage circuit 207 High-band constant current circuit 300 Voltage conversion circuit 301 Comparison circuit 400 Multi-band constant voltage circuit 407 Multi-band constant current circuit 415 Voltage comparison unit 416 Count unit 418 Memory unit 500 VI conversion circuit 701, 702

Abstract

Disclosed is a solid state imaging device provided with a function for simultaneously allowing a faster start up, lower noise, and higher dynamic range. The solid state imaging device (1) is provided with: multiple unit pixels (5) arranged in a matrix; a vertical signal line (45) and a read-out current source (50) provided in each pixel row; a voltage conversion circuit (300) for generating a voltage other than the power source voltage; a vertical scanning circuit (40) for driving, with the voltage generated by the voltage conversion circuit (300), the unit pixels (5) in order by row, and reading out the signal voltage for each pixel via the vertical signal lines (45) and the read-out current sources (50); a low bandwidth constant voltage circuit (100) for supplying a first voltage to the read-out current source (50); and a high bandwidth constant voltage circuit (200) for supplying to the voltage conversion circuit (300) a second voltage having a frequency component higher than that of the first voltage.

Description

固体撮像装置Solid-state imaging device
 本発明は、固体撮像装置に関し、特に、起動高速化と低ノイズ化及び高ダイナミックレンジ化とを両立させる機能を備えた固体撮像装置に関する。 The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device having a function for achieving both high-speed startup, low noise, and high dynamic range.
 光を電気信号に変換する固体撮像装置は、デジタルビデオカメラ、デジタルスチルカメラ及びファクシミリ等の種々の機器に使用されている。固体撮像装置として、CCD(Charge Coupled Device)イメージセンサ、及びCMOS(Complementary Metal-Oxide Semiconductor)イメージセンサが知られている。 Solid-state imaging devices that convert light into electrical signals are used in various devices such as digital video cameras, digital still cameras, and facsimiles. As a solid-state imaging device, a CCD (Charge Coupled Device) image sensor and a CMOS (Complementary Metal-Oxide Semiconductor) image sensor are known.
 従来のCMOSイメージセンサとして、電源電圧とは異なる電圧を生成する電圧変換回路を備え、当該電圧変換回路による生成電圧を用いて画素を駆動することで性能を向上させた固体撮像装置が知られている。 As a conventional CMOS image sensor, a solid-state imaging device having a voltage conversion circuit that generates a voltage different from a power supply voltage and driving a pixel using a voltage generated by the voltage conversion circuit is known. Yes.
 以下、電圧変換回路として昇圧回路を備える特許文献1に記載された従来の固体撮像装置の構成について、図12を参照して説明する。 Hereinafter, a configuration of a conventional solid-state imaging device described in Patent Document 1 including a booster circuit as a voltage conversion circuit will be described with reference to FIG.
 図14は、特許文献1に示された従来の固体撮像装置1000の構成を示すブロック図である。 FIG. 14 is a block diagram illustrating a configuration of a conventional solid-state imaging device 1000 disclosed in Patent Document 1. In FIG.
 固体撮像装置1000は、入射光量に応じた信号を出力する受光素子を含む単位画素1003が2次元マトリクス状に複数配列された画素アレイ1010を有し、各単位画素1003からは画素信号が出力される。単位画素1003は、いわゆる4トランジスタ型の画素セルであり、フォトダイオード1030と、転送トランジスタ1031と、リセットトランジスタ1032と、選択トランジスタ1033と、読み出しトランジスタ1034と、を備える。各単位画素1003中の読み出しトランジスタ1034は、画素列毎に設けられた読み出し電流源1050によって、ソースフォロア回路(以降、画素ソースフォロアと呼ぶ)を構成している。これにより、画素信号は、画素ソースフォロア回路によって、垂直信号線1045を介して読み出される。 The solid-state imaging device 1000 includes a pixel array 1010 in which a plurality of unit pixels 1003 including a light receiving element that outputs a signal corresponding to the amount of incident light is arranged in a two-dimensional matrix, and a pixel signal is output from each unit pixel 1003. The The unit pixel 1003 is a so-called four-transistor pixel cell, and includes a photodiode 1030, a transfer transistor 1031, a reset transistor 1032, a selection transistor 1033, and a reading transistor 1034. The read transistor 1034 in each unit pixel 1003 forms a source follower circuit (hereinafter referred to as a pixel source follower) by a read current source 1050 provided for each pixel column. Thus, the pixel signal is read out through the vertical signal line 1045 by the pixel source follower circuit.
 固体撮像装置1000は、さらに、昇圧回路1100と、垂直走査部1040と、水平走査部1060と、水平選択トランジスタ1061と、アンプ1069と、AD変換部1080と、信号処理部1090とを備える。垂直走査部1040は、選択した行の各トランジスタ1031~1033を駆動することで、フォトダイオード1030のリセットと画素信号の読み出しとを行う。読み出された画素信号は、水平走査部1060が水平選択トランジスタ1061を列順次に選択することにより、水平信号線1062を介してアンプ1069へ順次供給される。アンプ1069へ読み出された画素信号は、AD変換部1080によって、AD変換され、信号処理部1090によって、信号処理がされた後に、固体撮像装置1000から外部へ出力される。 The solid-state imaging device 1000 further includes a booster circuit 1100, a vertical scanning unit 1040, a horizontal scanning unit 1060, a horizontal selection transistor 1061, an amplifier 1069, an AD conversion unit 1080, and a signal processing unit 1090. The vertical scanning unit 1040 drives the transistors 1031 to 1033 in the selected row, thereby resetting the photodiode 1030 and reading out the pixel signal. The read pixel signals are sequentially supplied to the amplifier 1069 via the horizontal signal line 1062 when the horizontal scanning unit 1060 selects the horizontal selection transistors 1061 in the column order. The pixel signal read to the amplifier 1069 is AD-converted by the AD conversion unit 1080, subjected to signal processing by the signal processing unit 1090, and then output from the solid-state imaging device 1000 to the outside.
 昇圧回路1100は、チャージポンプ等の電圧変換動作によって、入力される電源電圧以上の昇圧電圧を生成し、垂直走査部1040へ昇圧電圧を供給する。垂直走査部1040は、上記昇圧電圧によって、転送トランジスタ制御線1041、リセットトランジスタ制御線1042、選択トランジスタ制御線1043を介して、それぞれ、転送トランジスタ1031と、リセットトランジスタ1032と、選択トランジスタ1033とを駆動する。 The booster circuit 1100 generates a boosted voltage higher than the input power supply voltage by a voltage conversion operation such as a charge pump, and supplies the boosted voltage to the vertical scanning unit 1040. The vertical scanning unit 1040 drives the transfer transistor 1031, the reset transistor 1032, and the selection transistor 1033 through the transfer transistor control line 1041, the reset transistor control line 1042, and the selection transistor control line 1043, respectively, using the boosted voltage. To do.
 ここで、垂直走査部1040が、転送トランジスタ1031と、リセットトランジスタ1032と、選択トランジスタ1033とを電源電圧で駆動した場合には、各トランジスタのソース電位は電源電圧から閾値電圧分低下した電圧に抑制される。これにより、転送トランジスタによるフォトダイオード電荷の読み出し量と、選択トランジスタによるソースフォロア回路動作レンジと、リセットトランジスタによるソースフォロア回路ゲート印加電圧とが抑制されることになる。その結果、扱える信号量が減少するため、ダイナミックレンジが減少する。一方で、垂直走査部1040が、転送トランジスタ1031と、リセットトランジスタ1032と、選択トランジスタ1033とを、昇圧回路1100の供給する昇圧電圧で駆動した場合には、各トランジスタはソース電位を電源電圧として動作可能となる。その結果、フォトダイオード電荷の十分な読み出しと、ソースフォロア回路の電源電圧までの出力と、ソースフォロア回路ゲートへの電源電圧そのものの印加とが可能となり、扱える信号量が増加するため、高ダイナミックレンジ化が可能となる。 Here, when the vertical scanning unit 1040 drives the transfer transistor 1031, the reset transistor 1032, and the selection transistor 1033 with the power supply voltage, the source potential of each transistor is suppressed to a voltage that is lower than the power supply voltage by the threshold voltage. Is done. Thereby, the readout amount of the photodiode charge by the transfer transistor, the source follower circuit operation range by the selection transistor, and the source follower circuit gate applied voltage by the reset transistor are suppressed. As a result, the amount of signals that can be handled is reduced, so that the dynamic range is reduced. On the other hand, when the vertical scanning unit 1040 drives the transfer transistor 1031, the reset transistor 1032, and the selection transistor 1033 with the boosted voltage supplied from the booster circuit 1100, each transistor operates using the source potential as the power supply voltage. It becomes possible. As a result, sufficient readout of the photodiode charge, output up to the power supply voltage of the source follower circuit, and application of the power supply voltage itself to the source follower circuit gate are possible, and the amount of signals that can be handled increases, so a high dynamic range Can be realized.
 また、図14における読み出し電流源1050への入力電圧をはじめとして、昇圧回路1100の基準電圧等に含まれるアンプ用の電流源など、固体撮像装置1000には、定電圧または定電流入力を必要とする回路が数多く存在する。特に、読み出し電流源1050の基準電圧に混入したノイズは、全列に共通に影響していわゆる横線ノイズとなるため、画質への影響は非常に大きい。読み出し電流源1050への入力電圧や昇圧回路1100の基準電圧等に含まれるアンプ用の電流源のノイズ対策として、ローパスフィルタを設け、ノイズ帯域制限を行うことで、ノイズを除去し、出力される定電圧信号を低ノイズ化することができることが知られている。 Further, the solid-state imaging device 1000 requires a constant voltage or a constant current input, such as an input current to the read current source 1050 in FIG. 14 and a current source for an amplifier included in the reference voltage of the booster circuit 1100 and the like. There are many circuits that do this. In particular, noise mixed in the reference voltage of the read current source 1050 affects all the columns in common and becomes so-called horizontal noise, so the influence on the image quality is very large. As a noise countermeasure for the amplifier current source included in the input voltage to the read current source 1050, the reference voltage of the booster circuit 1100, etc., a low-pass filter is provided and noise band is limited to output the noise. It is known that the constant voltage signal can be reduced in noise.
特開2000-224495号公報JP 2000-224495 A
 前述した従来の固体撮像装置においては、昇圧回路の使用によって、高ダイナミックレンジ化が可能となり、ローパスフィルタからなる低ノイズ回路の使用によって、低ノイズ化が可能となる。 In the above-described conventional solid-state imaging device, a high dynamic range can be achieved by using a booster circuit, and a low noise can be achieved by using a low-noise circuit including a low-pass filter.
 しかしながら、昇圧回路は、昇圧回路を起動してから、正常な昇圧電圧値が出力されるまでに、時間を要する回路であって、固体撮像装置としての起動時間として許容可能なレベルまで、昇圧回路の起動時間を短縮する必要がある。その一方で、低ノイズ回路の使用は、回路自体の帯域を制限し、ローパスフィルタの立ち上がり遅延などによって、定電圧及び定電流の供給自体が遅延することになる。したがって、例えば、低ノイズ回路から定電圧が入力された昇圧回路は、定電圧が正常に入力されるまで正常動作できないため、低ノイズ化の代償として、さらに起動が遅れることとなる。さらに、低ノイズ回路によるノイズ削減効果をあげるため、帯域を大きく制限すればするほど、ローパスフィルタを構成する容量を大きくしなければならず、起動は遅れることとなる。 However, the booster circuit is a circuit that requires time until the normal boosted voltage value is output after the booster circuit is started up, and the booster circuit reaches a level acceptable as the start-up time as the solid-state imaging device. It is necessary to shorten the startup time. On the other hand, the use of a low noise circuit limits the bandwidth of the circuit itself and delays the supply of constant voltage and constant current due to the rise delay of the low pass filter. Therefore, for example, a booster circuit to which a constant voltage is input from a low noise circuit cannot operate normally until the constant voltage is normally input. Therefore, the start-up is further delayed as a price for reducing noise. Furthermore, in order to increase the noise reduction effect by the low noise circuit, the larger the band is, the larger the capacity constituting the low-pass filter must be, and the start-up will be delayed.
 上述した昇圧回路及び低ノイズ回路に起因して起動時間が長くなるという弊害の中で、近年の固体撮像装置における画質性能向上の要求に応えるため、および、画素の微細化による単位画素セルの感度低下に反してSNを向上させるため、ノイズを制限する必要性はますます強くなっている。このため、帯域制限によるノイズ除去においては、帯域制限をより低周波数まで行うこと、すなわち、ローパスフィルタのノイズ除去下限周波数を決定するカットオフ周波数を、より低周波数に設定することで、より大きくノイズを削減することが必要となっている。 In response to the recent demand for improvement in image quality performance in solid-state imaging devices and the sensitivity of unit pixel cells due to pixel miniaturization, in the adverse effect of long startup time due to the booster circuit and low noise circuit described above In order to improve SN against the decline, the need to limit noise is becoming increasingly strong. For this reason, in noise removal by band limitation, the band limitation is performed to a lower frequency, that is, the cutoff frequency that determines the noise removal lower limit frequency of the low-pass filter is set to a lower frequency, thereby increasing the noise. It is necessary to reduce.
 このため、昇圧回路の起動遅延は、増加の一途を辿っている。その解決のためには、昇圧回路のスイッチサイズを増大させることでスイッチ経路の抵抗を下げる、あるいはスイッチング周波数を増加させるといった方法によって、駆動能力を向上させて、起動速度をあげることが挙げられる。しかし、スイッチ経路の低抵抗化は、スイッチング時の突入電流を増加させ、スイッチング周波数の増加は、スイッチング頻度を増加させる。その結果、昇圧回路の発するスイッチングノイズ自体も増大することとなり、低ノイズ回路による低ノイズ化の効果を損ねることとなる。起動時間の遅延、スイッチングノイズの増大にもかかわらず、高ダイナミックレンジの実現には、昇圧回路は必須であり、昇圧回路を使用しないという選択はできない。 For this reason, the startup delay of the booster circuit is steadily increasing. In order to solve the problem, it is possible to improve the driving capability and increase the starting speed by increasing the switch size of the booster circuit to reduce the resistance of the switch path or increasing the switching frequency. However, lowering the resistance of the switch path increases the inrush current during switching, and increasing the switching frequency increases the switching frequency. As a result, the switching noise itself generated by the booster circuit also increases, and the noise reduction effect of the low noise circuit is impaired. Despite start-up time delay and switching noise increase, a booster circuit is indispensable for realizing a high dynamic range, and it is impossible to select not to use a booster circuit.
 以上述べたように、従来の固体撮像装置においては、起動高速化と、低ノイズ化及び高ダイナミックレンジ化との両立が困難である、といった課題が生じている。しかし、ノイズ、起動時間及びダイナミックレンジの関係についての課題も知見も明示されていない。 As described above, the conventional solid-state imaging device has a problem that it is difficult to achieve both high-speed startup, low noise, and high dynamic range. However, there are no issues or knowledge about the relationship between noise, start-up time and dynamic range.
 上記課題に鑑み、本発明は、起動高速化と、低ノイズ化及び高ダイナミックレンジ化とを両立させる機能を備えた固体撮像装置を提供することを目的とする。 In view of the above problems, an object of the present invention is to provide a solid-state imaging device having a function of achieving both high-speed startup, low noise, and high dynamic range.
 上記の課題を解決するために、本発明の一態様に係る固体撮像装置は、行列状に配置され、光を信号電圧に変換する複数の画素と、画素列ごとに設けられた垂直信号線と、画素列ごとに設けられ、第1電圧が供給されることにより前記垂直信号線に前記信号電圧を読み出すための電流を供給する電流源回路と、第2電圧が供給されることにより電源電圧とは異なる電圧を生成する電圧変換回路と、前記電圧変換回路で生成された電圧を用いて前記複数の画素を行順次に駆動し、対応する行内の画素から前記垂直信号線及び前記電流源回路を介して前記信号電圧を読み出す垂直走査回路と、前記電流源回路に前記第2電圧よりも高周波成分が除去された前記第1電圧を供給する第1の定電圧回路と、前記電圧変換回路に、前記第2電圧を供給する第2の定電圧回路とを備えることを特徴とする。 In order to solve the above problems, a solid-state imaging device according to one embodiment of the present invention includes a plurality of pixels that are arranged in a matrix and convert light into a signal voltage, and a vertical signal line provided for each pixel column. A current source circuit that is provided for each pixel column and supplies a current for reading the signal voltage to the vertical signal line by being supplied with a first voltage; and a power supply voltage by being supplied with a second voltage. Uses a voltage conversion circuit for generating different voltages, drives the plurality of pixels in a row sequence using the voltage generated by the voltage conversion circuit, and connects the vertical signal line and the current source circuit from the pixels in the corresponding row. A vertical scanning circuit that reads out the signal voltage via the first voltage circuit, a first constant voltage circuit that supplies the current source circuit with the first voltage from which a higher frequency component is removed than the second voltage, and the voltage conversion circuit. Supply the second voltage Characterized in that it comprises a second constant voltage circuit that.
 この構成により、垂直走査回路は、各画素を駆動するための駆動電圧を、電源電圧ではなく、電圧変換回路の供給する電圧で駆動することが可能となる。よって、各画素の有するトランジスタのソース電位は電源電圧から閾値電圧分低下した電圧に抑制されることなく、電源電圧まで動作可能となる。その結果、信号電圧を十分反映した画素信号を各画素から出力できるため、高ダイナミックレンジ化が可能となる。 With this configuration, the vertical scanning circuit can drive the driving voltage for driving each pixel not by the power supply voltage but by the voltage supplied by the voltage conversion circuit. Accordingly, the source potential of the transistor included in each pixel can be operated up to the power supply voltage without being suppressed to a voltage lower than the power supply voltage by the threshold voltage. As a result, since a pixel signal that sufficiently reflects the signal voltage can be output from each pixel, a high dynamic range can be achieved.
 また、高帯域を含む第2電圧を出力する第2の定電圧回路は、帯域制限が行われていないためノイズ量は大きいが、定電圧回路としての起動時間は高速となる。一方、低帯域の第1電圧を出力する第1の定電圧回路は、帯域制限を行うためノイズ量は小さいがローパスフィルタを構成する抵抗や容量により起動時間が低速となる。この点、電圧変換回路の生成電圧は、画素トランジスタのスイッチ電圧として論理動作目的で供給されるため生成電圧自体のノイズが画素出力に伝播する寄与度は低いので、帯域制限を行っていない基準電圧を供給しても画質として大きな問題とはならない。 Also, the second constant voltage circuit that outputs the second voltage including the high band has a large amount of noise because the band is not limited, but the startup time as the constant voltage circuit is fast. On the other hand, the first constant voltage circuit that outputs the first voltage in the low band has a small amount of noise because the band is limited, but the start-up time is slow due to the resistors and capacitors that constitute the low-pass filter. In this regard, the generated voltage of the voltage conversion circuit is supplied for the purpose of logical operation as the switch voltage of the pixel transistor, so the contribution of noise of the generated voltage itself to the pixel output is low, so the reference voltage without band limitation Is not a big problem for the image quality.
 一方で、各画素の信号電圧を読み出すための電流源回路に混入したノイズは、画素出力に大きく伝播し、画質に大きく影響する。特に、電流源回路の基準電圧に混入したノイズは、全列に共通に影響するため、いわゆる横線ノイズとなり、画質への影響は非常に大きい。 On the other hand, noise mixed in the current source circuit for reading out the signal voltage of each pixel is largely propagated to the pixel output and greatly affects the image quality. In particular, noise mixed in the reference voltage of the current source circuit affects all the columns in common, so that it becomes so-called horizontal noise, and the influence on the image quality is very large.
 本構成により、電流源回路への基準電圧供給に、低帯域の第1電圧を出力する第1の定電圧回路を用いることで、基準電圧のノイズ量を抑制し画素出力の低ノイズ化がなされる。帯域制限の影響により、定電圧回路自体の起動遅延自体が大きくなるので、信号電圧の読み出し動作を開始するまでの遅延は大きくなるが、電圧変換回路の起動までに、読み出し動作が起動していれば、固体撮像装置としての起動時間には影響しない。この点、電圧変換回路の起動と、低帯域である第1の定電圧回路とは並列動作が可能である。したがって、電圧変換回路の起動時間を、読み出し動作起動時間に充てることができるため、第1の定電圧回路に対して、十分な帯域制限を行うことが可能となる。よって、固体撮像装置としての起動時間を劣化させることなく、低ノイズ化及び高ダイナミックレンジ化を実現することができる。 With this configuration, by using the first constant voltage circuit that outputs the first voltage in the low band for supplying the reference voltage to the current source circuit, the noise amount of the reference voltage is suppressed and the noise of the pixel output is reduced. The The start-up delay of the constant voltage circuit itself increases due to the band limitation, so the delay before starting the signal voltage read operation increases, but the read operation must be started before the voltage conversion circuit starts up. For example, it does not affect the startup time of the solid-state imaging device. In this respect, the activation of the voltage conversion circuit and the first constant voltage circuit having a low bandwidth can be operated in parallel. Therefore, since the start time of the voltage conversion circuit can be used as the read operation start time, it is possible to perform sufficient band limitation on the first constant voltage circuit. Therefore, it is possible to realize low noise and high dynamic range without degrading the startup time as a solid-state imaging device.
 また、固体撮像装置は、さらに、前記第1の定電圧回路に接続される第1の容量素子と、前記第2の定電圧回路に接続され、前記第1の容量素子と容量値が異なる第2の容量素子とを備えてもよい。 The solid-state imaging device is further connected to the first capacitor element connected to the first constant voltage circuit and the second constant voltage circuit, and has a capacitance value different from that of the first capacitor element. 2 capacitive elements.
 これにより、定電圧回路のインピーダンスを抵抗とし、定電圧回路に接続された容量値の異なる容量素子とで帯域特性の異なるローパスフィルタが構成される。この場合、抵抗素子を不要とできる。よって、電流源回路に接続される第1の定電圧回路の出力電圧の帯域制限度合いと、電圧変換回路に接続される第2の定電圧回路の出力電圧の帯域制限度合いとを、ノイズ除去及び遅延時間短縮化の必要性に応じて異ならせることが可能となる。 Thus, a low-pass filter having a different band characteristic is formed by a capacitor having a different capacitance value connected to the constant voltage circuit using the impedance of the constant voltage circuit as a resistor. In this case, a resistance element can be dispensed with. Therefore, the band limitation degree of the output voltage of the first constant voltage circuit connected to the current source circuit and the band limitation degree of the output voltage of the second constant voltage circuit connected to the voltage conversion circuit are reduced by noise and It becomes possible to make it different according to the necessity of shortening the delay time.
 また、固体撮像装置は、さらに、前記第1の定電圧回路に接続される第1のフィルタ回路と、前記第2の定電圧回路に接続され、前記第1のフィルタ回路よりも高い通過帯域を有する第2のフィルタ回路とを備えてもよい。 Further, the solid-state imaging device is further connected to the first filter circuit connected to the first constant voltage circuit and to the second constant voltage circuit, and has a higher pass band than the first filter circuit. And a second filter circuit.
 これにより、電流源回路に接続される第1の定電圧回路の出力電圧の帯域制限度合いを、電圧変換回路に接続される第2の定電圧回路の出力電圧の帯域制限度合いより高く設定できる。よって、遅延時間を劣化させることなく電流源回路におけるノイズ除去を強化させることが可能となる。 Thereby, the band restriction degree of the output voltage of the first constant voltage circuit connected to the current source circuit can be set higher than the band restriction degree of the output voltage of the second constant voltage circuit connected to the voltage conversion circuit. Therefore, it is possible to enhance noise removal in the current source circuit without deteriorating the delay time.
 また、前記第1の定電圧回路及び前記第2の定電圧回路の一方は、容量素子が接続されており、前記第1の定電圧回路及び前記第2の定電圧回路の他方は、容量素子が接続されていなくてもよい。 Further, one of the first constant voltage circuit and the second constant voltage circuit is connected to a capacitive element, and the other of the first constant voltage circuit and the second constant voltage circuit is a capacitive element. May not be connected.
 これにより、回路部品点数の低減に寄与しつつ、第1の定電圧回路の出力電圧の帯域制限度合いと、第2の定電圧回路の出力電圧の帯域制限度合いとを、ノイズ除去及び遅延時間短縮化の必要性に応じて異ならせることが可能となる。 This contributes to the reduction in the number of circuit components, while reducing the band limitation of the output voltage of the first constant voltage circuit and the band limitation of the output voltage of the second constant voltage circuit, and reducing the delay time. It becomes possible to make it different according to the necessity of conversion.
 また、前記第1の定電圧回路には、フィルタ回路が接続されており、前記第2の定電圧回路には、フィルタ回路が接続されていなくてもよい。 Further, a filter circuit may be connected to the first constant voltage circuit, and a filter circuit may not be connected to the second constant voltage circuit.
 これにより、回路部品点数の低減に寄与しつつ、遅延時間を劣化させることなく電流源回路におけるノイズ除去を強化させることが可能となる。 This makes it possible to enhance noise removal in the current source circuit without degrading the delay time while contributing to the reduction in the number of circuit components.
 また、前記第1の定電圧回路と前記第2の定電圧回路とは、第3の定電圧回路に含まれ、前記第3の定電圧回路は、前記第1の定電圧回路の構成要素と前記第2の定電圧回路の構成要素とを一部共用し、前記第1の定電圧回路からの前記第1電圧と前記第2の定電圧回路からの前記第2電圧とを独立に出力してもよい。 In addition, the first constant voltage circuit and the second constant voltage circuit are included in a third constant voltage circuit, and the third constant voltage circuit includes components of the first constant voltage circuit and A part of the components of the second constant voltage circuit is shared, and the first voltage from the first constant voltage circuit and the second voltage from the second constant voltage circuit are independently output. May be.
 これにより、電圧変換回路への定電圧と電流源回路への定電圧とを、単一の低電圧回路から供給することが可能となる。例えば、電圧変換回路への定電圧は、第3の定電圧回路の有する定電圧回路ユニットを介して出力させ、電流源回路への定電圧は、第3の定電圧回路の有する定電圧回路ユニットと帯域制限抵抗とを介して出力させる。よって、回路規模の縮小化を実現しつつ、起動高速化と、低ノイズ化及び高ダイナミックレンジ化とを両立させることが可能となる。 This makes it possible to supply a constant voltage to the voltage conversion circuit and a constant voltage to the current source circuit from a single low voltage circuit. For example, the constant voltage to the voltage conversion circuit is output via the constant voltage circuit unit included in the third constant voltage circuit, and the constant voltage to the current source circuit is output from the constant voltage circuit unit included in the third constant voltage circuit. And output through a band limiting resistor. Therefore, it is possible to achieve both high-speed startup, low noise, and high dynamic range while realizing a reduction in circuit scale.
 また、上記の課題を解決するために、本発明の一態様に係る固体撮像装置は、行列状に配置され、光を信号電圧に変換する複数の画素と、画素列ごとに設けられた複数の垂直信号線と、画素列ごとに設けられ、第1電流が供給されることにより前記垂直信号線に前記信号電圧を読み出すための電流を供給する電流源回路と、第2電流が供給されることにより電源電圧とは異なる電圧を生成する電圧変換回路と、前記電圧変換回路で生成された電圧を用いて前記複数の画素を行順次に駆動し、対応する行内の画素から前記垂直信号線及び前記電流源回路を介して前記信号電圧を読み出す垂直走査回路と、前記電流源回路に前記第2電流よりも高周波成分が除去された前記第1電流を供給する第1の定電流回路と、前記電圧変換回路に、前記第2電流を供給する第2の定電流回路とを備えることを特徴とする。 In order to solve the above problems, a solid-state imaging device according to one embodiment of the present invention includes a plurality of pixels arranged in a matrix and converting light into a signal voltage, and a plurality of pixels provided for each pixel column. A vertical signal line, a current source circuit that is provided for each pixel column, supplies a current for reading the signal voltage to the vertical signal line by supplying a first current, and a second current is supplied. A voltage conversion circuit that generates a voltage different from the power supply voltage, and the plurality of pixels are driven in a row sequence using the voltage generated by the voltage conversion circuit, and the vertical signal lines and the pixels from the pixels in the corresponding row are driven. A vertical scanning circuit that reads out the signal voltage via a current source circuit; a first constant current circuit that supplies the first current from which a high-frequency component is removed from the second current to the current source circuit; and the voltage In the conversion circuit, the first Characterized in that it comprises a second constant current circuit for supplying a current.
 この構成により上記同様、信号電圧を十分反映した画素信号を各画素から出力できるため、高ダイナミックレンジ化が可能となる。 With this configuration, as described above, since a pixel signal that sufficiently reflects the signal voltage can be output from each pixel, a high dynamic range can be achieved.
 また、第2の定電流回路は、ノイズ量は大きいが起動時間は高速となる。一方、第1の定電流回路は、ノイズ量は小さいが起動時間が低速となる。この点、電圧変換回路の生成電圧自体のノイズが画素出力に伝播する寄与度は低いので、帯域制限を行っていない基準電流を供給しても画質として大きな問題とはならない。 Also, the second constant current circuit has a large amount of noise, but the startup time is fast. On the other hand, the first constant current circuit has a small amount of noise but a low startup time. In this regard, since the contribution of noise generated by the voltage conversion circuit itself to the pixel output is low, even if a reference current that is not band-limited is supplied, it does not pose a significant problem in image quality.
 一方で、各画素の信号電圧を読み出すための電流源回路に混入したノイズは、画素出力に大きく伝播し、画質に大きく影響する。特に、電流源回路の基準電流に混入したノイズは、全列に共通に影響するため、いわゆる横線ノイズとなり、画質への影響は非常に大きい。 On the other hand, noise mixed in the current source circuit for reading out the signal voltage of each pixel is largely propagated to the pixel output and greatly affects the image quality. In particular, noise mixed in the reference current of the current source circuit affects all columns in common, so that it becomes so-called horizontal noise, and the influence on image quality is very large.
 本構成により、電流源回路への基準電流供給に、低帯域の第1電流を出力する第1の定電流回路を用いることで、基準電流のノイズ量を抑制し画素出力の低ノイズ化がなされる。帯域制限の影響により、定電流回路自体の起動遅延自体が大きくなるので、信号電圧の読み出し動作を開始するまでの遅延は大きくなるが、電圧変換回路の起動までに、読み出し動作が起動していれば、固体撮像装置としての起動時間には影響しない。この点、電圧変換回路の起動と、低帯域である第1の定電流回路とは並列動作が可能である。したがって、電圧変換回路の起動時間を、読み出し動作起動時間に充てることができるため、第1の定電流回路に対して、十分な帯域制限を行うことが可能となる。よって、固体撮像装置としての起動時間を劣化させることなく、低ノイズ化及び高ダイナミックレンジ化を実現することができる。 With this configuration, by using the first constant current circuit that outputs the first current in the low band for supplying the reference current to the current source circuit, the noise amount of the reference current is suppressed and the noise of the pixel output is reduced. The Due to the band limitation, the startup delay of the constant current circuit itself increases, so the delay until the signal voltage read operation starts increases, but the read operation must be started before the voltage conversion circuit starts. For example, it does not affect the startup time of the solid-state imaging device. In this respect, the activation of the voltage conversion circuit and the first constant current circuit having a low bandwidth can be operated in parallel. Therefore, since the startup time of the voltage conversion circuit can be used for the read operation startup time, it is possible to perform sufficient band limitation on the first constant current circuit. Therefore, it is possible to realize low noise and high dynamic range without degrading the startup time as a solid-state imaging device.
 また、各列の電流源回路に対して、基準電圧ではなく基準電流を供給するため、ミラー回路を構成することとなる。この構成により、電流源回路のソース電位がノイズ等で変動した場合の画素出力へのノイズ伝播が抑制される。 Also, a mirror circuit is configured to supply a reference current instead of a reference voltage to the current source circuits in each column. With this configuration, noise propagation to the pixel output when the source potential of the current source circuit fluctuates due to noise or the like is suppressed.
 また、固体撮像装置は、さらに、前記第1の定電流回路に接続される第1の容量素子と、前記第2の定電流回路に接続され、前記第1の容量素子と容量値が異なる第2の容量素子とを備えてもよい。 The solid-state imaging device is further connected to the first capacitor element connected to the first constant current circuit and the second constant current circuit, and has a capacitance value different from that of the first capacitor element. 2 capacitive elements.
 これにより、定電流回路のインピーダンスを抵抗とし、定電流回路に接続された容量値の異なる容量素子とで帯域特性の異なるローパスフィルタが構成される。この場合、抵抗素子を不要とできる。よって、電流源回路に接続される第1の定電流回路の出力電圧の帯域制限度合いと、電圧変換回路に接続される第2の定電流回路の出力電圧の帯域制限度合いとを、ノイズ除去及び遅延時間短縮化の必要性に応じて異ならせることが可能となる。 Thus, a low-pass filter having a different band characteristic is formed with a capacitor having a different capacitance value connected to the constant current circuit, using the impedance of the constant current circuit as a resistance. In this case, a resistance element can be dispensed with. Accordingly, the band limitation degree of the output voltage of the first constant current circuit connected to the current source circuit and the band limitation degree of the output voltage of the second constant current circuit connected to the voltage conversion circuit are reduced by noise and It becomes possible to make it different according to the necessity of shortening the delay time.
 また、固体撮像装置は、さらに、前記第1の定電流回路に接続される第1のフィルタ回路と、前記第2の定電流回路に接続され、前記第1のフィルタ回路よりも高い通過帯域を有する第2のフィルタ回路とを備えてもよい。 The solid-state imaging device further includes a first filter circuit connected to the first constant current circuit, and a second pass filter connected to the second constant current circuit, and having a higher passband than the first filter circuit. And a second filter circuit.
 これにより、電流源回路に接続される第1の定電流回路の出力電圧の帯域制限度合いを、電圧変換回路に接続される第2の定電流回路の出力電圧の帯域制限度合いより高く設定できる。よって、遅延時間を劣化させることなく電流源回路におけるノイズ除去を強化させることが可能となる。 Thereby, the band limit degree of the output voltage of the first constant current circuit connected to the current source circuit can be set higher than the band limit degree of the output voltage of the second constant current circuit connected to the voltage conversion circuit. Therefore, it is possible to enhance noise removal in the current source circuit without deteriorating the delay time.
 また、前記第1の定電流回路及び前記第2の定電流回路の一方は、容量素子が接続されており、前記第1の定電流回路及び前記第2の定電流回路の他方は、容量素子が接続されていなくてもよい。 Further, one of the first constant current circuit and the second constant current circuit is connected to a capacitor element, and the other of the first constant current circuit and the second constant current circuit is a capacitor element. May not be connected.
 これにより、回路部品点数の低減に寄与しつつ、第1の定電流回路の出力電圧の帯域制限度合いと、第2の定電流回路の出力電圧の帯域制限度合いとを、ノイズ除去及び遅延時間短縮化の必要性に応じて異ならせることが可能となる。 Thereby, while contributing to the reduction of the number of circuit components, the band limitation degree of the output voltage of the first constant current circuit and the band limitation degree of the output voltage of the second constant current circuit are reduced by noise and the delay time is shortened. It becomes possible to make it different according to the necessity of conversion.
 また、前記第1の定電流回路には、フィルタ回路が接続されており、前記第2の定電流回路には、フィルタ回路が接続されていなくてもよい。 Further, a filter circuit may be connected to the first constant current circuit, and a filter circuit may not be connected to the second constant current circuit.
 これにより、回路部品点数の低減に寄与しつつ、遅延時間を劣化させることなく電流源回路におけるノイズ除去を強化させることが可能となる。 This makes it possible to enhance noise removal in the current source circuit without degrading the delay time while contributing to the reduction in the number of circuit components.
 また、前記第1の定電流回路及び前記第2の定電流回路の少なくとも一方は、電圧を分圧することにより電流を生成する定電流回路であってもよい。 Further, at least one of the first constant current circuit and the second constant current circuit may be a constant current circuit that generates a current by dividing a voltage.
 また、前記第1の定電流回路は、第4の定電圧回路及び第1の電圧電流変換回路から構成され、前記第2の定電流回路は、前記第4の定電圧回路及び第2の電圧電流変換回路から構成され、前記第1の定電流回路と前記第2の定電流回路とは、第3の定電流回路に含まれ、前記第3の定電流回路は、前記第1の定電流回路と前記第2の定電圧回路とで前記第4の定電圧回路を共用し、前記第1の定電流回路からの前記第1定電流と前記第2の定電流回路からの前記第2電流とを独立に出力してもよい。 The first constant current circuit includes a fourth constant voltage circuit and a first voltage / current conversion circuit, and the second constant current circuit includes the fourth constant voltage circuit and the second voltage. The first constant current circuit and the second constant current circuit are included in a third constant current circuit, and the third constant current circuit includes the first constant current circuit. The circuit and the second constant voltage circuit share the fourth constant voltage circuit, and the first constant current from the first constant current circuit and the second current from the second constant current circuit And may be output independently.
 これにより、電圧変換回路への定電流と電流源回路への定電流とを、単一の定電流回路から供給することが可能となる。例えば、電圧変換回路への定電流は、第3の定電圧回路及び第2の電圧電流変換回路を介して出力させ、電流源回路への定電流は、第3の定電圧回路及び第1の電圧電流変換回路を介して出力させる。よって、回路規模の縮小化を実現しつつ、起動高速化と、低ノイズ化及び高ダイナミックレンジ化とを両立させることが可能となる。 This makes it possible to supply a constant current to the voltage conversion circuit and a constant current to the current source circuit from a single constant current circuit. For example, the constant current to the voltage conversion circuit is output via the third constant voltage circuit and the second voltage current conversion circuit, and the constant current to the current source circuit is the third constant voltage circuit and the first voltage conversion circuit. The output is made via a voltage-current conversion circuit. Therefore, it is possible to achieve both high-speed startup, low noise, and high dynamic range while realizing a reduction in circuit scale.
 また、固体撮像装置は、さらに、前記第1の電圧電流変換回路に接続される第3の容量素子と、前記第2の電圧電流変換回路に接続され、前記第3の容量素子と容量値が異なる第4の容量素子とを備えてもよい。 The solid-state imaging device is further connected to the third capacitor element connected to the first voltage-current converter circuit and to the second voltage-current converter circuit, and the capacitance value of the third capacitor element is A different fourth capacitor element may be provided.
 これにより、電圧電流変換回路のインピーダンスを抵抗とし、電圧電流変換回路に接続された容量値の異なる容量素子とで帯域特性の異なるローパスフィルタが構成される。この場合、抵抗素子を不要とできる。よって、電流源回路に接続される第1の電圧電流変換回路の出力電圧の帯域制限度合いと、電圧変換回路に接続される第2の電圧電流変換回路の出力電圧の帯域制限度合いとを、ノイズ除去及び遅延時間短縮化の必要性に応じて異ならせることが可能となる。 Thus, a low-pass filter having a different band characteristic is formed by a capacitive element having a different capacitance value connected to the voltage-current converter circuit, using the impedance of the voltage-current converter circuit as a resistor. In this case, a resistance element can be dispensed with. Therefore, the band limitation degree of the output voltage of the first voltage-current conversion circuit connected to the current source circuit and the band limitation degree of the output voltage of the second voltage-current conversion circuit connected to the voltage conversion circuit are expressed as noise. It becomes possible to make it different according to the necessity of removal and delay time shortening.
 また、固体撮像装置は、さらに、前記第1の電圧電流変換回路に接続される第3のフィルタ回路と、前記第2の電圧電流変換回路に接続され、前記第3のフィルタ回路よりも高い通過帯域を有する第4のフィルタ回路とを備えてもよい。 The solid-state imaging device further includes a third filter circuit connected to the first voltage-current conversion circuit and a second filter-current conversion circuit connected to the second voltage-current conversion circuit and having a higher pass than the third filter circuit. And a fourth filter circuit having a band.
 これにより、電流源回路に接続される第1の電圧電流変換回路の出力電流の帯域制限度合いを、電圧変換回路に接続される第2の電圧電流変換回路の出力電流の帯域制限度合いより高く設定できる。よって、遅延時間を劣化させることなく電流源回路におけるノイズ除去を強化させることが可能となる。 Thereby, the band limitation degree of the output current of the first voltage-current conversion circuit connected to the current source circuit is set higher than the band limitation degree of the output current of the second voltage-current conversion circuit connected to the voltage conversion circuit. it can. Therefore, it is possible to enhance noise removal in the current source circuit without deteriorating the delay time.
 また、前記第1の電圧電流変換回路及び前記第2の電圧電流変換回路の一方は、容量素子が接続されており、前記第1の電圧電流変換回路及び前記第2の電圧電流変換回路の他方は、容量素子が接続されていなくてもよい。 One of the first voltage-current conversion circuit and the second voltage-current conversion circuit is connected to a capacitive element, and the other of the first voltage-current conversion circuit and the second voltage-current conversion circuit. May not be connected to the capacitor.
 これにより、回路部品点数の低減に寄与しつつ、第1の電圧電流変換回路の出力電流の帯域制限度合いと、第2の電圧電流変換回路の出力電流の帯域制限度合いとを、ノイズ除去及び遅延時間短縮化の必要性に応じて異ならせることが可能となる。 Thereby, while contributing to the reduction in the number of circuit components, the band limitation degree of the output current of the first voltage-current converter circuit and the band limit degree of the output current of the second voltage-current converter circuit are reduced with noise and delayed. It becomes possible to make it different according to the necessity of time reduction.
 また、前記第1の電圧電流変換回路には、フィルタ回路が接続されており、前記第2の電圧電流変換回路には、フィルタ回路が接続されていなくてもよい。 Further, a filter circuit may be connected to the first voltage-current conversion circuit, and a filter circuit may not be connected to the second voltage-current conversion circuit.
 これにより、回路部品点数の低減に寄与しつつ、遅延時間を劣化させることなく電流源回路におけるノイズ除去を強化させることが可能となる。 This makes it possible to enhance noise removal in the current source circuit without degrading the delay time while contributing to the reduction in the number of circuit components.
 本発明の固体撮像装置によれば、(1)垂直走査回路が、電源電圧でなく電圧変換回路の供給する電圧で各画素を駆動し、(2)高帯域の周波数成分を有する電圧が電圧変換回路に供給され、低帯域の周波数成分に制限された電圧が電流源回路に供給されるので、固体撮像装置としての起動時間を劣化させることなく、低ノイズ化及び高ダイナミックレンジ化を両立させることが可能となる。 According to the solid-state imaging device of the present invention, (1) a vertical scanning circuit drives each pixel with a voltage supplied from a voltage conversion circuit instead of a power supply voltage, and (2) a voltage having a high frequency component is converted into a voltage. Since the voltage supplied to the circuit and limited to the frequency component in the low band is supplied to the current source circuit, it is possible to achieve both low noise and high dynamic range without degrading the startup time as a solid-state imaging device. Is possible.
図1は、本発明の実施の形態1に係る固体撮像装置1の構成を示すブロック図である。FIG. 1 is a block diagram showing a configuration of a solid-state imaging device 1 according to Embodiment 1 of the present invention. 図2は、本発明の固体撮像装置の有する単位画素5及び垂直走査回路40の構成の一例を示すブロック図である。FIG. 2 is a block diagram showing an example of the configuration of the unit pixel 5 and the vertical scanning circuit 40 included in the solid-state imaging device of the present invention. 図3は、本発明の固体撮像装置の有するカラムADC56の構成の一例を示すブロック図である。FIG. 3 is a block diagram showing an example of the configuration of the column ADC 56 included in the solid-state imaging device of the present invention. 図4は、本発明の固体撮像装置の有する電圧変換回路300の構成の一例を示すブロック図である。FIG. 4 is a block diagram illustrating an example of the configuration of the voltage conversion circuit 300 included in the solid-state imaging device of the present invention. 図5Aは、本発明の実施の形態1に係る固体撮像装置1の有する低帯域定電圧回路100の構成の一例を示すブロック図である。FIG. 5A is a block diagram illustrating an example of a configuration of the low-band constant voltage circuit 100 included in the solid-state imaging device 1 according to Embodiment 1 of the present invention. 図5Bは、本発明の実施の形態1に係る固体撮像装置1の有する高帯域定電圧回路200の構成の一例を示すブロック図である。FIG. 5B is a block diagram illustrating an example of a configuration of the high-band constant voltage circuit 200 included in the solid-state imaging device 1 according to Embodiment 1 of the present invention. 図6は、本発明の実施の形態2に係る固体撮像装置2の構成を示すブロック図である。FIG. 6 is a block diagram showing a configuration of the solid-state imaging device 2 according to Embodiment 2 of the present invention. 図7Aは、本発明の実施の形態2に係る固体撮像装置2の有する低帯域定電流回路107の構成の第1の例を示すブロック図である。FIG. 7A is a block diagram illustrating a first example of the configuration of the low-band constant current circuit 107 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. 図7Bは、本発明の実施の形態2に係る固体撮像装置2の有する高帯域定電流回路207の構成の第1の例を示すブロック図である。FIG. 7B is a block diagram illustrating a first example of the configuration of the high-band constant current circuit 207 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. 図8Aは、本発明の実施の形態2に係る固体撮像装置2の有する低帯域定電流回路107の構成の第2の例を示すブロック図である。FIG. 8A is a block diagram illustrating a second example of the configuration of the low-band constant current circuit 107 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. 図8Bは、本発明の実施の形態2に係る固体撮像装置2の有する高帯域定電流回路207の構成の第2の例を示すブロック図である。FIG. 8B is a block diagram illustrating a second example of the configuration of the high-band constant current circuit 207 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. 図9Aは、本発明の実施の形態2に係る固体撮像装置2の有する低帯域定電流回路107の構成の第3の例を示すブロック図である。FIG. 9A is a block diagram showing a third example of the configuration of the low-band constant current circuit 107 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. 図9Bは、本発明の実施の形態2に係る固体撮像装置2の有する高帯域定電流回路207の構成の第3の例を示すブロック図である。FIG. 9B is a block diagram illustrating a third example of the configuration of the high-band constant current circuit 207 included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. 図10は、本発明の実施の形態3に係る固体撮像装置3の構成を示すブロック図である。FIG. 10 is a block diagram showing a configuration of the solid-state imaging device 3 according to Embodiment 3 of the present invention. 図11は、本発明の実施の形態3に係る固体撮像装置3の有する複数帯域定電圧回路400の構成を示すブロック図である。FIG. 11 is a block diagram showing a configuration of a multiband constant voltage circuit 400 included in the solid-state imaging device 3 according to Embodiment 3 of the present invention. 図12は、本発明の実施の形態4に係る固体撮像装置4の構成を示すブロック図である。FIG. 12 is a block diagram showing a configuration of the solid-state imaging device 4 according to Embodiment 4 of the present invention. 図13は、本発明の実施の形態4に係る固体撮像装置4の有する複数帯域定電流回路407の構成を示すブロック図である。FIG. 13 is a block diagram showing a configuration of a multiband constant current circuit 407 included in the solid-state imaging device 4 according to Embodiment 4 of the present invention. 図14は、特許文献1に示された従来の固体撮像装置1000の構成を示すブロック図である。FIG. 14 is a block diagram illustrating a configuration of a conventional solid-state imaging device 1000 disclosed in Patent Document 1. In FIG.
 (実施の形態1)
 以下、図面を参照しながら、本発明の実施の形態1に係る固体撮像装置1の構成及び動作について説明する。
(Embodiment 1)
Hereinafter, the configuration and operation of the solid-state imaging device 1 according to Embodiment 1 of the present invention will be described with reference to the drawings.
 本実施の形態に係る固体撮像装置1は、ノイズを低減するために帯域を制限した低帯域定電圧回路と、起動の高速化のため帯域を制限しない高帯域低電圧回路を備え、低帯域低電圧回路を、少なくとも画素ソースフォロア回路の読み出し電流源に供給し、高帯域低電圧回路を、少なくとも電圧変換回路に供給することで、起動高速化と、低ノイズ化及び高ダイナミックレンジ化とを両立する。 The solid-state imaging device 1 according to the present embodiment includes a low-band constant voltage circuit that limits the band in order to reduce noise, and a high-band low-voltage circuit that does not limit the band for speeding up the start. By supplying the voltage circuit to at least the readout current source of the pixel source follower circuit and supplying the high-band low-voltage circuit to at least the voltage conversion circuit, both high-speed startup, low noise, and high dynamic range are achieved. To do.
 図1は、本発明の実施の形態1に係る固体撮像装置1の構成を示すブロック図である。同図に記載された固体撮像装置1は、画素アレイ10と、垂直走査回路40と、複数の転送トランジスタ制御線41と、複数のリセットトランジスタ制御線42と、複数の選択トランジスタ制御線43と、複数の垂直信号線45と、複数の読み出し電流源50と、複数のカラムADC56と、参照信号生成部57と、水平信号線55と、水平走査回路60と、複数の水平制御線65と、出力回路67と、タイミング制御部70と、少なくとも一つの高帯域定電圧回路200と、少なくとも一つの低帯域定電圧回路100と、低帯域定電圧回路の帯域を制限するための帯域制限容量101と、少なくとも一つの電圧変換回路300とを備える。 FIG. 1 is a block diagram showing a configuration of a solid-state imaging device 1 according to Embodiment 1 of the present invention. The solid-state imaging device 1 illustrated in FIG. 1 includes a pixel array 10, a vertical scanning circuit 40, a plurality of transfer transistor control lines 41, a plurality of reset transistor control lines 42, a plurality of selection transistor control lines 43, A plurality of vertical signal lines 45, a plurality of read current sources 50, a plurality of column ADCs 56, a reference signal generator 57, a horizontal signal line 55, a horizontal scanning circuit 60, a plurality of horizontal control lines 65, and an output A circuit 67, a timing control unit 70, at least one high-band constant voltage circuit 200, at least one low-band constant voltage circuit 100, and a band limiting capacitor 101 for limiting the band of the low-band constant voltage circuit; And at least one voltage conversion circuit 300.
 なお、図1に示す各機能ブロックは、画素アレイ10から見て、片側のみに配置されているが、画素アレイ10の両側に配置される構成であっても良い。 Each functional block shown in FIG. 1 is arranged on only one side when viewed from the pixel array 10, but may be arranged on both sides of the pixel array 10.
 画素アレイ10は、行列状に配置された複数の単位画素5を備え、単位画素5は、受光した光を光電変換して信号電圧に変換する。複数の垂直信号線45は、単位画素5の列に対応して設けられ、対応する列の単位画素5より出力された信号電圧を伝達する。 The pixel array 10 includes a plurality of unit pixels 5 arranged in a matrix, and the unit pixels 5 photoelectrically convert the received light into signal voltages. The plurality of vertical signal lines 45 are provided corresponding to the columns of the unit pixels 5 and transmit the signal voltages output from the unit pixels 5 of the corresponding columns.
 図2は、本発明の固体撮像装置の有する単位画素5及び垂直走査回路40の構成の一例を示すブロック図である。 FIG. 2 is a block diagram showing an example of the configuration of the unit pixel 5 and the vertical scanning circuit 40 included in the solid-state imaging device of the present invention.
 単位画素5は、いわゆる4トランジスタ型の単位画素セルであり、フォトダイオード30と、転送トランジスタ31と、リセットトランジスタ32と、選択トランジスタ33と、読み出しトランジスタ34(以降、総じて画素トランジスタと呼ぶ)とを備える画素である。 The unit pixel 5 is a so-called four-transistor unit pixel cell, and includes a photodiode 30, a transfer transistor 31, a reset transistor 32, a selection transistor 33, and a readout transistor 34 (hereinafter collectively referred to as a pixel transistor). It is a pixel provided.
 読み出しトランジスタ34は、同列に配された複数の単位画素間で、列毎に設けられた垂直信号線45にて共通接続され、画素列毎に設けられた電流源回路である読み出し電流源50と、選択トランジスタ33が導通した行の読み出しトランジスタ34とによって、ソースフォロア回路(以降、画素ソースフォロアと呼ぶ)を構成する。画素信号は、画素ソースフォロアによって、垂直信号線45を介して、読み出される。 The read transistor 34 is connected in common by a vertical signal line 45 provided for each column between a plurality of unit pixels arranged in the same column, and a read current source 50 which is a current source circuit provided for each pixel column. A source follower circuit (hereinafter referred to as a pixel source follower) is constituted by the read transistor 34 in the row in which the selection transistor 33 is conducted. The pixel signal is read out by the pixel source follower via the vertical signal line 45.
 なお、本実施の形態においては、4トランジスタ型の単位画素5を例示したが、単位画素5は、選択トランジスタ33が存在しない、いわゆる3トランジスタ型の単位画素であってもよく、複数のフォトダイオード30に対して、読み出しトランジスタ34を共有する、いわゆる多画素1セルの単位画素であってもよい。また、単位画素5を構成する各トランジスタは、NMOSトランジスタ及びPMOSトランジスタのいずれであっても良く、垂直信号線45が、一つの列に対して複数本存在しても良い。また、フォトダイオード30からの信号電圧を垂直信号線45へ出力できる構成であれば、単位画素5は、図2の構成に制限されるものではない。 In the present embodiment, the 4-transistor type unit pixel 5 is illustrated, but the unit pixel 5 may be a so-called 3-transistor type unit pixel in which the selection transistor 33 does not exist, and a plurality of photodiodes. 30 may be a unit pixel of a so-called multi-pixel 1 cell sharing the readout transistor 34. Each transistor constituting the unit pixel 5 may be either an NMOS transistor or a PMOS transistor, and a plurality of vertical signal lines 45 may exist for one column. Further, the unit pixel 5 is not limited to the configuration shown in FIG. 2 as long as the signal voltage from the photodiode 30 can be output to the vertical signal line 45.
 垂直走査回路40は、タイミング制御部70からの情報に基づいて、どの行の画素信号を読み出すかを決定するデコーダ44と、画素内の各画素トランジスタを駆動する複数の垂直ドライバ47とで構成される。なお、本実施の形態では、垂直ドライバ47は、各画素トランジスタについて、同一の構成を例示したが、リセットトランジスタ制御線42を駆動する垂直ドライバ47のみに昇圧電圧を供給するなど、少なくとも一つの垂直ドライバ47に、電圧変換回路300からの電圧が供給されていれば、本発明の目的と範囲を逸脱しない。また、垂直ドライバ47にHレベルとしての昇圧電圧と、Lレベルとしての負の降圧電圧が供給されるなど、一つの垂直ドライバ47に、複数の電圧変換回路300からの異なる電圧が供給されていても、同様に本発明の目的と範囲を逸脱しない。 The vertical scanning circuit 40 includes a decoder 44 that determines which row of pixel signals to read based on information from the timing control unit 70, and a plurality of vertical drivers 47 that drive each pixel transistor in the pixel. The In this embodiment, the vertical driver 47 has the same configuration as each pixel transistor. However, at least one vertical driver 47 supplies a boosted voltage only to the vertical driver 47 that drives the reset transistor control line 42. As long as the voltage from the voltage conversion circuit 300 is supplied to the driver 47, it does not depart from the object and scope of the present invention. Further, different voltages from a plurality of voltage conversion circuits 300 are supplied to one vertical driver 47, such as a boosted voltage as an H level and a negative stepped down voltage as an L level are supplied to the vertical driver 47. However, it does not depart from the object and scope of the present invention.
 垂直走査回路40は、転送トランジスタ制御線41と、リセットトランジスタ制御線42と、選択トランジスタ制御線43と、を順次アクティブにすることで、単位画素5の行を順次選択して垂直走査を行い、選択された行の信号電圧は、列毎に画素ソースフォロアを介して、カラムADC56へ伝送される。 The vertical scanning circuit 40 sequentially activates the transfer transistor control line 41, the reset transistor control line 42, and the selection transistor control line 43 to sequentially select the rows of the unit pixels 5 and perform vertical scanning. The signal voltage of the selected row is transmitted to the column ADC 56 via the pixel source follower for each column.
 例えば、m行目の単位画素5においては、まず、リセットトランジスタ制御線42によってリセットトランジスタ32が導通することで、読み出しトランジスタ34のゲート部電圧、いわゆるフローティングディフュージョン部の電圧がリセットされる。 For example, in the unit pixel 5 in the m-th row, first, the reset transistor 32 is turned on by the reset transistor control line 42, whereby the gate voltage of the read transistor 34, that is, the so-called floating diffusion voltage is reset.
 続いて選択トランジスタ制御線43によって選択トランジスタ33は導通し、フローティングディフュージョン部のリセット後の電圧は、m行目の単位画素5のリセットレベルの電圧Vrstとして、読み出しトランジスタ34を介して垂直信号線45へ出力され、後段のカラムADC56へ供給されてAD変換される。 Subsequently, the selection transistor 33 is turned on by the selection transistor control line 43, and the voltage after resetting the floating diffusion portion is set as the reset level voltage Vrst of the unit pixel 5 in the m-th row through the readout transistor 34 and the vertical signal line 45. And supplied to the column ADC 56 at the subsequent stage for AD conversion.
 続いて、フォトダイオード30は、露光時間中に受光した光を光電変換して得られる電荷を蓄積する。所定の露光時間終了後に、転送トランジスタ制御線41によってm行目の単位画素5において、転送トランジスタ31が導通し、フォトダイオード30の蓄積電荷がフローティングディフュージョン部へ転送される。転送された電荷は、m行目の単位画素5のリセットレベルの電圧Vrstに受光光量に応じたm行目の信号レベルの電圧Vsigを重畳した電圧(Vrst+Vsig)として、読み出しトランジスタ34を介して垂直信号線45へ出力され、後段のカラムADC56へ供給されてAD変換される。このように2度のAD変換の結果により生じる信号の差分を抽出する、いわゆる2重サンプリング動作によって、受光光量に応じたm行目の単位画素5の信号レベルを得ることができる。 Subsequently, the photodiode 30 accumulates charges obtained by photoelectrically converting light received during the exposure time. After the predetermined exposure time, the transfer transistor 31 is turned on in the unit pixel 5 in the m-th row by the transfer transistor control line 41, and the charge accumulated in the photodiode 30 is transferred to the floating diffusion portion. The transferred charge is vertically transmitted through the read transistor 34 as a voltage (Vrst + Vsig) obtained by superimposing the voltage Vsig of the m-th row signal level corresponding to the amount of received light on the reset level voltage Vrst of the unit pixel 5 of the m-th row. The signal is output to the signal line 45 and supplied to the subsequent column ADC 56 for AD conversion. Thus, the signal level of the unit pixel 5 in the m-th row corresponding to the amount of received light can be obtained by a so-called double sampling operation that extracts a difference between signals generated as a result of two AD conversions.
 なお、以上説明した単位画素5の駆動方法は、一例である。本発明の目的と範囲は、画素信号の処理を限定せず、m行目の単位画素5のリセットレベルの電圧Vrstと、m行目の受光光量に応じたm行目の信号レベルの電圧VsigとをカラムADC56へ供給できる駆動方法であれば、例示した駆動方法に制限されるものではない。さらには、カラムADC56が存在せず、図12に図示した従来の固体撮像装置のごとく、アナログ信号として水平選択した後、単一のADCにて変換を行う駆動方法であってもよい。 Note that the driving method of the unit pixel 5 described above is an example. The object and scope of the present invention do not limit the processing of the pixel signal, but the reset level voltage Vrst of the m-th unit pixel 5 and the m-th row signal level voltage Vsig according to the m-th received light amount. Is not limited to the illustrated driving method. Further, there may be a driving method in which the column ADC 56 does not exist and the conversion is performed by a single ADC after horizontal selection as an analog signal as in the conventional solid-state imaging device illustrated in FIG.
 また、図1に記載された固体撮像装置1においては、単位画素5の出力に対する信号増幅手段が設けられていないが、単位画素5の出力からカラムADC56の入力へ至る信号経路に、AGC(Auto Gain Control)等の信号増幅手段、いわゆるカラムアンプが設けられても良い。この場合には、カラムADC56へ入力される信号の信号レベルを大きくすることが可能となり、その結果、AD変換における入力換算S/Nを良化させ、固体撮像装置1として画質を向上させることができる。カラムアンプとしては、定電流性の負荷をソース接地増幅回路で駆動する、いわゆるシングルエンドのインバータアンプが好適に用いられるが、信号増幅手段であればこの構成に制限されるものではなく、差動増幅回路等の増幅手段が用いられても良い。また、カラムADC56へ入力される信号をサンプルホールドするためのサンプルホールド手段が設けられても良い。カラムADC56へ入力される信号のサンプルホールド手段が備えられる場合には、カラムADC56の変換動作と、単位画素5から垂直信号線45への信号読み出しとを並列動作させる、いわゆるパイプライン化が可能となり、固体撮像装置1としてフレームレートを向上させることができる。 In the solid-state imaging device 1 shown in FIG. 1, no signal amplifying means is provided for the output of the unit pixel 5, but an AGC (Auto) is provided in the signal path from the output of the unit pixel 5 to the input of the column ADC 56. A signal amplifying means such as Gain Control), a so-called column amplifier may be provided. In this case, the signal level of the signal input to the column ADC 56 can be increased. As a result, the input conversion S / N in AD conversion is improved, and the image quality of the solid-state imaging device 1 can be improved. it can. As the column amplifier, a so-called single-ended inverter amplifier that drives a constant-current load with a source-grounded amplifier circuit is preferably used. Amplifying means such as an amplifier circuit may be used. Further, a sample hold means for sample holding the signal input to the column ADC 56 may be provided. In the case where sample hold means for the signal input to the column ADC 56 is provided, it is possible to perform so-called pipeline operation in which the conversion operation of the column ADC 56 and the signal reading from the unit pixel 5 to the vertical signal line 45 are operated in parallel. As a result, the frame rate of the solid-state imaging device 1 can be improved.
 図3は、本発明の固体撮像装置の有するカラムADC56の構成の一例を示すブロック図である。 FIG. 3 is a block diagram showing an example of the configuration of the column ADC 56 included in the solid-state imaging device of the present invention.
 カラムADC56は、垂直信号線45に対応して設けられ、対応する垂直信号線45により伝達された信号電圧をデジタル信号に変換する。参照信号生成部57は、各列のカラムADC56に供給される共通の参照信号を生成する。 The column ADC 56 is provided corresponding to the vertical signal line 45, and converts the signal voltage transmitted through the corresponding vertical signal line 45 into a digital signal. The reference signal generation unit 57 generates a common reference signal supplied to the column ADC 56 of each column.
 次に、図3を用いてカラムADC56の構成とAD変換動作について説明する。 Next, the configuration of the column ADC 56 and the AD conversion operation will be described with reference to FIG.
 本実施の形態では、カラムADC56は、いわゆるシングルスロープ型AD変換回路として例示するが、逐次比較等、他のADC方式であっても、本発明の目的と範囲を逸脱しない。本実施の形態におけるカラムADC56は、各列の垂直信号線45に出力された複数の信号電圧を同時にデジタル信号に変換する。 In the present embodiment, the column ADC 56 is exemplified as a so-called single slope AD converter circuit, but other ADC methods such as successive approximation do not depart from the object and scope of the present invention. The column ADC 56 in the present embodiment simultaneously converts a plurality of signal voltages output to the vertical signal lines 45 of each column into digital signals.
 カラムADC56は、電圧比較部415と、カウント部(カウンタ)416と、メモリ部418とを備え、参照信号生成部57からの共通の参照信号が入力される。 The column ADC 56 includes a voltage comparison unit 415, a count unit (counter) 416, and a memory unit 418, and a common reference signal from the reference signal generation unit 57 is input thereto.
 参照信号生成部57は、時間経過と共に徐々に変化する参照信号電圧(ランプ波形信号電圧)Vslopeを生成する。参照信号電圧Vslopeは、滑らかなスロープ状の波形であっても階段状の波形であっても良く、ある傾きで推移する波形であればその波形は特に制限されるものではない。参照信号電圧Vslopeの傾きも、同様に正負のいずれであっても良い。参照信号生成部57は、DAC(デジタルアナルグコンバータ)に増加もしくは減少するコード値を与えDAC出力をフィルタリングすることでも、容量素子を用いて積分動作させることでも構成できる。なお、本構成は、ある傾きで推移する波形を生成できる参照信号生成部57であれば、特に制限されるものではない。 The reference signal generator 57 generates a reference signal voltage (ramp waveform signal voltage) Vslope that gradually changes over time. The reference signal voltage Vslope may be a smooth slope waveform or a stepped waveform, and the waveform is not particularly limited as long as the waveform changes with a certain slope. Similarly, the slope of the reference signal voltage Vslope may be either positive or negative. The reference signal generation unit 57 can be configured by filtering the DAC output by giving a code value that increases or decreases to a DAC (digital analog converter), or by performing an integration operation using a capacitive element. This configuration is not particularly limited as long as it is a reference signal generation unit 57 that can generate a waveform that changes with a certain inclination.
 電圧比較部415は、垂直信号線45に出力されデジタル信号に変換される信号電圧と、電圧比較部415へ入力され漸次変化する参照信号電圧Vslopeとの大小を比較する。電圧比較部415は、好適には、よく知られるオフセットキャンセル機能を備えた差動比較器で構成されるが、いわゆるチョッパコンパレータ等で構成されても良く、垂直信号線45の信号電圧と、参照信号電圧Vslopeとを比較できる電圧比較部415であればその構成は特に制限されるものではない。 The voltage comparison unit 415 compares the signal voltage output to the vertical signal line 45 and converted into a digital signal with the reference signal voltage Vslope that is input to the voltage comparison unit 415 and gradually changes. The voltage comparison unit 415 is preferably composed of a differential comparator having a well-known offset cancellation function, but may be composed of a so-called chopper comparator or the like, and the signal voltage of the vertical signal line 45 and the reference The configuration is not particularly limited as long as the voltage comparison unit 415 can compare the signal voltage Vslope.
 カウント部416は、電圧比較部415が比較を開始してから電圧比較部415の比較結果が変化するまでの時間、つまり垂直信号線45の信号電圧と、参照信号電圧Vslopeとの大小関係が変化するまで(電圧比較部415の出力が反転するまで)の時間をカウントすることでAD変換を行う。つまり、カウント部416は、比較を開始してから信号電圧と参照信号電圧Vslopeとの大小関係が変化するまで入力されるクロックCLKをカウントすることによりAD変換を行う。AD変換終了後、カウント部416は、デジタル信号値(カウント値)をメモリ部418に伝送し、メモリ部418は、伝送されたデジタル信号値を記憶する。このAD変換は、リセットレベルの電圧Vrstと、リセットレベルVrstに受光光量に応じた信号レベル電圧Vsigを重畳した電圧(Vrst+Vsig)とに対して2度行われ、その差分情報より単位画素5の信号レベルが得られる。本2重サンプリング動作は、本発明にとって必須ではなく、信号レベルVsigについてのみAD変換を行っても、本発明の目的と範囲を逸脱しない。 The counting unit 416 changes the time from when the voltage comparison unit 415 starts comparison until the comparison result of the voltage comparison unit 415 changes, that is, the magnitude relationship between the signal voltage of the vertical signal line 45 and the reference signal voltage Vslope. A / D conversion is performed by counting the time until the output of the voltage comparison unit 415 is inverted. That is, the count unit 416 performs AD conversion by counting the input clock CLK from the start of comparison until the magnitude relationship between the signal voltage and the reference signal voltage Vslope changes. After the AD conversion is completed, the count unit 416 transmits the digital signal value (count value) to the memory unit 418, and the memory unit 418 stores the transmitted digital signal value. This AD conversion is performed twice on the reset level voltage Vrst and the voltage (Vrst + Vsig) obtained by superimposing the reset level Vrst on the signal level voltage Vsig corresponding to the amount of received light. The signal of the unit pixel 5 is obtained from the difference information. A level is obtained. This double sampling operation is not essential for the present invention, and even if AD conversion is performed only for the signal level Vsig, it does not depart from the object and scope of the present invention.
 水平走査回路60は、タイミング制御部70からの情報に基づいて、順次、水平制御線65を制御する。これにより、列ごとにメモリ部418に記憶されたデジタル信号値は水平信号線55へ読み出され、出力回路67へ供給される。 The horizontal scanning circuit 60 sequentially controls the horizontal control lines 65 based on information from the timing control unit 70. As a result, the digital signal value stored in the memory unit 418 for each column is read to the horizontal signal line 55 and supplied to the output circuit 67.
 出力回路67は、伝送されたデジタル信号値を外部に出力する。出力回路67として好適にはLVDS等の高速伝送回路が用いられるが、デジタル信号値を出力することが可能な出力手段であれば出力回路67の出力方式、回路及び構成は特に制限されるものではなく、またシリアル出力及びパラレル出力の種別や、その出力ポート数なども特に制限されるものではない。 The output circuit 67 outputs the transmitted digital signal value to the outside. A high-speed transmission circuit such as LVDS is preferably used as the output circuit 67, but the output method, circuit, and configuration of the output circuit 67 are not particularly limited as long as the output means can output a digital signal value. Further, the type of serial output and parallel output, the number of output ports, and the like are not particularly limited.
 本実施の形態に係る固体撮像装置1の特徴は、少なくとも一つの高帯域定電圧回路200と、少なくとも一つの低帯域定電圧回路100と、少なくとも一つの電圧変換回路300とを備える点にある。 The feature of the solid-state imaging device 1 according to the present embodiment is that it includes at least one high-band constant voltage circuit 200, at least one low-band constant voltage circuit 100, and at least one voltage conversion circuit 300.
 この構成により、垂直走査回路40は、転送トランジスタ31、リセットトランジスタ32及び選択トランジスタ33のゲート駆動HIGHレベルを、電源電圧ではなく、電圧変換回路300の供給する昇圧電圧で駆動することが可能となる。よって、各トランジスタのソース電位は電源電圧から閾値電圧低下した電圧に抑制されることなく、電源電圧まで動作可能となる。その結果、フォトダイオード電荷の十分な読み出し、ソースフォロア回路の電源電圧までの出力、及び、ソースフォロア回路ゲートへの電源電圧そのものの印加が可能となり、扱える信号量が増加するため、高ダイナミックレンジ化が可能となる。 With this configuration, the vertical scanning circuit 40 can drive the gate drive HIGH levels of the transfer transistor 31, the reset transistor 32, and the selection transistor 33 with the boosted voltage supplied from the voltage conversion circuit 300 instead of the power supply voltage. . Therefore, the source potential of each transistor can be operated up to the power supply voltage without being suppressed to a voltage lower than the threshold voltage from the power supply voltage. As a result, sufficient readout of the photodiode charge, output up to the power supply voltage of the source follower circuit, and application of the power supply voltage itself to the source follower circuit gate become possible, and the amount of signals that can be handled increases, resulting in a high dynamic range. Is possible.
 また、垂直走査回路40は、転送トランジスタ31、リセットトランジスタ32及び選択トランジスタ33のゲート駆動LOWレベルを、グランド電位ではなく、電圧変換回路300の供給する負の降圧電圧で駆動することが可能となる。よって、各トランジスタのオフ時のゲート電位は負の降圧電圧となり、各画素トランジスタでのオフリーク電流の発生を抑制し、画像としてのキズや浮きといった異常を抑制し、高画質化が図られる。 Further, the vertical scanning circuit 40 can drive the gate drive LOW level of the transfer transistor 31, the reset transistor 32, and the selection transistor 33 with a negative step-down voltage supplied from the voltage conversion circuit 300, instead of the ground potential. . Therefore, the gate potential when each transistor is turned off becomes a negative step-down voltage, and the occurrence of off-leakage current in each pixel transistor is suppressed, and abnormalities such as scratches and floating as an image are suppressed, thereby achieving high image quality.
 以上説明のように、少なくとも一つの電圧変換回路300によって、電源電圧以上の昇圧電圧、あるいは負の降圧電圧を生成し、垂直走査回路40へ供給し、画素トランジスタの駆動に用いることにより、高ダイナミックレンジ化と高画質化が実現される。 As described above, by using at least one voltage conversion circuit 300 to generate a boosted voltage higher than the power supply voltage or a negative stepped-down voltage, supply it to the vertical scanning circuit 40, and use it for driving the pixel transistor, high dynamics can be achieved. Range and high image quality are realized.
 図4は、本発明の固体撮像装置の有する電圧変換回路300の構成の一例を示すブロック図である。同図に記載された電圧変換回路300は、いわゆるチャージポンプ型昇圧回路であって、スイッチSW1~SW4と、ポンプ容量Cpと、平滑容量Coutと、生成電圧を検出するための分圧抵抗R1及びR2と、生成電圧を検出して昇圧動作を制御する比較回路301とを備える。 FIG. 4 is a block diagram showing an example of the configuration of the voltage conversion circuit 300 included in the solid-state imaging device of the present invention. The voltage conversion circuit 300 shown in the figure is a so-called charge pump type booster circuit, and includes switches SW1 to SW4, a pump capacitor Cp, a smoothing capacitor Cout, a voltage dividing resistor R1 for detecting a generated voltage, and R2 and a comparison circuit 301 that detects the generated voltage and controls the boosting operation.
 電圧変換回路300は、スイッチSW1~SW4のスイッチング動作により、ポンプ容量Cpに電圧としてエネルギーを蓄積する動作と、当該エネルギーを平滑容量Coutへ移送する動作とを繰り返すことで、電源電圧よりも高い電圧を生成する。本実施の形態では、ポンプ容量Cpにエネルギーを蓄積する際にはスイッチSW1及びSW3が導通し、上記エネルギーを平滑容量Coutへ移送する際にはスイッチSW2及びSW4が導通する。 The voltage conversion circuit 300 repeats the operation of accumulating energy as a voltage in the pump capacitor Cp and the operation of transferring the energy to the smoothing capacitor Cout by the switching operation of the switches SW1 to SW4, thereby increasing the voltage higher than the power supply voltage. Is generated. In the present embodiment, the switches SW1 and SW3 are turned on when energy is stored in the pump capacitor Cp, and the switches SW2 and SW4 are turned on when the energy is transferred to the smoothing capacitor Cout.
 比較回路301は、上記生成電圧が所望の電圧となるように、スイッチング動作を制御し、電源電圧と異なる所望の電圧を生成する。本実施の形態では、分圧抵抗R1及びR2による検出電圧が入力される基準電圧を超えた時点で、比較回路301出力が反転し、スイッチング動作用のCLK入力がゲートされる。これにより、スイッチング動作が停止し、生成電圧が所望の電圧値となる。 The comparison circuit 301 controls the switching operation so that the generated voltage becomes a desired voltage, and generates a desired voltage different from the power supply voltage. In the present embodiment, when the detection voltage by the voltage dividing resistors R1 and R2 exceeds the input reference voltage, the output of the comparison circuit 301 is inverted and the CLK input for switching operation is gated. Thereby, the switching operation is stopped, and the generated voltage becomes a desired voltage value.
 なお、電圧変換回路300は、昇圧回路であっても、負の降圧回路であってもよく、いわゆるチャージポンプ型回路であっても、スイッチングレギュレータ型回路であっても、本発明の目的と範囲を逸脱しない。 The voltage conversion circuit 300 may be a step-up circuit or a negative step-down circuit, and may be a so-called charge pump type circuit or a switching regulator type circuit. Not deviate from.
 一般的に、電圧変換回路300は、基準電圧及び基準電流の少なくとも一つを必要とする。本実施例では、比較回路301において、電圧比較のため基準電圧と、比較回路の回路動作のための基準電流とを必要とする。 Generally, the voltage conversion circuit 300 requires at least one of a reference voltage and a reference current. In this embodiment, the comparison circuit 301 requires a reference voltage for voltage comparison and a reference current for circuit operation of the comparison circuit.
 図5A及び図5Bは、それぞれ、本発明の実施の形態1に係る固体撮像装置1の有する高帯域定電圧回路200及び低帯域定電圧回路100の構成の一例を示すブロック図である。本実施の形態では、固体撮像装置1は、少なくとも一つの高帯域定電圧回路200と、少なくとも一つの低帯域定電圧回路100とを備える。 5A and 5B are block diagrams showing examples of configurations of the high-band constant voltage circuit 200 and the low-band constant voltage circuit 100 included in the solid-state imaging device 1 according to Embodiment 1 of the present invention, respectively. In the present embodiment, the solid-state imaging device 1 includes at least one high-band constant voltage circuit 200 and at least one low-band constant voltage circuit 100.
 高帯域定電圧回路200は、一般的なバンドギャップリファレンス回路(図中のBGR)105の出力に対して、帯域制限なく第2電圧を出力する第2の定電圧回路である。一方、低帯域定電圧回路100は、一般的なバンドギャップリファレンス回路105の出力に対して、帯域制限抵抗102及び帯域制限容量101によるローパスフィルタ103を挿入することにより、帯域制限を行って第1電圧を出力する第1の定電圧回路である。高帯域定電圧回路200は、帯域制限が行われていないため、ノイズ量は大きいが、定電圧回路としての起動時間は高速となる。一方、低帯域定電圧回路100は、帯域制限を行うため、ノイズ量は小さく、低ノイズ回路としての使用が可能であるが、ローパスフィルタ103を構成する抵抗や容量により、定電圧回路としての起動時間が低速となる。 The high band constant voltage circuit 200 is a second constant voltage circuit that outputs a second voltage with no band limitation to the output of a general band gap reference circuit (BGR in the figure) 105. On the other hand, the low-band constant voltage circuit 100 performs band limitation by inserting a low-pass filter 103 including a band-limiting resistor 102 and a band-limiting capacitor 101 with respect to the output of a general band-gap reference circuit 105 to perform first band limitation. It is the 1st constant voltage circuit which outputs a voltage. Since the high-band constant voltage circuit 200 is not band-limited, the amount of noise is large, but the startup time as the constant-voltage circuit is fast. On the other hand, since the low-band constant voltage circuit 100 performs band limitation, the amount of noise is small and the low-band voltage circuit 100 can be used as a low-noise circuit. Time is slow.
 また、帯域制限容量101については、帯域を大きく制限するため、外付け容量の使用が好適であるが、必ずしも外付け容量である必要はなく、十分な帯域制限が行えれば、同一半導体基板上の容量を用いても本発明の目的と範囲を逸脱しない。また、本実施の形態では、バンドギャップリファレンス回路105を例示したが、電圧を生成する電圧源回路であれば、例えば、抵抗分圧による電圧生成回路等であっても、本発明の目的と範囲を逸脱しない。さらに、本実施の形態では、低帯域定電圧回路100のみに第1のフィルタ回路であるローパスフィルタ103を接続した例を例示したが、起動時間に影響のない範囲で高帯域定電圧回路200に第2のフィルタ回路であるローパスフィルタを接続しても、本発明の目的と範囲を逸脱しない。この場合には、低帯域定電圧回路100に接続されたローパスフィルタの帯域は、高帯域定電圧回路200に接続されたローパスフィルタの帯域よりも低く設定されることとなる。また、必ずしも、ローパスフィルタにて帯域制限を行う必要性はなく、他の帯域制限手段による帯域制限であってもよい。さらに、帯域制限抵抗と帯域制限容量によってローパスフィルタを構成するのではなく、帯域制限のための容量素子のみを接続した場合であっても、帯域制限容量前段の回路出力インピーダンスを抵抗として、ローパスフィルタが構成されるため、本実施の形態と同様の効果が得られ、かつ抵抗素子を不要とできる。この場合であっても、低帯域定電圧回路100に第1の容量素子が接続されるだけでなく、起動時間に影響のない範囲で高帯域定電圧回路200に第1の容量素子と容量値の異なる第2の容量素子が接続された構成であっても、本発明の目的と範囲を逸脱しない。この場合には、第1の容量素子で構成されたローパスフィルタの帯域は、第2の容量素子で構成されたローパスフィルタの帯域よりも低く設定されることとなる。また、電圧出力数は限定されるものではなく、2以上の任意の電圧出力数が存在しても良い。 For the band limiting capacitor 101, it is preferable to use an external capacitor in order to greatly limit the band. However, it is not always necessary to use an external capacitor. The use of this capacity does not depart from the purpose and scope of the present invention. In the present embodiment, the band gap reference circuit 105 is exemplified. However, if the voltage source circuit generates a voltage, the object and scope of the present invention are applicable to, for example, a voltage generation circuit using resistance voltage division. Not deviate from. Furthermore, in the present embodiment, an example in which the low-pass filter 103 that is the first filter circuit is connected only to the low-band constant voltage circuit 100 is illustrated. However, the high-band constant voltage circuit 200 is not affected by the startup time. Even if a low-pass filter, which is the second filter circuit, is connected, it does not depart from the object and scope of the present invention. In this case, the band of the low pass filter connected to the low band constant voltage circuit 100 is set lower than the band of the low pass filter connected to the high band constant voltage circuit 200. In addition, it is not always necessary to perform band limitation using a low-pass filter, and band limitation by another band limiting unit may be used. In addition, a low-pass filter is not configured with a band-limiting resistor and a band-limiting capacitor, but even when only a capacitive element for band-limiting is connected, the circuit output impedance of the previous stage of the band-limiting capacitor is used as a resistor, Therefore, the same effect as in the present embodiment can be obtained, and a resistance element can be dispensed with. Even in this case, not only the first capacitive element is connected to the low-band constant voltage circuit 100 but also the first capacitive element and the capacitance value are connected to the high-band constant voltage circuit 200 within a range that does not affect the startup time. Even the configuration in which the second capacitive elements having different values are connected does not depart from the object and scope of the present invention. In this case, the band of the low-pass filter composed of the first capacitor element is set lower than the band of the low-pass filter composed of the second capacitor element. Further, the number of voltage outputs is not limited, and there may be an arbitrary number of voltage outputs of 2 or more.
 電圧変換回路300は、平滑のための大きな容量を有することと、昇圧、あるいは降圧動作を行うために、スイッチング動作を繰り返す必要があることから、起動時間を要する。固体撮像装置1において、起動時間として許容できる時間は、例えば数十ms~数百msなど、アプリケーション等によって、様々ではあるが、必ず許容可能な起動遅延時間という制約が存在する。電圧変換回路300が起動するまでは、正常な撮像は行えないため、電圧変換回路300の起動遅延は、上記制約に影響を与えない範囲に抑制される必要がある。また、電圧変換回路300の起動遅延は、昇圧または降圧動作に要する時間と、基準電圧及び基準電流が正常に供給されるまでの時間とで決定される。 The voltage conversion circuit 300 requires a start-up time because it has a large capacity for smoothing and it is necessary to repeat the switching operation in order to perform the step-up or step-down operation. In the solid-state imaging device 1, the allowable time as the activation time varies depending on the application, such as several tens of ms to several hundred ms, but there is always a limitation of an allowable activation delay time. Since normal imaging cannot be performed until the voltage conversion circuit 300 is activated, the activation delay of the voltage conversion circuit 300 needs to be suppressed within a range that does not affect the above-described restriction. The startup delay of the voltage conversion circuit 300 is determined by the time required for the step-up or step-down operation and the time until the reference voltage and the reference current are normally supplied.
 本実施の形態では、電圧変換回路300への基準電圧供給には、高帯域定電圧回路200が用いられるため、定電圧回路自体の起動遅延は小さく、電圧変換回路300の起動は、低帯域定電圧回路100を用いた場合と比して、高速化される。電圧変換回路300の起動が高速化されることにより、起動時間に余裕が生じる分、電圧変換回路300として、スイッチサイズを縮小して、スイッチ経路の抵抗を上げる、あるいはスイッチング周波数を低下させるといったことも可能となる。この場合、スイッチング時の突入電流が減少し、スイッチング頻度が低下することにより、昇圧回路の発するスイッチングノイズ自体も減少させ、さらなる低ノイズ化を図ることができる。また、電圧変換回路300の生成電圧は、画素トランジスタのスイッチ電圧として論理動作目的で供給され、かつ、電圧変換回路300自体が一つの帯域制限を成すため生成電圧自体のノイズが画素出力に伝播する寄与度は低いので、帯域制限を行っていない基準電圧及び基準電流を供給しても画質として大きな問題とはならない。 In the present embodiment, since the high-band constant voltage circuit 200 is used for supplying the reference voltage to the voltage conversion circuit 300, the start-up delay of the constant voltage circuit itself is small, and the start-up of the voltage conversion circuit 300 is low-band constant. The speed is increased compared to the case where the voltage circuit 100 is used. Since the startup of the voltage conversion circuit 300 is speeded up, there is a margin in the startup time, so that the voltage conversion circuit 300 reduces the switch size, increases the resistance of the switch path, or decreases the switching frequency. Is also possible. In this case, the inrush current at the time of switching is reduced and the switching frequency is lowered, so that the switching noise itself generated by the booster circuit is also reduced, and the noise can be further reduced. The generated voltage of the voltage conversion circuit 300 is supplied as a switch voltage of the pixel transistor for the purpose of logical operation, and the voltage conversion circuit 300 itself forms one band limit, so that noise of the generated voltage itself propagates to the pixel output. Since the degree of contribution is low, supplying a reference voltage and a reference current that are not band-limited does not pose a major problem in image quality.
 一方で、読み出し電流源50と、読み出しトランジスタ34とで構成される画素ソースフォロアに混入したノイズは、画素出力に大きく伝播し、画質に大きく影響する。特に読み出し電流源50の基準電圧に混入したノイズは、全列に共通に影響するため、いわゆる横線ノイズとなり、画質への影響は非常に大きい。よって、読み出し電流源50への基準電圧は、ノイズを大きく制限する必要がある。 On the other hand, the noise mixed in the pixel source follower composed of the read current source 50 and the read transistor 34 is largely propagated to the pixel output and greatly affects the image quality. In particular, noise mixed in the reference voltage of the read current source 50 affects all the columns in common, so that it becomes so-called horizontal noise, and the influence on the image quality is very large. Therefore, the reference voltage to the read current source 50 needs to greatly limit noise.
 本実施の形態では、読み出し電流源50への基準電圧供給に、低帯域定電圧回路100を用いることで、基準電圧のノイズ量を抑制し、画素出力の低ノイズ化がなされる。また、帯域制限の影響により、定電圧回路自体の起動遅延自体が大きく、画素ソースフォロアの動作開始までの遅延は大きくなるが、電圧変換回路300の起動までに、画素ソースフォロアが起動していれば、固体撮像装置1としての起動時間には影響しない。この点、電圧変換回路300の起動と、低帯域定電圧回路100とは並列動作が可能である。したがって、電圧変換回路300の起動時間と、同一の数十ms~数百msといった起動時間を画素ソースフォロアに与えることができるため、低帯域定電圧回路100に対して、十分な帯域制限を行うことが可能となる。よって、固体撮像装置1としての起動時間を劣化させることなく、大きくノイズを削減することができる。 In this embodiment, by using the low-band constant voltage circuit 100 to supply the reference voltage to the read current source 50, the amount of noise of the reference voltage is suppressed, and the noise of the pixel output is reduced. In addition, due to the band limitation, the startup delay of the constant voltage circuit itself is large and the delay until the operation of the pixel source follower is increased. However, the pixel source follower has been started up before the voltage conversion circuit 300 is started up. For example, it does not affect the startup time of the solid-state imaging device 1. In this regard, the activation of the voltage conversion circuit 300 and the low-band constant voltage circuit 100 can be operated in parallel. Therefore, the start time of the voltage conversion circuit 300 and the same start time such as several tens ms to several hundred ms can be given to the pixel source follower, so that sufficient band limitation is performed on the low band constant voltage circuit 100. It becomes possible. Therefore, noise can be greatly reduced without degrading the startup time of the solid-state imaging device 1.
 以上述べたように、本実施の形態に係る固体撮像装置1は、少なくとも一つの高帯域定電圧回路200を備え、高帯域定電圧回路200で生成された第2電圧を、少なくとも電圧変換回路300にて使用する。また、固体撮像装置1は、少なくとも一つの低帯域定電圧回路100を備え、低帯域定電圧回路100で生成された第1電圧を、少なくとも読み出し電流源50にて使用する。これにより、固体撮像装置1としての起動時間と、低ノイズ化及び高ダイナミックレンジ化との両立が可能となる。 As described above, the solid-state imaging device 1 according to the present embodiment includes at least one high-band constant voltage circuit 200 and converts at least the voltage conversion circuit 300 using the second voltage generated by the high-band constant voltage circuit 200. Used in. In addition, the solid-state imaging device 1 includes at least one low-band constant voltage circuit 100 and uses at least the read current source 50 with the first voltage generated by the low-band constant voltage circuit 100. As a result, it is possible to achieve both a start-up time as the solid-state imaging device 1 and a reduction in noise and a high dynamic range.
 (実施の形態2)
 以下、図面を参照しながら、本発明の実施の形態2に係る固体撮像装置2の構成及び動作について説明する。なお、以下では、実施の形態1に係る固体撮像装置1との相違点についてのみ説明する。
(Embodiment 2)
Hereinafter, the configuration and operation of the solid-state imaging device 2 according to Embodiment 2 of the present invention will be described with reference to the drawings. Hereinafter, only differences from the solid-state imaging device 1 according to Embodiment 1 will be described.
 本実施の形態に係る固体撮像装置2は、実施の形態1に係る固体撮像装置1に対して、低帯域定電圧回路及び高帯域定電圧回路の代わりに、低帯域定電流回路及び高帯域定電流回路を使用するとうい点で異なる。また、電流源回路である読み出し電流源50へのゲート入力が基準電圧ではなく、読み出し電流源50がミラー回路を構成し、基準電流が読み出し電流源50への入力となる点で異なる。 The solid-state imaging device 2 according to the present embodiment is different from the solid-state imaging device 1 according to the first embodiment in that a low-band constant current circuit and a high-band constant voltage circuit are used instead of the low-band constant voltage circuit and the high-band constant voltage circuit. Use of the current circuit is different. Further, the difference is that the gate input to the read current source 50 which is a current source circuit is not a reference voltage, the read current source 50 forms a mirror circuit, and the reference current becomes an input to the read current source 50.
 図6は、本発明の実施の形態2に係る固体撮像装置2の構成を示すブロック図である。また、図7A及び図7Bは、それぞれ、本発明の実施の形態2に係る固体撮像装置2の有する低帯域定電流回路107及び高帯域定電流回路207の構成の第1の例を示すブロック図である。なお、図1と同様の要素については同一の符号が付されている。固体撮像装置2は、低帯域定電流回路107、高帯域定電流回路207及び読み出し電流源50への入力部を除いて、実施の形態1に係る固体撮像装置1と同じ構成を有している。 FIG. 6 is a block diagram showing a configuration of the solid-state imaging device 2 according to Embodiment 2 of the present invention. 7A and 7B are block diagrams showing first examples of the configurations of the low-band constant current circuit 107 and the high-band constant current circuit 207, respectively, included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. It is. In addition, the same code | symbol is attached | subjected about the element similar to FIG. The solid-state imaging device 2 has the same configuration as that of the solid-state imaging device 1 according to the first embodiment, except for the input unit to the low-band constant current circuit 107, the high-band constant current circuit 207, and the readout current source 50. .
 本実施の形態において、高帯域定電流回路207は、一般的なバンドギャップリファレンス回路105の出力に対して、VI変換回路500によって得られる電流を、帯域制限なく第2電流として出力する第2の定電流回路である。一方、低帯域定電流回路107は、一般的なバンドギャップリファレンス回路105の出力に対して、VI変換回路500によって得られる電流を、帯域制限容量101によって、帯域制限を行って第1電流として出力する第1の定電流回路である。なお、本実施の形態で例示するVI変換回路500及び帯域制限容量101の接続方法は一例であり、VI変換作用を有する回路であれば、VI変換回路500の構成を限定するものではない。例えば、単純なソース接地回路であってもよい。また、VI変換回路500の出力電流の帯域が制限されれば、VI変換回路の帯域制限方法を制限するものではない。例えば、帯域制限容量の接続ではなく、フィルタ回路をVI変換回路内に構成、もしくは接続しても良い。また、電流出力数は限定されるものではなく、2本以上の任意の電流出力数が存在しても良い。 In the present embodiment, the high-band constant current circuit 207 outputs the current obtained by the VI conversion circuit 500 as the second current without band limitation with respect to the output of the general bandgap reference circuit 105. It is a constant current circuit. On the other hand, the low-band constant current circuit 107 limits the band obtained by the VI conversion circuit 500 to the output of the general band gap reference circuit 105 by the band-limiting capacitor 101 and outputs it as the first current. The first constant current circuit. Note that the connection method between the VI conversion circuit 500 and the band limiting capacitor 101 exemplified in this embodiment is an example, and the configuration of the VI conversion circuit 500 is not limited as long as the circuit has a VI conversion function. For example, a simple source grounding circuit may be used. Further, if the band of the output current of the VI conversion circuit 500 is limited, the band limiting method of the VI conversion circuit is not limited. For example, the filter circuit may be configured or connected in the VI conversion circuit instead of the connection of the band limiting capacitor. Further, the number of current outputs is not limited, and there may be an arbitrary number of current outputs of two or more.
 高帯域定電流回路207は、帯域制限が行われていないため、ノイズ量は大きいが、定電流回路としての起動時間は高速となる。一方で、低帯域定電流回路107は、帯域制限を行うため、ノイズ量は小さく、低ノイズ回路としての使用が可能であるが、帯域制限容量101の充電遅延によって、定電流回路としての起動時間は低速となる。 The high-band constant current circuit 207 has a large amount of noise because the band is not limited, but the startup time as a constant-current circuit is fast. On the other hand, since the low-band constant current circuit 107 performs band limitation, the amount of noise is small, and the low-band constant current circuit 107 can be used as a low-noise circuit. Is slow.
 また、帯域制限容量101については、帯域を大きく制限するため、外付け容量の使用が好適であるが、必ずしも外付け容量である必要はなく、十分な帯域制限が行えれば、同一半導体基板上の容量を用いても本発明の目的と範囲を逸脱しない。また、本実施の形態では、VI変換回路の前段として、バンドギャップ回路を例示したが、電圧を生成する電圧源回路であれば、例えば抵抗分圧による電圧生成回路等であっても、本発明の目的と範囲を逸脱しない。また、本実施の形態では、低帯域定電流回路107のみに第1の容量素子である帯域制限容量101を接続した例を例示したが、起動時間に影響のない範囲で高帯域定電流回路207に第2の容量素子である帯域制限容量を接続しても、本発明の目的と範囲を逸脱しない。この場合には、低帯域定電流回路107に接続された帯域制限容量は、高帯域定電流回路207に接続された帯域制限容量よりも大きく設定されることとなる。また、フィルタ回路をVI変換回路内に構成もしくは接続して帯域制限する場合であっても、低帯域定電流回路107のみに第1のフィルタ回路を接続するだけでなく、起動時間に影響のない範囲で高帯域定電流回路207に第2のフィルタ回路を接続しても良い。この場合にも、低帯域定電流回路107に接続された帯域制限容量は、高帯域定電流回路207に接続された帯域制限容量よりも大きく設定されることとなる。 For the band limiting capacitor 101, it is preferable to use an external capacitor in order to greatly limit the band. However, it is not always necessary to use an external capacitor. The use of this capacity does not depart from the purpose and scope of the present invention. In the present embodiment, the band gap circuit is exemplified as the previous stage of the VI conversion circuit. However, the present invention is applicable to a voltage generation circuit that generates a voltage, for example, a voltage generation circuit using resistance voltage division. Does not deviate from the purpose and scope of In the present embodiment, an example in which the band limiting capacitor 101 as the first capacitor is connected only to the low-band constant current circuit 107 is illustrated. However, the high-band constant current circuit 207 is not affected by the start-up time. Even if the band limiting capacitor which is the second capacitor element is connected, it does not depart from the object and scope of the present invention. In this case, the band limiting capacity connected to the low band constant current circuit 107 is set larger than the band limiting capacity connected to the high band constant current circuit 207. Even when the band is limited by configuring or connecting the filter circuit in the VI conversion circuit, not only the first filter circuit is connected to the low-band constant current circuit 107 but also the start-up time is not affected. A second filter circuit may be connected to the high-band constant current circuit 207 in the range. Also in this case, the band limiting capacity connected to the low band constant current circuit 107 is set larger than the band limiting capacity connected to the high band constant current circuit 207.
 図8A及び図8Bは、それぞれ、本発明の実施の形態2に係る固体撮像装置2の有する低帯域定電流回路107及び高帯域定電流回路207の構成の第2の例を示すブロック図である。ここで、高帯域定電流回路207と低帯域定電流回路107とは、バンドギャップリファレンス回路105とVI変換回路500を用いるのではなく、図8A及び図8Bに例示するように、分圧回路701を用いて、電源電圧を分圧することによって電流を生成しても、本発明を逸脱しない。 8A and 8B are block diagrams illustrating a second example of the configuration of the low-band constant current circuit 107 and the high-band constant current circuit 207, respectively, included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. . Here, the high-band constant current circuit 207 and the low-band constant current circuit 107 do not use the band gap reference circuit 105 and the VI conversion circuit 500, but a voltage dividing circuit 701 as illustrated in FIGS. 8A and 8B. Even if the current is generated by dividing the power supply voltage by using, it does not depart from the present invention.
 また、電源電圧を分圧するのではなく、任意の固定電圧を分圧することで、電流を生成することも可能である。 It is also possible to generate a current by dividing an arbitrary fixed voltage instead of dividing the power supply voltage.
 固定電圧を分圧することによって電流を生成した場合においても、帯域制限容量705によって、低帯域定電流回路107を構成することが可能である。 Even when the current is generated by dividing the fixed voltage, the low-band constant current circuit 107 can be configured by the band-limiting capacitor 705.
 図8Aでは、帯域制限容量705によって、帯域を制限した例を図示したが、ゲート電圧にフィルタ回路を挿入する等、別の手段によって帯域制限を行っても良く、高帯域定電流回路207においても、低帯域定電流回路107よりも帯域が高ければ、帯域制限を行っていても、本発明を逸脱しない。 In FIG. 8A, an example in which the band is limited by the band limiting capacitor 705 is illustrated, but band limiting may be performed by another means such as inserting a filter circuit in the gate voltage. If the band is higher than that of the low-band constant current circuit 107, the present invention does not depart from the present invention even if the band is limited.
 図9A及び図9Bは、それぞれ、本発明の実施の形態2に係る固体撮像装置2の有する低帯域定電流回路107及び高帯域定電流回路207の構成の第3の例を示すブロック図である。図8A及び図8Bでは、抵抗とMOSトランジスタで分圧を行った例を例示したが、分圧回路に関しても、固定電圧の分圧による電流生成という要件を満たせば、本発明を逸脱しない。例えば、図9A及び図9Bに図示するように、直列接続された2つのMOSトランジスタで分圧を行う等、他の手段によって分圧を行い、電源電圧をはじめとする固定電圧から電流を生成しても、本発明を逸脱しない。 9A and 9B are block diagrams showing a third example of the configuration of the low-band constant current circuit 107 and the high-band constant current circuit 207, respectively, included in the solid-state imaging device 2 according to Embodiment 2 of the present invention. . 8A and 8B exemplify the example in which the voltage is divided by the resistor and the MOS transistor, but the voltage dividing circuit does not depart from the present invention as long as the requirement of current generation by dividing the fixed voltage is satisfied. For example, as shown in FIGS. 9A and 9B, voltage is divided by other means such as dividing by two MOS transistors connected in series, and a current is generated from a fixed voltage such as a power supply voltage. However, it does not depart from the present invention.
 電圧変換回路300は、前述のとおり、起動時間を要し、電圧変換回路300が起動するまでは、正常な撮像は行えないため、電圧変換回路300の起動遅延は、固体撮像装置2としての起動時間制約に影響を与えない範囲に抑制する必要がある。 As described above, the voltage conversion circuit 300 requires a startup time, and normal imaging cannot be performed until the voltage conversion circuit 300 is started. Therefore, the startup delay of the voltage conversion circuit 300 is the startup of the solid-state imaging device 2. It is necessary to limit to a range that does not affect the time constraint.
 本実施の形態では、電圧変換回路300への基準電流供給に、高帯域定電流回路207を用いるため、定電流回路自体の起動遅延は小さく、電圧変換回路300の起動は、低帯域定電流回路107を用いた場合と比して、高速化される。前述のとおり、電圧変換回路300の起動が高速化されることにより、スイッチング時の突入電流の減少や、スイッチング頻度を低下させることが可能となり、昇圧回路の発するスイッチングノイズ自体も減少させ、さらなる低ノイズ化を図ることができる。また、前述のとおり、電圧変換回路300の生成電圧は、帯域制限を行っていない基準電圧及び基準電流を供給しても大きな問題とはならないが、画素ソースフォロアに混入したノイズは、画素出力に大きく伝播し、画質に大きく影響する。 In this embodiment, since the high-band constant current circuit 207 is used for supplying the reference current to the voltage conversion circuit 300, the start-up delay of the constant-current circuit itself is small, and the start-up of the voltage conversion circuit 300 is performed by the low-band constant current circuit. Compared with the case of using 107, the speed is increased. As described above, since the startup of the voltage conversion circuit 300 is accelerated, it is possible to reduce the inrush current at the time of switching and to reduce the switching frequency, and to reduce the switching noise itself generated by the booster circuit. Noise can be reduced. As described above, the generated voltage of the voltage conversion circuit 300 is not a big problem even if a reference voltage and a reference current that are not band-limited are supplied, but noise mixed in the pixel source follower is not output to the pixel output. Propagation greatly affects the image quality.
 本実施の形態では、読み出し電流源50への基準電流供給に、低帯域定電流回路107を用いることで、基準電流のノイズ量を抑制し、画素出力の低ノイズ化がなされる。また、帯域制限の影響により、定電流回路自体の起動遅延自体が大きく、画素ソースフォロアの動作開始までの遅延が大きくなる。この点、電圧変換回路300の起動と、低帯域定電流回路107とは並列動作が可能であり、電圧変換回路300の起動時間と同一の数十ms~数百msといった起動時間を画素ソースフォロアに与えることができる。よって、低帯域定電流回路107に対して、十分な帯域制限を行うことができ、固体撮像装置2としての起動時間を劣化させることなく、大きくノイズを削減することができる。 In the present embodiment, by using the low-band constant current circuit 107 for supplying the reference current to the read current source 50, the noise amount of the reference current is suppressed and the noise of the pixel output is reduced. In addition, due to the band limitation, the startup delay of the constant current circuit itself is large, and the delay until the operation of the pixel source follower is large. In this regard, the activation of the voltage conversion circuit 300 and the low-band constant current circuit 107 can be operated in parallel, and the activation time such as several tens ms to several hundreds ms, which is the same as the activation time of the voltage conversion circuit 300, is set as the pixel source follower. Can be given to. Therefore, sufficient band limitation can be performed on the low-band constant current circuit 107, and noise can be greatly reduced without deteriorating the startup time of the solid-state imaging device 2.
 以上述べたように、本実施の形態に係る固体撮像装置2は、少なくとも一つの高帯域定電流回路207を備え、高帯域定電流回路207で生成された第2電流を、少なくとも電圧変換回路300にて使用する。また、固体撮像装置2は、少なくとも一つの低帯域定電流回路107を備え、低帯域定電流回路107で生成された第1電流を、少なくとも読み出し電流源50にて使用する。これにより、固体撮像装置2としての起動時間と、低ノイズ化及び高ダイナミックレンジ化との両立が可能となる。 As described above, the solid-state imaging device 2 according to the present embodiment includes at least one high-band constant current circuit 207, and at least the voltage conversion circuit 300 converts the second current generated by the high-band constant current circuit 207. Used in. The solid-state imaging device 2 includes at least one low-band constant current circuit 107 and uses at least the read current source 50 the first current generated by the low-band constant current circuit 107. As a result, it is possible to achieve both a start-up time as the solid-state imaging device 2 and a low noise and high dynamic range.
 また、各列の画素ソースフォロアに対して、基準電圧ではなく、基準電流を供給するためにミラー回路を構成することで、読み出し電流源50のソース電位がノイズ等で変動した場合の画素出力へのノイズ伝播が抑制される。 In addition, by forming a mirror circuit to supply a reference current instead of a reference voltage to the pixel source followers in each column, the pixel output when the source potential of the read current source 50 fluctuates due to noise or the like can be obtained. Noise propagation is suppressed.
 (実施の形態3)
 以下、図面を参照しながら、本発明の実施の形態3に係る固体撮像装置3の構成及び動作について説明する。なお、以下では、実施の形態1に係る固体撮像装置1との相違点についてのみ説明する。
(Embodiment 3)
Hereinafter, the configuration and operation of the solid-state imaging device 3 according to Embodiment 3 of the present invention will be described with reference to the drawings. Hereinafter, only differences from the solid-state imaging device 1 according to Embodiment 1 will be described.
 本実施の形態に係る固体撮像装置3は、実施の形態1に係る固体撮像装置1に対して、低帯域定電圧回路及び高帯域定電圧回路の代わりに複数帯域定電圧回路400を使用するという点で異なる。 The solid-state imaging device 3 according to the present embodiment uses a multi-band constant voltage circuit 400 instead of the low-band constant voltage circuit and the high-band constant voltage circuit with respect to the solid-state imaging device 1 according to the first embodiment. It is different in point.
 図10は、本発明の実施の形態3に係る固体撮像装置3の構成を示すブロック図である。また、図11は、本発明の実施の形態3に係る固体撮像装置3の有する複数帯域定電圧回路400の構成を示すブロック図である。なお、図1と同様の要素については同一の符号が付されている。固体撮像装置3は、複数帯域定電圧回路400を除いて、実施の形態1に係る固体撮像装置1と同じ構成を有している。 FIG. 10 is a block diagram showing a configuration of the solid-state imaging device 3 according to Embodiment 3 of the present invention. FIG. 11 is a block diagram showing a configuration of a multiband constant voltage circuit 400 included in the solid-state imaging device 3 according to Embodiment 3 of the present invention. In addition, the same code | symbol is attached | subjected about the element similar to FIG. The solid-state imaging device 3 has the same configuration as the solid-state imaging device 1 according to Embodiment 1 except for the multiband constant voltage circuit 400.
 本実施の形態において、複数帯域定電圧回路400は、一般的なバンドギャップリファレンス回路105の単一出力に対して、帯域制限なく出力した高帯域定電圧出力と、帯域制限抵抗102及び帯域制限容量101によるローパスフィルタ103を挿入することにより帯域制限を行った低帯域定電圧出力とを備える第3の定電圧回路である。つまり、複数帯域定電圧回路400は、第1の定電圧回路である低帯域定電圧回路100と第2の定電圧回路である高帯域定電圧回路200とを含み、低帯域定電圧回路100の構成要素と高帯域定電圧回路200の構成要素とを一部共用し、低帯域定電圧回路からの定電圧と高帯域定電圧回路からの定電圧とを独立に出力する。また、本実施の形態では、バンドギャップ回路を例示したが、電圧を生成する電圧源回路であれば、例えば抵抗分圧による電圧生成回路等であっても、本発明の目的と範囲を逸脱しない。また、電圧出力数は限定されるものではなく、2本以上の任意の電圧出力数が存在しても良い。 In the present embodiment, the multi-band constant voltage circuit 400 includes a high-band constant voltage output that is output without band limitation, a band-limiting resistor 102, and a band-limiting capacitor with respect to a single output of a general band gap reference circuit 105. The third constant voltage circuit includes a low-band constant voltage output that is band-limited by inserting a low-pass filter 103 by 101. That is, the multi-band constant voltage circuit 400 includes a low-band constant voltage circuit 100 that is a first constant voltage circuit and a high-band constant voltage circuit 200 that is a second constant voltage circuit. Part of the components and the components of the high-band constant voltage circuit 200 are shared, and the constant voltage from the low-band constant voltage circuit and the constant voltage from the high-band constant voltage circuit are output independently. In this embodiment, the band gap circuit is exemplified. However, as long as the voltage source circuit generates voltage, for example, a voltage generation circuit using resistance voltage division does not depart from the object and scope of the present invention. . Further, the number of voltage outputs is not limited, and there may be an arbitrary number of voltage outputs of two or more.
 高帯域定電圧出力は、帯域制限が行われていないため、ノイズ量は大きいが、定電圧回路としての起動時間は高速となる。一方で、低帯域定電圧出力は、帯域制限を行うため、ノイズ量は小さく、低ノイズ回路としての使用が可能であるが、ローパスフィルタ103を構成する抵抗や容量によって、定電圧回路としての起動時間は低速となる。 The high-band constant voltage output has a large amount of noise because the band is not limited, but the startup time as a constant-voltage circuit is fast. On the other hand, the low-band constant voltage output is band-limited, so the amount of noise is small and can be used as a low-noise circuit. Time is slow.
 また、帯域制限容量101については、帯域を大きく制限するため、外付け容量の使用が好適であるが、必ずしも外付け容量である必要はなく、十分な帯域制限が行えれば、同一半導体基板上の容量を用いても本発明の目的と範囲を逸脱しない。また、本実施の形態では、低帯域定電圧出力のみに第1のフィルタ回路であるローパスフィルタを接続した例を例示したが、起動時間に影響のない範囲で高帯域定電圧出力に第2のフィルタ回路であるローパスフィルタを接続しても、本発明の目的と範囲を逸脱しない。この場合には、低帯域定電圧出力に接続されたローパスフィルタの帯域は、高帯域定電圧出力に接続されたローパスフィルタの帯域よりも低く設定されることとなる。また、必ずしも、ローパスフィルタにて帯域制限を行う必要性はなく、他の帯域制限手段による帯域制限であってもよい。さらに、帯域制限抵抗と帯域制限容量によってローパスフィルタを構成するのではなく、帯域制限のための容量素子のみを接続した場合であっても、帯域制限容量前段の回路出力インピーダンスを抵抗として、ローパスフィルタが構成されるため、本実施の形態と同様の効果が得られ、かつ抵抗素子が不要とできる。 For the band limiting capacitor 101, it is preferable to use an external capacitor in order to greatly limit the band. However, it is not always necessary to use an external capacitor. The use of this capacity does not depart from the purpose and scope of the present invention. In this embodiment, an example in which the low-pass filter, which is the first filter circuit, is connected only to the low-band constant voltage output, but the second high-band constant voltage output is not affected by the start-up time. Even if a low-pass filter, which is a filter circuit, is connected, it does not depart from the object and scope of the present invention. In this case, the band of the low-pass filter connected to the low-band constant voltage output is set lower than the band of the low-pass filter connected to the high-band constant voltage output. In addition, it is not always necessary to perform band limitation using a low-pass filter, and band limitation by another band limiting unit may be used. In addition, a low-pass filter is not configured with a band-limiting resistor and a band-limiting capacitor, but even when only a capacitive element for band-limiting is connected, the circuit output impedance of the previous stage of the band-limiting capacitor is used as a resistor, Therefore, the same effect as in the present embodiment can be obtained, and a resistance element can be dispensed with.
 なお、本実施の形態で例示する複数帯域定電圧回路400は一例であり、単一の定電圧回路から複数の帯域の定電圧出力が生成されれば、その詳細回路を制限するものではない。 Note that the multi-band constant voltage circuit 400 exemplified in this embodiment is an example, and if a constant voltage output of a plurality of bands is generated from a single constant voltage circuit, the detailed circuit is not limited.
 電圧変換回路300は、前述のとおり、起動時間を要し、電圧変換回路300が起動するまでは、正常な撮像は行えないため、電圧変換回路300の起動遅延は、固体撮像装置3としての起動時間制約に影響を与えない範囲に抑制する必要がある。 As described above, the voltage conversion circuit 300 requires a startup time, and normal imaging cannot be performed until the voltage conversion circuit 300 is started. Therefore, the startup delay of the voltage conversion circuit 300 is the startup of the solid-state imaging device 3. It is necessary to limit to a range that does not affect the time constraint.
 本実施の形態では、電圧変換回路300への基準電圧供給に、複数帯域定電圧回路400の高帯域定電圧出力を用いるため、定電圧回路自体の起動遅延は小さく、電圧変換回路300の起動は、低帯域電圧出力を用いた場合と比して、高速化される。前述のとおり、電圧変換回路300の起動が高速化されることにより、スイッチング時の突入電流の減少や、スイッチング頻度を低下させることが可能となり、昇圧回路の発するスイッチングノイズ自体も減少させ、さらなる低ノイズ化を図ることができる。また、前述のとおり、電圧変換回路300の生成電圧は、帯域制限を行っていない基準電圧及び基準電流を供給しても大きな問題とはならないが、画素ソースフォロアに混入したノイズは、画素出力に大きく伝播し、画質に大きく影響する。 In the present embodiment, since the high-band constant voltage output of the multi-band constant voltage circuit 400 is used to supply the reference voltage to the voltage conversion circuit 300, the start-up delay of the constant voltage circuit itself is small, and the start-up of the voltage conversion circuit 300 is Compared with the case where a low-band voltage output is used, the speed is increased. As described above, since the startup of the voltage conversion circuit 300 is accelerated, it is possible to reduce the inrush current at the time of switching and to reduce the switching frequency, and to reduce the switching noise itself generated by the booster circuit. Noise can be reduced. As described above, the generated voltage of the voltage conversion circuit 300 is not a big problem even if a reference voltage and a reference current that are not band-limited are supplied, but noise mixed in the pixel source follower is not output to the pixel output. Propagation greatly affects the image quality.
 本実施の形態では、読み出し電流源50への基準電圧供給に、低帯域定電圧出力を用いることで、基準電圧のノイズ量を抑制し、画素出力の低ノイズ化がなされる。また、帯域制限の影響により、定電圧回路自体の起動遅延自体が大きく、画素ソースフォロアの動作開始までの遅延が大きくなる。この点、電圧変換回路300の起動と、低帯域定電圧出力と、は並列動作が可能であり、電圧変換回路300の起動時間と同一の数十ms~数百msといった起動時間を画素ソースフォロアに与えることができる。よって、低帯域定電圧出力に対して、十分な帯域制限を行うことができ、固体撮像装置3としての起動時間を劣化させることなく、大きくノイズを削減することができる。 In this embodiment, by using a low-band constant voltage output for supplying the reference voltage to the read current source 50, the amount of noise of the reference voltage is suppressed, and the noise of the pixel output is reduced. Further, due to the band limitation, the start-up delay of the constant voltage circuit itself is large, and the delay until the operation of the pixel source follower is large. In this respect, the start-up of the voltage conversion circuit 300 and the low-band constant-voltage output can be performed in parallel, and the start-up time such as several tens to several hundreds of ms that is the same as the start-up time of the voltage conversion circuit 300 Can be given to. Therefore, sufficient band limitation can be performed on the low-band constant voltage output, and noise can be greatly reduced without degrading the startup time as the solid-state imaging device 3.
 以上述べたように、本実施の形態に係る固体撮像装置3は、複数帯域定電圧回路400を備え、複数帯域定電圧回路400で生成された第2電圧である高帯域定電圧を、少なくとも電圧変換回路300にて使用する。また、固体撮像装置3は、複数帯域定電圧回路400で生成された第1電圧である低帯域定電圧を、少なくとも読み出し電流源50にて使用する。これにより、固体撮像装置3としての起動時間と、低ノイズ化及び高ダイナミックレンジ化との両立が可能となる。 As described above, the solid-state imaging device 3 according to the present embodiment includes the multi-band constant voltage circuit 400, and at least the high-band constant voltage that is the second voltage generated by the multi-band constant voltage circuit 400 is at least a voltage. Used in the conversion circuit 300. The solid-state imaging device 3 uses at least the read current source 50 with the low-band constant voltage that is the first voltage generated by the multi-band constant voltage circuit 400. As a result, it is possible to achieve both a start-up time as the solid-state imaging device 3 and a low noise and high dynamic range.
 (実施の形態4)
 以下、図面を参照しながら、本発明の実施の形態4に係る固体撮像装置4の構成及び動作について説明する。なお、以下では、実施の形態1に係る固体撮像装置1との相違点についてのみ説明する。
(Embodiment 4)
Hereinafter, the configuration and operation of the solid-state imaging device 4 according to Embodiment 4 of the present invention will be described with reference to the drawings. Hereinafter, only differences from the solid-state imaging device 1 according to Embodiment 1 will be described.
 本実施の形態に係る固体撮像装置4は、実施の形態2に係る固体撮像装置2に対して、低帯域定電流回路及び高帯域定電流回路の代わりに、複数帯域定電流回路407を使用するという点で異なる。また、読み出し電流源50へのゲート入力が基準電圧ではなく、読み出し電流源50がミラー回路を構成し、基準電流が読み出し電流源50への入力となる点で異なる。 The solid-state imaging device 4 according to the present embodiment uses a multi-band constant current circuit 407 instead of the low-band constant current circuit and the high-band constant current circuit with respect to the solid-state imaging device 2 according to the second embodiment. It is different in that. Also, the gate input to the read current source 50 is not a reference voltage, the read current source 50 forms a mirror circuit, and the reference current becomes an input to the read current source 50.
 図12は、本発明の実施の形態4に係る固体撮像装置4の構成を示すブロック図である。また、図13は本発明の実施の形態4に係る固体撮像装置4の有する複数帯域定電流回路407の構成を示すブロック図である。なお、図2と同様の要素については同一の符号が付されており、それらに関する詳しい説明はここでは省略する。この固体撮像装置4は、複数帯域定電流回路407を除いて、実施の形態2に係る固体撮像装置2と同じ構成を有している。 FIG. 12 is a block diagram showing a configuration of the solid-state imaging device 4 according to Embodiment 4 of the present invention. FIG. 13 is a block diagram showing a configuration of a multiband constant current circuit 407 included in the solid-state imaging device 4 according to Embodiment 4 of the present invention. The same elements as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted here. The solid-state imaging device 4 has the same configuration as the solid-state imaging device 2 according to the second embodiment except for the multi-band constant current circuit 407.
 本実施の形態において、複数帯域定電流回路407は、第4の定電圧回路である一般的なバンドギャップリファレンス回路105の単一出力に対して、第2の電圧電流変換回路であるVI変換回路500によって得られる電流を帯域制限なく出力した高帯域定電流出力と、第1の電圧電流変換回路であるVI変換回路500によって得られる電流を帯域制限容量101により帯域制限を行った低帯域定電流出力とを備える第3の定電流回路である。つまり、複数帯域定電流回路407は、第1の定電流回路である低帯域定電流回路107と第2の定電流回路である高帯域定電流回路207とを含み、低帯域定電流回路107と高帯域定電流回路207との共通構成要素であるバンドギャップリファレンス回路105を共用し、低帯域定電流回路からの定電流と高帯域定電流回路からの定電流とを独立に出力する。なお、本実施の形態で例示するVI変換回路500及び帯域制限容量101の接続方法は一例であり、VI変換作用を有する回路であれば、VI変換回路500の構成を限定するものではない。例えば、単純なソース接地回路であってもよい。また、VI変換回路500の出力電流の帯域が制限されれば、VI変換回路の帯域制限方法を制限するものではない。例えば、帯域制限容量の接続ではなく、フィルタ回路をVI変換回路内に構成または接続しても良い。また、電流出力数は限定されるものではなく、2本以上の任意の電流出力数が存在しても良い。 In the present embodiment, the multi-band constant current circuit 407 is a VI conversion circuit that is a second voltage-current conversion circuit for a single output of a general bandgap reference circuit 105 that is a fourth constant voltage circuit. 500, a high-band constant current output in which the current obtained by 500 is output without band limitation, and a low-band constant current in which the current obtained by the VI conversion circuit 500, which is the first voltage-current conversion circuit, is band-limited by the band-limiting capacitor 101. And a third constant current circuit having an output. That is, the multi-band constant current circuit 407 includes a low-band constant current circuit 107 that is a first constant current circuit and a high-band constant current circuit 207 that is a second constant current circuit. The band gap reference circuit 105 which is a common component with the high-band constant current circuit 207 is shared, and the constant current from the low-band constant current circuit and the constant current from the high-band constant current circuit are output independently. Note that the connection method between the VI conversion circuit 500 and the band limiting capacitor 101 exemplified in this embodiment is an example, and the configuration of the VI conversion circuit 500 is not limited as long as the circuit has a VI conversion function. For example, a simple source grounding circuit may be used. Further, if the band of the output current of the VI conversion circuit 500 is limited, the band limiting method of the VI conversion circuit is not limited. For example, the filter circuit may be configured or connected in the VI conversion circuit instead of the connection of the band limiting capacitor. Further, the number of current outputs is not limited, and there may be an arbitrary number of current outputs of two or more.
 高帯域定電流出力は、帯域制限が行われていないため、ノイズ量は大きいが、定電流回路としての起動時間は高速となる。一方で、低帯域定電流出力は、帯域制限を行うため、ノイズ量は小さく、低ノイズ回路としての使用が可能であるが、帯域制限容量101の充電遅延によって、定電流回路としての起動時間は低速となる。 The high-band constant current output has a large amount of noise because the band is not limited, but the startup time as a constant-current circuit is fast. On the other hand, the low-band constant current output is band-limited, so the amount of noise is small and can be used as a low-noise circuit. However, due to the charging delay of the band-limiting capacitor 101, the startup time as a constant-current circuit is Slow.
 また、帯域制限容量101については、帯域を大きく制限するため、外付け容量の使用が好適であるが、必ずしも外付け容量である必要はなく、十分な帯域制限が行えれば、同一半導体基板上の容量を用いても本発明の目的と範囲を逸脱しない。また、本実施の形態では、バンドギャップ回路を例示したが、電圧を生成する電圧源回路であれば、例えば抵抗分圧による電圧生成回路等であっても、本発明の目的と範囲を逸脱しない。本実施の形態では、低帯域定電流出力を出力するVI変換回路のみに第3の容量素子である帯域制限容量を接続した例を例示したが、起動時間に影響のない範囲で高帯域定電流出力を出力するVI変換回路に第4の容量素子である帯域制限容量を接続しても、本発明の目的と範囲を逸脱しない。この場合には、低帯域定電流出力を出力するVI変換回路に接続された帯域制限容量は高帯域定電流出力を出力するVI変換回路に接続された帯域制限容量よりも大きく設定されることとなる。また、フィルタ回路をVI変換回路内に構成もしくは接続して帯域制限する場合であっても、低帯域定電流出力を出力するVI変換回路のみに第3のフィルタ回路を接続するだけでなく、起動時間に影響のない範囲で高帯域定電流出力を出力するVI変換回路に第4のフィルタ回路を接続しても良い。この場合にも、低帯域定電流出力の帯域は、高帯域定電流出力の帯域よりも低く設定されることとなる。 For the band limiting capacitor 101, it is preferable to use an external capacitor in order to greatly limit the band. However, it is not always necessary to use an external capacitor. The use of this capacity does not depart from the purpose and scope of the present invention. In this embodiment, the band gap circuit is exemplified. However, as long as the voltage source circuit generates voltage, for example, a voltage generation circuit using resistance voltage division does not depart from the object and scope of the present invention. . In the present embodiment, the example in which the band limiting capacitor, which is the third capacitor element, is connected only to the VI conversion circuit that outputs the low-band constant current output. However, the high-band constant current is not affected by the start-up time. Even if a band limiting capacitor, which is the fourth capacitor element, is connected to the VI conversion circuit that outputs the output, it does not depart from the object and scope of the present invention. In this case, the band limiting capacity connected to the VI conversion circuit that outputs the low-band constant current output is set to be larger than the band limiting capacity connected to the VI conversion circuit that outputs the high-band constant current output. Become. Even if the band is limited by configuring or connecting the filter circuit in the VI conversion circuit, not only the third filter circuit is connected to the VI conversion circuit that outputs a low-band constant current output, but also the startup. A fourth filter circuit may be connected to a VI conversion circuit that outputs a high-band constant current output within a range that does not affect time. Also in this case, the low-band constant current output band is set lower than the high-band constant current output band.
 電圧変換回路300は、前述のとおり、起動時間を要し、電圧変換回路300が起動するまでは、正常な撮像は行えないため、電圧変換回路300の起動遅延は、固体撮像装置4としての起動時間制約に影響を与えない範囲に抑制する必要がある。 As described above, the voltage conversion circuit 300 requires a start-up time, and normal imaging cannot be performed until the voltage conversion circuit 300 is started. Therefore, the start-up delay of the voltage conversion circuit 300 is the start-up of the solid-state imaging device 4. It is necessary to limit to a range that does not affect the time constraint.
 本実施の形態では、電圧変換回路300への基準電流供給に、複数帯域定電流回路407の高帯域定電流出力を用いるため、定電流回路自体の起動遅延は小さく、電圧変換回路300の起動は、低帯域定電流出力を用いた場合と比して、高速化される。前述のとおり、電圧変換回路300の起動が高速化されることにより、スイッチング時の突入電流の減少や、スイッチング頻度を低下させることが可能となり、昇圧回路の発するスイッチングノイズ自体も減少させ、さらなる低ノイズ化を図ることができる。また、前述のとおり、電圧変換回路300の生成電圧は、帯域制限を行っていない基準電圧及び基準電流を供給しても大きな問題とはならないが、画素ソースフォロアに混入したノイズは、画素出力に大きく伝播し、画質に大きく影響する。 In this embodiment, since the high-band constant current output of the multi-band constant current circuit 407 is used to supply the reference current to the voltage conversion circuit 300, the start-up delay of the constant current circuit itself is small, and the start-up of the voltage conversion circuit 300 is Compared with the case where a low-band constant current output is used, the speed is increased. As described above, since the startup of the voltage conversion circuit 300 is accelerated, it is possible to reduce the inrush current at the time of switching and to reduce the switching frequency, and to reduce the switching noise itself generated by the booster circuit. Noise can be reduced. As described above, the generated voltage of the voltage conversion circuit 300 is not a big problem even if a reference voltage and a reference current that are not band-limited are supplied, but noise mixed in the pixel source follower is not output to the pixel output. Propagation greatly affects the image quality.
 本実施の形態では、読み出し電流源50への基準電流供給に、低帯域定電流出力を用いることで、基準電流のノイズ量を抑制し、画素出力の低ノイズ化がなされる。また、帯域制限の影響により、定電流回路自体の起動遅延自体が大きく、画素ソースフォロアの動作開始までの遅延が大きくなる。この点、電圧変換回路300の起動と、低帯域定電流出力とは並列動作が可能であり、電圧変換回路300の起動時間と同一の数十ms~数百msといった起動時間を画素ソースフォロアに与えることができる。よって、低帯域定電流出力に対して、十分な帯域制限を行うことができ、固体撮像装置4としての起動時間を劣化させることなく、大きくノイズを削減することができる。 In this embodiment, by using a low-band constant current output for supplying the reference current to the read current source 50, the amount of noise of the reference current is suppressed, and the noise of the pixel output is reduced. In addition, due to the band limitation, the startup delay of the constant current circuit itself is large, and the delay until the operation of the pixel source follower is large. In this respect, the startup of the voltage conversion circuit 300 and the low-band constant current output can be operated in parallel. Can be given. Therefore, sufficient band limitation can be performed on the low-band constant current output, and noise can be greatly reduced without degrading the startup time as the solid-state imaging device 4.
 以上述べたように、本実施の形態に係る固体撮像装置4は、複数帯域定電流回路407を備え、複数帯域定電流回路407で生成された第2電流である高帯域定電流を、少なくとも電圧変換回路300にて使用する。また、固体撮像装置4は、複数帯域定電圧回路400で生成された第1電流である低帯域定電流を、少なくとも読み出し電流源50に使用する。これにより、固体撮像装置4としての起動時間と、低ノイズ化及び高ダイナミックレンジ化との両立が可能となる。 As described above, the solid-state imaging device 4 according to the present embodiment includes the multi-band constant current circuit 407, and at least the high-band constant current that is the second current generated by the multi-band constant current circuit 407 is at least a voltage. Used in the conversion circuit 300. Further, the solid-state imaging device 4 uses the low-band constant current that is the first current generated by the multi-band constant voltage circuit 400 for at least the read current source 50. As a result, it is possible to achieve both a start-up time as the solid-state imaging device 4 and a reduction in noise and a high dynamic range.
 また、各列の画素ソースフォロアに対して、基準電圧ではなく、基準電流を供給するためにミラー回路を構成することで、読み出し電流源50のソース電位がノイズ等で変動した場合の画素出力へのノイズ伝播が抑制される。 In addition, by forming a mirror circuit to supply a reference current instead of a reference voltage to the pixel source followers in each column, the pixel output when the source potential of the read current source 50 fluctuates due to noise or the like can be obtained. Noise propagation is suppressed.
 以上、実施の形態1~4について説明してきたが、本発明に係る固体撮像装置は、上記実施の形態に限定されるものではない。実施の形態1~4における任意の構成要素を組み合わせて実現される別の実施の形態や、実施の形態1~4に対して本発明の主旨を逸脱しない範囲で当業者が思いつく各種変形を施して得られる変形例や、本発明に係る固体撮像装置を内蔵した各種機器も本発明に含まれる。 Although the first to fourth embodiments have been described above, the solid-state imaging device according to the present invention is not limited to the above-described embodiments. Other embodiments realized by combining arbitrary constituent elements in the first to fourth embodiments, and various modifications conceivable by those skilled in the art without departing from the gist of the present invention to the first to fourth embodiments. Modifications obtained in this way and various devices incorporating the solid-state imaging device according to the present invention are also included in the present invention.
 なお、本発明の実施の形態に係る固体撮像装置1~4において、単位画素5は、それぞれ1つのフォトダイオード、転送トランジスタ、フローティングディフュージョン、リセットトランジスタ及び増幅トランジスタを有する構造、いわゆる1画素1セル構造をとっている。しかし、本発明の固体撮像装置は、上記1画素1セル構造のほか、複数のフォトダイオードを含み、さらに、フローティングディフュージョン、リセットトランジスタ及び増幅トランジスタのいずれか、あるいは、すべてを単位セル内で共有する構造、いわゆる多画素1セル構造を用いることが出来る。 In the solid-state imaging devices 1 to 4 according to the embodiments of the present invention, each unit pixel 5 has a structure having one photodiode, a transfer transistor, a floating diffusion, a reset transistor, and an amplification transistor, so-called one-pixel one-cell structure. Have taken. However, the solid-state imaging device of the present invention includes a plurality of photodiodes in addition to the one-pixel / one-cell structure, and further shares any one or all of the floating diffusion, the reset transistor, and the amplification transistor in the unit cell. A structure, a so-called multi-pixel 1-cell structure can be used.
 また、本発明の固体撮像装置1~4は、フォトダイオードが半導体基板の表面、すなわち、トランジスタのゲート端子及び配線が形成された面と同じ面側に形成される構造であってもよいし、フォトダイオードが半導体基板の裏面、すなわちトランジスタのゲート端子及び配線が形成された面に対して裏面側に形成される、いわゆる、裏面照射型イメージセンサ(裏面照射型固体撮像装置)の構造を用いることも出来る。 The solid-state imaging devices 1 to 4 of the present invention may have a structure in which the photodiode is formed on the surface of the semiconductor substrate, that is, on the same side as the surface on which the gate terminal and the wiring of the transistor are formed. Use a so-called back-illuminated image sensor (back-illuminated solid-state imaging device) structure in which the photodiode is formed on the back surface side of the semiconductor substrate, that is, the surface on which the gate terminal and wiring of the transistor are formed. You can also.
 本発明に係る固体撮像装置は、高速起動、低ノイズ及び高ダイナミックレンジ等の高画質が求められるデジタルスチルカメラ及びデジタルビデオカメラ等として有用である。 The solid-state imaging device according to the present invention is useful as a digital still camera, a digital video camera, and the like that require high image quality such as high-speed startup, low noise, and high dynamic range.
 1、2、3、4、1000  固体撮像装置
 5、1003  単位画素
 10、1010  画素アレイ
 30、1030  フォトダイオード
 31、1031  転送トランジスタ
 32、1032  リセットトランジスタ
 33、1033  選択トランジスタ
 34、1034  読み出しトランジスタ
 40  垂直走査回路
 41、1041  転送トランジスタ制御線
 42、1042  リセットトランジスタ制御線
 43、1043  選択トランジスタ制御線
 44  デコーダ
 45、1045  垂直信号線
 47  垂直ドライバ
 50、1050  読み出し電流源
 55、1062  水平信号線
 56  カラムADC
 57  参照信号生成部
 60  水平走査回路
 61、1061  水平選択トランジスタ
 65  水平制御線
 67  出力回路
 70  タイミング制御部
 100  低帯域定電圧回路
 101、705、706  帯域制限容量
 102  帯域制限抵抗
 103  ローパスフィルタ
 105  バンドギャップリファレンス回路
 107  低帯域定電流回路
 200  高帯域定電圧回路
 207  高帯域定電流回路
 300  電圧変換回路
 301  比較回路
 400  複数帯域定電圧回路
 407  複数帯域定電流回路
 415  電圧比較部
 416  カウント部
 418  メモリ部
 500  VI変換回路
 701、702  分圧回路
 1040  垂直走査部
 1060  水平走査部
 1069  アンプ
 1080  AD変換部
 1090  信号処理部
 1100  昇圧回路
1, 2, 3, 4, 1000 Solid- state imaging device 5, 1003 Unit pixel 10, 1010 Pixel array 30, 1030 Photodiode 31, 1031 Transfer transistor 32, 1032 Reset transistor 33, 1033 Select transistor 34, 1034 Read transistor 40 Vertical scan Circuit 41, 1041 Transfer transistor control line 42, 1042 Reset transistor control line 43, 1043 Selection transistor control line 44 Decoder 45, 1045 Vertical signal line 47 Vertical driver 50, 1050 Read current source 55, 1062 Horizontal signal line 56 Column ADC
57 Reference signal generation unit 60 Horizontal scanning circuit 61, 1061 Horizontal selection transistor 65 Horizontal control line 67 Output circuit 70 Timing control unit 100 Low-band constant voltage circuit 101, 705, 706 Band-limiting capacitor 102 Band-limiting resistor 103 Low-pass filter 105 Band gap Reference circuit 107 Low-band constant current circuit 200 High-band constant voltage circuit 207 High-band constant current circuit 300 Voltage conversion circuit 301 Comparison circuit 400 Multi-band constant voltage circuit 407 Multi-band constant current circuit 415 Voltage comparison unit 416 Count unit 418 Memory unit 500 VI conversion circuit 701, 702 Voltage dividing circuit 1040 Vertical scanning unit 1060 Horizontal scanning unit 1069 Amplifier 1080 AD conversion unit 1090 Signal processing unit 1100 Booster circuit

Claims (17)

  1.  行列状に配置され、光を信号電圧に変換する複数の画素と、
     画素列ごとに設けられた垂直信号線と、
     画素列ごとに設けられ、第1電圧が供給されることにより前記垂直信号線に前記信号電圧を読み出すための電流を供給する電流源回路と、
     第2電圧が供給されることにより電源電圧とは異なる電圧を生成する電圧変換回路と、
     前記電圧変換回路で生成された電圧を用いて前記複数の画素を行順次に駆動し、対応する行内の画素から前記垂直信号線及び前記電流源回路を介して前記信号電圧を読み出す垂直走査回路と、
     前記電流源回路に前記第2電圧よりも高周波成分が除去された前記第1電圧を供給する第1の定電圧回路と、
     前記電圧変換回路に、前記第2電圧を供給する第2の定電圧回路とを備える
     固体撮像装置。
    A plurality of pixels arranged in a matrix and converting light into a signal voltage;
    A vertical signal line provided for each pixel column;
    A current source circuit that is provided for each pixel column and supplies a current for reading the signal voltage to the vertical signal line by supplying a first voltage;
    A voltage conversion circuit that generates a voltage different from the power supply voltage by being supplied with the second voltage;
    A vertical scanning circuit that drives the plurality of pixels in a row sequence using the voltage generated by the voltage conversion circuit, and reads the signal voltage from the pixels in the corresponding row via the vertical signal line and the current source circuit; ,
    A first constant voltage circuit for supplying the first voltage from which a high frequency component is removed from the second voltage to the current source circuit;
    A solid-state imaging device comprising: a second constant voltage circuit that supplies the second voltage to the voltage conversion circuit.
  2.  さらに、
     前記第1の定電圧回路に接続される第1の容量素子と、
     前記第2の定電圧回路に接続され、前記第1の容量素子と容量値が異なる第2の容量素子とを備える
     請求項1に記載の固体撮像装置。
    further,
    A first capacitive element connected to the first constant voltage circuit;
    The solid-state imaging device according to claim 1, further comprising a second capacitor element connected to the second constant voltage circuit and having a capacitance value different from that of the first capacitor element.
  3.  さらに、
     前記第1の定電圧回路に接続される第1のフィルタ回路と、
     前記第2の定電圧回路に接続され、前記第1のフィルタ回路よりも高い通過帯域を有する第2のフィルタ回路とを備える
     請求項1に記載の固体撮像装置。
    further,
    A first filter circuit connected to the first constant voltage circuit;
    The solid-state imaging device according to claim 1, further comprising: a second filter circuit connected to the second constant voltage circuit and having a higher passband than the first filter circuit.
  4.  前記第1の定電圧回路及び前記第2の定電圧回路の一方は、容量素子が接続されており、
     前記第1の定電圧回路及び前記第2の定電圧回路の他方は、容量素子が接続されていない
     請求項1に記載の固体撮像装置。
    A capacitor element is connected to one of the first constant voltage circuit and the second constant voltage circuit,
    The solid-state imaging device according to claim 1, wherein a capacitive element is not connected to the other of the first constant voltage circuit and the second constant voltage circuit.
  5.  前記第1の定電圧回路には、フィルタ回路が接続されており、
     前記第2の定電圧回路には、フィルタ回路が接続されていない
     請求項1に記載の固体撮像装置。
    A filter circuit is connected to the first constant voltage circuit,
    The solid-state imaging device according to claim 1, wherein a filter circuit is not connected to the second constant voltage circuit.
  6.  前記第1の定電圧回路と前記第2の定電圧回路とは、第3の定電圧回路に含まれ、
     前記第3の定電圧回路は、前記第1の定電圧回路の構成要素と前記第2の定電圧回路の構成要素とを一部共用し、前記第1の定電圧回路からの前記第1電圧と前記第2の定電圧回路からの前記第2電圧とを独立に出力する
     請求項1~5のいずれか1項に記載の固体撮像装置。
    The first constant voltage circuit and the second constant voltage circuit are included in a third constant voltage circuit,
    The third constant voltage circuit partially shares components of the first constant voltage circuit and components of the second constant voltage circuit, and the first voltage from the first constant voltage circuit. 6. The solid-state imaging device according to claim 1, wherein the first voltage and the second voltage from the second constant voltage circuit are independently output.
  7.  行列状に配置され、光を信号電圧に変換する複数の画素と、
     画素列ごとに設けられた複数の垂直信号線と、
     画素列ごとに設けられ、第1電流が供給されることにより前記垂直信号線に前記信号電圧を読み出すための電流を供給する電流源回路と、
     第2電流が供給されることにより電源電圧とは異なる電圧を生成する電圧変換回路と、
     前記電圧変換回路で生成された電圧を用いて前記複数の画素を行順次に駆動し、対応する行内の画素から前記垂直信号線及び前記電流源回路を介して前記信号電圧を読み出す垂直走査回路と、
     前記電流源回路に前記第2電流よりも高周波成分が除去された前記第1電流を供給する第1の定電流回路と、
     前記電圧変換回路に、前記第2電流を供給する第2の定電流回路とを備える
     固体撮像装置。
    A plurality of pixels arranged in a matrix and converting light into a signal voltage;
    A plurality of vertical signal lines provided for each pixel column;
    A current source circuit that is provided for each pixel column and supplies a current for reading the signal voltage to the vertical signal line by supplying a first current;
    A voltage conversion circuit that generates a voltage different from the power supply voltage by supplying the second current;
    A vertical scanning circuit that drives the plurality of pixels in a row sequence using the voltage generated by the voltage conversion circuit, and reads the signal voltage from the pixels in the corresponding row via the vertical signal line and the current source circuit; ,
    A first constant current circuit for supplying the current source circuit with the first current from which a higher frequency component is removed than the second current;
    A solid-state imaging device comprising: a second constant current circuit that supplies the second current to the voltage conversion circuit.
  8.  さらに、
     前記第1の定電流回路に接続される第1の容量素子と、
     前記第2の定電流回路に接続され、前記第1の容量素子と容量値が異なる第2の容量素子とを備える
     請求項7に記載の固体撮像装置。
    further,
    A first capacitive element connected to the first constant current circuit;
    The solid-state imaging device according to claim 7, further comprising a second capacitor element connected to the second constant current circuit and having a capacitance value different from that of the first capacitor element.
  9.  さらに、
     前記第1の定電流回路に接続される第1のフィルタ回路と、
     前記第2の定電流回路に接続され、前記第1のフィルタ回路よりも高い通過帯域を有する第2のフィルタ回路とを備える
     請求項7に記載の固体撮像装置。
    further,
    A first filter circuit connected to the first constant current circuit;
    The solid-state imaging device according to claim 7, further comprising: a second filter circuit connected to the second constant current circuit and having a higher pass band than the first filter circuit.
  10.  前記第1の定電流回路及び前記第2の定電流回路の一方は、容量素子が接続されており、
     前記第1の定電流回路及び前記第2の定電流回路の他方は、容量素子が接続されていない
     請求項7に記載の固体撮像装置。
    A capacitor element is connected to one of the first constant current circuit and the second constant current circuit,
    The solid-state imaging device according to claim 7, wherein a capacitive element is not connected to the other of the first constant current circuit and the second constant current circuit.
  11.  前記第1の定電流回路には、フィルタ回路が接続されており、
     前記第2の定電流回路には、フィルタ回路が接続されていない
     請求項7に記載の固体撮像装置。
    A filter circuit is connected to the first constant current circuit,
    The solid-state imaging device according to claim 7, wherein a filter circuit is not connected to the second constant current circuit.
  12.  前記第1の定電流回路及び前記第2の定電流回路の少なくとも一方は、電圧を分圧することにより電流を生成する定電流回路である
     請求項7~11のいずれか1項に記載の固体撮像装置。 
    12. The solid-state imaging according to claim 7, wherein at least one of the first constant current circuit and the second constant current circuit is a constant current circuit that generates a current by dividing a voltage. apparatus.
  13.  前記第1の定電流回路は、第4の定電圧回路及び第1の電圧電流変換回路から構成され、
     前記第2の定電流回路は、前記第4の定電圧回路及び第2の電圧電流変換回路から構成され、
     前記第1の定電流回路と前記第2の定電流回路とは、第3の定電流回路に含まれ、
     前記第3の定電流回路は、前記第1の定電流回路と前記第2の定電圧回路とで前記第4の定電圧回路を共用し、前記第1の定電流回路からの前記第1定電流と前記第2の定電流回路からの前記第2電流とを独立に出力する
     請求項7に記載の固体撮像装置。
    The first constant current circuit includes a fourth constant voltage circuit and a first voltage / current conversion circuit,
    The second constant current circuit includes the fourth constant voltage circuit and a second voltage / current conversion circuit,
    The first constant current circuit and the second constant current circuit are included in a third constant current circuit,
    In the third constant current circuit, the first constant current circuit and the second constant voltage circuit share the fourth constant voltage circuit, and the first constant current circuit outputs the first constant current circuit. The solid-state imaging device according to claim 7, wherein a current and the second current from the second constant current circuit are independently output.
  14.  さらに、
     前記第1の電圧電流変換回路に接続される第3の容量素子と、
     前記第2の電圧電流変換回路に接続され、前記第3の容量素子と容量値が異なる第4の容量素子とを備える
     請求項13に記載の固体撮像装置。
    further,
    A third capacitive element connected to the first voltage-current conversion circuit;
    The solid-state imaging device according to claim 13, further comprising: a fourth capacitor element connected to the second voltage-current conversion circuit and having a capacitance value different from that of the third capacitor element.
  15.  さらに、
     前記第1の電圧電流変換回路に接続される第3のフィルタ回路と、
     前記第2の電圧電流変換回路に接続され、前記第3のフィルタ回路よりも高い通過帯域を有する第4のフィルタ回路とを備える
     請求項13に記載の固体撮像装置。
    further,
    A third filter circuit connected to the first voltage-current converter circuit;
    The solid-state imaging device according to claim 13, further comprising: a fourth filter circuit connected to the second voltage-current conversion circuit and having a higher passband than the third filter circuit.
  16.  前記第1の電圧電流変換回路及び前記第2の電圧電流変換回路の一方は、容量素子が接続されており、
     前記第1の電圧電流変換回路及び前記第2の電圧電流変換回路の他方は、容量素子が接続されていない
     請求項13に記載の固体撮像装置。
    One of the first voltage-current conversion circuit and the second voltage-current conversion circuit is connected to a capacitive element,
    The solid-state imaging device according to claim 13, wherein a capacitive element is not connected to the other of the first voltage-current conversion circuit and the second voltage-current conversion circuit.
  17.  前記第1の電圧電流変換回路には、フィルタ回路が接続されており、
     前記第2の電圧電流変換回路には、フィルタ回路が接続されていない
     請求項13に記載の固体撮像装置。
    A filter circuit is connected to the first voltage-current conversion circuit,
    The solid-state imaging device according to claim 13, wherein a filter circuit is not connected to the second voltage-current conversion circuit.
PCT/JP2011/002789 2010-07-01 2011-05-19 Solid state imaging device WO2012001870A1 (en)

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