JP4641750B2 - Three-phase AC inspection device - Google Patents

Description

  The present invention relates to a three-phase alternating current inspection apparatus that inspects the state of the three-phase alternating current, such as the phase order and the phase failure.

As this type of three-phase AC inspection apparatus, a three-phase AC inspection apparatus disclosed in Japanese Patent Laid-Open No. 4-262272 is known. This three-phase AC inspection device is composed of a zero-cross signal generating circuit that converts R-phase, S-phase, and T-phase three-phase AC signals into pulse signals (digital signals) and three flip-flops (D-flip-flops). A phase comparison circuit for comparing the phases of the R phase, S phase and T phase based on the R phase, S phase and T phase pulse signals outputted from the zero cross signal generating circuit and each flip-flop A NAND element that inputs the output of each of the flip-flops, and a NOR element that inputs the output of each flip-flop. Based on the combination of the logic state (High or Low) of the output of the NAND element and the logic state of the output of the NOR element, It is configured to be able to determine the state of three-phase alternating current (phase order and phase loss).
Japanese Patent Laid-Open No. 4-262272 (Page 2, Fig. 1-2)

  However, the conventional three-phase AC inspection apparatus has the following problems. That is, in this three-phase AC inspection device, the logic state (active or inactive) of the R-phase pulse signal is detected by using the S-phase pulse signal as a clock in one flip-flop of the phase comparator, and In one flip-flop, the T-phase pulse signal is used as a clock to detect the logic state of the S-phase pulse signal, and in the other flip-flop, the R-phase pulse signal is used as a clock to detect the T-phase pulse. The logic state of the signal is detected. Therefore, as shown in FIG. 2 of the same publication, this three-phase alternating current inspection apparatus has a two-phase alternating current that is lost even when one phase of the star-connected three-phase alternating current is lost. Since the previous state is maintained, the phase loss can be reliably detected. However, in the case of delta-connected three-phase alternating current, when one phase is lost, an alternating current with a reverse polarity is generated in the other two phases with the phase reversed by 180 degrees. In the flip-flop that inputs the pulse signal for, the polarities of the pulse signal input as the clock and the pulse signal input as the data are switched almost simultaneously. For this reason, there is a possibility that a setup time and a hold time of data with respect to the clock are insufficient and an output becomes unstable. Therefore, this three-phase AC inspection device has a problem that it is not possible to accurately detect the phase loss of the delta-connected three-phase AC.

  The present invention has been made to solve such a problem, and is capable of accurately detecting the phase sequence and the state of phase loss for star-connected three-phase AC and delta-connected three-phase AC. The main purpose is to provide an inspection device.

In order to achieve the above object, the three-phase alternating current inspection apparatus according to claim 1 compares the input three-phase alternating current R-phase waveform, S-phase waveform and T-phase waveform with predetermined threshold values, respectively. a waveform shaping circuit having a duty ratio rather smaller than 50%, and the active period of each other when open-phase in the three-phase alternating current is not generated is outputted by synchronizing the digital signal overlapping with the phase waveform A delay circuit for delaying one of the digital signals, and the one digital signal among the digital signals in synchronization with the transition of the delayed one digital signal from inactive to active. A first flip-flop circuit for detecting and outputting a logic state of one digital signal whose phase is advanced with respect to the signal; In synchronization with the transition of the digital signal from inactive to active, the logic state of the other digital signal whose phase is delayed with respect to the one digital signal among the digital signals is detected and output. And a clear circuit that outputs a clear signal that causes the flip-flop circuit to deactivate its output signal when all of the logic states of the digital signals are inactive.

According to the three-phase AC inspection apparatus of claim 1, the waveform shaping circuit compares the R phase waveform, the S phase waveform, and the T phase waveform with the predetermined threshold values, respectively, and the duty ratio when active is more than 50%. small rather, and the active period of each other when open-phase in the three-phase alternating current is not generated outputs synchronizes the digital signal overlapping each phase waveform, the delay circuit delays the first digital signal, The first flip-flop circuit detects the logic state of one digital signal whose phase is advanced with respect to the one digital signal in synchronization with the transition of the delayed one digital signal from inactive to active. The second flip-flop circuit outputs one digit of each digital signal in synchronization with the transition of the one digital signal from inactive to active. The logic state of the other digital signal whose phase is delayed with respect to the digital signal is detected and output, and the clear circuit outputs its output signal to each flip-flop circuit when all the logic states of each digital signal are inactive. By outputting a clear signal that deactivates the three-phase AC line that is delta-connected and the three-phase AC line that is star-connected based on the logic states of the output signal and inverted output signal of each flip-flop circuit It is possible to reliably detect the phase order and phase loss.

  The best mode of a three-phase AC inspection apparatus according to the present invention will be described below with reference to the accompanying drawings.

  First, the configuration of the three-phase AC inspection apparatus 1 will be described with reference to the drawings.

  As shown in FIG. 1, the three-phase AC inspection apparatus 1 includes three waveform shaping circuits 2, 3, 4, a clear circuit 5, three AND circuits 6, 7, 8, a delay circuit 9, and two flip-flop circuits 10. , 11 and a determination circuit 12 and inspects the state of the three-phase alternating current (phase order and phase loss) based on the input three-phase alternating current R-phase waveform, S-phase waveform and T-phase waveform.

  As an example, each of the waveform shaping circuits 2, 3, and 4 includes a Schmitt trigger circuit (not shown) in which the threshold values VH and VL are set to positive voltage values slightly higher than zero volts. Therefore, each waveform shaping circuit 2, 3, 4 compares the input R-phase waveform, S-phase waveform, and T-phase waveform with the respective threshold values VH, VL, thereby forming the R-phase waveform, S-phase waveform, and T-phase waveform. The duty ratio when the logic state is active (high in this example as an example) is always slightly smaller than 50% (an example of a duty ratio smaller than 50% in the present invention) of the digital signals Sr, Ss, St is output in synchronization with the R phase waveform, the S phase waveform, and the T phase waveform. In this case, for example, when the R phase waveform, the S phase waveform, and the T phase waveform are AC voltage waveforms having an amplitude of 10 V, the threshold values VH and VL are respectively defined as 1.5 V and 0.8 V, respectively.

  The clear circuit 5 inputs the respective digital signals Sr, Ss, St, and when the logic states of all the digital signals Sr, Ss, St are inactive, the logic state of the clear signal Scl is made active and the flip-flop circuit 10 and 11 are made inactive in the state of their output signals. In this example, the clear circuit 5 is configured by a three-input OR element as an example. Therefore, the clear circuit 5 sets the logic state of the clear signal Scl to Low (active) when all the digital signals Sr, Ss, St are Low (inactive). In this specification, when the logic state of the signal is active, it is also referred to as “signal is active”, and when the logic state of the signal is inactive, it is also referred to as “signal is inactive”.

  Each AND circuit 6, 7, 8 is connected to the supply line of each digital signal Sr, Ss, St in order to align the supply timing of the clear signal Scl and each digital signal Sr, Ss, St to each flip-flop circuit 10, 11. Interposed and outputs the logical product of the digital signals Sr, Ss, St and the clear signal Scl as digital signals Sr1, Ss1, St1. Note that when the circuit configuration does not require the supply timing of the clear signal Scl and the digital signals Sr, Ss, St to be aligned, the interposition is omitted, and the digital signals Sr, Ss, St are transferred to the flip-flop circuits 10, 11 and the delay circuit 9 can be directly input. The delay circuit 9 inputs one digital signal Ss1 of the digital signals Sr1, Ss1, St1, and delays the digital signal Ss1 slightly (time td) (a delay amount for delaying one digital signal in the present invention). Example) Output as clock signal Sck. In this case, the delay time td is defined as 2 ms, for example.

  The flip-flop circuit (first flip-flop circuit in the present invention) 10 is constituted by a D-flip-flop circuit as an example, and inputs a digital signal Sr1 to an input terminal (D terminal) and inputs it to a clock terminal (CK terminal). The clock signal Sck is input, and the clear signal Scl is input to the clear terminal (CL terminal). With this configuration, the flip-flop circuit 10 causes the clock signal Sck obtained by delaying the digital signal Ss1 to transition (rise) from inactive (Low as an example in this example) to active (High in this example as an example). In synchronism, the logic state of one of the digital signals Sr whose phase is advanced with respect to the digital signal Ss in the normal phase is detected and the output signal Sr2 and the inverted output signal Sr3 are detected. Is output. The flip-flop circuit (second flip-flop circuit in the present invention) 11 is constituted by a D-flip-flop circuit as an example, and a digital signal St1 is input to an input terminal (D terminal) and the clock terminal (CK terminal) is input. The clock signal Sck is input, and the clear signal Scl is input to the clear terminal (CL terminal). With this configuration, the flip-flop circuit 11 synchronizes with the transition (rising) of the clock signal Sck from inactive (in this example, Low) to active (in this example, High). Among them, the logic state of the other digital signal St whose phase is delayed with respect to the digital signal Ss in the normal phase is detected, and the output signal St2 and the inverted output signal St3 are output. In this example, each of the flip-flop circuits 10 and 11 is constituted by a D-flip flop circuit, but may be constituted by a flip-flop circuit such as a JK-flip flop circuit or an RS-flip flop circuit.

  The determination circuit 12 inputs the output signal Sr2 and the inverted output signal Sr3 of the flip-flop circuit 10, and the output signal St2 and the inverted output signal St3 of the flip-flop circuit 11, and inputs the logic of each signal Sr2, Sr3, St2, St3. Based on the state, a determination process for detecting a three-phase AC state (phase order and phase loss) is executed. In this example, the determination circuit 12 includes, as an example, two NAND elements 12a and 12b, a CPU 12c, and a memory (not shown). In this case, the NAND element 12a receives the output signal Sr2 and the inverted output signal St3 and outputs the logical product signal So1 to the CPU 12c. The NAND element 12b receives the inverted output signal Sr3 and the output signal St2, and outputs the logical product signal So2 to the CPU 12c. The CPU 12c operates according to the operation program stored in the memory, and compares each logic state of the input logical product signals So1 and So2 with the contents of the determination table (see FIG. 4) stored in advance in the memory. Execute the judgment process.

  Next, the operation of the three-phase AC inspection apparatus 1 will be described with reference to FIG.

  In this three-phase AC inspection apparatus 1, each digital signal Sr, Ss, St is inactive (Low) until a sufficient power supply voltage is supplied to each waveform shaping circuit 2, 3, 4 immediately after power-on. Is in a state. For this reason, the clear circuit 5 sets the clear signal Scl to active (Low). Accordingly, the outputs of the flip-flop circuits 10 and 11 are cleared, and the output signals Sr2 and St2 are maintained at Low and the inverted output signals Sr3 and St3 are maintained at High.

  On the other hand, in a state where a sufficient power supply voltage is supplied to each internal component, each waveform shaping circuit 2, 3, 4 has an R-phase waveform input from a star-connected (or delta-connected) three-phase AC line, The S phase waveform and the T phase waveform are shaped, and digital signals Sr, Ss, St are output. When no phase loss occurs in the three-phase alternating current as in the period T2 shown in FIG. 2, the waveform shaping circuits 2, 3, and 4 are out of phase with each other by 120 degrees and have the same period as each phase waveform. Digital signals Sr, Ss, and St are output. Specifically, in the waveform shaping circuit 2, the Schmitt trigger circuit in which the thresholds VH and VL are defined as 1.5 V and 0.8 V, respectively, is shown in FIG. The digital signal Sr is shifted to High when crossing VH (1.5 V), and then the digital signal Sr is shifted to Low when the R-phase waveform crosses the threshold VL (0.8 V) while decreasing. At the same time, the digital signal Sr is kept low until the R phase waveform rises again and crosses the threshold value VH (1.5 V). Since the Schmitt trigger circuit in which the threshold values VH and VL are both set to positive voltage values is provided as described above, the period A during which the digital signal Sr is active (High) is always in the R phase as shown in FIG. It is slightly shorter than the half cycle of the waveform (B / 2: B is one cycle of the R-phase waveform). Further, the period of the digital signal Sr coincides with the period B of the R-phase waveform as described above. Therefore, the waveform shaping circuit 2 outputs a digital signal Sr whose duty ratio (A / B × 100) is always slightly smaller than 50% and free from whiskers (hazard) at the rising and falling portions. Since the waveform shaping circuits 3 and 4 have the same configuration as each waveform shaping circuit 2, similarly, the active (High) duty ratio is always slightly smaller than 50%, and a beard ( Digital signals Sr, St without hazard are output.

  When no phase loss has occurred in the three-phase alternating current, the clear circuit 5 has the clear signal because the active periods of the digital signals Sr, Ss, St overlap each other as in the period T2 shown in FIG. Scl is always kept inactive (High). Further, as shown in FIG. 2, each of the AND circuits 6, 7, and 8 receives the clear signal Scl and the logic that are input after being delayed by the propagation time of the clear circuit 5 when the digital signals Sr, Ss, and St are input. The digital signals Sr1, Ss1, and St1 are output, respectively. The delay circuit 9 delays the digital signal Ss1 by time td and outputs it as a clock signal Sck. Therefore, the flip-flop circuits 10 and 11 repeatedly detect and output the logic states of the input digital signals Sr1 and St1 in synchronization with the rising edge of the clock signal Sck because the clear signal Scl is inactive. To do. Specifically, as shown in a period T1 in FIG. 2, the flip-flop circuit 10 detects and outputs the logic state (High) of the digital signal Sr1 in synchronization with the first rising edge of the clock signal Sck, and outputs the flip-flop. The clock circuit 11 detects and outputs the logic state (Low) of the digital signal St1 in synchronization with the first rising edge of the clock signal Sck. Therefore, as shown in the figure, when the phase loss has not occurred, the flip-flop circuit 10 always detects that the digital signal Sr1 is High, and the flip-flop circuit 11 indicates that the digital signal St1 is Low. Always detect. Thereby, as shown in the figure, the flip-flop circuit 10 always maintains the output signal Sr2 at High (the inverted output signal Sr3 is Low). On the other hand, the flip-flop circuit 11 always maintains the output signal St2 at Low (the inverted output signal St3 is High).

  On the other hand, in the determination circuit 12, the CPU 12c executes determination processing based on the logical product signals So1 and So2 output from the NAND elements 12a and 12b, and detects the state (phase order and phase loss) about the three-phase alternating current. To do. Specifically, when the R phase waveform, the S phase waveform, and the T phase waveform are input in this order (normal phase), the digital signal Sr, the digital signal Ss, and the digital signal St are also in the period T2 in FIG. Are generated in this order. Therefore, as shown in FIG. 2, the logical product signal So1 is always active (Low) because both the input output signal Sr2 and the inverted output signal St3 are High. Further, as shown in the figure, the logical product signal So2 is always inactive (High) because the input output signal St2 and the inverted output signal Sr3 are both Low. Therefore, the CPU 12c compares the detected logic states of the logical product signals So1 and So2 with the contents of the determination table stored in the memory, as shown in the first row from the top of FIG. It is determined that the phase alternating current is a normal phase and no phase loss has occurred.

  Further, when the T phase waveform, the S phase waveform, and the R phase waveform are input in this order (reverse phase), the digital signal St, the digital signal Ss, and the digital signal Sr are also transmitted as shown in the period T4 in FIG. Occurs in order. In this state, as shown in the figure, the logical product signal So1 is always inactive (High) because both the input output signal Sr2 and the inverted output signal St3 are Low. Further, as shown in the figure, the logical product signal So2 is always active (Low) because the input output signal St2 and the inverted output signal Sr3 are both high. Therefore, the CPU 12c compares the detected logic states of the logical product signals So1 and So2 with the contents of the determination table stored in the memory, as shown in the second row from the top in FIG. It is determined that the phase alternating current is in the opposite phase and no phase loss has occurred.

  On the other hand, in the delta-connected three-phase AC line, when one of the R phase and the T phase (for example, the R phase) is open, the digital signal Sr is always inactive (period T3 in FIG. 2). Low), and the digital signal Ss and the digital signal St have a relationship in which the phase is inverted by 180 degrees. Even in this state, the waveform shaping circuits 3 and 4 reshape the R phase waveform and the T phase waveform so that the duty ratio at the time of active (High) is always slightly smaller than 50%. As shown, the high periods of the digital signals Ss and St do not overlap. For this reason, the clear circuit 5 shifts the clear signal Scl to active (Low) periodically (with a period of 1/2 of the three-phase AC period) during the period in which the phase loss occurs. Therefore, each flip-flop circuit 10, 11 continues to clear the output signal Sr2 (inverted output signal Sr3) and the output signal St2 (inverted output signal St3) periodically. Further, even when the phase loss occurs, the clock signal Sck is continuously output. However, since the R phase waveform is lost as in the period T3 in FIG. Sr1 is always kept low. The clock signal Sck is delayed by the time td by the delay circuit 9 with respect to the digital signal Ss. Therefore, the flip-flop circuit 10 always sets the digital signal Sr2 to Low at the rising edge of the clock signal Sck, and the flip-flop circuit 11 always sets the digital signal St2 to Low at the rising edge of the clock signal Sck. As a result, as shown in the figure, since the output signals Sr2 and St2 are always kept low, both the logical product signals So1 and So2 are always inactive (High). Therefore, the CPU 12c compares the detected logic states of the logical product signals So1 and So2 with the contents of the determination table stored in the memory, as shown in the third row from the top in FIG. It is determined that a phase failure has occurred in the phase alternating current.

  In addition, in the three-phase AC line connected in delta connection, when the S phase is open, the digital signal Ss is always inactive (Low) as in the period T5 in FIG. 3, and the digital signal Sr and the digital signal St has a relationship in which the phase is inverted by 180 degrees. Even in this state, the waveform shaping circuits 3 and 4 reshape the R phase waveform and the T phase waveform so that the duty ratio at the time of active (High) is always slightly smaller than 50%. As shown, the high periods of the digital signals Sr and St do not overlap. For this reason, the clear circuit 5 shifts the clear signal Scl to active (Low) periodically (with a period of 1/2 of the three-phase AC period) during the period in which the phase loss occurs. Further, the clock signal Sck is always kept inactive (Low). Therefore, the flip-flop circuits 10 and 11 periodically clear the output signal Sr2 (inverted output signal Sr3) and the output signal St2 (inverted output signal St3) and maintain LoW together. As a result, as shown in the figure, both the logical product signals So1 and So2 are always inactive (High). Therefore, the CPU 12c compares the detected logic states of the logical product signals So1 and So2 with the contents of the determination table stored in the memory, as shown in the third row from the top in FIG. It is determined that a phase failure has occurred in the phase alternating current.

  Further, in the star-connected three-phase AC line, when any one of the normal phase R phase, S phase, and T phase is lost, the phase of the digital signals Sr, Ss, St is changed. Only the corresponding digital signals are missing, and the digital signals corresponding to the phases that are not missing are output from the waveform shaping circuits 2, 3, and 4 in the same state as when no missing phases occur. For example, when the R phase is lost in the normal phase state, only the digital signal Sr is lost as shown in the period T6 in FIG. 5, and the other two digital signals Ss and St are It is output from the waveform shaping circuits 3 and 4 in the same state. However, since the clear signal Scl periodically becomes active (Low) when the R phase is open, each flip-flop circuit 10, 11 periodically clears its output (output signal Sr2, etc.). . Further, the digital signal Sr1 is always inactive (Low) at the rising edge of the clock signal Sck, and the digital signal St1 is also always inactive (Low). Therefore, the flip-flop circuits 10 and 11 always maintain the output signals Sr2 and St2 at Low. As a result, as shown in the figure, both the logical product signals So1 and So2 are always inactive (High). Therefore, the CPU 12c compares the detected logic states of the logical product signals So1 and So2 with the contents of the determination table stored in the memory, as shown in the third row from the top in FIG. It is determined that a phase failure has occurred in the phase alternating current.

  Further, when the T phase is lost, as shown in the period T7 in FIG. 5, only the digital signal St is lost, and the other two digital signals Sr and Ss are in the same state as before the occurrence of the lost phase. Output from the shaping circuits 3 and 4. In this case, since the clear signal Scl periodically becomes active (Low) as shown in the synchronous period T7, each flip-flop circuit 10, 11 outputs (output signal Sr2) each time the clear signal Scl becomes Low. Etc.) are cleared to Low. On the other hand, unlike the case where the R phase is lost, the digital signal Sr1 is always active (High) at the rising edge of the clock signal Sck, so that the flip-flop circuit 10 outputs (output signal) every time the clock signal Sck rises. Sr2) is moved to High. Therefore, the output signal Sr2 output from the flip-flop circuit 10 is toggled (High and Low are repeated). As a result, as shown in the figure, the logical product signal So1 also toggles in synchronization with the output signal Sr2. On the other hand, the logical product signal So2 is always inactive (High). Therefore, the CPU 12c compares the detected logic states of the logical product signals So1 and So2 with the contents of the determination table stored in the memory, as shown in the second row from the bottom of FIG. It is determined that a phase failure has occurred in the phase alternating current. Note that “High / Low” in the determination table shown in the figure indicates a state in which the corresponding signal toggles.

  Although not shown, when the S phase is lost, the clear signal Scl periodically becomes active (Low) in the same manner as when either the R phase or the T phase is lost. Therefore, each time the clear signal Scl becomes Low, the flip-flop circuits 10 and 11 clear the output (the output signal Sr2 and the like). Further, since the S phase is lost, the clock signal Sck is not supplied to the flip-flop circuits 10 and 11. Therefore, each flip-flop circuit 10, 11 always maintains its output (output signals Sr2, St2) at Low. As a result, the logical product signals So1 and So2 are always inactive (High). The CPU 12c compares the detected logic state of each of the logical product signals So1 and So2 with the contents of the determination table stored in the memory, and as shown in the third row from the top in FIG. It is determined that a phase failure has occurred.

  In addition, with reference to FIG. 5, the example in which one of the normal phase R phase, S phase, and T phase is lost in the star-connected three-phase AC line has been described. In the AC line, when the R phase out of the R phase, S phase, and T phase in the reverse phase state is lost, the output signal Sr2 is always low, so the logical product signal So1 is always high, and the output signal St2 , Toggles the logical product signal So2. Further, when the S phase or the T phase out of the R phase, S phase, and T phase in the reverse phase state is lost, the output signals Sr2, St2 are always low, so that the AND signals So1, So2 are both Always High. Therefore, the CPU 12c compares the detected logic states of the logical product signals So1 and So2 with the contents of the determination table stored in the memory, so that the R phase in the reverse phase state in the star-connected three-phase AC line is obtained. When a phase is lost, as shown in the fifth row from the top in FIG. 4, it is determined that a missing phase has occurred in the three-phase alternating current. In addition, when the S-phase or T-phase in the reverse phase is lost in the star-connected three-phase AC line, the CPU 12c generates an open-phase in the three-phase AC as shown in the third row from the top in FIG. It is determined that

  Thus, according to the three-phase AC inspection apparatus 1, the waveform shaping circuits 2, 3, and 4 are activated by comparing the R-phase waveform, the S-phase waveform, and the T-phase waveform with the predetermined threshold values VH and VL, respectively (for example, The digital signal Sr, Ss, St whose duty ratio is slightly smaller than 50% is output in synchronization with each phase waveform, and the delay circuit 9 outputs one of the digital signals Sr, Ss, St. (For example, the digital signal Ss) is slightly delayed, and the flip-flop circuit 10 is synchronized with the transition (rise) of one digital signal from inactive (for example, Low) to active (for example, High). Logic of one digital signal (for example, digital signal Sr) whose phase is advanced with respect to one digital signal of Ss and St The flip-flop circuit 11 detects and outputs the state, and the digital signal Sr, Ss, St is synchronized with the transition (rise) of one digital signal from inactive (for example, Low) to active (for example, High). The logic state of the other digital signal (for example, the digital signal St) that is delayed in phase with respect to one of the digital signals is detected and output, and the clear circuit 5 outputs the logic state of each digital signal Sr, Ss, St. Are all inactive (for example, Low), by outputting a clear signal Scl for making the output signals Sr2 and St2 inactive (for example, Low) to the flip-flop circuits 10 and 11, respectively. , 11 output signals Sr2, St2 and inverted output signals Sr3, St3. Based on the click state, the phase order and open phase of the delta-connected three-phase AC line and star-connected three-phase AC line can be reliably detected.

  In addition, this invention is not limited to said structure. For example, the above configuration includes two NAND elements 12a and 12b and a CPU 12c, and each logic state of the output signals Sr2 and St2 and the inverted output signals Sr3 and St3, specifically, each of the logical product signals So1 and So2. Although the CPU 12c employs the determination circuit 12 that detects the phase order and phase loss of the delta-connected three-phase AC line and the star-connected three-phase AC line based on the logic state, the invention is not limited to this. For example, a configuration in which the CPU 12c directly inputs the output signals Sr2 and St2 and the inverted output signals Sr3 and St3 to detect the phase sequence and the open phase of the three-phase AC line can be adopted. In the above configuration, the active logic states of the digital signals Sr, Ss, St, the clear signal Scl, the digital signals Sr1, Ss1, St1, the clock signal Sck, and the output signals Sr2, St2 are set to High, and the logical product signal So1. , So2 has been described as an example in which each active logic state is Low, but the active logic state of each signal can be defined as appropriate, and can be set to either High or Low. In this case, the circuit configuration shown in FIG. 1 is changed as appropriate, and the contents of the determination table shown in FIG. 4 are changed as appropriate.

1 is a block diagram showing a configuration of a three-phase AC inspection device 1. FIG. It is a timing chart for demonstrating operation | movement of the three-phase alternating current inspection apparatus 1 in the normal phase state about the three-phase alternating current line of a delta connection. It is a timing chart for demonstrating operation | movement of the three-phase alternating current inspection apparatus 1 in the reverse phase state about the three-phase alternating current line of a delta connection. It is explanatory drawing which shows the content of the determination table. It is a timing chart for demonstrating operation | movement of the three-phase alternating current inspection apparatus 1 in the normal phase state about the three-phase alternating current line of a star connection. 6 is a timing chart for explaining a waveform shaping operation by the waveform shaping circuit 2;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Three-phase alternating current inspection apparatus 2-4 Waveform shaping circuit 5 Clear circuit 9 Delay circuit 10, 11 Flip-flop circuit Scl Clear signal Sr, Ss, Ss1, St Digital signal Sr2, St2 Output signal Sr3, St3 Inverted output signal VH, VL Threshold

Claims (1)

R-phase waveform of the input three-phase alternating current, open-phase by comparing the S-phase waveforms and T-phase waveform each with a predetermined threshold, the duty ratio when the active rather smaller than 50%, and the three-phase AC A waveform shaping circuit that outputs a digital signal in which the active periods of each other overlap when they are not generated in synchronization with the respective phase waveforms;
A delay circuit for delaying one of the digital signals;
In synchronization with the transition of the delayed one digital signal from inactive to active, the logic state of one of the digital signals whose phase is advanced with respect to the one digital signal is detected. A first flip-flop circuit that outputs
In synchronism with the transition of the delayed one digital signal from inactive to active, the logic state of the other digital signal whose phase is delayed with respect to the one digital signal of the digital signals is detected. A second flip-flop circuit that outputs
A three-phase alternating current inspection apparatus comprising: a clear circuit that outputs a clear signal that causes each flip-flop circuit to deactivate its output signal when the logic states of the respective digital signals are all inactive.

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