JP4635079B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device.

  A conventional light emitting device will be described with reference to the drawings. FIG. 18 shows an example of a conventional InGaAlP visible light LED.

  In the LED 100 shown in FIG. 18, InGaAlP epitaxial growth layers 84, 85, and 86 that contribute to light emission are formed on an N-type GaAs substrate 82. Although not shown in the figure, a buffer layer may be provided between the substrate and the epitaxial growth layer in accordance with required specifications in order to obtain a high-quality light emitting layer.

  Electrodes 89 for supplying current are respectively provided on the upper surface of the epitaxial growth layer 86 and the lower surface of the substrate 82. Although not shown in the figure, a layer for diffusing current and a layer for making electrical contact are often provided between the upper electrode 89 and the epitaxial growth layer 86. Of the epitaxial growth layers 84, 85, 86, the active layer 85 emits light by recombination of carriers. The epitaxial growth layers 84 and 86 formed above and below the active layer 85 are clad layers 84 and 86 having a wider band gap than the active layer in order to confine carriers and increase luminous efficiency.

  For these epitaxial growth layers 84, 85 and 86, the band gap needs to be optimally selected according to the design in order to adjust the emission wavelength and confine carriers. For good epitaxial growth, it is desirable that the lattice constant of the epitaxial growth layer is matched with the lattice constant of the substrate 82. Since InGaAlP, which is a Group 3-5 compound, contains three types of In, Ga, and Al as Group 3 components, the band gap and lattice constant can be designed independently by selecting these composition ratios.

For example, the composition of the epitaxial growth layer following equation _{1n x (Ga 1-y A1} y) 1-x P ······· 1)
When the In composition ratio x is set to 0.5, the lattice constant is substantially matched with the GaAs substrate, and the band gap is reduced by adjusting the composition ratio y of A1 and Ga while maintaining x = 0.5. Can be controlled.

  For example, when obtaining a red light emitting LED having a wavelength of 644 nm, the composition ratio of the active layer 85 is x = 0.5, y = 0.043, and the composition of the cladding layers 84, 86 is x = 0.5, y = It may be set to 0.7. When a green light emitting LED having a wavelength of 562 nm is obtained, the composition ratio of the active layer 85 is x = 0.5, y = 0,454, and the composition of the cladding layers 84, 86 is x = 0.5, y = It may be 1.00, that is, InAlP.

  As described above, the InGaA1P-based epitaxial growth layer can select the emission wavelength within the visible light region. In addition, since epitaxial growth that is lattice-matched to the most common GaAs substrate as a compound semiconductor substrate is possible, there is an advantage that acquisition of the substrate and epitaxial growth are relatively easy.

  However, on the other hand, the GaAs substrate has a drawback of absorbing light in the visible light region. For this reason, since a part of light emitted from the InGaA1P epitaxial growth layer is absorbed by the GaAs substrate, the brightness of the LED is inevitably lowered. In order to avoid a reduction in luminance, a material transparent to the visible light region may be used for the substrate. As a general transparent material, there is GaP. However, since the GaP substrate is not lattice-matched with the InGaA1P system, it is difficult to achieve good epitaxial growth. In order to solve this problem, US Pat. No. 5,376,580 filed in 1993 proposes a method of wafer bonding of an InGaA1P epitaxial growth layer and a GaP substrate. This proposal is a method in which a GaAs substrate is removed from an epitaxial growth layer, and a GaP substrate is adhered instead, and heat treatment is performed while pressure is applied, and integration is performed. Although this method can increase the brightness of the LED, it is difficult to handle because the epitaxially grown layer is thin after removing the GaAs substrate, and it is necessary to use a special device because it performs heat treatment while applying pressure. There were problems with stability and productivity.

  Next, wafer bonding will be described. If two types of wafers can be bonded and integrated, a laminated structure of different materials can be obtained freely regardless of the lattice constant, or different materials can be embedded inside as represented by SOI (Silicon on Insulater). For this reason, various wafer bonding techniques have been proposed for a long time. For example, a bonding method in which heat treatment is performed while pressing two wafers as described above is described in Japanese Patent No. 765892 filed in 1970. Wafer bonding has been a technique that has been sought for a long time, but it has not been put into practical use for a long time because it is difficult to integrate the entire surface of the wafer.

  The present inventors have developed a technique called “direct bonding” or “direct bonding” as a technique that can withstand practical use. For example, Patent Document 1 discloses direct bonding between Si wafers. Further, the direct bonding of compound semiconductor wafers is described in Patent Document 2.

  In the direct bonding technique, two substrates having mirror surfaces are brought into close contact with each other at room temperature in an atmosphere substantially free from foreign matters, and then bonded and integrated by heat treatment. Since the entire surface is in close contact before the heat treatment, the entire surface can be joined without leaving an unbonded portion, and it is not necessary to apply pressure during the heat treatment. The mechanism of direct bonding between Si wafers is considered as follows.

That is, first, OH groups are formed on the surface of the wafer by washing or washing with water. Therefore, when the wafer surfaces are brought into contact with each other, OH groups are attracted by hydrogen bonds, and the wafers are brought into close contact with each other at room temperature. The adhesion is strong, and if it is a normal wafer warp, it will be corrected and the entire surface will adhere. During the heat treatment, a dehydration condensation reaction (Si—OH: HO—Si → Si—O—Si + H ₂ O) occurs at a temperature higher than 100 ° C., and the wafers are bonded to each other through oxygen atoms to increase the adhesive strength. Go. At higher temperatures, the diffusion and rearrangement of atoms in the vicinity of the bonding interface occurs, and the wafer is integrated in strength and electrical properties. The adhesion mechanism of compound semiconductors is considered to be the same.

  Next, an example of a method of manufacturing an LED including an InGaAlP-based epitaxial growth layer that is in close contact with a GaP substrate using direct bonding will be described with reference to FIG.

  First, as shown in FIG. 19A, an N-type cladding layer 94, an active layer 95, and a P-type cladding layer 96 are grown on an N-type GaAs substrate 92. Next, as shown in FIG. 19B, a GaP substrate 91 is directly bonded to the surface of the epitaxial growth layer 96. Further, as shown in FIG. 19C, when the GaAs substrate 92 is removed by polishing or etching and the electrodes 99 are provided on the upper surface of the N-type cladding layer 94 and the lower surface of the GaP substrate 91 upside down, As shown in FIG. 19D, an InGaA1P-based LED using GaP as a substrate 91 is obtained.

  In this way, when different materials are directly bonded, particularly when the surface of the epitaxial growth layer is directly bonded, there is a problem described below as compared with, for example, direct bonding of the same kind of wafers of Si or GaAs.

  First, the surface of the epitaxial growth layer has more adhesion of particles (foreign matter such as dust) than the wafer surface. For this reason, there is a problem that bonding at room temperature is hindered, the entire surface is not bonded even after heat treatment, and an unbonded portion called a void is generated. Generally, the wafer surface is kept clean, and a clean wafer is also used for the substrate for epitaxial growth. However, reactants accumulate during the epitaxial growth, and foreign matter adheres during the pre-processing and post-processing of the epitaxial growth process. At present, particle adhesion to the surface of the epitaxial growth layer is unavoidable to some extent.

  Secondly, since the wafer is warped by epitaxial growth, there is a problem that the entire surface of the wafer cannot be adhered at room temperature.

  Third, since there is a difference in thermal expansion between different materials, thermal stress is generated during the heat treatment, and there is a problem that the bonded substrate is broken by the stress.

  Fourth, because there is a difference in thermal expansion between different types of materials, even if the bonded substrate does not break, a “displacement” occurs at the adhesion interface during the heat treatment for adhesion, and this “deviation” Therefore, there is a problem that the entire surface of the substrate cannot be adhered uniformly.

Fifth, there is a problem that electrical resistance is generated at the bonding interface. That is, as a result of the inventors' original study, it has been found that when the wafers are bonded to each other, an electrical resistance component is generated at the bonding interface. When, for example, an LED is formed using such an adhesive substrate, the electrical resistance at the adhesive interface increases the operating voltage of the LED, causing problems such as defective light emission and heat generation.
Japanese Patent No. 1420109 Japanese Patent No. 2040637

  The present invention provides an adhesion type semiconductor substrate and a semiconductor light emitting device which are directly and stably adhered to an epitaxial growth layer formed on a semiconductor substrate over the entire surface.

According to one aspect of the present invention, the first semiconductor device includes a stacked body in which a mixed crystal of a compound semiconductor is epitaxially grown on a first semiconductor substrate, and a first cladding layer, an active layer, and a second cladding layer are sequentially deposited. Forming an epitaxial growth layer of
A main surface of the second semiconductor substrate or a second epitaxial growth layer formed on the main surface is placed so as to be in contact with the first epitaxial growth layer and integrally joined;
Removing the first semiconductor substrate and exposing the first epitaxial growth layer;
Forming an electrode on the exposed surface side of the first epitaxial growth layer and the back surface side of the second semiconductor substrate,
In the step of integrally bonding, the second surface of the first surface of the first semiconductor substrate is formed with respect to a surface on which one of the (111) A surface and the (111) B surface appears preferentially. A method for manufacturing a semiconductor light emitting device, comprising: joining a surface on which one of the (111) A surface and the (111) B surface appears preferentially among the main surfaces of the semiconductor substrate. Provided.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor light-emitting device which adheres to the epitaxial growth layer formed on the semiconductor substrate directly and stably over the whole surface can be provided.

  Hereinafter, some embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. In this embodiment, the adhesive semiconductor substrate according to the present invention is applied to an InGaAlP-based LED.

  FIG. 1 is a schematic cross-sectional view showing the InGaAlP-based LED of this embodiment. The LED 1 shown in the figure is integrated with an active layer 15, a laminate 10 formed of an N-type clad layer 14 and a P-type clad layer 16 laminated with the active layer 15 interposed therebetween, and a lower surface of the laminate. And an electrode 19 formed on the upper surface side of the N-type cladding layer 14 and on the lower surface of the GaP substrate 11, respectively.

  The laminated body 10 is formed by epitaxially growing a mixed crystal of a compound semiconductor using a GaAs substrate (not shown) as a growth substrate. If the bonding surface with the P-type cladding layer 16 is a main surface of the GaP substrate 11, the main surface is mirror-finished, and the laminate 10 is directly bonded at room temperature while being formed on the growth substrate. . The growth substrate is removed after the close bonding.

  Both the active layer 15 and the two cladding layers 14 and 16 can be expressed by the above-described composition formula 1). As will be described later, the respective layers are lattice-matched with the growth substrate, particularly at room temperature, by suitably selecting each composition. Therefore, the warpage of the growth substrate is greatly reduced, and as a result, the entire surface of the GaP substrate 11 can be bonded to the stacked body 10.

  In this embodiment, the GaP substrate 11 is P-type with a diameter of 2 inches and a thickness of 250 μm, the P-type cladding layer 16 has a thickness of 0.6 μm, and the composition ratio is the above-mentioned formula 1) X = 0.5 and y = 1.0. The active layer 15 has a thickness of 0.6 μm and a composition ratio of x = 0.5 and y = 0.28. Furthermore, the N-type cladding layer 14 has a thickness of 0.6 μm, and the composition ratios are x = 0.5 and y = 1.0.

  Thus, since LED1 of this embodiment is formed on the GaP board | substrate 11 which does not absorb the light of visible region, it can be made to light-emit with high brightness | luminance. When the light emission characteristics of the LED 1 were evaluated, it was confirmed that the LED 1 had brightness twice or more that of the LED 100 having the conventional GaAs substrate shown in FIG.

(Second Embodiment)
Next, as a second embodiment of the present invention, an embodiment of a method for manufacturing an adhesive semiconductor substrate will be described with reference to the drawings. In the following description, it explains as a specific example applied to manufacture of InGaAlP type LED, and shows some examples of a manufacturing method of LED1 shown in FIG. 1 more specifically.

(First embodiment)
First, a first embodiment of a method for manufacturing an adhesive semiconductor substrate according to the present invention will be described with reference to FIG. In this embodiment, particle adhesion to the surface of the epitaxial growth layer formed on the first semiconductor substrate is solved. A feature of this embodiment is that a cover layer is formed on the surface of the epitaxial wafer, and the second semiconductor substrate is formed. Before adhering directly to the epiwafer, the particles adhering to the epiwafer are removed together with the cover layer.

  2A to 2D are schematic cross-sectional views for specifically explaining the manufacturing method of this embodiment. Note that FIG. 2 is a description in which FIG. 1 is turned upside down.

  As shown in FIG. 2A, an epi-wafer for direct bonding includes a buffer layer 18, an N-type cladding layer 14, an active layer 15, a P-type cladding layer 16, and a surface cover layer 17 on an N-type GaAs substrate 12. Are sequentially stacked. These epitaxial growth layers are formed by, for example, MOCVD (Metal Organic Chemical Vapor Deposition).

The N-type GaAs substrate 12 has a diameter of 2 inches and a thickness of 250 μm, is doped with Si as a carrier at a carrier concentration of about 1E18 / cm ³ , and its main surface has a mirror finish. The buffer layer 18 is GaAs and has a thickness of 0.5 μm. The uppermost surface cover layer 17 is made of GaAs and has a thickness of 0.1 μm.

  Next, after cleaning the epiwafer with a surfactant, the epiwafer is immersed in a mixed solution of sulfuric acid 8, hydrogen peroxide solution 1, and water 1 in a volume ratio, and etching is performed, as shown in FIG. The surface cover layer 17 was removed. This mixed solution selectively etches the GaAs cover layer. It was observed that the surface cover layer 17 was removed in a few seconds, but the immersion was continued for 1 minute to completely remove the surface of the P clad layer 16. Expressed.

  Subsequently, the epi wafer from which the surface cover layer 17 was removed and the GaP substrate 11 were directly bonded to obtain an adherend shown in FIG. Hereinafter, the direct bonding process will be described in more detail.

  As a pretreatment for direct bonding, the GaP substrate 11 was washed with a surfactant, immersed in dilute hydrofluoric acid to remove the natural oxide film on the surface, washed with water, and then dried with a spinner. Further, after removing the surface cover layer 17 by the above-described method, the epiwafer was subjected to dilute hydrofluoric acid treatment for removing the oxide film in the same manner as the GaP substrate 11, and then washed with water and spinner dried. All of these pretreatments were performed in a clean atmosphere in a clean room.

  Next, the pre-processed epi-wafer was placed with the epitaxial growth layer facing upward, and the GaP substrate 11 was placed thereon with the mirror surface facing downward, and was brought into close contact at room temperature. Since GaP is transparent, the contact state can be visually observed. When the GaP substrate 11 was placed on the epi-wafer, the epi-wafer was warped so as to form a convex shape in front view, so that the central portion of the GaP substrate 11 was first adhered. The contact part naturally spreads toward the peripheral part of the GaP substrate 11 just by leaving it as it is, and the entire surface except the chamfered part of the periphery of the GaP substrate 11 was in close contact within 1 minute. The same operation was repeated, and a total of 10 groups were brought into close contact with each other at room temperature. For comparison with this example, an epi-wafer without the cover layer 17 was prepared, and room temperature adhesion was attempted through the same steps as in this example except for etching the cover layer. As a result, in the epitaxial wafer not provided with the cover layer 17, voids were generated in 6 out of 10 sets, and one set could not be adhered at room temperature.

  As the final step of direct bonding, the adherends that were in close contact at room temperature were placed upright on a quartz boat and placed in a diffusion furnace for heat treatment. The adherends were divided into 5 groups, and one was heat-treated at 800 ° C and the other at 400 ° C. In either case, the treatment time is 1 hour, and the atmosphere is argon containing 10% hydrogen. After the heat treatment process, the 800 ° C. adherend was broken in 3 out of 5 or cracked on the epiwafer side. On the other hand, none of the 5 sets heat-treated at 400 ° C. were cracked or cracked. Such a difference according to the temperature in the heat treatment process is that the thermal expansion coefficient is generated when the room temperature adherend is heat treated at a high temperature because the epitaxial growth wafer having GaAs as a substrate and the GaP substrate 11 have different thermal expansion coefficients. As a result, the adherend is destroyed. When the heat treatment temperature was low, the difference in thermal expansion at the time of temperature increase and the heat shrinkage difference at the time of temperature decrease were almost proportional to the temperature, so that the heat treatment at 400 ° C. did not cause destruction.

  Next, as shown in FIG. 2D, the GaAs substrate 12 of the epiwafer was removed. This process of removing the GaAs substrate 12 was performed by immersing the adherend in a mixed solution of ammonia and hydrogen peroxide and selectively etching GaAs. This etching also removed the GaAs buffer layer 18 at the same time.

  Finally, an electrode 19 was provided on the GaP substrate 11 and the N-type cladding layer 14 to obtain the LED 1 shown in FIG.

  The first embodiment of the semiconductor light emitting device according to the present invention has been described above centering on the step of bonding after removing the GaAs cover layer on the InGaAlP epitaxial growth layer by selective etching. However, it is not always necessary to remove all of the cover layer, and a part of the cover layer may be removed from the surface within a range in which a similar effect can be obtained. Moreover, you may remove the surface part of the epitaxial growth layer to adhere | attach, without providing a cover layer.

  In this example, the cladding layer directly bonded is a layer that contributes to light emission. Therefore, in order to precisely control the thickness, a cover layer is provided and then completely removed by selective etching. .

  The surface particle removal method of the present embodiment is effective not only in the direct adhesion between the above-described InGaA1P-based epitaxial growth layer and the GaP substrate but also in the case of wafer bonding to the epitaxial growth layer. Also, the bonding method is not limited to the direct bonding described above, and the particles on the bonding surface are bonded even in a method of heat treatment while applying a load, a method of bonding by applying a voltage, and a method of bonding using an adhesive layer or an adhesive material. Therefore, the surface particle removal method of this embodiment is applicable.

(Second embodiment)
Next, a description will be given of a second embodiment of the method for manufacturing a contact type semiconductor substrate according to the present invention. This example solves the problem that the room temperature adhesion in the direct bonding process becomes incomplete by adjusting the lattice constant of the InGaA1P-based material when the warp of the epi-wafer is large. Other manufacturing methods are substantially the same as those of the first embodiment described above. This example will also be described with reference to the schematic cross-sectional view of FIG. 2 as a specific example applied to the manufacturing method of the LED 1 shown in FIG.

  In the first embodiment described above, the entire surface can be adhered using an epitaxial wafer having an InGaAlP epitaxial growth layer with a total thickness of 1.8 μm and a GaP substrate with a thickness of 250 μm. This epiwafer had a warp of 11 μm to 18 μm, but as a result of room temperature adhesion correcting the epiwafer warp, and as a result of warping the GaP substrate in accordance with the epiwafer, the entire surface adhered.

  On the other hand, the same direct adhesion was attempted using an epitaxial wafer having a total thickness of 3.6 μm of InGaAlP epitaxial growth layer and a GaP substrate having a thickness of 350 μm. The epitaxial wafer has the same composition of the substrate and each epitaxial growth layer as in the first embodiment, and the thickness is the same for the active layer 15, the buffer layer 18 and the cover layer 17, but the N-type cladding layer 14 and the P-type cladding layer. Each 16 is as thick as 1.5 μm. As a result, the warp of the epiwafer was 24 to 36 μm, which was increased in proportion to the total thickness of the InGaA1P epitaxial growth layer.

  In this case, the central region of the epiwafer adhered at room temperature, but the entire surface could not be adhered. Here, when the epiwafer was adsorbed to a flat vacuum chuck, the entire surface could be adhered. From this, it can be seen that the reason why the entire surface cannot be bonded is that the epi-wafer warpage is large, and that the GaP substrate is thick and difficult to deform, so that the room temperature adhesion cannot correct the warpage of the wafer.

  The feature of this embodiment is that the lattice constant is adjusted by using the characteristics of the InGaA1P-based material without changing the characteristics affecting the light emission such as the band gap, thereby reducing the warpage of the epi-wafer. The 1nGaAlP-based material is a mixed crystal of InP, GaP, and A1P. In general, according to a law called Vegard's law, the lattice constant or band gap of a mixed crystal is a value obtained by averaging the lattice constant and band gap of a substance constituting the mixed crystal according to the composition ratio. For some 1nGaAlP materials, the composition ratio x, y in the formula (1), the composition ratio of InP, GaP, AlP converted from these x and y, the lattice constant and the band gap calculated from this composition ratio according to the Bekaard rule, Is shown in FIG. The lattice constant is shown together with the ratio of the lattice constant of GaAs to 0.56533 nm. In the figure, numbers 1, 2, and 3 are cases of 1nP, AlP, and GaP, respectively, as can be seen from the corresponding composition ratios, and the values in this column were used for the calculation of the lattice constant and the band gap. .

  The composition of the epi-wafer that was not fully adhered at room temperature described in the first embodiment of the method for manufacturing an adhesive-type semiconductor substrate according to the present invention is shown in the columns of Nos. 4 and 5 and explained in the prior art. The compositions of the conventional red LED and green LED are shown in the columns of Nos. 6-9. For conventional red and green LEDs, both lattice constants are larger than GaAs, which causes the epi-wafer to warp.

  Conventionally, the lattice constant of the epitaxial growth layer has been matched with the lattice constant of the substrate at a high temperature for epitaxial growth. This is intended to reduce the lattice distortion during growth and to obtain a high quality epitaxial growth layer. However, even if the lattice constants match at high temperatures, the thermal expansion coefficient of the epitaxial growth layer and the thermal expansion coefficient of the substrate are generally different, so if they are lowered to room temperature in the bonding process, the lattice constants do not match, which causes warpage. ing.

  The feature of this embodiment is that the lattice matching at room temperature is emphasized in order to realize direct bonding, and the warpage of the epi wafer is reduced. The specific means is as follows.

  In FIG. 3, columns 10 to 19 show changes in the lattice constant when the In composition x of the cladding layer is reduced based on the epi-wafer (number 5) that cannot be adhered to the entire surface at room temperature. . When x is 0.47 and the lattice constant is the same as that of GaAs, when the value is lower than 0.47, the lattice constant is smaller than that of GaAs. Therefore, an epi-wafer was prototyped by changing only the composition of the cladding layer, and a direct adhesion test was performed. When the value of x was reduced, the warpage of the epiwafer was reduced. When x = 0.47, the warpage was as small as 6 to 12 μm, and the entire surface could be adhered at room temperature. There was a GaP substrate that could be adhered to the entire surface even when x = 0.48 or x = 0.49. When x was set to 0.45, the lattice mismatch during growth increased and crystal defects increased. Since the allowable range of the value of x depends on the thickness of the epitaxial growth layer and the thickness of the GaP substrate to be bonded, it cannot be defined unconditionally, but if it is smaller than 0.5, the effect of reducing the warp is 0. If it is less than .45, there is a disadvantage in epitaxial growth. Although the band gap is increased by reducing the In composition, the clad layer has a function of confining carriers and does not emit light directly, so it hardly affects the emission wavelength. In this example, the composition of the active layer was not changed in order to avoid a change in the emission wavelength. In addition, since the warpage of the wafer becomes an obstacle to wafer bonding regardless of the method, the present embodiment is not limited to direct bonding between the InGaA1P epitaxial growth layer and the GaP wafer, and the same applies to other wafer bonding. It has the effect.

(Third embodiment)
Next, a third embodiment of the method for manufacturing an adhesive semiconductor substrate according to the present invention will be described with reference to the drawings. This embodiment shows a method for solving the problem of destruction due to a difference in thermal expansion between wafers directly bonded.

  In the first embodiment described above, the heat treatment temperature was lowered to 400 ° C., thereby avoiding the substrate destruction due to the direct adhesion heat treatment. Since the amount of thermal expansion is substantially proportional to the heat treatment temperature, a decrease in the heat treatment temperature contributes to prevention of substrate destruction. On the other hand, when the heat treatment temperature is lowered, the movement and rearrangement of atoms at the bonding interface becomes insufficient, and thus there is a possibility that the bonding becomes incomplete. In this embodiment, since the manufacturing method of the adhesive semiconductor substrate is applied to LED manufacturing, it is required that the bonding strength can withstand the LED manufacturing process and that a current can flow across the bonding interface. In the first example, with respect to the bonding strength, a sufficient strength for manufacturing the LED according to the present invention was obtained even by heat treatment at 400 ° C. In order to evaluate the electric resistance of the direct adhesion interface, the voltage VF was measured when a constant current of 20 mmA was passed in the forward direction. At this time, in order to reduce the contact resistance of the electrode, a GaAs contact layer was provided between the cladding layer and the electrode by using the etching stop layer of FIG. Among the LEDs of the first embodiment, those subjected to adhesive heat treatment at 800 ° C. have an average VF of 2.0 V and a maximum of 2. At 1V, it was the same as the VF of the conventional LED. On the other hand, the average VF of LEDs subjected to adhesive heat treatment at 400 ° C. is 2. While it is the same level at 1V, the maximum is as large as 3.2V, indicating that there is a part where direct adhesion is incomplete. This measurement result suggests that a decrease in the difference in thermal expansion of the wafer due to a decrease in the heat treatment temperature may not be compatible with the adhesion integrity.

  The manufacturing method of the adhesive type semiconductor substrate of a present Example is demonstrated referring FIG. FIG. 4A shows an epi-wafer used for the manufacturing method of this embodiment. The epiwafer shown in the figure differs from the epiwafer shown in FIG. 2A in that an etching stop layer 33 is formed between the GaAs buffer layer 38 and the GaAs substrate 32, and the other points are substantially the same. The etching stop layer 33 is InAlP having a thickness of 0.2 μm. A GaP wafer 31 to be described later is also substantially the same as that of the first embodiment.

  First, as shown in FIGS. 4A to 4C, the steps up to room temperature bonding in the direct bonding step were performed in the same manner as in the first example.

  Next, the GaAs substrate 32 is removed before heat treatment. This is a feature of this embodiment. 4C was immersed in a mixed solution of ammonia and hydrogen peroxide solution, and the GaAs substrate 32 was removed by etching. Since this etching solution does not etch InAlP, the etching stopper layer 33 remains on the surface after the etching as shown in FIG.

  After removing the GaAs substrate 32, heat treatment was performed as in the first embodiment. The processing temperature was set to 800 ° C., which is the higher of the two temperatures used in the first embodiment.

  Next, as shown in FIG. 4 (e), after the heat treatment, the etching stop layer 33 is removed by etching with a mixed solution of phosphoric acid, hydrogen peroxide solution, and water, and sulfuric acid, hydrogen peroxide solution, and water are removed. A part of the buffer layer 38 is left behind by etching with the mixed solution, and an electrode 39 is provided on the lower part of the GaP substrate 31 and the part where the upper buffer layer of the N-type clad layer 34 is left as in the first embodiment. LED 2 shown in FIG. 4F was obtained. The remaining buffer layer serves as a contact layer.

  When heat treatment was performed at 800 ° C., 3 of the 5 bonded bodies were broken in the first example, but all 5 groups were not broken and no cracks were observed in this example. In addition, the characteristics of the LED 2 of this example were the same as those manufactured from the adherend that was not broken by the heat treatment at 800 ° C. among the adherends of the first example in both luminance and VF.

  The reason why the GaAs substrate 32 on the epi-wafer is removed before the heat treatment to avoid the destruction of the adherend due to the heat treatment is as follows. That is, the destruction of the adherend is based on the difference between the thermal expansion coefficient of the epi wafer and the thermal expansion coefficient of the GaP substrate 31. Since most of the volume of the epi wafer is composed of the GaAs substrate 32, the average thermal expansion coefficient of the epi wafer is approximately equal to GaAs. Since GaAs has a larger thermal expansion coefficient than GaP, the average thermal expansion coefficient of the epi-wafer is also larger than that of the GaP substrate 31. On the other hand, despite the fact that the lattice constant of the epitaxial growth layer is adapted to the GaAs substrate 32, the epitaxial wafer is warped convexly on the epitaxial wafer side. This indicates that the thermal expansion coefficient of the epitaxial growth layer is smaller than the thermal expansion coefficient of the GaAs substrate 32. Therefore, if the GaAs substrate 32 is removed from the epi-wafer, the average thermal expansion coefficient of the epi-wafer becomes the thermal expansion coefficient of the epitaxial growth layer and is close to the GaP substrate 31. As a result, the adherend is not destroyed even after heat treatment. Therefore, even if not all of the GaAs substrate 32 is removed before the heat treatment, even if a part of the GaAs substrate 32 is removed, the average thermal expansion coefficient of the epi wafer approaches the GaP substrate 31, and the effect of preventing destruction of the adherend during the heat treatment. There is.

  In this embodiment, the etching stop layer 33 is used so that the N-type cladding layer 34 is not exposed during the heat treatment. The purpose of this is to prevent P (phosphorus) having a high vapor pressure from evaporating when the InGaAlP-based material is heated at a high temperature, which may cause so-called phosphorus removal. Thus, it is desirable not to expose the epitaxial growth layer directly involved in light emission such as the active layer and the cladding layer during the heat treatment.

  Regarding the direct bonding between different materials, in Japanese Patent No. 2801672, the present inventors have proposed a method in which one wafer is thinned and heat-treated at a high temperature after heat-treating at a low temperature. This method reduces the thermal stress applied to the other wafer by making one wafer thinner, and does not reduce the thermal stress by changing the average thermal expansion coefficient of the entire epi-wafer as in this embodiment. .

  In the method for manufacturing an adhesive substrate according to the present invention, it is also possible to remove the epiwafer substrate after heat treatment is performed at a low temperature to obtain a predetermined adhesive strength, and then heat treatment is performed at a predetermined high temperature. However, when the electrical characteristics of the adhesive surface become a problem as in this embodiment, it is desirable to perform the low-temperature heat treatment at a low temperature of 100 to 300 ° C. or lower. The reason for this is as follows. That is, the adhesion strength increases with the progress of the dehydration condensation reaction, but at the same time, the amount of desorbed water also increases. The adhesion reaction may be completed by raising the temperature as it is. However, once the heat treatment is stopped, moisture is fixed at the adhesion interface, and even if the temperature is raised again, there is a high possibility that the electrical characteristics will be adversely affected.

(Third embodiment)
Next, a third embodiment of the present invention will be described. This embodiment is characterized in that when two wafers are bonded, the orientation is aligned so that the “back” of one wafer and the “front” of the other wafer are bonded together in terms of crystallography. Have.

  FIG. 5 is a conceptual diagram for explaining a method of bonding substrates according to the present embodiment.

  That is, the semiconductor substrate is usually obtained by slicing a single crystal ingot as illustrated in FIG. 5A in a predetermined crystal orientation.

  Conventionally, as illustrated in FIG. 5B, the surfaces 111A and 112A of the wafers 111 and 112 sliced from the ingot IG are mirror-polished, and an epitaxial layer (not shown) is formed on the surfaces as necessary. Layers and the like were formed, and then bonded so that the surfaces 111A and 112A face each other.

  Here, regarding the resistance of the bonding interface, there is a difference between bonding of silicon (Si) and bonding of a compound. That is, between silicon (Si), regardless of the crystal orientation of the wafer to be bonded, if the carrier concentration on the bonding surface is increased and the bonding heat treatment temperature is selected within an appropriate range, no electrical resistance is generated at the interface. For example, even if the (111) plane is bonded to the (100) plane, the (100) plane wafers are rotated by 45 degrees, and there is no interface resistance.

  On the other hand, in the case of bonding a compound, particularly an LED wafer, resistance is generated at the interface unless the carrier orientation is increased and the plane orientation between the bonded wafers is not matched. According to this phenomenon, in order to reduce the interfacial resistance, a method in which wafers having the same angle of inclination with respect to the crystal direction are bonded to each other without rotating each other by aligning the directions of the crystal rotation directions. (USP) No. 5,661,316.

  On the other hand, as a result of trying the bonding by combining various crystal directions, the present inventor is not sufficient only to match the tilt and rotation direction of the wafer, particularly in a wafer having a plane inclined with respect to the crystal, We found that bonding the “back” surface of the other wafer to the “front” surface of one wafer has a significant effect on reducing the interfacial resistance.

  That is, in the present embodiment, as shown in FIG. 5C, the back surface 111 </ b> B of the wafer 111 and the front surface 112 </ b> A of the wafer 112 are bonded to face each other. As described later in detail, the present inventor has found that the adhesion can improve the crystallinity of the adhesion interface and can greatly reduce the electrical resistance component.

  For example, taking a group III-V compound semiconductor having a zinc-blende structure as an example, as shown in FIG. 5 (a), a single crystal ingot IG grown in the [100] direction has an axis of growth. There are a direction in which the (111) A plane appears and a direction in which the (111) B plane appears. Here, the (111) A plane is, for example, an atomic plane in which a group III element appears predominantly on the surface, and the (111) B plane is an atomic plane in which a group V element appears predominantly on the surface.

  The surfaces of the semiconductor substrates 111 and 112 obtained by slicing the single crystal ingot from the single crystal ingot in a direction inclined at a predetermined angle with respect to the (111) A plane are surfaces on which the physical properties of the (111) A plane appear predominantly. 111A and 112A. On the other hand, the back surfaces 111B and 112B of these semiconductor substrates 111 and 112 are surfaces on which the physical properties of the (111) B surface appear predominantly.

  The reason why the crystal is tilted and sliced is that the substrate having the tilted surface orientation is more convenient for epitaxial growth than the substrate having the so-called “just” orientation, so that the (100) plane is generally tilted in the (111) plane direction. . However, in the case of a compound semiconductor such as GaAs or GaP, as described above, there are two types on the (111) plane, one of which is covered with group III Ga and the other is group V As or P. Covered. It is known that when a crystal is processed so that the (111) plane becomes the front surface, the front surface and the back surface are different from each other.

  In the case of FIG. 5, for example, when slicing is performed so that the front surface side is inclined to the (111) III group surface, the back surface is inclined to the (111) V group surface. Therefore, as shown in FIG. 5C, bonding the front and back surfaces of the two semiconductor substrates includes a surface inclined to the (111) group III surface and a surface inclined to the (111) group V surface. It is none other than gluing.

  The (100) plane is inclined to the (111) III group plane, and the (100) plane and the (111) plane are mixed, and the ratio of group III atoms is high. Conversely, the plane inclined to the (111) group V plane has a high ratio of group V atoms. When both are combined, the ratio of group III and group V is maintained at the bonding interface, dangling bonds that adversely affect electrical characteristics are reduced, and electrical resistance can be reduced.

  Therefore, when the materials of the semiconductor substrates to be bonded are the same, it is desirable that the inclination angles of the surfaces are close to each other between the two substrates. In this case, the balance between the group III atom and the group V atom is most favorable.

  On the other hand, when semiconductor substrates made of different materials are bonded to each other, it is desirable to adjust the surface inclination angle in accordance with the physical properties of the two. This is because when the materials are different, the ratio of the group III atom or the group V atom to the tilt angle may be different.

  In the case of a semiconductor substrate having a surface with a small inclination angle (off-angle) in the direction in which anisotropy appears (for example, <111> direction in GaAs or GaP), dangling bonds can be formed even if the surfaces are combined. The number is small and the increase in interfacial resistance tends to be relatively small. On the other hand, when the inclination angle is 10 degrees or more, a remarkable effect can be obtained by combining the back surface and the front surface.

  On the other hand, according to the results of the study by the present inventors, even when the surface has a small inclination angle, for example, when a substrate having a (100) just surface with an inclination angle of 0 degrees is bonded, the back surface and the surface are bonded. Then the effect is seen. Conventionally, the (100) plane was considered to be electrically equivalent to the back surface and the front surface. However, III-V compound semiconductors such as GaAs and GaP have a zinc flash structure, where group III atoms and group V atoms are arranged in different face-centered lattice positions, and these lattices are diagonal to each other. It is shifted by 1/4 of the lattice constant. Therefore, the (100) plane is presumed that one of the group III atom or the group V atom comes out on the outermost surface and the other is inside the ¼ lattice. In this case, on the back surface of the substrate, atoms opposite to the front surface appear on the outermost surface in order to maintain electrical neutrality. For these reasons, it is considered that even when the (100) just surface is bonded, the front surface and the back surface are bonded together in order to reduce the number of dangling bonds and increase the interface resistance.

  The present embodiment also has a remarkable effect when two semiconductor substrates sliced from different ingots are bonded.

  FIG. 6 is a conceptual diagram showing a state in which semiconductor substrates sliced from two different ingots are bonded. For example, as shown in FIG. 5A, the semiconductor substrate 11 having an off-angle inclined in the (111) direction is sliced from a GaP single crystal ingot grown in the [100] direction. The semiconductor substrate 11 has a front surface 11A in which a component of (111) A plane appears strongly and a back surface 11B in which a component of (111) B plane appears strongly. Similarly, as shown in FIG. 6B, the semiconductor substrate 12 sliced from the GaAs ingot with an off-angle is also composed of the surface 12A in which the (111) A plane component is strongly expressed and the (111) B plane component. Has a back surface 12B that strongly appears.

  When bonding these two substrates, the back surface 11B and the front surface 12A are bonded. Alternatively, the front surface 11A and the back surface 12B are bonded. By adhering the front and back surfaces in this way, the balance between group III atoms and group V atoms at the interface is improved, dangling bonds and crystal defects are reduced, and electrical resistance is also greatly reduced. be able to.

  Note that the “front” and “back” of the semiconductor substrate sliced from different single crystal ingots can be determined by the growth direction of the ingot, that is, the orientation with respect to the seed crystal. That is, normally, the crystal orientation of the seed crystal is made constant when growing the ingot. Therefore, even in different ingots, the orientation of the (111) A plane or the (111) B plane has a certain relationship with the growth direction. In other words, in each of the semiconductor substrates sliced from different ingots, the side close to the seed crystal is defined as the “front” surface, and the opposite surface is defined as the “back” surface. The surface may be bonded.

  In the case of a compound semiconductor wafer that is generally commercially available, a linear cut portion called “index flat (IF)” or the like is formed on the wafer for the purpose of distinguishing between the (111) A surface and the B surface. It is often provided in the department. In such a case, the “front” and “back” of the wafer can be easily identified.

  The determination of “front” and “back” of a semiconductor substrate sliced from different ingots can also be made by mesa etching. That is, when mesa etching is performed on a GaAs or GaP wafer, the cross-sectional shapes of the mesas orthogonal to each other present a forward mesa and a reverse mesa. Further, the forward mesa directions are orthogonal to each other on the front surface and the back surface of the same wafer. The directions of the forward mesa and the reverse mesa appear corresponding to the orientations of the (111) A plane and the (111) B plane of the crystal, respectively. Therefore, the front side and the back side of the semiconductor substrate can be distinguished by the direction of the forward mesa and the reverse mesa.

  When the front and back surfaces of two semiconductor substrates are bonded, the forward mesa directions of the bonded surfaces are orthogonal to each other, and the opposite surfaces of the bonded surfaces, that is, the two wafers are bonded to one sheet. The forward mesa directions of one surface and the other surface of the new wafer are perpendicular to each other.

  Next, fourth to sixth examples will be described as specific examples of the present embodiment.

(Fourth embodiment)
First, as a fourth embodiment, a specific example in which the interface resistance of the bonded wafer is measured will be described.

  GaP wafers 111 and 112 were cut from the GaP single crystal ingot grown in the [100] direction as shown in FIG. Each of the cut wafers 111 and 112 is divided into two, and one set is a mirror surface formed by polishing the upper surfaces (front surfaces) 111A and 112A as shown in FIG. As shown in FIG. 5C, the lower surface (back surface) 111B of the wafer 111 and the upper surface (front surface) 112A of the wafer 112 were mirror-polished. The wafer whose surface is polished is inclined in the (111) Ga plane direction, and the wafer whose rear side is polished is inclined in the (111) P plane direction.

  Using these two sets of wafers, the surfaces were bonded together by a combination of the front and back surfaces, and the electrical resistances at the interfaces were compared.

  The bonding method was the same as the method described in detail later, and the heat treatment was performed at 800 ° C. A GaP epitaxial layer with different carrier concentrations was grown on the GaP adhesion surface, and the carrier concentration at the adhesion interface was adjusted to various values. The bonded wafer was provided with electrodes on both sides and half-diced so that the bonding surface had a size of 250 μm □, the IV characteristics were measured, and the bulk resistance of the GaP substrate was subtracted to determine the resistance at the bonding interface.

FIG. 7 is a graph showing the relationship between the carrier concentration of the adhesive surface and the interface resistance. In the figure, black circles represent the surfaces bonded together, and white triangles represent the surfaces bonded together. In adhesion between surfaces (black circles), increasing the carrier concentration decreases the interface resistance but does not reduce it to zero. On the other hand, in the combination of the back surface and the front surface (white triangle) of the present invention, even when the carrier concentration is low, the interface resistance is very low, and when the carrier concentration increases to about 2 × 10 ¹⁸ cm ⁻³ , the interface resistance is increased. Could be reduced to substantially zero.

  Note that the relationship between the carrier concentration and the interface resistance is the same even without the surface epilayer. If a substrate having a high carrier concentration is used, the interface resistance can be lowered without the epilayer.

(Fifth embodiment)
Next, as a fifth embodiment, a result of trial evaluation of an LED by the same process as that in FIG. 2 will be described.

  First, a GaAs wafer 12 inclined by 15 degrees in the (111) Ga plane direction was prepared, and LED structures 18 to 17 made of InGaAlP were epitaxially grown thereon as shown in FIG. The adhesion surface (surface of the p-type cladding layer 16) of the quaternary epitaxial wafer thus obtained is inclined 15 degrees in the (111) Ga plane direction, like the substrate.

  Next, as the GaP wafer 11, two GaP wafers inclined by 15 degrees in the (111) Ga plane direction were prepared, one of which was polished on the front side and the other was polished on the back side.

  Thereafter, the polished surface of the GaP wafer was bonded to the clad layer 16 as shown in FIG.

  Further, as shown in FIG. 2D, the GaAs substrate 12 was removed, and the operating voltage of the obtained LED was examined.

  As a result, the operating voltage at the time of 20 mA energization of the LED in which the adhesion surface of the GaP wafer 11 is inclined to the (111) Ga surface as in the GaAs substrate 12 was 4.5V. On the other hand, according to this embodiment, the operating voltage when the 20 mA energization of the LED with the adhesion surface of the GaP wafer 11 inclined to the (111) P surface is significantly reduced to 2 V, and the interface resistance is clearly reduced. It was.

(Sixth embodiment)
Next, a specific example in which wafers having a (100) just surface orientation are bonded together will be described as a sixth embodiment.

First, a wafer having a (100) just surface orientation was cut out from a GaP single crystal ingot and defined as a surface and a surface close to the seed crystal of the ingot. Next, the front side or the back side of these wafers was processed into a mirror surface, and a GaP layer having a layer thickness of 0.2 μm and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ was epitaxially grown on the mirror surface. Here, the reason why the carrier concentration of the epitaxial GaP layer is relatively low is that, as described above with reference to FIG. 7, the lower the carrier concentration, the greater the influence of the combination of the adhesive surfaces on the interface resistance, and the easier the comparison. .

  In this way, the front surfaces of the wafers or the front and back surfaces were bonded to each other with the epitaxial layer interposed therebetween, and the interface resistance was measured.

  As a result, when the surfaces were bonded to each other, the current-voltage characteristics at the interface were not ohmic, and a voltage of about 2.2 V was generated near the interface when 20 mA was applied. On the other hand, in the case where the front surface and the back surface are bonded, the current-voltage characteristics are linear and show ohmic properties, and the resistance when 20 mA is energized is as small as 0.8 V.

  The reason why a large resistance is generated in the case where the surfaces are bonded together is considered to be that dangling bonds trap carriers and the carrier concentration on the bonded surface is lowered. In other words, even in the case of a (100) just substrate, there are “front” and “back” of the wafer corresponding to the growth direction of the ingot, and the interfacial resistance is reduced by bonding the “front” and “back”. It was found that it could be significantly reduced.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. The present embodiment is characterized in that, when two wafers are bonded, the “deviation” due to thermal expansion is alleviated by pressing only a part of the wafer, not the entire wafer.

  FIG. 8 is a conceptual diagram for explaining the present embodiment. That is, when adhering two wafers A and B based on any of the above-described embodiments, the present inventor has independently studied how to hold and press these wafers.

  FIGS. 8A and 8B show a pressure holding method according to this embodiment, and FIGS. 8C and 8D show a pressure holding method as a comparative example.

  First, from the comparative example, in the example shown in FIG. 8C, the two wafers A and B are placed on a sufficiently wide jig J3 in a stacked state, and the load is applied from above. Is not applied. According to such a method, since the wafers A and B can freely expand and contract in the in-plane direction S, there is no problem such as cracking due to a difference in thermal expansion coefficient or the like, but adhesion is often insufficient. .

  Further, in the example shown in FIG. 8D, the two wafers A and B are held by the sufficiently wide jigs J3 and J4 and pressed by the load P. In this case, although pressure is applied, it becomes difficult for the wafers A and B to expand and contract in the in-plane direction, and the “break” such as a difference in thermal expansion coefficient cannot be absorbed and relaxed, and the wafer breaks. Sometimes.

  On the other hand, in the present embodiment, as shown in FIG. 8A, the jigs J1 and J1 that are arranged so as to face each other without pressing the entire surfaces of the two wafers A and B and Pressurize with weight P by J2. When the wafers A and B are made of different materials, a “deviation” due to a difference in thermal expansion coefficient occurs with heating. On the other hand, according to the present embodiment, by holding and pressing only a part of the wafer, portions other than the pressing portion can be easily expanded and contracted in the in-plane direction S. As a result, the bonding can be performed while allowing a “displacement” due to a difference in thermal expansion.

  In order to pressurize only a part of the wafer, as shown in FIG. 8B, only the contact area of one jig J1 may be smaller than the wafer. Also in this case, the entire wafer B is held by the jig J3, but the load P is applied only partially from the jig J1 on the wafer A. As a result, the wafers A and B can expand and contract in the in-plane direction S, and can absorb and mitigate “displacement” caused by the difference in thermal expansion coefficient.

  Hereinafter, examples of the present embodiment will be described.

(Seventh embodiment)
9A to 9D are schematic cross-sectional views for specifically explaining the manufacturing method of the present embodiment.

  First, as shown in FIG. 9A, an epi-wafer to be directly bonded includes a buffer layer 18, an n-type cladding layer 14, an active layer 15, a p-type cladding layer 16, and a surface on an n-type GaAs substrate 12. Cover layers 17 are sequentially laminated. These epitaxial growth layers are formed by, for example, MOCVD (Metal Organic Chemical Vapor Deposition).

The n-type GaAs substrate 12 has a size of 2 inches in diameter and a thickness of 250 μm, is doped with Si as a carrier at a carrier concentration of about 1E18 / cm ³ , and its main surface has a mirror finish. The buffer layer 18 is GaAs and has a thickness of 0.5 μm. The uppermost surface cover layer 17 has a two-layer structure, the lower side being a GaAs layer 17A having a thickness of 0.1 μm and the upper side being an InGaAlP layer 17B having a thickness of 0.2 μm.

  Next, the epiwafer is immersed in a mixed solution of ammonia and hydrogen peroxide to remove deposits on the back side. Next, the epiwafer is cleaned with a surfactant, and then the InGaAlP cover layer 17B with phosphoric acid at 70 ° C. Was etched. This etching selectively stops at the lower GaAs layer 17A. Next, etching was performed by immersing the epiwafer in a mixed solution of ammonia 1, hydrogen peroxide solution 15 by volume ratio, and the lower GaAs cover layer 17A was removed as shown in FIG. 9B. This mixed solution selectively etches the GaAs cover layer 17A. It was observed that the surface cover layer 17A was removed in a few seconds, but the immersion was continued for 1 minute so that the surface of the p-type cladding layer 16 was removed. Fully exposed.

Next, the epi-wafer from which the surface cover layer 17 was removed was directly bonded to the GaP substrate 11 on which a high-concentration GaP layer having a thickness of 0.2 μm and a carrier concentration of 2 × 10 ¹⁸ cm ⁻³ was grown, and FIG. The adherend shown in c) was obtained. Hereinafter, the direct bonding process will be described in more detail.

  As a pretreatment for direct bonding, the GaP substrate 11 was washed with a surfactant, immersed in dilute hydrofluoric acid to remove the natural oxide film on the surface, washed with water, and then dried with a spinner. Further, after removing the surface cover layer 17 by the above-described method, the epiwafer was subjected to dilute hydrofluoric acid treatment for removing the oxide film in the same manner as the GaP substrate 11, and then washed with water and spinner dried. All of these pretreatments were performed in a clean atmosphere in a clean room.

  As described above with respect to the third embodiment, it goes without saying that the crystal orientation may be adjusted so that the front surface and the back surface of the epi wafer and the GaP substrate 11 are bonded to each other also in this embodiment.

  Next, the pre-processed epi-wafer was placed with the epitaxial growth layer facing upward, and the GaP substrate 11 was placed thereon with the mirror surface facing downward, and was brought into close contact at room temperature. Since GaP is transparent, the contact state can be visually observed. When the GaP substrate 11 was placed on the epi-wafer, the epi-wafer was warped so as to form a convex shape in front view, so that the central portion of the GaP substrate 11 was first adhered. The contact part naturally spreads toward the peripheral part of the GaP substrate 11 just by leaving it as it is, and the entire surface except the chamfered part of the periphery of the GaP substrate 11 was in close contact within 1 minute. The same operation was repeated, and a total of 15 groups were brought into close contact with the room temperature.

  As the final step of direct bonding, the adherend adhered at room temperature was placed in a diffusion furnace and heat treated at 800 ° C. The atmosphere is argon containing 10% hydrogen.

  The adherends were divided into 3 groups of 5 groups, and different heat treatment jigs were used at the same time for comparison.

  As an example of the present invention, as illustrated in FIG. 8 (a), a substrate closely attached by a carbon plate with a 5φ circular protrusion at the center is sandwiched from above and below, and a 120 g carbon weight is placed thereon. Only the central part of the wafer was pressed. With this jig, all the wafers could be bonded together, and the wafer was not cracked.

  As a comparative example, as illustrated in FIG. 8C, the wafer was placed on a flat carbon plate and heat-treated in an unloaded state without placing anything on it. In this method, two of the five sheets had large peeling portions exceeding 30% in area. There was no cracking of the wafer.

  As another comparative example, as illustrated in FIG. 8D, the wafer was sandwiched between flat carbon plates, and a weight was placed on the entire surface to heat-treat. In this case, two of the five sheets were cracked, and the remaining three sheets did not reach full adhesion. Since the peripheral part of the wafer, including the broken wafer, was bonded and the central part was peeled off, the peripheral part that was thick due to the variation in the thickness of the wafer was bonded first, and the deviation of the interface due to thermal expansion was absorbed. It is thought that the cause was the failure.

  As described above, according to this embodiment, it was confirmed that the bonding process can be performed with a high yield by partially holding and pressing the wafer.

(Fifth embodiment)
Next, as a fifth embodiment of the present invention, a semiconductor light emitting device having a substrate that is transparent to light from the light emitting layer will be described. That is, the semiconductor light emitting device according to this embodiment is typically a light emitting device that can be formed using the substrate bonding technique described above with respect to the first to fourth embodiments.

  First, as the semiconductor light emitting device according to the present embodiment, an example in which the luminance of light emission is improved by reducing the area of the light emitting layer contributing to light emission relative to the area of the transparent substrate will be described. FIG. 10A is a conceptual diagram showing a cross-sectional configuration of an LED according to this embodiment, and FIG. 10B is a conceptual diagram showing a cross-sectional configuration of a conventional LED as a comparative example.

  That is, each of the LEDs has a clad layer 14, an active layer 15, and a clad layer 16 on a GaP substrate 11 which is a transparent substrate, and electrodes 19A and 19B are provided above and below. However, FIG. 10 is a conceptual diagram. In practice, various elements such as a contact layer, a current confinement layer, and a current diffusion layer may be provided in addition to these.

  In the conventional LED, as shown in FIG. 10B, the active layer 15 and the transparent substrate 11 have the same size and the same area as viewed from above. Such a conventional LED can be manufactured, for example, by dividing a wafer in which a large number of LED structures are formed by dicing or cleaving into a large number of LED chips.

  On the other hand, in this embodiment, the area of the stacked body 10 including the active layer 15 is smaller than the transparent substrate 11. When the area of the active layer 15 is reduced in this way, the light emission luminance of the LED is improved. Hereinafter, a mechanism for increasing the luminance of the LED when the area of the active layer is reduced will be described.

  The LED emits light when the injected carriers are recombined by passing a current. In the case of the LED shown in FIGS. 10A and 10B, the injected carriers are confined in the active layer 15 sandwiched between the cladding layers 14 and 16, and recombine there. However, recombination of carriers includes not only light emission accompanied by light emission but also non-light emission recombination without light emission. For example, when recombination occurs through a crystal defect level or an interface level, recombination occurs without light emission.

  Since non-radiative recombination is faster than luminescent recombination, injected carriers tend to preferentially cause non-radiative recombination. On the other hand, since the density of defect states and interface states is limited in the crystal, when non-radiative recombination is saturated at a certain current, a current exceeding that is consumed for radiative recombination to emit light. It comes to occur. Therefore, when the same amount of current is applied to the LED, the current component consumed by non-radiative recombination can be reduced by flowing it in a small area, and the ratio of radiative recombination to the injected current, that is, the luminous efficiency is increased. be able to. That is, the luminance of the LED can be increased by reducing the area of the active layer 15.

  However, if the area of the light emitting layer is reduced, there is a problem in that light emission is blocked by the electrode 19A and the light extraction efficiency is lowered. On the other hand, it is advantageous if the substrate is transparent.

  That is, since the light emitting layer of the LED is thinner than the substrate, the light emitted from the light emitting layer to the substrate side is absorbed by the substrate and cannot be extracted outside in an LED having an opaque substrate. That is, in the case of an LED using an opaque substrate, only light emitted upward from the light emitting layer can be extracted to the outside. However, when the light emitting layer is made small with such an opaque substrate LED, the decrease in extraction efficiency due to the light shielding of the upper electrode 19A becomes larger than the increase in light emission efficiency, and the brightness of the LED decreases.

  For the same reason, it is not preferable to reduce not only the light emitting layer but also the area of the substrate at the same time even for the transparent substrate LED. In the transparent substrate LED, as shown in FIG. 10A, the light emitted from the light emitting layer to the substrate side is transmitted through the substrate 11 and reflected by the lower electrode 19B. When the upper surface S of the transparent substrate 11 is exposed on both sides of the laminate 10 as the light emitting layer, the light reflected by the lower electrode 19B can be extracted from the exposed portion S. For this reason, even if the laminate 10 as the light emitting layer is made small, the extraction efficiency is not lowered unless the area of the substrate 11 is made small.

  FIG. 11 is a graph showing the relationship between the ratio of the area of the light emitting layer to the chip area and the external light emission intensity in the InGaAlP-based LED having the transparent substrate as illustrated in FIG. That is, this figure shows data of InGaAlP-based LEDs formed by bonding a GaP substrate, the chip size is 300 μm square, and the upper electrode size is 120 μφ.

  As shown in the figure, the emission intensity increases as the area of the light emitting layer is reduced. When the area ratio becomes 0.3, the emission intensity increases to about 1.2 times that in the case of the ratio 1. As described above, in the LED using the transparent substrate, when the light emitting layer is formed to be smaller than the substrate, it is possible to improve the light emission efficiency in the active layer 15 and to suppress the decrease in the light extraction efficiency.

  Next, a specific example of the method for manufacturing the light emitting device of this embodiment will be described.

  12 and 13 are process cross-sectional views showing the main part of the method for manufacturing the semiconductor light emitting device of this embodiment.

  The structure of the epi-wafer used for direct bonding is as shown in FIG. 12A, and the epitaxial layers 93 to 982 are grown on the GaAs substrate 12 by MOCVD. Here, the n-type GaAs substrate 12 has a diameter of 2 inches, a thickness of 250 μm, Si doping, a carrier concentration of about 1e18 / cm 3, and a mirror finish. The etching stopper layer 93 is InAlP and has a thickness of 0.2 μm. The GaAs contact layer 94 has a thickness of 0.02 μm and a carrier concentration of 1e18 / cm 3. The InGaAlP current spreading layer 95 is InGaAlP having an Al composition of 0.3 and a thickness of 1.5 μm, and the N-type cladding layer 14 is InGaAlP having an Al composition of 0.6 and a thickness of 0.6 μm. The active layer 15 is InGaAlP having an Al composition of 0.13 and a thickness of 0.4 μm. The P-type cladding layer 16 is InGaAlP having an Al composition of 0.6 and has a thickness of 0.6 μm. The InGaP adhesive layer 97 has a thickness of 0.1 μm, the GaAs cover layer 981 has a thickness of 0.1 μm, and the InAlP cover layer 982 has a thickness of 0.15 μm.

  Next, this epi-wafer is cleaned with a surfactant, immersed in a mixed solution of ammonia 1 and hydrogen peroxide solution 15 in a volume ratio, the lower side of the GaAs substrate 12 is etched, and the epi-wax adhered to the back surface of the epi-wafer. The reaction product and the like are removed. At this time, the front side of the epi-wafer (the upper side in the figure) is covered with the InAlP cover layer 982, and is not etched.

  Next, after cleaning the epiwafer again with a surfactant, the surface InAlP cover layer 982 is removed with phosphoric acid. Subsequently, the GaAs cover layer 981 is removed with a mixed solution of sulfuric acid 8, hydrogen peroxide solution 1, and water 1 in volume ratio. This mixed solution selectively etches the GaAs cover layer. After the etching, an InGaP adhesive layer appears on the surface of the epi-wafer.

  Next, the epi wafer from which the surface cover layer was removed and the GaP wafer 11 were directly bonded to obtain an bonded body shown in FIG. Hereinafter, the direct bonding process will be described in detail.

  A GaP wafer having a diameter of 2 inches, a thickness of 250 μm, and a p-type mirror finish was used. In order to reduce the electrical resistance of the bonding interface, a high concentration layer may be epitaxially grown on the GaP surface.

  Here, as described above with reference to the third embodiment, it is desirable to adjust the crystal orientations of the epi layer and the GaP layer so that the bonding surfaces of the epi layer and the GaP layer have a “front” and “back” relationship.

  As a pretreatment for direct bonding, the GaP wafer was washed with a surfactant, immersed in dilute hydrofluoric acid to remove the natural oxide film on the surface, washed with water, and then dried with a spinner. Further, after removing the surface cover layer, the epiwafer was subjected to dilute hydrofluoric acid treatment for removing the oxide film, similarly to the GaP substrate, and then washed with water and spinner dried. All of these pretreatments were performed in a clean atmosphere in the clean room.

  Next, the pre-processed epi-wafer was placed facing upward, and the GaP wafer 11 was placed thereon so that the mirror surface would be facing downward, and adhered at room temperature. Since the GaP wafer 11 is transparent, the contact state can be observed. When the wafers were stacked, the epi-wafer warped convexly, so that the central part of the wafer was in close contact first. By simply leaving it as it is, the close contact part naturally spreads, and the entire surface is in close contact except for the chamfered part of the edge of the wafer.

  Also in this step, as described above with reference to the fourth embodiment, by pressing only a part of the wafer, cracking can be suppressed and bonding can be performed reliably.

  As the final step of direct bonding, the wafers that were in close contact at room temperature were arranged in a quartz boat and placed in a diffusion furnace for heat treatment. The heat treatment temperature is 800 ° C., the time is 1 hour, and the atmosphere is argon containing 10% hydrogen.

  Next, the GaAs substrate 12 of the epiwafer was removed. First, the adhesive body was immersed in a mixed solution of ammonia and hydrogen peroxide solution, and GaAs was selectively etched. This etching stops at the InAlP etching stop layer. Next, etching was performed with phosphoric acid at 70 ° C., and the InAlP etching stop layer 93 was selectively removed, thereby obtaining a stacked body shown in FIG.

  Next, an electrode 19B made of gold (Au) / Zn alloy and gold (Au) is provided on the back surface (lower side in the figure) of the GaP substrate 11 of this laminate, and the surface of the GaAs contact layer 94 (upper side in the figure). Is provided with an electrode 19A made of gold (Au) / Ge alloy and gold (Au). Then, the upper electrode 19A was processed into a circle having a diameter of 200 μm at a pitch of 300 μm by PEP (photo-engraving process) to obtain the structure of FIG.

  Next, in order to make the area of the light emitting layer smaller than the area of the transparent substrate, etching was performed using the gold electrode 19A as a mask, and the epi layers 94 to 97 were etched as shown in FIG. Here, the GaAs epi layer 94 was etched with a mixed solution of ammonia and hydrogen peroxide, and the InGaAlP-based epi layers 94 to 16 and the InGaP epi layer 97 were etched with an HBr—Br solution.

  Finally, as shown in FIG. 13C, the electrode 19A is re-patterned into a circle having a diameter of 120 μm, and the wafer is cleaved and separated into 300 μm square at the portion indicated by the alternate long and short dash line C, and the structure shown in FIG. LED chip was obtained.

  In FIG. 10A, a part of the epi layer in FIG. 13C is omitted.

  Next, as another example of the present embodiment, a manufacturing method for reducing the area of the light emitting layer prior to wafer bonding will be described.

  FIG. 14 is a process cross-sectional view illustrating the main part of the manufacturing method of the present embodiment.

  First, as shown in FIG. 14A, an epitaxial wafer in which a stacked body 10 as a light emitting layer is formed on a GaAs substrate 12 is formed. This epiwafer was subjected to blade dicing vertically and horizontally at a pitch of 300 μm, for example, and grooves G having a width of 100 μm and a depth of 20 μm were provided as shown in FIG.

  Next, as shown in FIG. 14C, the GaP substrate 11 is bonded.

  Next, as shown in FIG. 14D, the GaAs substrate 12 is removed, and the electrodes 19A and 19B are formed upside down.

  Finally, element separation was performed along the alternate long and short dash line C by cleavage or blade dicing, and an LED chip was obtained as shown in FIG.

  When the epi wafer formed on the GaAs substrate 12 and the GaP substrate 11 are bonded, stress is generated due to the difference in thermal expansion coefficient between GaAs and GaP, and warping after bonding or, if severe, the wafer is broken. .

  In this embodiment, as shown in FIG. 14C, since the groove G is formed on the surface of the epi-wafer and the bonded portion is divided into small areas at the time of wafer bonding, the stress is relieved, warping and breaking The advantage that there is less is obtained.

  In addition, when the wafers are bonded together, air may be caught between the two wafers to generate an unbonded portion. If the groove G is provided as in this embodiment, the entrained air can be released to the outside of the wafer, and there is also an advantage that the occurrence of unbonded portions is reduced.

  In the above-described embodiment, the example in which the epi-wafer surface is divided by blade dicing before bonding is described. However, the groove G may be formed by patterning the wafer surface by PEP.

  Next, a modified example of the semiconductor light emitting device of this embodiment will be described.

  FIG. 15 is a conceptual diagram showing a modification of the semiconductor light emitting device of this embodiment. That is, in the present modification, the stacked body 10 as the light emitting layer is reduced to substantially the same area as the upper electrode 19A.

  In this structure, since the electrode 19A covers the entire top surface of the laminate 10 as the light emitting layer, the light emitted upward from the light emitting layer is reflected by the electrode 19A and enters the transparent substrate 11, and is externally transmitted from the side surface of the substrate 11 to the outside. Or is reflected from the lower electrode 19B and taken out from the upper surface S of the substrate 11 that is not covered by the electrode 19A.

  The light emitting element of this modification is functionally different from the embodiment of FIG. 10A and the conventional example of FIG. 10B in that light extracted from the upper surface of the LED almost passes through the light emitting layer 16. There is no point. In other words, in this modified example, the active layer 15 acts as a relatively small light source, and most of the light emitted from this light source passes through the substrate 11 and is reflected by the lower electrode 19B, and is reflected from the upper surface S to the outside. To be taken out.

  The emission wavelength of the LED is determined by the band gap of the active layer 15. The clad layers 14 and 16 are designed to have a larger band gap than the active layer in order to confine carriers, and do not absorb light emitted from the active layer 15. However, the active layer 15 itself absorbs light emitted by itself. A layer with a small band gap such as a GaAs contact layer necessary for electrical connection also absorbs light emission. Therefore, absorption is less if the light is extracted without passing through an active layer or a contact layer including a light absorbing layer. In this respect, the modified example illustrated in FIG. 14 is advantageous.

  In order to obtain the structure of FIG. 15, for example, in the process shown in FIGS. 12 to 13, the first patterning of the electrode 19 </ b> A shown in FIG. 13A is performed with the size of FIG. The light emitting layer may be etched using the electrode 19A as a mask.

  Alternatively, the light-emitting element of FIG. 15 can be manufactured by a completely different method. 16 is a process cross-sectional view illustrating a main part of the method for manufacturing the semiconductor light emitting device illustrated in FIG. 15.

  First, as shown in FIG. 16A, the upper and lower electrodes 19A and 19B are attached to the entire surface and separated into chips without patterning.

  Next, as shown in FIG. 16B, the wire W is bonded to the chip thus obtained. Then, on the electrode 19A, the ball portion 19C in which the wire W is formed in a ball shape is connected.

  Next, using the ball portion 19C as a mask, the upper electrode 19A and the laminated body 10 as the light emitting layer are etched to obtain the structure shown in FIG.

  According to the method described above, it is possible to emit light by energization through the wire W when the stacked body 10 is etched. In other words, the etching can be stopped when the optimum light emission intensity is obtained by performing the etching while causing the light emitting element to emit light and monitoring its output.

  Next, a semiconductor light emitting device as another example of the present embodiment will be described.

  FIG. 17 is a conceptual diagram showing the configuration of the semiconductor light emitting device according to this example. That is, in the light emitting device of this example, the step ST is provided on the side surface of the transparent substrate 11, and the upper part thereof is made small according to the size of the laminate 10 as the light emitting layer.

  In this structure, after the GaP wafer 11 is bonded and a GaAs substrate (not shown) is removed by selective etching, for example, in the state shown in FIGS. 12 (c) and 16 (a), it is transparent from the light emitting layer side beyond the light emitting layer. It is obtained by providing a groove by blade dicing or etching up to the top of the substrate 11.

  In the light emitting device of this embodiment, the light incident on the transparent substrate 11 from the active layer 15 is not only extracted directly or reflected once, but also reflected inside the transparent substrate 11 in a complicated manner. Often taken outside. In general, the light extraction efficiency is higher when the shape of the light extraction portion is complicated, and according to the present embodiment, by providing a step in the transparent substrate 11, it is possible to further improve the light extraction efficiency.

  In the example shown in FIG. 17, the upper portion of the transparent substrate 11 is made one step smaller than the lower portion. However, the light extraction efficiency may be further improved by narrowing down to two or more steps. is there.

  The first to fifth embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  For example, the material of a wafer to be bonded or a semiconductor element using the same is not limited to GaAs or GaP, and the same effect can be obtained by applying the present invention to other various compound semiconductors.

  Further, with respect to the laminated structure of the semiconductor light emitting device, the same effect can be obtained by adding various elements such as a contact layer and a current diffusion layer. In addition to this, for example, the case where an MQW (multiple-quantum well) structure is adopted for the active layer and the case where an MQB (multiple-quantum barrier) is adopted for the clad layer can be similarly applied.

  Furthermore, the present invention is not limited to LEDs, and can be similarly applied to semiconductor lasers and other various semiconductor elements.

1 is a schematic cross-sectional view showing an embodiment of an adhesive semiconductor substrate according to the present invention. It is a schematic sectional drawing explaining the 1st Example and 2nd Example of the manufacturing method of the adhesion type semiconductor substrate concerning this invention. It is a table | surface which shows the structural ratio of the InGaAlP material used for the manufacturing method of the adhesion type semiconductor substrate concerning this invention, a lattice constant, and a band gap. It is a schematic sectional drawing explaining the 3rd Example of the manufacturing method of the adhesion type semiconductor substrate concerning this invention. It is a conceptual diagram for demonstrating the adhesion method of the board | substrate concerning 3rd Embodiment of this invention. It is the conceptual diagram showing a mode that the semiconductor substrate sliced from two different ingots was adhere | attached. It is a graph showing the relationship between the carrier concentration of an adhesion surface and interface resistance. It is a conceptual diagram for demonstrating 4th Embodiment of this invention. 9A to 9D are schematic sectional views for specifically explaining the manufacturing method of the seventh embodiment of the present invention. FIG. 10A is a conceptual diagram illustrating a cross-sectional configuration of an LED according to a fifth embodiment of the present invention, and FIG. 10B is a conceptual diagram illustrating a cross-sectional configuration of a conventional LED as a comparative example. . FIG. 11 is a graph showing the relationship between the ratio of the area of the light emitting layer to the chip area and the external light emission intensity in the InGaAlP-based LED having the transparent substrate as illustrated in FIG. 10. It is process sectional drawing showing the principal part of the manufacturing method of the semiconductor light-emitting device of 5th Embodiment of this invention. It is process sectional drawing showing the principal part of the manufacturing method of the semiconductor light-emitting device of 5th Embodiment of this invention. It is process sectional drawing showing the principal part of the manufacturing method which makes the area of a light emitting layer small prior to wafer adhesion | attachment. It is a conceptual diagram showing the semiconductor light-emitting device which made the laminated body 10 as a light emitting layer small to the substantially same area as upper electrode 19A. FIG. 16 is a process cross-sectional view illustrating a main part of the method for manufacturing the semiconductor light emitting element illustrated in FIG. 15. 2 is a conceptual diagram illustrating a configuration of a semiconductor light emitting device in which a step ST is provided on a side surface of a transparent substrate 11. It is a schematic sectional drawing which shows an example of InGaAlP visible light LED by a prior art. FIG. 19 is a schematic cross-sectional view showing a conventional method for manufacturing the LED shown in FIG. 18.

Explanation of symbols

1,2,100 InGaAl LED
10 Stack 11, 31, 91 GaP wafer 12, 32, 82, 92 GaAs wafer 33 Etching stop layer 14, 34, 84, 94 N-type cladding layer 15, 35, 85, 95 Active layer 16, 36, 86, 96 P-type cladding layer 17, 37 Cover layer 18, 38 Buffer layer 19, 39, 89, 99 Electrode

Claims (3)

Epitaxially growing a compound semiconductor mixed crystal on a first semiconductor substrate to form a first epitaxial growth layer including a stacked body in which a first cladding layer, an active layer, and a second cladding layer are sequentially deposited;
A main surface of the second semiconductor substrate or a second epitaxial growth layer formed on the main surface is placed so as to be in contact with the first epitaxial growth layer and integrally joined;
Removing the first semiconductor substrate and exposing the first epitaxial growth layer;
Forming an electrode on the exposed surface side of the first epitaxial growth layer and the back surface side of the second semiconductor substrate,
In the step of integrally bonding, the second surface of the first surface of the first semiconductor substrate is formed with respect to a surface on which one of the (111) A surface and the (111) B surface appears preferentially. Bonding a surface in which either one of the (111) A surface and the (111) B surface appears preferentially among the main surfaces of the semiconductor substrate. The first semiconductor substrate is formed mainly of GaAs,
The first epitaxial growth layer is formed so as to lattice match with GaAs of the first semiconductor substrate,
The method of manufacturing a semiconductor light emitting element according to claim 1, wherein the second semiconductor substrate is formed with GaP as a main component. The first semiconductor substrate has a surface inclined at a first inclination angle from a (100) plane to a (111) Ga plane direction;
3. The method of manufacturing a semiconductor light emitting element according to claim 2, wherein the second semiconductor substrate has a surface inclined at a second inclination angle from a (100) plane to a (111) P plane direction.

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