JP4451683B2 - Semiconductor light emitting device, manufacturing method thereof, and light emitting diode - Google Patents

Semiconductor light emitting device, manufacturing method thereof, and light emitting diode Download PDF

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JP4451683B2
JP4451683B2 JP2004065748A JP2004065748A JP4451683B2 JP 4451683 B2 JP4451683 B2 JP 4451683B2 JP 2004065748 A JP2004065748 A JP 2004065748A JP 2004065748 A JP2004065748 A JP 2004065748A JP 4451683 B2 JP4451683 B2 JP 4451683B2
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light emitting
semiconductor
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emitting element
transparent substrate
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JP2004297056A5 (en
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良一 竹内
亙 鍋倉
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Showa Denko KK
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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Description

この発明は、透明基板を用いた半導体発光素子、その製造方法および発光ダイオードに関する。   The present invention relates to a semiconductor light emitting device using a transparent substrate, a manufacturing method thereof, and a light emitting diode.

従来、半導体発光素子(以下、単に「発光素子」という)の高輝度化や機械的強度の向上を目的として、半導体層を積層させたその不透明半導体基板を除去し透明基板を接着する技術が知られている。そして、半導体層の表面に透明基板を接合する方法は、技術的に難しく多種類の方法が考案され、例えば下記の特許文献1,2,3で知られている。   2. Description of the Related Art Conventionally, for the purpose of increasing the brightness of a semiconductor light emitting element (hereinafter simply referred to as “light emitting element”) and improving the mechanical strength, a technique for removing the opaque semiconductor substrate on which the semiconductor layers are laminated and bonding the transparent substrate is known. It has been. And the method of joining a transparent substrate to the surface of a semiconductor layer is technically difficult, and many kinds of methods are devised, for example, the following patent documents 1, 2, and 3 are known.

特許第3230638号公報Japanese Patent No. 3230638 特開平6−302857号公報JP-A-6-302857 特開2002−246640号公報JP 2002-246640 A

特許文献1には、半導体層に透明な基板を高温下で圧力をかけながら直接接着する方法が記載され、特許文献2には、直接ウェーハボンディング法を利用して接着する方法が記載され、また特許文献3には、エポキシ樹脂などの透明粘着物質を利用して接着する方法が記載されている。   Patent Document 1 describes a method of directly bonding a transparent substrate to a semiconductor layer while applying pressure at a high temperature. Patent Document 2 describes a method of directly bonding using a wafer bonding method. Patent Document 3 describes a method of bonding using a transparent adhesive material such as an epoxy resin.

上記の特許文献1〜3のうち、特許文献1,2の直接接合法は、一般的に700℃以上の高温・高圧力が必要となり、半導体層に大きなストレスがかかる。また、軟化しない固体同士の接合であるため、表面が平滑でないと接合が不均一となり、接合不良が多発する。さらに、高温での接合は、熱膨張係数の差による反りの発生や機械的応力によるストレスが大きくなり、冷却中に割れたり、クラックが入ることが多く、発光部の品質低下を招き、安定的に製造するには高度な技術および設備が必要である。   Of the above Patent Documents 1 to 3, the direct bonding methods of Patent Documents 1 and 2 generally require a high temperature and high pressure of 700 ° C. or higher, and a large stress is applied to the semiconductor layer. Moreover, since it is joining of solids which do not soften, if the surface is not smooth, joining will become non-uniform | heterogenous and joining failure will occur frequently. Furthermore, bonding at high temperatures is more stable due to the occurrence of warpage due to differences in thermal expansion coefficient and stress due to mechanical stress, which often cracks or cracks during cooling, leading to deterioration in the quality of the light emitting part. Advanced technology and equipment are required for manufacturing.

一方、特許文献3の接着方法では、低温で接合できるため、高温でのストレス、表面の荒れによる接合不良は改善されるが、樹脂系の材料は、高温に耐えられないため、接着後の工程に大きな制約を受けるという課題がある。例えば、接着後のオーミック電極形成では400℃以上の熱処理が実施されるが、その際に樹脂系の材料が変質し、接着層が不透明となる問題点が発生する。   On the other hand, in the bonding method of Patent Document 3, since bonding can be performed at a low temperature, bonding failure due to stress at high temperature and surface roughness is improved. However, since a resin-based material cannot withstand high temperature, a process after bonding is performed. There is a problem of being subject to significant restrictions. For example, when forming an ohmic electrode after bonding, a heat treatment at 400 ° C. or higher is performed. However, at this time, the resin-based material changes in quality and the adhesive layer becomes opaque.

また、特許文献1,2におけるストレスの発生や、特許文献3における接着層の変質により、ダイシングやスクライブなどの素子分離工程で、接合部の剥がれやクラックが多発する。このため、低温、低ストレスで接着し、かつ耐熱性を満足する接着方法を両立するのが困難であった。   In addition, due to the occurrence of stress in Patent Documents 1 and 2 and the alteration of the adhesive layer in Patent Document 3, peeling of the joints and cracks frequently occur in element separation processes such as dicing and scribing. For this reason, it has been difficult to achieve both an adhesion method that adheres at low temperature and low stress and satisfies heat resistance.

本発明は、上記の問題点に鑑み提案されたもので、700℃以下の低温、低圧力の接合条件においても接着力の高く、耐熱性に優れた接着層を見出し、接合時に発生するストレスを減少でき、安定生産が可能となる高輝度の半導体発光素子、その製造方法および発光ダイオードを提供することを目的とする。   The present invention has been proposed in view of the above-described problems, and has found an adhesive layer having high adhesive force and excellent heat resistance even under low temperature and low pressure bonding conditions of 700 ° C. or lower, and stress generated during bonding. An object of the present invention is to provide a high-luminance semiconductor light-emitting device that can be reduced and can be stably produced, a method for manufacturing the same, and a light-emitting diode.

上記目的を達成するために、本発明は、(1)半導体発光素子であって、発光部を含む半導体層と、前記発光部の発光波長に対して透明な透明基板と、前記半導体層と前記透明基板とを接合する低融点ガラス層と、を含み、前記低融点ガラス層は熱膨張係数が2〜9×10 -6 /Kであり、前記透明基板は熱膨張係数2〜9×10 -6 /Kのガラスからなる、ことを特徴としている。 To achieve the above object, the present invention provides (1) a semiconductor light emitting element, a semiconductor layer including a light emitting portion, a transparent transparent substrate to the emission wavelength of the light emitting portion, the semiconductor layer and the seen containing a low-melting point glass layer for bonding the transparent substrate, wherein the low-melting-point glass layer is the thermal expansion coefficient of 2~9 × 10 -6 / K, the transparent substrate is thermal expansion coefficient of 2 to 9 × 10 -6 / K glass .

また、本発明は、(2)上記した(1)に記載の発明の構成に加えて、前記低融点ガラス層は軟化点が500℃以上700℃以下であり、前記半導体層と透明基板とを接合する際の接着温度が500℃以上700℃以下である、ことを特徴としている。   In addition to (2) the configuration of the invention described in (1) above, the low melting point glass layer has a softening point of 500 ° C. or more and 700 ° C. or less, and the semiconductor layer and the transparent substrate are combined. The bonding temperature at the time of joining is 500 ° C. or more and 700 ° C. or less.

また、本発明は、()上記した(1)または(2)に記載の発明の構成に加えて、前記低融点ガラス層は鉛を含まない、ことを特徴としている。 Further, the present invention is characterized in that ( 3 ) in addition to the configuration of the invention described in (1) or (2) above, the low-melting glass layer does not contain lead.

本発明は、()上記した(1)乃至()に記載の発明の構成に加えて、前記低融点ガラス層はSiO2、ZnO、B23を主成分とする、ことを特徴としている。 The present invention (4) in addition to the structure of the invention according to the above (1) to (3), the low-melting-point glass layer is SiO 2, ZnO, and B 2 O 3 as a main component, characterized in that It is said.

さらに、本発明は、()上記した(1)乃至()に記載の発明の構成に加えて、前記透明基板は厚さが70μm以上300μm以下である、ことを特徴としている。 Furthermore, the present invention is characterized in that ( 5 ) in addition to the configuration of the invention described in (1) to ( 4 ) above, the transparent substrate has a thickness of 70 μm or more and 300 μm or less.

本発明は、()上記した(1)乃至()に記載の発明の構成に加えて、前記発光部はAlGaInPからなる、ことを特徴としている。 The present invention is characterized in that ( 6 ) in addition to the configuration of the invention described in the above (1) to ( 5 ), the light emitting portion is made of AlGaInP.

また、本発明は、()上記した(1)乃至()に記載の発明の構成に加えて、前記発光部はGaInN混晶を含む、ことを特徴としている。 Further, the present invention is characterized in that ( 7 ) in addition to the configuration of the invention described in (1) to ( 5 ) above, the light emitting portion includes a GaInN mixed crystal.

また、本発明は、()上記した(1)乃至()に記載の発明の構成に加えて、前記発光部は、量子井戸構造を備えた、シングルへテロ構造またはダブルへテロ構造である、ことを特徴としている。 In addition to the configuration of the invention described in ( 8 ) above (1) to ( 7 ), the present invention provides the light emitting portion having a single heterostructure or a double heterostructure having a quantum well structure. It is characterized by that.

また、本発明は、()上記した(1)乃至()に記載の発明の構成に加えて、前記半導体層はAsを含まない、ことを特徴としている。 In addition to the configuration of the invention described in ( 9 ) (1) to ( 8 ), the present invention is characterized in that the semiconductor layer does not contain As.

また、本発明は、(10)上記した(1)乃至()に記載の発明の構成に加えて、前記半導体層の第1の極性を有する表面に形成した第1のオーミック電極と、前記第1の極性を有する表面およびその表面に形成した第1のオーミック電極を覆う金属反射層と、前記半導体層の第2の極性を有する表面に形成した第2のオーミック電極と、を有することを特徴としている。
また、本発明は、(11)半導体発光素子であって、発光部を含む半導体層と、前記発光部の発光波長に対して透明な透明基板と、前記半導体層と透明基板とを接合する低融点ガラス層と、を含み、前記低融点ガラス層は熱膨張係数が2〜9×10 -6 /Kであり、前記透明基板はGaPからなる、ことを特徴としている。
In addition to ( 10 ) the configuration of the invention described in (1) to ( 9 ) above, the present invention provides a first ohmic electrode formed on a surface having a first polarity of the semiconductor layer, A metal reflective layer covering a surface having the first polarity and the first ohmic electrode formed on the surface; and a second ohmic electrode formed on the surface having the second polarity of the semiconductor layer. It is a feature.
In addition, the present invention provides (11) a semiconductor light emitting device, wherein a semiconductor layer including a light emitting part, a transparent substrate transparent to the light emission wavelength of the light emitting part, and a low bond between the semiconductor layer and the transparent substrate are bonded. A melting point glass layer, wherein the low melting point glass layer has a thermal expansion coefficient of 2 to 9 × 10 −6 / K, and the transparent substrate is made of GaP.

本発明は、(12)半導体発光素子の製造法であって、発光波長に対して不透明な半導体基板上に発光部を含む半導体層を成長する工程と、前記発光部の発光波長に対して透明で、熱膨張係数が2〜9×10 -6 /Kのガラスからなる透明基板の表面に形成した、熱膨張係数が2〜9×10 -6 /Kの低融点ガラス層と前記半導体層の表面に形成した、熱膨張係数が2〜9×10-6/Kの低融点ガラス層とを接合する工程と、前記不透明な半導体基板を除去する工程と、前記不透明な半導体基板の除去工程後の半導体層にオーミック電極を形成する工程とを含む、ことを特徴としている。 The present invention relates to ( 12 ) a method for producing a semiconductor light emitting device, comprising a step of growing a semiconductor layer including a light emitting portion on a semiconductor substrate opaque to the light emitting wavelength, and transparent to the light emitting wavelength of the light emitting portion. in thermal expansion coefficient is formed on the surface of a transparent substrate made of glass 2~9 × 10 -6 / K, and the low-melting glass layer in the thermal expansion coefficient of 2~9 × 10 -6 / K, the semiconductor layer Bonding a low melting point glass layer having a thermal expansion coefficient of 2 to 9 × 10 −6 / K formed on the surface of the substrate, a step of removing the opaque semiconductor substrate, and a step of removing the opaque semiconductor substrate And a step of forming an ohmic electrode in a subsequent semiconductor layer.

また、本発明は、(13)上記した(12)に記載の発明の構成に加えて、前記透明基板の表面への低融点ガラス層の形成、および前記半導体層の表面への低融点ガラス層の形成は、真空蒸着法またはスパッタリング法による、ことを特徴としている。 In addition to the structure of the invention described in ( 13 ) above ( 12 ), the present invention provides a low melting point glass layer on the surface of the transparent substrate and a low melting point glass layer on the surface of the semiconductor layer. The formation of is characterized by vacuum deposition or sputtering.

また、本発明は、(14)上記した(12)または(13)に記載の発明の構成に加えて、前記半導体層はMOCVD法を用いて成長する、ことを特徴としている。 In addition to the structure of the invention described in ( 14 ) ( 12 ) or ( 13 ), the present invention is characterized in that the semiconductor layer is grown using an MOCVD method.

さらに、本発明は、(15)上記した(12)乃至(14)に記載の発明の構成に加えて、前記半導体基板の除去工程に選択エッチング処理を含む、ことを特徴としている。 Furthermore, the present invention is characterized in that ( 15 ) in addition to the configuration of the invention described in ( 12 ) to ( 14 ) above, a selective etching process is included in the removal step of the semiconductor substrate.

また、本発明は、(16上記した(1)乃至(11)に記載の半導体発光素子を用いた発光ダイオードである。 Moreover, this invention is ( 16 ) The light emitting diode using the semiconductor light-emitting device as described in said (1) thru | or (11) .

この発明の半導体発光素子、その製造方法および発光ダイオードでは、半導体層と透明基板との接合を低融点ガラスを介在させて行うようにしたので、700℃以下の低温、低圧力の接合条件においても強力に接着させることができ、半導体層へのストレスや熱膨張係数の差による反りを大幅に低減することができる。また、冷却中に割れたり、クラックが入るようなこともない。   In the semiconductor light-emitting device, the manufacturing method thereof, and the light-emitting diode of the present invention, the semiconductor layer and the transparent substrate are bonded with a low-melting glass interposed therebetween, so that even under low-temperature and low-pressure bonding conditions of 700 ° C. or lower. It can be strongly bonded, and warpage due to stress on the semiconductor layer or difference in thermal expansion coefficient can be greatly reduced. In addition, there is no breakage or cracking during cooling.

また、耐熱性に優れた接着層を形成できるので、接着後のオーミック電極形成で400℃以上の熱処理を施しても、接着層が変質したり不透明となるようなことも防止することができる。   In addition, since an adhesive layer having excellent heat resistance can be formed, it is possible to prevent the adhesive layer from being denatured or becoming opaque even when heat treatment at 400 ° C. or higher is performed in forming an ohmic electrode after bonding.

したがって、割れ、剥がれがほとんど発生せず、高輝度、高品質の発光素子を安定して生産することができる。   Therefore, almost no cracking or peeling occurs, and a high-luminance and high-quality light-emitting element can be stably produced.

以下に、この発明の実施の形態を図面に基づいて詳細に説明する。   Embodiments of the present invention will be described below in detail with reference to the drawings.

図1はこの発明の半導体発光素子の製造工程を概略的に示す図で、(a)はその第1段階の積層構造を、(b)は第2段階の積層構造を示している。なお、(b)は、(a)に対して上下反転させて図示している。   1A and 1B are diagrams schematically showing a manufacturing process of a semiconductor light emitting device according to the present invention, in which FIG. 1A shows a first-stage stacked structure and FIG. 1B shows a second-stage stacked structure. Note that (b) is shown upside down with respect to (a).

この発明の半導体発光素子10は、図1に示すような製造工程を経て形成される。すなわち、図1(a)に示す第1段階では、先ず発光波長に対して不透明な半導体基板1上に、発光部2aを含む半導体層2を成長させ、その半導体層2の表面に低融点ガラス層3aを形成する。また、発光部2aの発光波長に対して透明な透明基板4の表面に低融点ガラス層3bを形成する。そして、図1(b)に示す第2段階では、半導体層2の表面に形成した低融点ガラス層3aと透明基板4の表面に形成した低融点ガラス層3bとを接合させて一体化するとともに、半導体層2から半導体基板1を除去する。このようにして、発光部2aを含む半導体層2と、発光部2aの発光波長に対して透明な透明基板4と、半導体層2と透明基板4とを接合する低融点ガラス層3(3a,3b)とを含む、この発明に係る積層体10が得られる。   The semiconductor light emitting device 10 of the present invention is formed through a manufacturing process as shown in FIG. That is, in the first stage shown in FIG. 1A, first, a semiconductor layer 2 including a light emitting portion 2a is grown on a semiconductor substrate 1 that is opaque to the emission wavelength, and a low melting point glass is formed on the surface of the semiconductor layer 2. Layer 3a is formed. Moreover, the low melting glass layer 3b is formed on the surface of the transparent substrate 4 that is transparent to the emission wavelength of the light emitting portion 2a. In the second stage shown in FIG. 1B, the low-melting glass layer 3a formed on the surface of the semiconductor layer 2 and the low-melting glass layer 3b formed on the surface of the transparent substrate 4 are joined and integrated. The semiconductor substrate 1 is removed from the semiconductor layer 2. In this way, the semiconductor layer 2 including the light emitting part 2a, the transparent substrate 4 transparent to the light emission wavelength of the light emitting part 2a, and the low melting point glass layer 3 (3a, 3a, 3) joining the semiconductor layer 2 and the transparent substrate 4 3b) is obtained, according to the present invention.

上記の低融点ガラス層3を形成する低融点ガラスは、酸化鉛、酸化ホウ素、酸化亜鉛、酸化珪素などが含まれるガラスであるが、環境負荷の点から鉛を含まない材質が望ましい。熱膨張係数、軟化点から、酸化亜鉛、酸化ホウ素、酸化珪素を主成分とする低融点ガラスが適する。低融点ガラスの形成方法は、印刷、蒸着、スパッタ法等があるが、膜厚が薄く制御しやすい、蒸着、スパッタ法が望ましい。特にスパッタ法は、表面状態が良好で最適である。低融点ガラスは、熱膨張係数が半導体層2および半導体基板1と近い、2〜9×10-6/Kの範囲が望ましい。熱膨張係数の差が大きいと半導体へのストレスや割れの原因となる。低融点ガラスは、軟化点付近の温度の熱処理で接着層として機能する。半導体層2の輝度低下の可能性があるため、この接着時の熱処理温度は、700℃以下が望ましく、後工程の耐熱性を考慮すると500℃以上が望ましい。 The low-melting-point glass forming the low-melting-point glass layer 3 is glass containing lead oxide, boron oxide, zinc oxide, silicon oxide, etc., but a material containing no lead is desirable from the viewpoint of environmental load. From the viewpoint of thermal expansion coefficient and softening point, low melting point glass mainly composed of zinc oxide, boron oxide and silicon oxide is suitable. The low-melting glass can be formed by printing, vapor deposition, sputtering, etc., but vapor deposition and sputtering are preferable because the film thickness is thin and easy to control. In particular, the sputtering method is optimal because of its good surface condition. The low-melting glass preferably has a thermal expansion coefficient in the range of 2 to 9 × 10 −6 / K, which is close to that of the semiconductor layer 2 and the semiconductor substrate 1. If the difference in thermal expansion coefficient is large, it will cause stress and cracking on the semiconductor. The low melting point glass functions as an adhesive layer by heat treatment at a temperature near the softening point. Since there is a possibility that the luminance of the semiconductor layer 2 may be lowered, the heat treatment temperature at the time of adhesion is preferably 700 ° C. or lower, and is preferably 500 ° C. or higher in consideration of heat resistance in the subsequent process.

透明基板4の熱膨張係数は半導体層2および半導体基板1と近い、2〜9×10-6/Kの範囲が望ましい。熱膨張係数の差が大きいと半導体層2へのストレスや割れの原因となる。 The thermal expansion coefficient of the transparent substrate 4 is preferably in the range of 2-9 × 10 −6 / K, which is close to that of the semiconductor layer 2 and the semiconductor substrate 1. If the difference in thermal expansion coefficient is large, it will cause stress and cracking on the semiconductor layer 2.

透明基板4は、石英、ガラス、サファイア、GaP、SiC、AlGaAs、GaAsP、ZnSe等の発光波長に対し透明な材料や、ITO(酸化インジウム錫)等からなる透明導電膜の材料を選定すれば良いが、こららの材料のうち、安価で加工のしやすいガラス、GaP基板が望ましい。   For the transparent substrate 4, a material that is transparent with respect to the emission wavelength, such as quartz, glass, sapphire, GaP, SiC, AlGaAs, GaAsP, and ZnSe, or a transparent conductive film material that is made of ITO (indium tin oxide) or the like may be selected. However, among these materials, glass and a GaP substrate that are inexpensive and easy to process are desirable.

透明基板4の厚さは、チップへの加工しやすさから300μm以下が望ましく、透明基板4の半導体層2への接着時の割れの発生防止やダイボンドなどのチップ組立て工程のハンドリングの点から70μm以上の厚さが望ましい。   The thickness of the transparent substrate 4 is desirably 300 μm or less from the viewpoint of ease of processing into a chip, and is 70 μm from the viewpoint of preventing the occurrence of cracking when the transparent substrate 4 is bonded to the semiconductor layer 2 and handling the chip assembly process such as die bonding. The above thickness is desirable.

半導体基板1は、GaAs、InP、GaP、Si等が使用できる。発光部2aは、GaP、AlGaInP混晶、GaAlAs混晶、GaAsP混晶、GaInN混晶等の公知の発光素子で利用されている半導体を用いることができる。   As the semiconductor substrate 1, GaAs, InP, GaP, Si, or the like can be used. For the light emitting part 2a, a semiconductor used in a known light emitting element such as GaP, AlGaInP mixed crystal, GaAlAs mixed crystal, GaAsP mixed crystal, and GaInN mixed crystal can be used.

発光部2aは、シングルヘテロ構造、ダブルヘテロ構造、量子井戸構造など通常使用されている発光部の構造を利用できる。また、量子井戸構造を備えた、シングルへテロ構造またはダブルへテロ構造としてもよい。特に、厚膜化が困難で、格子整合の点から通常の構造では不透明なGaAs基板を用いるAlGaInPからなる発光部2aに対して、本発明は、半導体発光素子の高輝度化の効果が大きい。   As the light emitting portion 2a, a structure of a light emitting portion that is usually used, such as a single hetero structure, a double hetero structure, or a quantum well structure, can be used. Moreover, it is good also as a single hetero structure or a double hetero structure provided with the quantum well structure. In particular, the present invention has a great effect of increasing the luminance of the semiconductor light emitting device for the light emitting portion 2a made of AlGaInP using a GaAs substrate which is difficult to increase in thickness and has a normal structure in terms of lattice matching.

高輝度の発光部2aを得るには半導体基板1に対して、格子定数の整合した発光部2aの材質を選定し、半導体層2を成長させることが望ましい。成長方法は、液相成長法、MBE法、MOCVD法等、公知の技術を使用できるが、量産性、品質面からMOCVD法が最も好ましい。半導体層2には、発光部2aに加えて、従来技術で使用されている半導体基板1との緩衝層、ブラッグ反射層、選択エッチングの為のエッチングストップ層、オーミック電極の接触抵抗を下げるコンタクト層、電流拡散層、電流の流れる領域を制御する電流阻止層、電流狭窄層などを組み合わせることができる。これらの層は、製造方法、コスト、品質に応じて、必要な層を適切に組み合わせればよい。   In order to obtain the light emitting portion 2a having high luminance, it is desirable to select the material of the light emitting portion 2a having a lattice constant matched to the semiconductor substrate 1 and grow the semiconductor layer 2. As a growth method, a known technique such as a liquid phase growth method, MBE method, MOCVD method or the like can be used, but the MOCVD method is most preferable in terms of mass productivity and quality. In addition to the light emitting portion 2a, the semiconductor layer 2 includes a buffer layer with the semiconductor substrate 1 used in the prior art, a Bragg reflection layer, an etching stop layer for selective etching, and a contact layer that lowers the contact resistance of the ohmic electrode. In addition, a current spreading layer, a current blocking layer for controlling a current flowing region, a current constricting layer, and the like can be combined. These layers may be appropriately combined with necessary layers according to the manufacturing method, cost, and quality.

透明基板4側の低融点ガラス層3bと半導体層2側の低融点ガラス層3aとを重ね合わせて熱処理を行う方法は、オーブン、電気炉、赤外線ランプ、ホットプレートなどの公知の熱処理手段を利用できる。熱処理時に接合面がずれない程度の1g/cm2以上の圧力を加えるとより接合の均一性、接着強度が向上するが、発光部2aへのストレスの低減を考慮すると100g/cm2以下が望ましい。熱処理は、ストレスを低減し、発光部2aの劣化を抑制するため700℃未満で、冷却速度を制御して行うのが望ましい。 The method of performing heat treatment by superimposing the low melting point glass layer 3b on the transparent substrate 4 side and the low melting point glass layer 3a on the semiconductor layer 2 side uses known heat treatment means such as an oven, an electric furnace, an infrared lamp, a hot plate, etc. it can. When a pressure of 1 g / cm 2 or more is applied so that the bonding surface does not shift during heat treatment, the bonding uniformity and adhesive strength are further improved. However, in consideration of the reduction of stress on the light emitting portion 2a, 100 g / cm 2 or less is desirable. . The heat treatment is desirably performed at a temperature lower than 700 ° C. and controlling the cooling rate in order to reduce stress and suppress deterioration of the light emitting portion 2a.

半導体基板1は、機械加工、研磨、化学的エッチング等の方法により除去できる。特に化学的エッチングの中で、材質によるエッチング速度の差を利用した選択エッチングが、量産性、再現性、均一性の面で最適な方法である。   The semiconductor substrate 1 can be removed by methods such as machining, polishing, and chemical etching. In particular, in chemical etching, selective etching using the difference in etching rate depending on the material is the optimum method in terms of mass productivity, reproducibility, and uniformity.

上記の積層体10から発光素子を構成するには、光取り出し面を透明基板4とし、半導体基板1を除去して露出させた第1の極性の半導体層2の表面に第1の電極を形成し、また半導体層2の一部を除去して露出させた第2の極性の半導体層2の表面に第2の電極を形成し、さらに第1の電極とその下地の半導体層2の表面とを覆う金属反射層を設けるようにする。この構造は所謂、フリップチップ型の素子構造であり、反射層で光の取り出し効率を向上させることができる。なお、この素子構造についての詳細は後述する。   In order to construct a light emitting element from the above-described laminate 10, the light extraction surface is the transparent substrate 4, and the first electrode is formed on the surface of the semiconductor layer 2 having the first polarity exposed by removing the semiconductor substrate 1. In addition, a second electrode is formed on the surface of the second polarity semiconductor layer 2 exposed by removing a part of the semiconductor layer 2, and further, the first electrode and the surface of the underlying semiconductor layer 2 A metal reflective layer is provided to cover the surface. This structure is a so-called flip-chip type element structure, and the light extraction efficiency can be improved by the reflective layer. Details of the element structure will be described later.

その他の素子製造方法は、公知の発光素子の製造技術を利用でき、オーミック電極形成、素子分離、検査・評価工程を経て発光素子を製造する。さらに、発光素子をパッケージに組込んで発光ダイオード(ランプ)を製造できる。   Other element manufacturing methods can use known light-emitting element manufacturing techniques, and manufacture light-emitting elements through ohmic electrode formation, element separation, and inspection / evaluation processes. Furthermore, a light emitting diode (lamp) can be manufactured by incorporating a light emitting element into a package.

次に実施例1として作製した、この発明の半導体発光素子の構成例を図2〜図6を用いて順に説明する。   Next, structural examples of the semiconductor light emitting device of the present invention manufactured as Example 1 will be described in order with reference to FIGS.

図2は半導体発光素子に用いられる半導体エピタキシャルウェーハ(積層体)の層構造を示す図、図3および図4は図2の半導体エピタキシャルウェーハから作製したこの発明の半導体発光素子の構成例を示す図で、図3はその平面図、図4は図3のI−I線断面を示す図である。この実施例1で作製した半導体発光素子100は赤色発光を行う。   FIG. 2 is a diagram showing a layer structure of a semiconductor epitaxial wafer (laminated body) used in the semiconductor light emitting device, and FIGS. 3 and 4 are diagrams showing a configuration example of the semiconductor light emitting device of the present invention manufactured from the semiconductor epitaxial wafer of FIG. 3 is a plan view thereof, and FIG. 4 is a cross-sectional view taken along the line II of FIG. The semiconductor light emitting device 100 manufactured in Example 1 emits red light.

半導体発光素子100の製造に用いられる半導体エピタキシャルウェーハ10Aは、図2に示すように、Siをドープしたn形の(001)面から15°傾けた面を有するGaAs単結晶からなる半導体基板11上に順次、Siをドープしたn形のGaAsからなる緩衝層21、Siをドープしたn形の(Al0.5Ga0.50.5In0.5Pからなるエッチングストップ層22、発光部20a、およびZnをドープしたp型GaP層26からなる半導体層20を積層して構成されている。 As shown in FIG. 2, a semiconductor epitaxial wafer 10A used for manufacturing a semiconductor light emitting device 100 is formed on a semiconductor substrate 11 made of a GaAs single crystal having a surface inclined by 15 ° from an n-type (001) surface doped with Si. Next, a buffer layer 21 made of n-type GaAs doped with Si, an etching stop layer 22 made of n-type (Al 0.5 Ga 0.5 ) 0.5 In 0.5 P doped with Si, a light emitting portion 20a, and Zn doped The semiconductor layer 20 composed of the p-type GaP layer 26 is stacked.

上記の発光部20aは、ダブルヘテロ構造であり、Siをドープしたn形の(Al0.7Ga0.30.5In0.5Pからなる下部クラッド層23、アンドープの(Al0.2Ga0.80.5In0.5Pからなる発光層24、およびZnをドープしたp形の(Al0.7Ga0.30.5In0.5Pからなる上部クラッド層25から構成されている。 The light emitting portion 20a has a double hetero structure, and is composed of a Si-doped n-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P lower cladding layer 23, undoped (Al 0.2 Ga 0.8 ) 0.5 In 0.5 P And a top clad layer 25 made of Zn-doped p-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P.

上記の半導体エピタキシャルウェーハ10Aを形成する際には、先ず、上記の半導体層20の各層21〜26を、トリメチルアルミニウム((CH33Al)、トリメチルガリウム((CH33Ga)およびトリメチルインジウム((CH33In)をIII族構成元素の原料に用いた、減圧の有機金属化学気相堆積法(MOCVD法)により、半導体基板11上に積層した。Znのドーピング原料にはジエチル亜鉛((C252Zn)を使用した。Siのドーピング原料にはジシラン(Si26)を使用した。また、V族構成元素の原料としては、ホスフィン(PH3)またはアルシン(AsH3)を用いた。半導体層20を構成する各層21〜26の積層温度は730℃に統一した。 When the semiconductor epitaxial wafer 10A is formed, first, the layers 21 to 26 of the semiconductor layer 20 are made of trimethylaluminum ((CH 3 ) 3 Al), trimethyl gallium ((CH 3 ) 3 Ga) and trimethyl. The indium ((CH 3 ) 3 In) was laminated on the semiconductor substrate 11 by a low pressure metal organic chemical vapor deposition method (MOCVD method) using a group III constituent element material. Diethyl zinc ((C 2 H 5 ) 2 Zn) was used as a Zn doping raw material. Disilane (Si 2 H 6 ) was used as a Si doping material. Further, phosphine (PH 3 ) or arsine (AsH 3 ) was used as a raw material for the group V constituent elements. The lamination temperature of each of the layers 21 to 26 constituting the semiconductor layer 20 was unified to 730 ° C.

緩衝層21は、キャリア濃度を約5×1018cm-3とし、また層厚を約0.2μmとした。エッチングストップ層22は、キャリア濃度を約2×1018cm-3とし、層厚を約0.5μmとした。下部クラッド層23は、キャリア濃度を約8×1017cm-3、層厚を約1μmとした。発光層24は、アンドープで、層厚を0.5μmとした。上部クラッド層25は、キャリア濃度を約2×1017cm-3とし、層厚を1μmとした。GaP層26は、キャリア濃度を約5×1018cm-3とし、層厚を7μmとした。 The buffer layer 21 had a carrier concentration of about 5 × 10 18 cm −3 and a layer thickness of about 0.2 μm. The etching stop layer 22 has a carrier concentration of about 2 × 10 18 cm −3 and a layer thickness of about 0.5 μm. The lower cladding layer 23 had a carrier concentration of about 8 × 10 17 cm −3 and a layer thickness of about 1 μm. The light emitting layer 24 is undoped and has a thickness of 0.5 μm. The upper cladding layer 25 had a carrier concentration of about 2 × 10 17 cm −3 and a layer thickness of 1 μm. The GaP layer 26 had a carrier concentration of about 5 × 10 18 cm −3 and a layer thickness of 7 μm.

次に、半導体層20の表面に、ZnO、B23、SiO2からなる低融点ガラス(軟化点650℃、熱膨張係数4×10-6/K)をスパッタリング法で、0.3μm形成し、低融点ガラス層30aとした。 Next, 0.3 μm of low melting point glass (softening point 650 ° C., thermal expansion coefficient 4 × 10 −6 / K) made of ZnO, B 2 O 3 , SiO 2 is formed on the surface of the semiconductor layer 20 by sputtering. The low melting point glass layer 30a was obtained.

一方、透明基板40となる厚さ150μmのホウケイ酸ガラス(熱膨張係数7×10-6/K)の表面に、ZnO、B23、SiO2からなる低融点ガラス(軟化点650℃、熱膨張係数4×10-6/K)をスパッタリング法で、0.3μm形成し、低融点ガラス層30bとした。 On the other hand, a low-melting glass (softening point 650 ° C., made of ZnO, B 2 O 3 , SiO 2 on the surface of 150 μm thick borosilicate glass (thermal expansion coefficient 7 × 10 −6 / K) to be the transparent substrate 40. A thermal expansion coefficient of 4 × 10 −6 / K) was formed by sputtering to a thickness of 0.3 μm to form a low-melting glass layer 30b.

低融点ガラス層30a,30bの各表面が接触するように、半導体層20と透明基板40とを重ね合わせ、5g/cm2となる荷重をかけた状態で熱処理を行い、両者30a,30bを接着した。このときの接着温度条件は、650℃で30分とし、400℃までの冷却は、1℃/分の徐冷で行った。 The semiconductor layer 20 and the transparent substrate 40 are overlapped so that the surfaces of the low-melting glass layers 30a and 30b are in contact with each other, and heat treatment is performed in a state where a load of 5 g / cm 2 is applied, and both the 30a and 30b are bonded. did. The bonding temperature condition at this time was 650 ° C. for 30 minutes, and cooling to 400 ° C. was performed by slow cooling at 1 ° C./min.

次に、半導体基板11および緩衝層21をアンモニア系エッチャントにより選択的に除去した。   Next, the semiconductor substrate 11 and the buffer layer 21 were selectively removed with an ammonia-based etchant.

続いて、上記のようにして構成した半導体エピタキシャルウェーハ10Aに、電極等を形成して発光素子100を作製した(図3、図4)。すなわち、n形の極性を有するエッチングストップ層22の表面に、第1の電極として、Au・Ge合金からなるn形電極51を、厚さが0.3μmとなるように真空蒸着法により形成した。このn形電極51は、一般的なフォトリソグラフィー手段を利用してパターニングを施し、図3に示すような、幅を約20μmとする三角形の線状電極とした。   Subsequently, an electrode or the like was formed on the semiconductor epitaxial wafer 10A configured as described above to produce the light emitting device 100 (FIGS. 3 and 4). That is, an n-type electrode 51 made of an Au / Ge alloy was formed as a first electrode on the surface of the etching stop layer 22 having an n-type polarity by a vacuum deposition method so as to have a thickness of 0.3 μm. . The n-type electrode 51 was patterned using a general photolithography means to form a triangular linear electrode having a width of about 20 μm as shown in FIG.

n形電極51の表面および半導体層20(エッチングストップ層22)の表面に、スパッタ法でCrを0.05μm、次に金を約1μm積層させ、金属反射層52を形成した。その後、半導体層20を硫酸・過酸化水素系エッチャントでエッチングしてさらに除去し、p形の極性を有するGaP層26を露出させ、半径150μmの扇型領域とした。   On the surface of the n-type electrode 51 and the surface of the semiconductor layer 20 (etching stop layer 22), 0.05 μm of Cr and then about 1 μm of gold were laminated by sputtering to form a metal reflective layer 52. Thereafter, the semiconductor layer 20 was further removed by etching with a sulfuric acid / hydrogen peroxide-based etchant to expose the GaP layer 26 having p-type polarity to form a fan-shaped region having a radius of 150 μm.

上記のGaP層26上に、第2の電極を形成するために、半径130μm扇型の領域にパターンを形成し、先ず膜厚を0.5μmとする金・ベリリウム合金と、膜厚を1μmとする金とを、パターニングのレジスト表面に、一般的な真空蒸着法により被着させた。続けて、公知のリフトオフ法により、レジストを除去し、扇型のp型電極53を形成した。   In order to form the second electrode on the GaP layer 26, a pattern is formed in a fan-shaped region having a radius of 130 μm. First, a gold / beryllium alloy having a thickness of 0.5 μm, and a thickness of 1 μm The gold to be deposited was deposited on the patterning resist surface by a general vacuum deposition method. Subsequently, the resist was removed by a known lift-off method to form a fan-shaped p-type electrode 53.

次に、上記のn形電極51およびp型電極53の形成後、窒素気流中において480℃で15分間の合金化熱処理を施し、各電極51,53と半導体層20との低抵抗オーミック接触を形成した。   Next, after the formation of the n-type electrode 51 and the p-type electrode 53, a low resistance ohmic contact between each of the electrodes 51 and 53 and the semiconductor layer 20 is performed by performing an alloying heat treatment at 480 ° C. for 15 minutes in a nitrogen stream. Formed.

上記のようにして、n形電極51、p型電極53および金属反射層52を形成したエピタキシャルウェーハを通常のスクライブ法により素子の形状に裁断して個別に細分化し、半導体発光素子100とした。この半導体発光素子100は、図3に示すように、平面的に見て一辺を300μmとする正方形とし、厚さは約160μmとした。   As described above, the epitaxial wafer on which the n-type electrode 51, the p-type electrode 53, and the metal reflective layer 52 were formed was cut into the shape of the element by a normal scribing method, and individually divided into the semiconductor light emitting element 100. As shown in FIG. 3, the semiconductor light emitting device 100 has a square shape with a side of 300 μm as viewed in plan, and a thickness of about 160 μm.

さらに、この半導体発光素子100を用いて発光ダイオードを組み立てた。   Further, a light emitting diode was assembled using the semiconductor light emitting device 100.

図5はこの発明に係る発光ダイオードの平面図、図6は図5のII−II線断面を示す図である。1個の発光素子100を、基板63に形成された第1の電極端子64および第2の電極端子62に金のボールバンプ65を形成し、発光素子100のp形電極53と金属反射層52とをボールバンプ65に接触させ圧着し接続した。次に、透明なエポキシ樹脂61で封止し、発光ダイオード(LED)60を作製した。 FIG. 5 is a plan view of the light emitting diode according to the present invention, and FIG. 6 is a cross-sectional view taken along the line II-II of FIG. One light emitting element 100 is formed by forming gold ball bumps 65 on the first electrode terminal 64 and the second electrode terminal 62 formed on the substrate 63, and the p-type electrode 53 and the metal reflection layer 52 of the light emitting element 100. Were brought into contact with the ball bumps 65 and bonded by pressure bonding. Next, it was sealed with a transparent epoxy resin 61 to produce a light emitting diode (LED) 60.

上記のようにして作製したLED60の第1の電極端子64と第2の電極端子62に順方向に電流を流したところ、金属反射層52で反射され、透明基板40の表面および側面を介して、主波長を約620nmとする赤色の光が出射された。順方向に20ミリアンペア(mA)の電流を通流した際の順方向電圧(Vf:20mA当り)は、各電極51,53の良好なオーミック特性を反映し、約2.0ボルト(V)となった。このときの発光強度は、発光部20aの発光効率が高く、外部への取りだし効率も工夫されていることを反映し、160mcdの超高輝度であった。   When a forward current is passed through the first electrode terminal 64 and the second electrode terminal 62 of the LED 60 manufactured as described above, the current is reflected by the metal reflection layer 52 and passes through the surface and side surfaces of the transparent substrate 40. Then, red light having a dominant wavelength of about 620 nm was emitted. The forward voltage (Vf: per 20 mA) when a current of 20 milliamperes (mA) flows in the forward direction reflects the good ohmic characteristics of the electrodes 51 and 53, and is about 2.0 volts (V). became. The light emission intensity at this time was 160 mcd super high brightness reflecting that the light emission efficiency of the light emitting part 20a was high and the efficiency of taking out to the outside was devised.

なお、上記の実施例1ではn型の半導体基板11を用いてLED60を作製したが、p型の半導体基板を用いて作製したLEDでも本発明の効果が得られる。   In addition, in Example 1 described above, the LED 60 is manufactured using the n-type semiconductor substrate 11, but the effect of the present invention can be obtained even with an LED manufactured using the p-type semiconductor substrate.

また、本発明の発光部20aは、AlGaInPのダブルヘテロ構造を用いたが、発光波長、構造、材質、ドーパント等において公知の技術を利用した発光部でも本発明の効果が得られる。   In addition, although the AlGaInP double heterostructure is used for the light emitting section 20a of the present invention, the effects of the present invention can also be obtained with a light emitting section using a known technique in terms of emission wavelength, structure, material, dopant, and the like.

さらに上記の実施例1では、一般的なチップ型のLED60を示したが、形状の異なるいわゆる砲弾型やディスプレイ用のパッケージ、また、発光波長の異なる発光ダイオードでも同様の効果が得られる。   Further, in the first embodiment, a general chip-type LED 60 is shown, but the same effect can be obtained with a so-called bullet-type or display package having a different shape, or a light-emitting diode having a different emission wavelength.

上記の実施例1では、熱膨張係数が4×10-6/Kの低融点ガラスを用いて接着温度を650℃としたが、実施例2では、熱膨張係数が8×10-6/Kの低融点ガラスを用いて接着温度を500℃とした。その他の条件は実施例1と同じにして発光ダイオードを作製し、発光強度を測定した結果、150mcdで、実施例1と同様高輝度のものが得られた。 In Example 1 above, a low-melting glass having a thermal expansion coefficient of 4 × 10 −6 / K was used and the bonding temperature was 650 ° C., but in Example 2, the thermal expansion coefficient was 8 × 10 −6 / K. The adhesion temperature was set to 500 ° C. using a low melting point glass. The other conditions were the same as in Example 1, and a light-emitting diode was fabricated. The emission intensity was measured. As a result, a high brightness of 150 mcd was obtained as in Example 1.

(比較例) 上記の実施例1、2と同様なプロセスを用い、低融点ガラスの熱膨張係数、接着温度、透明基板の熱膨張係数を変化させて、各種の発光素子を作製した。その比較例1〜6と実施例1,2の評価結果を表1に示す。   (Comparative Example) Using the same process as in Examples 1 and 2 above, various light emitting devices were produced by changing the thermal expansion coefficient of the low melting point glass, the bonding temperature, and the thermal expansion coefficient of the transparent substrate. The evaluation results of Comparative Examples 1 to 6 and Examples 1 and 2 are shown in Table 1.

Figure 0004451683
Figure 0004451683

比較例1,2,4では、低融点ガラスの熱膨張係数が9×10-6/Kを超えており、また比較例3では、透明基板の熱膨張係数が2×10-6/Kを下回っており、半導体層の熱膨張係数、約5×10-6/Kとの差が大きくなるため、熱歪み等が発生し、プロセスの途中で割れや剥がれが発生して素子が作製できなかった。比較例5では、接着温度が700℃を超えており、その熱で半導体層の品質が劣化し、低輝度であった。 In Comparative Examples 1, 2, and 4, the low-melting glass has a thermal expansion coefficient exceeding 9 × 10 −6 / K, and in Comparative Example 3, the transparent substrate has a thermal expansion coefficient of 2 × 10 −6 / K. Since the difference between the thermal expansion coefficient of the semiconductor layer and about 5 × 10 −6 / K is large, thermal distortion occurs, and cracks and peeling occur during the process, and the device cannot be manufactured. It was. In Comparative Example 5, the bonding temperature exceeded 700 ° C., and the heat deteriorated the quality of the semiconductor layer, resulting in low luminance.

比較例6は、基板除去、ガラス貼り付けを行わない、実施例と同じエピタキシャルウェーハを用いて一般的な構造で作製した300μmピッチの半導体発光素子を図7、図8に示す。   Comparative Example 6 shows a 300 μm-pitch semiconductor light-emitting device manufactured with a general structure using the same epitaxial wafer as in Example, in which substrate removal and glass pasting are not performed, are shown in FIGS.

図7は比較例6で作製した半導体発光素子の平面図、図8は図7のIII−III線に沿った断面を示す図である。この半導体発光素子90は、GaAsからなる半導体基板91上に、半導体層92、第1のオーミック電極93を積層し、半導体基板91の裏面に第2のオーミック電極94を形成して構成されている。   7 is a plan view of the semiconductor light emitting device fabricated in Comparative Example 6, and FIG. 8 is a view showing a cross section taken along the line III-III of FIG. The semiconductor light emitting device 90 is configured by laminating a semiconductor layer 92 and a first ohmic electrode 93 on a semiconductor substrate 91 made of GaAs and forming a second ohmic electrode 94 on the back surface of the semiconductor substrate 91. .

比較例6では、上部の電極93を金ワイヤボンディングで接続する。この第1の電極93は、金・ベリリウム合金からなるp形オーミック電極を厚さが0.3μmとなるように形成し、さらに、金を1μmとなるように真空蒸着法により形成した。一般的なフォトリソグラフィー手段を利用してパターニングを施し、直径を130μmとする円形の第1の電極93を形成した。   In Comparative Example 6, the upper electrode 93 is connected by gold wire bonding. The first electrode 93 was formed by forming a p-type ohmic electrode made of a gold / beryllium alloy so as to have a thickness of 0.3 μm, and further using a vacuum vapor deposition method so that the thickness of gold became 1 μm. Patterning was performed using general photolithography means to form a circular first electrode 93 having a diameter of 130 μm.

その後、実施例と同様に作製したLEDの第1の電極端子と第2の電極端子に順方向に電流を通流したところ、半導体層92の表面および側面を介して、波長を約620nmとする赤色の光が出射された。順方向に20ミリアンペア(mA)の電流を通流した際の順方向電圧(Vf:20mA当り)は、約2.0ボルト(V)で、実施例1,2と同等であった。このときの発光強度は、60mcdであった。本発明の実施例1,2に対し半分以下の発光強度であった。これは、GaAs半導体基板91に発光が吸収されるため、外部への取りだし効率が低下したことによると考えられる。   Thereafter, when a forward current was passed through the first electrode terminal and the second electrode terminal of the LED manufactured in the same manner as in the example, the wavelength was set to about 620 nm through the surface and side surfaces of the semiconductor layer 92. Red light was emitted. The forward voltage (Vf: per 20 mA) when a current of 20 mA (mA) was passed in the forward direction was about 2.0 volts (V), which was the same as in Examples 1 and 2. The emission intensity at this time was 60 mcd. The emission intensity was less than half that of Examples 1 and 2 of the present invention. This is considered to be due to the fact that the emission efficiency is reduced because the GaAs semiconductor substrate 91 absorbs light emission.

以上述べたように、この発明では、半導体層と透明基板との接合を低融点ガラスを介在させて行うようにしたので、700℃以下の低温、低圧力の接合条件においても強力に接着させることができ、半導体層へのストレスや熱膨張係数の差による反りを大幅に低減することができる。また、冷却中に割れたり、クラックが入るようなこともない。   As described above, in the present invention, the semiconductor layer and the transparent substrate are bonded with the low-melting glass interposed therebetween, so that the semiconductor layer and the transparent substrate are strongly bonded even under a low temperature and low pressure bonding condition of 700 ° C. or lower. Therefore, warpage due to stress on the semiconductor layer and a difference in thermal expansion coefficient can be significantly reduced. In addition, there is no breakage or cracking during cooling.

また、耐熱性に優れた接着層を形成できるので、接着後のオーミック電極形成で400℃以上の熱処理を施しても、接着層が変質したり不透明となるようなことも防止することができる。
したがって、割れ、剥がれがほとんど発生せず、高輝度、高品質の発光素子を安定して生産することができる。
In addition, since an adhesive layer having excellent heat resistance can be formed, it is possible to prevent the adhesive layer from being denatured or becoming opaque even when heat treatment at 400 ° C. or higher is performed in forming an ohmic electrode after bonding.
Therefore, almost no cracking or peeling occurs, and a high-luminance and high-quality light-emitting element can be stably produced.

また、半導体層の表面の一部にオーミック電極と金属反射層を設けるようにしたので、発光部の光を効率よく外部へ取り出すことができ、超高輝度化が達成された。   In addition, since the ohmic electrode and the metal reflection layer are provided on a part of the surface of the semiconductor layer, the light from the light emitting part can be efficiently taken out to the outside, and ultra-high luminance is achieved.

また、発光ダイオードをフリップチップ構造としたため、発光ダイオードの組み立てが容易で、ワイヤの断線がなくなり信頼性が向上する。   In addition, since the light emitting diode has a flip chip structure, the light emitting diode can be easily assembled, and the wire is not broken, thereby improving the reliability.

この発明の半導体発光素子の製造工程を概略的に示す図で、(a)はその第1段階の積層構造を、(b)は第2段階の積層構造を示す。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows schematically the manufacturing process of the semiconductor light-emitting device of this invention, (a) shows the laminated structure of the 1st step, (b) shows the laminated structure of the 2nd step. 半導体発光素子に用いられる半導体エピタキシャルウェーハ(積層体)の層構造を示す図である。It is a figure which shows the layer structure of the semiconductor epitaxial wafer (laminated body) used for a semiconductor light-emitting device. 図2の半導体エピタキシャルウェーハから製造したこの発明の半導体発光素子の構成例を示す平面図である。、図4は図3のI−I線断面を示す図である。It is a top view which shows the structural example of the semiconductor light-emitting device of this invention manufactured from the semiconductor epitaxial wafer of FIG. 4 is a cross-sectional view taken along the line II of FIG. 図3のI−I線断面を示す図である。It is a figure which shows the II sectional view of FIG. この発明に係る発光ダイオードの平面図である。It is a top view of the light emitting diode which concerns on this invention. 図5のII−II線断面を示す図である。It is a figure which shows the II-II line cross section of FIG. 比較例6の半導体発光素子の平面図である。14 is a plan view of a semiconductor light emitting element of Comparative Example 6. FIG. 図7のIII−III線断面を示す図である。It is a figure which shows the III-III line cross section of FIG.

符号の説明Explanation of symbols

1 半導体基板
2 半導体層
2a 低融点ガラス層
2a 発光部
3 低融点ガラス層
3a 低融点ガラス層
3b 低融点ガラス層
4 透明基板
10 積層体
10 半導体発光素子
10A 半導体エピタキシャルウェーハ
11 半導体基板
20 半導体層
20a 発光部
21 緩衝層
22 エッチングストップ層
23 下部クラッド層
24 発光層
25 上部クラッド層
26 GaP層
30a 低融点ガラス層
30b 低融点ガラス層
40 透明基板
51 n形電極
52 金属反射層
53 p型電極
60 発光ダイオード(LED)
61 エポキシ樹脂
62 第1の電極端子
63 基板
64 第2の電極端子
65 ボールバンプ
90 半導体発光素子
91 GaAs基板
92 半導体層
93 第1の電極
94 第2の電極
100 半導体発光素子
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Semiconductor layer 2a Low melting glass layer 2a Light emission part 3 Low melting glass layer 3a Low melting glass layer 3b Low melting glass layer 4 Transparent substrate 10 Laminated body 10 Semiconductor light emitting element 10A Semiconductor epitaxial wafer 11 Semiconductor substrate 20 Semiconductor layer 20a Light emitting portion 21 Buffer layer 22 Etching stop layer 23 Lower clad layer 24 Light emitting layer 25 Upper clad layer 26 GaP layer 30a Low melting glass layer 30b Low melting glass layer 40 Transparent substrate 51 n-type electrode 52 Metal reflective layer 53 p-type electrode 60 Light emission Diode (LED)
61 Epoxy Resin 62 First Electrode Terminal 63 Substrate 64 Second Electrode Terminal 65 Ball Bump 90 Semiconductor Light Emitting Element 91 GaAs Substrate 92 Semiconductor Layer 93 First Electrode 94 Second Electrode 100 Semiconductor Light Emitting Element

Claims (16)

発光部を含む半導体層と、
前記発光部の発光波長に対して透明な透明基板と、
前記半導体層と前記透明基板とを接合する低融点ガラス層と、を含み、
前記低融点ガラス層は熱膨張係数が2〜9×10 -6 /Kであり、
前記透明基板は熱膨張係数2〜9×10 -6 /Kのガラスからなる、
ことを特徴とする半導体発光素子。
A semiconductor layer including a light emitting portion;
A transparent substrate transparent to the emission wavelength of the light emitting part,
And a low melting glass layer to bonding the transparent substrate and the semiconductor layer, only including,
The low-melting glass layer has a thermal expansion coefficient of 2 to 9 × 10 −6 / K,
The transparent substrate is made of glass having a thermal expansion coefficient of 2 to 9 × 10 −6 / K.
A semiconductor light emitting element characterized by the above.
前記低融点ガラス層は軟化点が500℃以上700℃以下であり、前記半導体層と前記透明基板とを接合する際の接着温度が500℃以上700℃以下である、請求項1に記載の半導体発光素子。   2. The semiconductor according to claim 1, wherein the low melting point glass layer has a softening point of 500 ° C. or more and 700 ° C. or less, and an adhesion temperature when the semiconductor layer and the transparent substrate are joined is 500 ° C. or more and 700 ° C. or less. Light emitting element. 前記低融点ガラス層は鉛を含まない、請求項1または2に記載の半導体発光素子。   The semiconductor light emitting element according to claim 1, wherein the low-melting glass layer does not contain lead. 前記低融点ガラス層はSiO2、ZnO、B23を主成分とする、請求項1乃至3の何れか1項に記載の半導体発光素子。 4. The semiconductor light-emitting element according to claim 1, wherein the low-melting glass layer contains SiO 2 , ZnO, and B 2 O 3 as main components. 前記透明基板は厚さが70μm以上300μm以下である、請求項1乃至4の何れか1項に記載の半導体発光素子。   5. The semiconductor light emitting element according to claim 1, wherein the transparent substrate has a thickness of 70 μm or more and 300 μm or less. 前記発光部はAlGaInPからなる、請求項1乃至5の何れか1項に記載の半導体発光素子。   The semiconductor light emitting element according to claim 1, wherein the light emitting portion is made of AlGaInP. 前記発光部はGaInN混晶を含む、請求項1乃至5の何れか1項に記載の半導体発光素子。   The semiconductor light-emitting element according to claim 1, wherein the light-emitting portion includes a GaInN mixed crystal. 前記発光部は、量子井戸構造を備えた、シングルへテロ構造またはダブルへテロ構造である、請求項1乃至7の何れか1項に記載の半導体発光素子。   8. The semiconductor light emitting element according to claim 1, wherein the light emitting portion has a single heterostructure or a double heterostructure having a quantum well structure. 9. 前記半導体層はAsを含まない、請求項1乃至8の何れか1項に記載の半導体発光素子。   The semiconductor light emitting element according to claim 1, wherein the semiconductor layer does not contain As. 前記半導体層の第1の極性を有する表面に形成した第1のオーミック電極と、
前記第1の極性を有する表面およびその表面に形成した第1のオーミック電極を覆う金属反射層と、
前記半導体層の第2の極性を有する表面に形成した第2のオーミック電極と、
を有する請求項1乃至9の何れか1項に記載の半導体発光素子。
A first ohmic electrode formed on a surface having a first polarity of the semiconductor layer;
A metal reflective layer covering the surface having the first polarity and the first ohmic electrode formed on the surface;
A second ohmic electrode formed on the surface of the semiconductor layer having the second polarity;
The semiconductor light emitting device according to claim 1, comprising:
発光部を含む半導体層と、
前記発光部の発光波長に対して透明な透明基板と、
前記半導体層と透明基板とを接合する低融点ガラス層と、を含み、
前記低融点ガラス層は熱膨張係数が2〜9×10-6/Kであり、
前記透明基板はGaPからなる、
ことを特徴とする半導体発光素子。
A semiconductor layer including a light emitting portion;
A transparent substrate transparent to the emission wavelength of the light emitting part,
A low melting point glass layer that joins the semiconductor layer and the transparent substrate,
The low-melting-point glass layer is the thermal expansion coefficient of 2~9 × 10 -6 / K,
The transparent substrate is made of GaP.
A semiconductor light emitting element characterized by the above.
発光波長に対して不透明な半導体基板上に発光部を含む半導体層を成長する工程と、
前記発光部の発光波長に対して透明で、熱膨張係数が2〜9×10-6/Kのガラスからなる透明基板の表面に形成した、熱膨張係数が2〜9×10-6/Kの低融点ガラス層と、前記半導体層の表面に形成した、熱膨張係数が2〜9×10-6/Kの低融点ガラス層とを接合する工程と、
前記不透明な半導体基板を除去する工程と、
前記不透明な半導体基板の除去工程後の半導体層にオーミック電極を形成する工程とを含む、
ことを特徴とする半導体発光素子の製造方法。
Growing a semiconductor layer including a light emitting portion on a semiconductor substrate opaque to the emission wavelength;
Transparent to the emission wavelength of the light emitting portion, the thermal expansion coefficient is formed on the surface of a transparent substrate made of glass 2~9 × 10 -6 / K, the thermal expansion coefficient of 2~9 × 10 -6 / K Bonding the low melting point glass layer and a low melting point glass layer having a thermal expansion coefficient of 2 to 9 × 10 −6 / K formed on the surface of the semiconductor layer;
Removing the opaque semiconductor substrate;
Forming an ohmic electrode in the semiconductor layer after the removal step of the opaque semiconductor substrate,
A method for manufacturing a semiconductor light emitting device.
前記透明基板の表面への低融点ガラス層の形成、および前記半導体層の表面への低融点ガラス層の形成は、真空蒸着法またはスパッタリング法による、請求項12に記載の半導体発光素子の製造方法。   The method for producing a semiconductor light-emitting element according to claim 12, wherein the formation of the low melting point glass layer on the surface of the transparent substrate and the formation of the low melting point glass layer on the surface of the semiconductor layer are performed by vacuum deposition or sputtering. . 前記半導体層はMOCVD法を用いて成長する、請求項12または13に記載の半導体発光素子の製造方法。   The method of manufacturing a semiconductor light emitting element according to claim 12, wherein the semiconductor layer is grown using an MOCVD method. 前記半導体基板の除去工程に選択エッチング処理を含む、請求項12乃至14の何れか1項に記載の半導体発光素子の製造方法。   The method for manufacturing a semiconductor light emitting element according to claim 12, wherein the step of removing the semiconductor substrate includes a selective etching process. 請求項1乃至11の何れか1項に記載の半導体発光素子を用いた発光ダイオード。   A light-emitting diode using the semiconductor light-emitting element according to claim 1.
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