JP4628531B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a plurality of types of semiconductor devices on the same substrate when the semiconductor device is manufactured on a substrate. In particular, the present invention relates to a lithography technique for forming a circuit pattern of a semiconductor device.
[0002]
In this specification, a semiconductor device refers to a combination of semiconductor elements (thin film transistors (hereinafter referred to as TFTs), thin film diodes, capacitors using semiconductors, and the like). Specifically, a display device using semiconductor elements ( Examples thereof include liquid crystal display devices (hereinafter referred to as LCDs, EL displays, etc.), image sensors using CMOS, CCD, etc., ICs, LSIs, and the like.
[0003]
[Prior art]
In recent years, due to the development of low-temperature polysilicon technology, driving circuits (shift register circuit, buffer circuit, sampling circuit) for driving pixels are simultaneously formed on the glass substrate together with the pixel portion of the LCD. It is still a dream story to obtain a structure in which various semiconductor devices such as an image sensor, a CPU, and a memory are integrated together with a display device. In this specification, the driver circuit formed over the glass substrate in combination with the pixel portion is not a single semiconductor device but a part of a display device.
[0004]
In this specification, the minimum line width of a semiconductor element or circuit pattern is referred to as a line width rule. In a circuit using a field effect transistor, the gate length is usually the line width rule in order to make the gate length the thinnest. However, if there is a pattern with a line width narrower than the gate length in the circuit, the length of the line width is the line width rule. It becomes a width rule. For example, a circuit having a TFT with a gate length of 1.5 μm and a source wiring with 1.3 μm has a line width rule of 1.3 μm.
[0005]
For LSIs such as CPUs and memories, it is desired to combine semiconductor elements having a line width rule of 3 μm or less, preferably submicron semiconductor elements (hereinafter collectively referred to as fine elements) of 1 μm or less.
[0006]
Currently, a line (hereinafter referred to as an LCD line) used for manufacturing an LCD using TFTs uses a large-area glass substrate (referred to as a mother glass) to indicate a plurality of liquid crystal displays. The panel is multi-sided. Here, the line refers to the entire manufacturing apparatus or the arrangement of the manufacturing apparatus used when producing a certain object. The size of the mother glass is about 360 x 465 mm for the second generation line, about 550 x 650 mm for the third generation line, and about 800 x 950 mm for the fourth generation line. I'm following.
[0007]
However, a large-area mother glass is difficult to superimpose in a pattern forming process (hereinafter referred to as a patterning process) due to the bending or shrinkage of the glass, which is one of the limitations of the line width rule. In addition, in the LCD line, a lithography technique for producing a fine element has not been established. For this reason, it has been difficult to form fine elements with existing LCD lines.
[0008]
On the other hand, a line used for IC fabrication (hereinafter referred to as an IC line) can produce a circuit having a line width rule of 1 μm or less on a semiconductor substrate, and has established a lithography technique for producing fine elements. ing. However, the IC line is designed with a maximum dimension of a circular substrate having a diameter of 8 inches or more recently 12 inches. As described above, in order to increase the productivity of the LCD line, a rectangular and large-area mother glass is used to make an LCD panel with a diagonal of several tens of inches (the length of the diagonal line unless otherwise specified). It is multifaceted. For this reason, it has been out of the question to apply the production of an LCD panel of several tens of inches to an IC line that can only use a substrate of a maximum of 12 inches.
[0009]
By the way, exposure apparatuses used in lithography technology for LCD lines and IC lines include a batch exposure method and a sequential exposure method, and contact exposure, proximity exposure, and mirror projection (hereinafter referred to as MPA) are used as a batch exposure method. There is a stepper as a sequential exposure method. Contact exposure and proximity exposure are inferior in terms of resolution and pattern defects, and thus are not used in processes that require fine processing.
[0010]
MPA is very advantageous in terms of productivity because the exposure range is as wide as 400 mm square and the processing capability is high. MPA is used for processing of a process that allows a sufficient overlap margin, such as an ion implantation process, in an IC line, and is used because it can collectively expose a panel of dozens of inches in an LCD line. However, the MPA line and space (L & S) resolution (hereinafter referred to as the L & S resolution) is 3 μm at most, and considering the margin (margin) such as overlay accuracy, the line width rule is 3 μm or more. Become. For this reason, it is difficult to produce a microelement with MPA, and a submicron semiconductor element cannot be produced.
[0011]
The stepper is a typical exposure means used in the patterning process. The stepper projects the pattern on the reticle with an optical system, and exposes the pattern on the resist by operating and stopping (step-and-repeat) the substrate-side stage. The stepper used in the IC line is a method in which the reticle pattern is reduced to 1/5 or 1/4 with an optical system and exposure is possible. Submicron semiconductor elements can be patterned, but the exposure range is the maximum. It is about 25 mm square.
[0012]
The stepper used in the LCD line employs a method in which the reticle pattern is reduced by half with the optical system, and is exposed at an equal magnification or 1.25 times, which is the stepper used in the IC line. In comparison, the exposure range is as large as 130 mm square. However, the resolution is 3 μm, and a pattern of fine elements cannot be formed.
[0013]
In a stepper, an excimer laser of g-line (wavelength 436 nm), h-line (wavelength 405 nm), i-line (wavelength 365 nm), KrF (wavelength 248 nm) or ArF (wavelength 193 nm) of a mercury lamp is used as a light source.
[0014]
[Problems to be solved by the invention]
An object of the present invention is to obtain a structure in which various semiconductor devices such as an image sensor, a CPU, and a memory are integrated on a glass substrate together with a display device. In other words, the present invention integrates a plurality of types of semiconductor devices, particularly semiconductor devices having fine elements, as one of them on a substrate. A display device having a size larger than 1 inch can be manufactured without using a fine element because only a small panel of about 1 inch can be produced due to the problem of the exposure range described later when the fine element is used. The semiconductor device finally becomes a product state through a process of cutting out a semiconductor circuit formed on the substrate and connecting wirings, etc. In this specification, even in the state of the semiconductor circuit formed on the substrate It is called a semiconductor device. Finally, the display device is completed by cutting out the active matrix panel formed on the substrate and performing various processes (LCD has a structure in which a panel having a counter electrode is bonded. This will be described later. However, for the sake of convenience, the present specification also refers to a display device even in the state of an active matrix panel.
[0015]
A substrate in which a display device and a semiconductor device having fine elements are mixedly mounted is hereinafter referred to as a mixed substrate. The display device and the semiconductor device using a microelement may be integrated as a single panel (that is, the display device and the semiconductor device may be electrically connected) or independent from each other. Also good.
[0016]
In the current LCD line, a lithography technique for producing a fine element has not been established. In addition, the technology for manufacturing LCD lines for large-area LCD panels has been established, but it is difficult to manufacture fine elements using exposure means with a narrow exposure range because of the use of large-area mother glass. It is. Furthermore, even if the lithographic technique is established and the size of the mother glass is set to an appropriate size in order to produce a fine element, the investment involved in changing the line and establishing a new one is enormous.
[0017]
Therefore, the present inventor considered that a part of the existing IC line is applied when manufacturing a fine element because a lithography technique for manufacturing an element having a line width rule of 1 μm or less has been established in the IC line. did.
[0018]
A high-temperature polysilicon LCD is manufactured using a manufacturing apparatus currently used in an IC line, but a high-temperature polysilicon LCD only forms a drive circuit on the same substrate at most. It does not form a type of semiconductor device.
[0019]
Various problems arise when trying to fabricate a mixed substrate by applying a part of an IC line. One of the factors is that a mixed substrate, such as a 4-inch display device having a larger substrate area than an IC or LSI, is manufactured on the same substrate.
[0020]
The first problem is that, as with the IC line, when a circular substrate (currently a maximum 12-inch circular substrate) is used in the mixed line, even when a semiconductor device having a large exclusive area with respect to the substrate is manufactured, multiple faces are taken. This means that a lot of wasted areas are formed on the substrate and productivity is lowered. For example, when a 4-inch display device is manufactured with respect to a 12-inch substrate, only four pieces can be obtained, and the area of use of the substrate is about 50%.
[0021]
For the first problem, the present inventors produce a semiconductor device having a small device area (a chip area for a circuit such as an IC or LSI, or a panel area for a display device) in an unnecessary portion of the substrate. Was dealt with. As a result, unnecessary portions of the substrate can be used effectively.
[0022]
The second problem is that if a stepper similar to an IC line is used as an exposure means in the patterning process of the mixed substrate, the exposure range is about 25 mm square at the maximum, so that a semiconductor device such as an LSI (usually 1 (normally 1) However, a semiconductor device having an area of 25 mm square or more, for example, a display device of 1 inch or more cannot be exposed in one shot.
[0023]
Divided exposure by a stepper is used for LCD production using an amorphous silicon TFT in an LCD line stepper. The stepper used in this LCD line can widen the exposure range but has a low resolution and cannot pattern fine elements. Further, the division exposure has a low joining accuracy, and when used in a semiconductor device having a fine element, patterning failure such as disconnection or short circuit of wiring occurs.
[0024]
Thus, the exposure range of the exposure means and the line width rule are in a trade-off relationship. When the exposure range is given priority, the line width rule becomes 3 μm or more. When the line width rule is given priority, for example, when trying to form a fine element, particularly a submicron element, the device area is limited to 25 mm square or less.
[0025]
In the conventional lithography process, it is natural that there is only one type of exposure means used for the resist. Therefore, the device area and the minimum line width of the semiconductor device are determined according to the performance of the exposure means.
[0026]
[Means for Solving the Problems]
The basic concept of the present invention is to overcome limitations on the device area and line width rule of a semiconductor device by exposing a resist that forms a pattern on a certain workpiece using a plurality of exposure means. is there.
[0027]
The edge rinsing method for resist includes peripheral exposure, but it is clear that the concept is completely different from the present invention. Further, a conventional mix-and-match method using a plurality of exposure apparatuses by appropriately selecting different exposure apparatuses according to the processes has been performed for a plurality of exposure processes, but this does not lead to the concept of the present invention. Although the concept of the present invention is wide and has infinite possibilities, the configuration is shown below as a concrete example that can be considered at present.
[0028]
That is, the present invention provides a method for manufacturing a semiconductor device, the step of forming a workpiece on a substrate, the step of applying a resist on the workpiece, the step of exposing a first pattern to the resist, A step of exposing the resist to the second pattern, and the exposure unit in the step of exposing the first pattern is different from the exposure unit in the step of exposing the second pattern.
[0029]
According to another aspect of the invention, there is provided a step of forming a workpiece on a substrate, a step of applying a resist on the workpiece, a step of exposing a first pattern to a part of the resist, and the resist A step of exposing the second pattern to the other part, and the exposure means in the step of exposing the first pattern is different from the exposure means in the step of exposing the second pattern, To do.
[0030]
Another invention is a method for manufacturing a display device and a semiconductor device having a microelement on the same substrate, and a film commonly used in the display device and the semiconductor device having the microelement. An exposure means in a lithography process for forming a pattern of a display device on the film, and a lithography for forming a pattern of a semiconductor device having fine elements in the film The exposure means in the process is different.
[0031]
Different exposure means in this specification means that the exposure apparatus is different, the exposure range is different, or the resolution is different. For example, when using a stepper and MPA, a stepper with an exposure range of 25 mm square and a stepper with an exposure range of 100 mm square, a stepper with a resolution of 0.35 μm and a stepper with a resolution of 3 μm are different exposures. Means. Of course, even if the same exposure apparatus is used, different exposure means are obtained if the light source is changed.
[0032]
The exposure apparatus has a radiant energy source (light source, electron beam source, or X-ray source) that exposes the resist, and the resist exposes the pattern on the original image (reticle or mask) using the radiant energy source. Device. As the exposure apparatus that can be used, a current stepper, MPA, and the like are mainly used, but a resist can be used in common for exposure by electron beam and exposure by X-ray, and the present invention can be applied.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below. FIG. 7 is a cross-sectional process diagram of the patterning process of the workpiece 702 formed on the substrate 701.
[0034]
FIG. 7A illustrates a substrate 701 having a workpiece 702. There is no particular limitation on the substrate 701 as long as the substrate can be used for manufacturing a semiconductor device. For example, a quartz substrate, a glass substrate, a plastic substrate, a semiconductor substrate, or the like can be used. The workpiece 702 is one of the coating films that constitute the semiconductor device, and is a coating film that particularly requires fine processing, such as a semiconductor film, a conductive film, or an insulating film. The processing of the workpiece includes etching the workpiece using the resist pattern as a mask, doping impurities into the workpiece using the resist pattern as a mask, and the like.
[0035]
The steps that require microfabrication in the manufacturing process of a semiconductor device include etching for forming an active layer, etching of a conductive film to be a gate electrode, doping for forming an LDD region, and an interlayer for opening a contact hole. There are etching of an insulating film, etching of a conductive film to be a source wiring, and the like.
[0036]
First, a resist 703 is applied over a workpiece (FIG. 7B). The coating method is not particularly limited, and a spin coater or a roll coater may be used. As the resist, either a positive type or a negative type can be used, and can be selected according to the light source of the exposure means. However, the present invention has no problem when the light sources of the two types of exposure means are the same, but when the light sources are different, it is necessary to use a material that is sufficiently sensitive to both light sources.
[0037]
In addition, when a chemical amplification resist takes time from exposure to post-exposure baking (PEB), it reacts with bases and moisture in the atmosphere, and bases and moisture from the substrate, and the resulting resist pattern has T-top and Problems such as skirting at the bottom of the pattern, rounding at the top of the pattern, and biting at the bottom of the pattern occur. For this reason, an exposure process of a pattern having a strict line width rule is performed after the two types of exposure means. That is, when a display device with a line width rule of 3 μm and a semiconductor device with 1 μm are manufactured at the same time, the display device pattern is exposed first, and then the LSI pattern is exposed. It is also effective to cluster from the first exposure means to the second exposure means (a configuration in which the atmosphere is not released halfway) and to remove moisture and bases in the atmosphere with a filter.
[0038]
Next, the resist was pre-baked to evaporate the residual solvent in the resist, thereby improving the adhesion between the resist and the workpiece and further stabilizing the resist characteristics.
[0039]
Then, first patterns 705a to 705c are formed on the resist by the first exposure unit. FIG. 7 illustrates the case where a positive resist is used, and the exposed regions 704a to 704d are dissolved and removed by a later development process (FIG. 7C). The exposure range of the first exposure means can be widened to expose a pattern with a large line width rule. In the case where a positive resist is used, the exposed resist is removed, and therefore an unnecessary portion of the resist on which the semiconductor device is not formed on the substrate is also exposed by the first exposure means having a wide exposure range. As an exposure apparatus to be used, a stepper having a wide exposure range such as that used in MPA or LCD lines may be used.
[0040]
Further, second patterns 707a and 707b are formed on the first pattern 705a by the second exposure means. Reference numerals 706a to 706 denote areas exposed by the second exposure means (FIG. 7D). In FIG. 7, since a positive resist is used, a part of the regions 704a and 704b exposed by the first exposure unit overlaps a part of the regions 706a and 706c exposed by the second exposure unit. Yes. The exposure range of the second exposure means becomes small because a pattern with a small line width rule is exposed due to the above-mentioned trade-off problem, but it is only necessary to expose only a necessary portion, for example, a portion of a semiconductor device having fine elements. The exposure apparatus used for the second exposure means is preferably a stepper capable of exposing a pattern of fine elements.
[0041]
Then, PEB is performed if necessary and developed. By this development step, resist patterns 705b, 705c, 707a and 707b formed by the first and second exposure means are formed (FIG. 7E).
[0042]
Using the resist pattern thus formed, the workpiece is etched or the workpiece is doped.
[0043]
In the following examples, specific implementations of the present invention will be described in an actual semiconductor device manufacturing process.
[0044]
【Example】
[Example 1]
FIG. 1 is a top view of a mixed substrate. In this embodiment, a display device 102 is provided on a circular substrate 101, a quartz substrate having a diameter of 12 inches in this embodiment, and a drive circuit is provided in the periphery in this embodiment. This is a configuration in which four active matrix panels are formed and a semiconductor device 103 having a small element area in a remaining area of the substrate and having a small device area, in this embodiment, a logic circuit. Each line width rule is set to 3.5 μm for the display device 102 and 0.8 μm for the semiconductor device 103. However, in the display device 102, the line width rule of 3.5 μm is determined by the TFT gate length in the drive circuit section.
[0045]
In this embodiment, a logic circuit (a signal dividing circuit, a D / A converter circuit, a γ correction circuit, a differential amplifier circuit, or the like) is manufactured as the semiconductor device 103, but an N-channel TFT (NTFT) and a P-channel TFT ( Various other circuits can be designed by combining (PTFT). The semiconductor device 103 may be formed in electrical connection with the display device 102 or may be formed independently.
[0046]
Since the display device 102 which is rectangular and has a large exclusive area is formed on the circular substrate 101, a useless portion is generated on the substrate. By forming the semiconductor device 103 in the useless portion, the substrate is effectively used.
[0047]
As the semiconductor device, an IC, an LSI, a display device, an image sensor, and the like can be given. If the semiconductor device is integrated with the display device, an IC, an LSI, or an image sensor may be formed and electrically connected to the display device 102. If an independent semiconductor device is formed, a display device or an image sensor having a small panel size may be formed.
[0048]
FIGS. 2 to 4 are cross-sectional views of a manufacturing process of a mixed substrate. A CMOS in which NTFT and PTFT, which are basic elements constituting a logic circuit, are combined as a semiconductor device 103 having fine elements on the left side of the drawing. A CMOS constituting the circuit portion is shown in the center of the drawing, and a pixel TFT and a storage capacitor of the display device 102 are shown on the right side of the drawing.
[0049]
First, a quartz substrate 201 is prepared as a substrate, and an amorphous silicon film (amorphous silicon) is formed thereon. At this time, a silicon nitride oxide film, a silicon oxide film, or a silicon nitride film (hereinafter referred to as an insulating film containing silicon) is formed as a base film, and an amorphous silicon film is continuously formed without being released to the atmosphere. Also good. By doing so, impurities such as boron contained in the atmosphere can be prevented from being adsorbed on the lower surface of the amorphous silicon film.
[0050]
In this embodiment, an amorphous silicon film is used, but another semiconductor film may be used. For example, a microcrystalline silicon (microcrystal silicon) film or an amorphous silicon germanium film may be used. In consideration of the subsequent thermal oxidation process, the film thickness is finally set to 25 to 40 nm in a state where the TFT is completed. In this embodiment, a film thickness of 65 nm is preliminarily set in anticipation of a film thickness reduction of 25 nm in the thermal oxidation process.
[0051]
Next, the amorphous silicon film is crystallized. In this embodiment, the technique described in JP-A-9-31260 is used as the crystallization means. The technique described in the publication uses an element selected from nickel, cobalt, palladium, germanium, platinum, iron, and copper as a catalyst element for promoting crystallization.
[0052]
In this embodiment, nickel is selected as the catalyst element, a layer containing nickel is formed on the amorphous silicon film, and crystallization is performed by heat treatment at 550 ° C. for 4 hours. Then, a crystalline silicon (polysilicon) film 202 is obtained. (FIG. 2A) The crystal structure of this crystalline silicon film will be described later.
[0053]
Here, an impurity element (phosphorus or boron) for controlling the threshold voltage of the TFT may be added to the crystalline silicon film 202. Phosphorus or boron may be divided, or only one of them may be added.
[0054]
In this embodiment, as means for forming a layer containing nickel on the amorphous silicon film, means for applying the solution containing nickel described in the above publication to the amorphous silicon film is used. A method or a vapor deposition method can also be used.
[0055]
Next, a mask film 203 made of a 100 nm thick silicon oxide film is formed on the crystalline silicon film 202, and the mask film is etched using a resist pattern (not shown) thereon to form an opening. Since it is not necessary to form a fine pattern in the phosphorus-added region formed later, the entire surface of the substrate was collectively exposed using MPA as an exposure apparatus in this mask film patterning step.
[0056]
In this state, an element belonging to Group 15 (phosphorus in this embodiment) is added to form phosphorus doped regions (phosphorus added regions) 205a and 205b. The concentration of phosphorus to be added is 5 × 10 ¹⁸ ~ 1x10 ²⁰ atoms / cm ^Three (Preferably 1 × 10 ¹⁹ ~ 5x10 ¹⁹ atoms / cm ^Three ) Is preferred. However, the concentration of phosphorus to be added is not limited to this concentration range because it varies depending on the temperature and time of the subsequent gettering step and the area of the phosphorus-doped region.
[0057]
Next, the resist pattern is removed, and heat treatment at 450 to 650 ° C. (preferably 500 to 600 ° C.) is applied for 2 to 16 hours to getter the nickel remaining in the crystalline silicon film. In order to obtain the gettering action, a temperature of about ± 50 ° C. from the maximum temperature of the thermal history is necessary. However, since the heat treatment for crystallization is performed at 550 to 600 ° C., the heat treatment at 500 to 650 ° C. is sufficient. A gettering effect can be obtained.
[0058]
In this embodiment, nickel is moved in the direction of the arrow (see FIG. 2B) by applying a heat treatment at 600 ° C. for 12 hours, and gettering is performed on the phosphorous doped regions 205a and 205b. Thus, the concentration of nickel remaining in the crystalline silicon film indicated by 204 is 2 × 10. ¹⁷ atoms / cm ^Three The following (preferably 1 × 10 ¹⁶ atoms / cm ^Three Or less). However, this concentration is a measurement result by mass secondary ion analysis (SIMS), and the concentration below this has not been confirmed at present due to the measurement limit (FIG. 2B).
[0059]
After the nickel gettering step is completed, a resist 206 for patterning the crystalline silicon film 204 is applied. As the resist 206, a diazonaphthoquinone-novolak resin-based resist was used with a spin coater. Thereafter, the substrate is pre-baked at 120 ° C. or lower for 30 seconds to 300 seconds, and in this embodiment, at 110 ° C. for 90 seconds, the residual solvent in the resist is volatilized to improve the adhesion between the resist and the workpiece, Stabilized characteristics.
[0060]
Then, as a first exposure step, the resist is exposed to a pattern for forming an active layer of the crystalline silicon film of the display device using the first exposure means (FIG. 2C). The resists 207a to 207c exposed in this step are dissolved and removed in a later development step.
[0061]
As the first exposure means, a stepper having a resolution of 3 μm, an exposure range of 120 mm square, and i-line of a mercury lamp as a light source was used. Then, as shown by the first exposure range 104 in FIG. 1, the pattern of the display device was exposed in one shot. Then, the substrate is sequentially stepped to expose patterns of other display devices. In this first exposure step, not only the display device portion but also the entire surface of the substrate is exposed to expose the resist in a region where neither the display device nor the semiconductor device is formed. At this time, a reticle pattern that does not expose the semiconductor device 103 is used.
[0062]
In this embodiment, a stepper is used as the first exposure means and exposure is performed by a step operation. However, the entire surface of the substrate may be collectively exposed using MPA.
[0063]
Subsequently, a second exposure process is performed in which a resist is exposed to a pattern for forming an active layer of the crystalline silicon film of the semiconductor device by using a second exposure means (FIG. 2D). The resists 208a and 208b exposed in the second exposure process are dissolved and removed in a later development process.
[0064]
As the second exposure means, a stepper using a mercury lamp i-line as a light source was used as in the first exposure means. However, the exposure range is 22 mm square, and the resolution is 0.35 μm, and it is possible to expose a pattern of fine elements. Then, as shown in the second exposure range 105 in FIG. 1, one semiconductor device 103 is exposed in one shot. Then, the substrate is sequentially stepped to expose patterns of other semiconductor devices.
[0065]
Since the channel width of the later TFT is determined by the patterning process of the crystalline silicon film, a semiconductor device having a fine element needs a very fine pattern. Therefore, the semiconductor device having fine elements was exposed using the second exposure means with a narrow exposure range and high resolution. On the other hand, a pattern of a display device that does not require a very fine pattern but has a large device area was exposed using the first exposure means having a wide exposure range and low resolution.
[0066]
In this embodiment, one semiconductor device 103 is exposed by one shot of the second exposure means. However, when the device area of the semiconductor device is small, a plurality of semiconductor devices are obtained by one shot of the second exposure means. Can be exposed simultaneously.
[0067]
In this embodiment, since the light sources of the first exposure means and the second exposure means are the same, the same resist can be applied to both means without any problem.
[0068]
Then, the exposed substrate is carried into a heating furnace, and PEB is performed at 100 to 140 ° C. for 30 to 300 seconds, and in this embodiment, 120 ° C. and 180 seconds. This PEB can reduce the influence of standing waves. A standing wave is likely to be generated when exposed to radiation energy of a single wavelength, and is formed according to the film thickness and wavelength of the resist. The standing wave causes a distribution in the resist exposure, resulting in a jagged shape in the pattern. In the case of using a chemically amplified resist, PEB is very important and strict temperature control is required.
[0069]
Then, the resist exposed by the developer (TMAH) is dissolved by a developing device such as a spin developer. Then, the developer and the resist dissolved in the developer are removed by washing with pure water. Using the resist patterns 209a to 209c thus formed as a mask, the crystalline semiconductor film is etched to form active layers 210 to 212. Thus, the active layer 210 in the CMOS of the semiconductor device, the active layer 211 of the drive circuit, the active layer 212 for the pixel TFT and the storage capacitor are formed. In this patterning step, it is desirable to completely remove the phosphorus-doped regions 205a and 205b that have captured nickel. (Fig. 3 (A))
[0070]
After ashing resist patterns 209a-c, a silicon oxide film 213 having a thickness of 110 nm is formed by plasma CVD, and resist patterns 214a-f are formed thereon. Next, an addition process of an element belonging to Group 15 is performed in that state. In this embodiment, 2 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three (Preferably 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three ) Impurity region containing phosphorus (n) ^- Regions) 215a to 215e are formed (FIG. 3B).
[0071]
Here, n formed in the CMOS of the semiconductor device ^- The exposure means for the resist patterns 214a and 214b in the region is selected depending on the CMOS structure. As will be described in detail in Embodiment 3, when the semiconductor device has the structure shown in FIG. 6B, a channel formation region is defined by this process, and thus a very strict pattern needs to be formed. . Therefore, the second exposure means used when forming the active layer 210 should be used when forming the pattern of the semiconductor device. However, in the structure shown in FIG. 6A, the overlay accuracy is important, but a fine pattern is not required. Therefore, if an MPA capable of batch exposure of the entire surface or a stepper having a large exposure area is used. Good. As will be described later, this step is unnecessary in the structure shown in FIG.
[0072]
In this embodiment, since the CMOS structure of the semiconductor device is the structure shown in FIG. 6A, the resist pattern 214a-f is formed by collectively exposing the entire surface of the substrate with MPA.
[0073]
In this step, phosphorus is basically added to a region to be NTFT. However, the NTFT used in the driver circuit portion of the semiconductor device and the display device is provided with resist patterns 214a and 214c on regions that will be channel formation regions and source regions later, and n only in regions that become drain regions. ^- Regions 215a and 215b are formed. Further, in the pixel TFT, subsequent channel formation regions 218a and b are defined.
[0074]
Next, the resist patterns 214a to 214f and the silicon oxide film 213 are removed, an insulating film containing silicon is formed by plasma CVD or sputtering, and a gate insulating film 219 is formed by patterning. This gate insulating film 219 is an insulating film that functions as a gate insulating film of the pixel TFT. In this embodiment, a silicon oxide film having a thickness of 60 nm is used. However, since the film thickness increases in the subsequent thermal oxidation step, the final thickness is set to 50 to 200 nm (preferably 80 to 120 nm) in consideration thereof. At this time, the gate insulating film 219 is formed in the pixel TFT portion, and is removed in the CMOS circuit of the semiconductor device, the CMOS circuit of the driver circuit portion, and the region serving as the storage capacitor (FIG. 3C).
[0075]
Note that in this embodiment, only the CMOS circuit is described, but the gate insulating film 219 is actually removed in a region to be a part of a semiconductor device or a drive circuit (particularly a circuit that requires high-speed operation). . It is desirable to leave the gate insulating film 219 only in the case of a circuit in which a high voltage is applied to the gate insulating film, such as a buffer circuit or a sampling circuit (also referred to as a sample hold circuit).
[0076]
In the step of patterning the gate insulating film 219, it was not necessary to form a particularly fine pattern, and exposure was performed by collective exposure using MPA.
[0077]
If the state of FIG. 3 (C) is obtained in this way, then, a heat treatment step for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) at a temperature of 800 to 1150 ° C. (preferably 900 to 1100 ° C.) is performed. Performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment step is performed at 950 ° C. for 30 minutes in an oxygen atmosphere.
[0078]
Note that the oxidizing atmosphere may be either a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer. Alternatively, an atmosphere in which a halogen element is included in an oxygen atmosphere may be used. This thermal oxidation process in an atmosphere containing a halogen element is effective because it can be expected to remove nickel used for crystallization.
[0079]
By performing the thermal oxidation process in this manner, 5 to 50 nm (preferably 10 to 30 nm) of silicon oxide is formed on the surface of the active layer of the semiconductor device and the drive circuit unit and the surface of the semiconductor layer exposed in the region serving as the storage capacitor. Films (thermal oxide films) 220, 221, 222 are formed. In this embodiment, a silicon oxide film having a thickness of 50 nm is formed. The silicon oxide film 220 is used as a CMOS gate insulating film of a semiconductor device, and the silicon oxide film 221 is used as a CMOS gate insulating film of a driver circuit portion. Is used as a dielectric of a storage capacitor.
[0080]
The oxidation reaction also proceeds at the interface between the gate insulating film 219 made of a silicon oxide film remaining in the pixel TFT and the semiconductor layer therebelow. Therefore, finally, the film thickness of the gate insulating film 223 of the pixel TFT has a film thickness of 110 nm in total of the 60 nm thick insulating film formed in advance and the 50 nm thick insulating film formed by thermal oxidation. It becomes an insulating film. In addition, the semiconductor layer of about 25 nm is oxidized by this thermal oxidation process, and the film thicknesses of the active layers 210, 211, and 212 become 40 nm. This film thickness is the film thickness of the active layer of the final TFT.
[0081]
When the thermal oxidation process is completed in this manner, a conductive film to be a TFT gate wiring and a capacitor electrode is formed next. As a material for forming the gate wiring and the capacitor electrode, a conductive film having heat resistance that can withstand a temperature of 700 to 1150 ° C. (preferably 900 to 1100 ° C.) is used. Typically, a conductive silicon film (for example, a phosphorus-doped silicon film or a boron-doped silicon film) or a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, or a titanium film) may be used. A silicided silicide film, a nitrided nitride film (such as a tantalum nitride film, a tungsten nitride film, or a titanium nitride film) or an alloy film combining these materials may be used. Moreover, the laminated film which laminated | stacked the above thin film freely combining may be sufficient. When the metal film is used, it is desirable to have a laminated structure with a silicon film in order to prevent oxidation of the metal film. In terms of preventing oxidation, a structure in which a metal film is covered with a silicon nitride film is effective. In this embodiment, a laminated film of a silicon film (a phosphorus-doped silicon film having conductivity) / tungsten nitride film / tungsten film (or a silicon film / tungsten silicide film from the lower layer) is provided at 400 nm as the conductive film.
[0082]
In this embodiment, the lowermost silicon film is formed by using a low pressure thermal CVD method. Since the gate insulating film of the semiconductor device and the drive circuit section is as thin as 5 to 50 nm, there is a risk of damaging the semiconductor layer (active layer) depending on the conditions when sputtering or plasma CVD is used. Therefore, a thermal CVD method capable of forming a film by a chemical vapor reaction is preferable.
[0083]
Then, although the conductive film is patterned, the gate wiring is a layer that is most required to be miniaturized in a circuit having a field effect transistor, and exposure means capable of exposing a fine pattern is used for patterning the gate wiring of the semiconductor device. There is a need. In this embodiment, a pattern having a gate length of 0.8 μm is formed using a stepper used when patterning the active layer 210.
[0084]
On the other hand, in the display device, a pattern having a gate length of 3.5 μm may be formed, and the pattern is formed using a stepper used for patterning the active layers 211 and 212.
[0085]
Then, based on the resist pattern, the conductive film is etched to hold the CMOS gate wirings 224 and 225 of the semiconductor device, the CMOS gate wirings 226 and 227 of the driving circuit, and the gate wirings 228 and 229 of the pixel TFT. A capacitor electrode 230 is formed (FIG. 3D).
[0086]
Next, resist patterns 231a to 231d are formed, and an element belonging to Group 15 (phosphorus in this embodiment) is added again. In this embodiment, 5 × 10 ¹⁹ ~ 3x10 ^{twenty one} atoms / cm ^Three (Preferably 1 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three ) Impurity region containing phosphorus (n) ⁺ Regions) 232, 233, 236, 237, 240, 241, 242, and 243 are formed. The resist pattern 231a of the semiconductor device need only be prevented from adding phosphorus to the CMOS PTFT and does not need to be made fine, so that it was formed by performing collective exposure on the entire surface of the substrate using MPA.
[0087]
This step may be performed separately for a semiconductor device having a thin gate insulating film or a CMOS of a driving circuit portion and a pixel TFT having a thick gate insulating film, or may be performed simultaneously. In addition, the phosphorus addition step may use an ion implantation method in which mass separation is performed, or a plasma doping method in which mass separation is not performed. The practitioner may set optimum values for the acceleration voltage, the dose amount, and the like.
[0088]
Through this step, a source region 232, a drain region 233, an LDD region 235, and a channel formation region 234 are defined in the CMOS NTFT of the semiconductor device. In addition, a source region 236, a drain region 237, an LDD region 239, and a channel formation region 238 are defined in the CMOS NTFT of the driver circuit portion. In the pixel portion, the source region 240, the drain region 242 and the LDD regions 244a to 244d of the pixel TFT, and n ⁺ The regions 241 and 243 and the storage capacitor electrode 245 are defined (the channel region of the pixel TFT is already n ^- Defined in the step of forming the region). (Fig. 4 (A))
[0089]
At this time, the LDD regions 244a to 244d of the pixel TFT are formed so as to partially overlap the gate wirings 228 and 229. By adopting this structure, a structure resistant to deterioration caused by hot carrier injection, such as a so-called GOLD (Gate-drain Overlapped LDD) structure, can be obtained. In addition, the portion that does not overlap with the gate wirings 228 and 229 has a great effect in order to prevent an increase in off current. In this embodiment, in the LDD regions 244a and 244d in contact with the source region 240 or the drain region 242, the length (width) of the portion overlapping the gate wirings 228 and 229 is 0.3 to 2.0 μm (preferably 0.5). To 1.0 μm), and the length (width) of the non-overlapping portion is 1.0 to 4.0 μm (preferably 2.0 to 3.0 μm).
[0090]
The CMOS NTFT of the semiconductor device and the driver circuit portion has a structure in which the LDD regions 235 and 39 overlap with the gate wirings 224 and 226.
[0091]
Next, regions other than the region that becomes the CMOS PTFT are hidden by the resist patterns 246a to 246c, and an element belonging to group 13 (boron in this embodiment) is added. In this embodiment, 3 × 10 ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three Adjust the concentration so that boron is added. The resist pattern 246a only needs to prevent boron from being added to the NTFT of the semiconductor device and does not need to be fine. Therefore, the resist pattern 246a is formed by performing collective exposure on the entire surface of the substrate using MPA.
[0092]
Of course, in this step, an ion implantation method that performs mass separation may be used, or a plasma doping method that does not perform mass separation may be used. The practitioner may set optimum values for the acceleration voltage, the dose amount, and the like.
[0093]
By this process, the source region 248, the drain region 247, and the channel formation region 249 of the PTFT forming the CMOS of the semiconductor device are demarcated, and the source region 251, the drain region 250, and the channel formation region of the PTFT forming the CMOS of the driving circuit portion are defined. 252 defines. (Fig. 4 (B))
[0094]
When all the impurity regions are thus formed, the resist patterns 246a to 246c are removed. Then, a protective film 253 made of a silicon nitride oxide film having a thickness of 200 nm is formed so as to cover the gate wirings 224 to 229 and the capacitor electrode 230. This protective film has an effect of preventing oxidation of the gate wirings 224 to 229 and the capacitor electrode 230. As the protective film 253, another insulating film containing silicon may be used.
[0095]
When the protective film is formed, a heat treatment process is performed for 20 minutes to 12 hours in a temperature range of 600 to 1000 ° C. (preferably 600 to 850 ° C.). In this embodiment, heat treatment at 800 ° C. for 1 hour is performed in an inert atmosphere. The impurity element added by this step is activated and the amorphous silicon film is recrystallized.
[0096]
When activation is completed, hydrogenation is performed. The hydrogenation treatment is a treatment for adding hydrogen excited by heat treatment or plasma treatment. In the case of heat treatment, a heat treatment step of 300 to 450 ° C. for 2 to 6 hours is performed in an atmosphere containing 3 to 100% hydrogen. good. The hydrogenation treatment may be performed after the source wiring and the drain wiring are formed.
[0097]
Next, a first interlayer insulating film 254 is formed. In this embodiment, an 800 nm thick silicon oxide film formed by plasma CVD is used. Then, contact holes for the source region and the drain region are formed.
[0098]
In the patterning process for forming the contact hole, if importance is attached to integration, fine contact holes may be formed in the CMOS source region and drain region of the semiconductor device using two exposure means. In a semiconductor device, a fine pattern is important for integration, but it is desirable to use the same exposure means as that of a display device in terms of productivity. Therefore, it is possible to use the same exposure means as the display device by devising the pattern of the active layer 210 and enlarging the portions where the contact holes in the source and drain regions are formed. In this embodiment, with emphasis on integration, the contact holes of the drive circuit CMOS and the pixel TFT are formed by the first exposure means in the same manner as the patterning of the active layer, and the CMOS of the semiconductor device is formed by using the second exposure means. The contact hole was patterned. Although not shown, in this step, lead-out contact holes are also formed in the gate wirings 224 to 229 and the storage capacitor electrode 230.
[0099]
Then, source wirings 255, 257, 258, 260, 261 and drain wirings 256, 259, 262 are formed. In this embodiment, these wirings are formed by a laminated film in which a conductive film mainly composed of aluminum is sandwiched between titanium films. Here, in FIG. 4, the drain wiring of the COMS is common to the NTFT and the PTFT. However, this is an outline for simplifying the drawing, and a drain wiring may be provided for each.
[0100]
For patterning the source wiring and the drain wiring, two exposure means are used similarly to the patterning of the active layer, and the source wirings 258, 260, 261 and the drain wirings 259, 262 of the driving circuit portion and the pixel TFT are the first Patterning is performed by exposure means. The source wirings 255 and 257 and the drain wiring 256 of the semiconductor device were patterned by the second exposure means. In this step, although not shown, lead electrodes are also formed on the gate wirings 224 to 229 and the storage capacitor electrode 230 through contact holes.
[0101]
Next, a passivation film 263 is formed. As the passivation film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or a stacked film of these insulating films and a silicon oxide film can be used. In this embodiment, a silicon nitride film having a thickness of 300 nm is used as a passivation film.
[0102]
In this embodiment, as a pretreatment for forming the silicon nitride film, plasma treatment using ammonia gas is performed, and the passivation film 263 is formed as it is. Since the hydrogen activated (excited) by the plasma by this pretreatment is confined in the first interlayer insulating film 254, the hydrogen termination of the active layer (semiconductor layer) of the TFT can be promoted.
[0103]
And if a passivation film is formed, the heat processing process of 350-450 degreeC will be performed. This is a heat treatment for improving the quality of the passivation film, but at the same time, the hydrogen added to the first interlayer insulating film is lowered to the lower layer by thermal diffusion. The active layer can be efficiently hydrogenated. Of course, this heat treatment itself may be performed in an atmosphere containing hydrogen.
[0104]
Next, an acrylic film having a thickness of 1 μm is formed as the second interlayer insulating film 264. In addition to the acrylic film, an organic resin film such as a polyimide film, a polyamide film, a polyimideamide film, or a BCB (benzocyclobutene) film can be used. These resin films are effective because of their low relative dielectric constant and high flatness.
[0105]
Then, a metal film is formed thereon to a thickness of 200 nm and patterned to form shielding films 265 and 266. In this embodiment, a titanium film or a laminated film of an aluminum film and a titanium film is used as the shielding film. Since the shielding film is a layer that requires little miniaturization and is not used in the CMOS of the semiconductor device, the entire substrate may be exposed and patterned by MPA.
[0106]
Next, a third interlayer insulating film 267 made of an organic resin material as in the second interlayer insulating film is formed to a thickness of 1 μm. Then, the third interlayer insulating film, the second interlayer insulating film, and the passivation film are sequentially etched to form a contact hole reaching the drain wiring 262 of the pixel TFT, and the pixel electrode 270 is formed. The pixel electrode may be a transparent conductive film in the case of a transmissive liquid crystal display device, and a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by sputtering. In the case of a reflective liquid crystal display device, a contact hole reaching the drain wiring of the pixel TFT is formed after the second interlayer insulating film and the passivation film are formed, and the shielding film can be used as the pixel electrode. The number of masks can be reduced by one compared to the transmission type.
[0107]
In this step, contact holes reaching the CMOS source wirings 255 and 257 of the semiconductor device are formed, and lead electrodes 268 and 269 are formed of ITO.
[0108]
Since the contact hole opening and the patterning process of the pixel electrode and the extraction electrode do not require fine processing, they are formed by collectively recording the entire surface of the substrate using MPA.
[0109]
In the mixed substrate of this embodiment, the thickness of the gate insulating film differs between the CMOS TFT and the pixel TFT of the semiconductor device and the drive circuit formed on the same substrate.
[0110]
Another feature is that the CMOS gate insulating film of the semiconductor device and the drive circuit and the dielectric of the storage capacitor provided in the pixel portion are simultaneously formed to simplify the process.
[0111]
As described above, the semiconductor device and the drive circuit are characterized in that the step for forming the thin gate insulating film of the CMOS serves as the step for thinning the dielectric of the storage capacitor. With such a configuration, the capacity of the storage capacitor can be increased without increasing the area.
[0112]
As one of the features of the present embodiment, productivity is improved by properly using two exposure means and one exposure means in a plurality of patterning steps. That is, two exposure means are used in the patterning process that requires fine processing, and a wide area is exposed by one exposure means in the patterning process that does not require fine processing. In this embodiment, the patterning process that requires fine processing includes the patterning process of the active layer 210, the patterning process of the gate wirings 224 and 225, the patterning process of the contact holes of the source wirings 255 and 257 and the drain wiring 256, and the source wiring 255. 257 and drain wiring 256 patterning step.
[0113]
Further, according to the manufacturing process of this embodiment, the final active layer (semiconductor layer) of the TFT is formed of a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice. Here, the experimental results up to the stage of forming the crystalline silicon film according to the manufacturing process of this embodiment and the results of analyzing the film thus formed will be described below.
[0114]
The crystalline silicon film formed in accordance with the above manufacturing process has a crystal structure in which a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) are gathered and arranged microscopically. This was easily confirmed by observation with TEM (transmission electron microscopy).
[0115]
Further, when electron diffraction and X-ray (X-ray) diffraction are used, the surface of the crystalline silicon film (portion-forming portion) has a {110} plane as the main orientation plane although the crystal axis includes some deviation. It was confirmed that it has. As a result of detailed observation of an electron diffraction photograph having a spot diameter of about 1.5 μm by the present applicant, diffraction spots corresponding to the {110} plane appear clearly, but each spot has a distribution on a concentric circle. Was confirmed.
[0116]
In addition, the present applicant observed the grain boundaries formed by contact of individual rod-like crystals with HR-TEM (high resolution transmission electron microscopy), and confirmed that the crystal lattice has continuity at the grain boundaries. . This was easily confirmed because the observed lattice fringes were continuously connected at the grain boundaries.
[0117]
Note that the continuity of the crystal lattice at the crystal grain boundary results from the fact that the crystal grain boundary is a grain boundary called a “planar grain boundary”. The definition of the planar grain boundary in this specification is “Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp.751”. -758, 1988 ”is the“ Planar boundary ”.
[0118]
According to the above paper, planar grain boundaries include twin grain boundaries, special stacking faults, and special twist grain boundaries. This planar grain boundary is characterized by being electrically inactive. That is, although it is a crystal grain boundary, it does not function as a trap that inhibits the movement of carriers, and thus can be regarded as substantially nonexistent.
[0119]
In particular, when the crystal axis (axis perpendicular to the crystal plane) is the <110> axis, the {211} twin grain boundary is also called a corresponding grain boundary of Σ3. The Σ value is a parameter that serves as a guideline indicating the degree of consistency of the corresponding grain boundary. It is known that the smaller the value, the better the grain boundary.
[0120]
As a result of observing the crystalline silicon film formed by the present applicant in accordance with the manufacturing process of this embodiment in detail using TEM, most of the crystal grain boundaries (90% or more, typically 95% or more) correspond to Σ3. It was found to be a grain boundary, that is, {211} twin grain boundary.
[0121]
That is, in the crystal grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110}, assuming that the angle formed by the lattice stripes corresponding to the {111} plane is θ, θ = 70.5 It is known that it becomes a corresponding grain boundary of Σ3 when it is °. In the crystalline silicon film formed in accordance with the manufacturing process of this example, each lattice fringe of adjacent crystal grains at the crystal grain boundary is exactly continuous at an angle of about 70.5 °. Therefore, this crystal grain boundary is {211}. I came to the conclusion that it was a twin grain boundary.
[0122]
Incidentally, when θ = 38.9 °, the corresponding grain boundary of Σ9 is obtained, but such other crystal grain boundaries also existed.
[0123]
Such a corresponding grain boundary is formed only between crystal grains having the same plane orientation. That is, since the crystalline silicon film formed in accordance with the manufacturing process of this embodiment has approximately {110} plane orientation, such a corresponding grain boundary can be formed over a wide range.
[0124]
Such a crystal structure (exactly, the structure of the crystal grain boundary) indicates that two different crystal grains are joined with extremely good consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and the trap level caused by crystal defects or the like is very difficult to create. Therefore, it can be considered that the semiconductor thin film having such a crystal structure is substantially free of crystal grain boundaries.
[0125]
Furthermore, it has been confirmed by TEM observation that defects existing in the crystal grains are almost disappeared by the heat treatment step (corresponding to the thermal oxidation step in this embodiment) at a high temperature of 700 to 1150 ° C. This is also clear from the fact that the number of defects is greatly reduced before and after this heat treatment step.
[0126]
This difference in the number of defects appears as a difference in spin density by electron spin resonance analysis (Electron Spin Resonance: ESR). At present, the spin density of the crystalline silicon film formed according to the fabrication process of this example is at least 5 × 10 ¹⁷ spins / cm ^Three Below (preferably 3 × 10 ¹⁷ spins / cm ^Three The following): However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be even lower.
[0127]
From the above, the crystalline silicon film obtained by carrying out this example is considered to be a single crystal silicon film or a substantially single crystal silicon film because there is substantially no crystal grains and no crystal grain boundaries. Good. The present applicant refers to a crystalline silicon film having such a crystal structure as CGS (Continuous Grain Silicon).
[0128]
For the description of CGS, reference may be made to the applications of Japanese Patent Application No. 10-044659, Japanese Patent Application No. 10-152316, Japanese Patent Application No. 10-152308, or Japanese Patent Application No. 10-152305 filed by the present applicant.
[0129]
[Example 2]
In this embodiment, an example of an active matrix panel in which a semiconductor device and a display device are electrically connected will be described with reference to FIG. In FIG. 5, a cross-sectional view of the CMOS constituting the semiconductor device is shown on the left side of the drawing, and a cross-sectional view of the pixel TFT and the storage capacitor of the CMOS and pixel portion constituting the driving circuit portion of the display device is shown in the center and right side of the drawing. The same reference numerals are used for parts common to the first embodiment.
[0130]
Up to the formation of the third interlayer insulating film, the same steps as those in Example 1 are performed. Then, in the step of forming the contact hole of the pixel electrode, at the same time, the third interlayer insulating film 267 ′ and the second interlayer insulating film 264 ′ formed on the CMOS of the semiconductor device and the drive circuit unit are all etched to form a passivation film. A contact hole for a CMOS lead electrode of the semiconductor device and a CMOS lead electrode of the drive circuit is opened at 263 ′.
[0131]
In the step of forming the pixel electrode 270, the extraction electrodes 268 ′ and 269 ′ are formed using the same conductive film as the pixel electrode. The drain electrode 256 of the semiconductor device and the source electrode 258 of the NTFT in the driver circuit portion of the display device are electrically connected by the extraction electrode 269 ′.
[0132]
Thus, in this embodiment, the semiconductor device and the display device are electrically connected using the same conductive film as the pixel electrode. This is because the exposure means for forming the wiring patterns 255 to 257 of the semiconductor device and the exposure means for forming the wiring patterns 258 to 262 of the drive circuit portion and the pixel portion are different in the pattern formation of the source wiring and the drain wiring. This is because it is difficult to electrically connect to the source wiring 236 of the driver circuit portion by extending the drain wiring 256 of the semiconductor device.
[0133]
In the present embodiment, the third interlayer insulating film and the second interlayer insulating film formed on the CMOS of the semiconductor device and the drive circuit section are all etched. This is because the pixel electrode 270 is preferably flat in the pixel portion, but in the semiconductor device and the drive circuit portion, the contact hole becomes deeper, thereby increasing the diameter of the contact hole and increasing the aspect ratio. Problems such as disconnection occur. Therefore, all of the third interlayer insulating film and the second interlayer insulating film of the semiconductor device and the drive circuit portion that need to be integrated can be etched to make the contact hole shallower and smaller. This configuration can also be applied in the first embodiment.
[0134]
[Example 3]
In this embodiment, the structure of a CMOS constituting a semiconductor device is shown in FIGS. A functional semiconductor device can be realized by selecting and arranging a CMOS having the structure shown in FIGS. 6A to 6C according to the required characteristics. 6A to 6C, PTFTs have the same structure.
[0135]
In the structure of FIG. 6A, the LDD region 501 of the NTFT is provided only between the channel region and the drain region so as to overlap the gate wiring, and has an effect of preventing deterioration of the on-current value due to hot carrier injection. This LDD region may be provided at least on the drain region side. The CMOS having this structure is preferably arranged in a circuit that requires high-speed operation. Note that the length of the LDD region 501 is preferably 0.3 to 1 μm (typically 0.5 to 0.8 μm).
[0136]
In the structure of FIG. 6B, the LDD regions 502 and 503 are provided so as to be sandwiched between both sides of the channel formation region, and the portion overlapping the gate wiring prevents deterioration due to hot carrier injection and does not overlap. The portion has an effect of preventing an increase in off current. The CMOS having this structure is preferably arranged in a circuit that requires reliability because the functions of the source region and the drain region are inverted. The length of the LDD region overlapping with the gate wiring is 0.3 to 2 μm (typically 1.0 to 1.5 μm), and the length of the LDD region not overlapping with the gate wiring is 1.0 to 2.5 μm (typical). Specifically, it may be 1.5 to 2.0 μm).
[0137]
6C is provided so that the LDD regions 505 and 506 are sandwiched between both sides of the channel formation region, and has an effect of preventing an increase in off-current because it does not overlap with the gate wiring. This structure is preferably arranged in a circuit in which the functions of the source region and the drain region are inverted, particularly in a circuit in which off current needs to be reduced.
[0138]
The structure shown in FIG. 6A can be obtained by applying the CMOS manufacturing method of the semiconductor device of Embodiment 1, and the structure shown in FIG. 6B can be obtained by applying the pixel TFT manufacturing process to the CMOS NTFT.
[0139]
One method for obtaining the structure of the NTFT in FIG. 6C will be described using the manufacturing process of the pixel TFT of Example 1 as an example. Step of adding phosphorus (n) in FIG. ^- ) Is not performed on the pixel TFT, and a source region and a drain region are formed by the resist patterns 231c and 231d of FIG. Then, after removing the resist patterns 231a to 231d, a phosphorus addition step (n ^- ) To the pixel TFT, and the LDD region is formed by self-alignment using the gate wiring of the NTFT as a mask. Thus, LDD regions that do not overlap with the gate wiring can be provided on both sides of the channel region. Step of adding phosphorus (n ^- In this case, phosphorus is also added to the source region and the drain region of the PTFT. However, since the p-type impurity is added 10 times or more in the subsequent boron adding step, the function of the PTFT as the source region and the drain region is increased. Has no effect.
[0140]
As described above, a functional semiconductor device can be formed by appropriately selecting CMOSs having different characteristics to be obtained as necessary and designing a circuit by using them appropriately.
[0141]
Note that the manufacturing process of Example 1 can be used to realize the configuration of this example. In addition, it is effective to apply the numerical range shown in the present embodiment in performing the manufacturing process of the first embodiment.
[0142]
[Example 4]
In this embodiment, a case where an active matrix panel is formed over a substrate in the manufacturing process shown in Embodiment 1 and a display device is actually manufactured using the panel will be described.
[0143]
When the state of FIG. 4C is obtained, an alignment film is formed on the pixel electrode 270 to a thickness of 80 nm. Next, a panel having a counter electrode with a color filter, a transparent electrode (counter electrode) and an alignment film formed on a glass substrate is prepared, and each alignment film is subjected to a rubbing treatment, and a sealing material (sealing) The active matrix panel and the panel having the counter electrode are bonded together using a material. In the meantime, the liquid crystal is held. Since this cell assembling process may use known means, a detailed description is omitted.
[0144]
In addition, what is necessary is just to provide the spacer for maintaining a cell gap as needed. Therefore, when the cell gap can be maintained without a spacer as in a display device of 1 inch or less, it is not particularly necessary.
[0145]
Next, the appearance of the display device manufactured as described above is shown in FIG. An active matrix panel (referring to a substrate on which TFTs in FIG. 4C are formed) 11 includes a pixel portion 12, a driver circuit (source driver circuit 13, gate driver circuit 14), and a logic circuit which is a semiconductor device having microelements (Signal dividing circuit, D / A converter circuit, γ correction circuit, differential amplifier circuit, etc.) 15 are formed, and an FPC (flexible printed circuit) 16 is attached. Reference numeral 17 denotes a panel having a counter electrode.
[0146]
The TFTs that form the pixel portion, the drive circuit, and the logic circuit are formed according to the manufacturing process of the first embodiment. Further, an optimum TFT structure may be disposed with reference to the first embodiment. Note that this embodiment can be freely combined with any of Embodiments 1 to 3.
[0147]
Example 5
The present invention can also be used when an interlayer insulating film is formed on a conventional MOSFET and a TFT is formed thereon. That is, it is also possible to realize a three-dimensional semiconductor device in which a reflective display device is formed on a semiconductor circuit.
[0148]
The semiconductor circuit may be formed on an SOI substrate such as SIMOX, Smart-Cut (registered trademark of SOITEC), ELTRAN (registered trademark of Canon Inc.), or the like.
[0149]
In addition, when implementing a present Example, you may combine any structure of Examples 1-4.
[0150]
Example 6
The present invention can also be applied to an active matrix EL display as a display device. An example is shown in FIG.
[0151]
FIG. 9 is a circuit diagram of an active matrix EL display. Reference numeral 81 denotes a pixel portion, and an X direction control circuit 82 and a Y direction control circuit 83 are provided around the pixel portion. Each pixel of the pixel portion 81 includes a switching TFT 84, a capacitor 85, a current control TFT 86, and an organic EL element 87. The switching TFT 84 has an X direction signal line 88a (or 88b) and a Y direction signal line 89a ( Or 89b and 89c) are connected. Further, power supply lines 90 a and 90 b are connected to the current control TFT 86.
[0152]
In the active matrix EL display of this embodiment, the CMOS of the drive circuit shown in the first embodiment is used as the X direction control circuit 82 and the Y direction control circuit 83, and the CMOS of the drive circuit shown in the first embodiment is used as the current control TFT 86. An NTFT can be used, and the pixel TFT shown in Embodiment 1 can be used as the switching TFT 84.
[0153]
Note that in the active matrix EL display of this embodiment, an EL layer may be formed by a known method after the active matrix substrate shown in FIG. 4C is manufactured. Therefore, the manufacturing process of Example 1 can be used.
[0154]
Example 7
The liquid crystal display device manufactured according to the present invention can use various liquid crystal materials. As such materials, TN liquid crystal, PDLC (polymer dispersion type liquid crystal), FLC (ferroelectric liquid crystal), AFLC (antiferroelectric liquid crystal), or a mixture of FLC and AFLC (antiferroelectric mixed liquid crystal). Can be mentioned.
[0155]
For example, `` H.Furue et al.; Characteristics and Drivng Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability, SID, 1998 '', `` T.Yoshida et al.; A Full- Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time, 841, SID97DIGEST, 1997 '', `` S.Inui et al.; Thresholdless antiferroelectricity in liquid crystals and its application to displays, 671-673, J.Mater.Chem.6 (4), 1996 "or the material disclosed in US Pat. No. 5,594,569 can be used.
[0156]
In particular, V-shaped (or U-shaped) is used for a thresholdless antiferroelectric mixed liquid crystal (Thresholdless Antiferroelectric LCD: TL-AFLC) that exhibits an electro-optic response characteristic in which transmittance continuously changes with respect to an electric field. Some have shown electro-optic response characteristics, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) has been found. Therefore, the power supply voltage for the pixel circuit may be about 5 to 8 V, and it is suggested that the drive circuit and the pixel circuit may be operated with the same power supply voltage.
That is, the power consumption of the entire liquid crystal display device can be reduced.
[0157]
Further, the ferroelectric liquid crystal and the antiferroelectric liquid crystal have an advantage that the response speed is faster than that of the TN liquid crystal. Since the TFT as used in the present invention can realize a TFT having a very high operation speed, a liquid crystal display device having a high image response speed that makes full use of the response speed of a ferroelectric liquid crystal or an anti-ferroelectric liquid crystal. Can be realized.
[0158]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.
[0159]
The configuration of this embodiment can be used for the display device shown in Embodiment 1, 2, 4 or 5. Needless to say, it is effective to use the liquid crystal display device of this embodiment as a display for an electronic device such as a personal computer.
[0160]
Example 8
The present invention can be implemented in all electronic devices in which a display device or a semiconductor device is incorporated.
[0161]
Such electronic devices include liquid crystal displays, video cameras, digital still cameras, projectors (rear type or front type), goggles type displays (head mounted displays), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones) An image playback device equipped with a recording medium (specifically, a telephone or an electronic book) (specifically, a recording medium such as a compact disc (CD), a laser disc (LD), or a digital video disc (DVD)) is played and the image is displayed. And a device equipped with a display that can be used. Examples of these electronic devices are shown in FIGS.
[0162]
FIG. 10A illustrates a personal computer, which includes a main body 2001, an image receiving portion 2002, a display device 2003, a keyboard 2004, and the like. The present invention can be used for the image receiving portion 2002 if an image sensor is formed as the display device 2003 and the semiconductor device.
[0163]
FIG. 10B illustrates a video camera which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be used for the image receiving portion 2106 if an image sensor is formed as the display device 2102 and the semiconductor device.
[0164]
FIG. 10C illustrates a goggle type display which includes a main body 2201, a display device 2202, an arm portion 2203, and the like. The present invention can be used for the display device 2202.
[0165]
FIG. 10D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium, which includes a main body 2301, a recording medium (CD, LD, DVD, etc.) 2302, an operation switch 2303, and a display device (a). 2304, a display device (b) 2305, and the like. Although the display device (a) mainly displays image information and the display device (b) mainly displays character information, the present invention can be used for these display devices (a) and (b). Note that the present invention can be used for a CD playback device, a game machine, or the like as an image playback device provided with a recording medium.
[0166]
FIG. 10E illustrates a front type projector, which includes a main body 2401, a light source, an optical system lens including a display system, an optical engine 2402, and the like, and can display an image on a screen 2403. The present invention can be used for a display device (not shown) built in the optical engine 2402. Note that the display device may be a method using three or a single device, and may be a transmissive display device or a reflective display device.
[0167]
FIG. 10F illustrates a rear projector, which includes a main body 2501, an optical engine 2502 including a light source, an optical system lens, and a display device, reflectors 2503 and 2504, a screen 2505, and the like. The present invention can be used for a display device (not shown) built in the optical engine 2502. Note that the display device may be a method using three or a single device, and may be a transmissive display device or a reflective display device.
[0168]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example can be implement | achieved combining the structure of Examples 1-7.
[0169]
【The invention's effect】
According to the present invention, since semiconductor devices having different line width rules can be arbitrarily formed over the same substrate, a product with high added value in which semiconductor devices such as a CPU and a memory are integrated in addition to a display device can be obtained.
[0170]
In addition, capital investment can be reduced by applying a part of the existing IC line.
[0171]
When a semiconductor device having a large exclusive area is formed on a circular substrate, a semiconductor device having a small device area can be formed in an excess portion, and the substrate can be used effectively.
[0172]
Further, since the two exposure means are used only in the necessary exposure process, a plurality of types of semiconductor devices can be manufactured without significantly reducing the productivity. In addition, it is possible to dispose TFTs having appropriate performance according to specifications required by each part of the semiconductor device, and the performance and reliability of the semiconductor device can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a top view of a mixed substrate.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of an active matrix panel.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of an active matrix panel.
FIG. 4 is a cross-sectional view showing a manufacturing process of an active matrix panel.
FIG. 5 is a cross-sectional view of an active matrix panel.
FIG. 6 is a cross-sectional view showing a structure of a CMOS.
FIG. 7 is a lithography process diagram for carrying out the present invention.
FIG. 8 is a diagram illustrating an appearance of a display device.
FIG 9 illustrates a circuit configuration of an active matrix EL display device.
FIG 10 illustrates an example of an electronic device.

Claims (7)

A method for manufacturing a semiconductor device having a display device and a logic circuit over a circular substrate,
Forming a workpiece on the circular substrate;
Applying a resist on the workpiece;
Exposing the circular substrate by a first exposure means to form a first pattern from an unexposed region of the resist ;
Said first pattern, is exposed by the first exposure means is different from a second exposure means to form a second pattern from the unexposed areas of the first pattern,
Removing all areas of the resist exposed by the first exposure means and all areas exposed by the second exposure means by a developing step;
The display device is formed from a portion of the workpiece that overlaps the region exposed by the first exposure means,
Forming the logic circuit from a portion of the workpiece that overlaps the previous second pattern,
Light of light source and the second exposure means of said first exposure means Ri same der,
The device area of the display device is larger than the device area of the logic circuit,
The display device is disposed near the center on the circular substrate,
The method for manufacturing a semiconductor device, wherein the logic circuit is arranged around the display device on the circular substrate . A method for manufacturing a semiconductor device having a display device and a logic circuit over a circular substrate,
Forming a workpiece on the circular substrate;
Applying a resist on the workpiece;
Exposing the circular substrate by a first exposure means to form a first pattern from an unexposed region of the resist ;
Said first pattern, is exposed by the first exposure means is different from a second exposure means to form a second pattern from the unexposed areas of the first pattern,
Removing all areas of the resist exposed by the first exposure means and all areas exposed by the second exposure means by a developing step;
The display device is formed from a portion of the workpiece that overlaps the region exposed by the first exposure means,
Forming the logic circuit from a portion of the workpiece that overlaps the previous second pattern,
Higher in the resolution in the second exposure unit than the resolution in the first exposure unit,
Light of light source and the second exposure means of said first exposure means Ri same der,
The device area of the display device is larger than the device area of the logic circuit,
The display device is disposed near the center on the circular substrate,
The method for manufacturing a semiconductor device, wherein the logic circuit is arranged around the display device on the circular substrate . In claim 1 or claim 2 ,
A manufacturing method of a semiconductor device, wherein an exposure apparatus in the first exposure means and an exposure apparatus in the second exposure means are different. In any one of Claim 1 thru | or 3 ,
Using a mirror projection in the first exposure means;
A method for manufacturing a semiconductor device, wherein a stepper is used in the second exposure means. In any one of Claims 1 thru | or 4 ,
A method for manufacturing a semiconductor device, wherein a minimum line width of the first pattern is different from a minimum line width of the second pattern. In any one of Claims 1 thru | or 5 ,
A method for manufacturing a semiconductor device, wherein a semiconductor film, a conductive film, or an insulating film is used for the workpiece. In any one of Claims 1 thru | or 6 ,
A method for manufacturing a semiconductor device, wherein a quartz substrate, a glass substrate, a plastic substrate, a semiconductor substrate, or an SOI substrate is used as the circular substrate.

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