JP4627286B2 - Semiconductor memory device and semiconductor device - Google Patents

Abstract

Disclosed is a module where semiconductor memory devices each having a DLL (Delay Lock Loop) are stacked or a multi-chip module (MCM) having the semiconductor memory devices, a dedicated pad for sharing a clock signal between one of the semiconductor memory devices and other semiconductor memory device is included. The clock signal is delay adjusted by the DLL. The DLL in the one semiconductor memory device is operated, while the DLL in the other semiconductor memory device is not operated. A flying lock clock signal synchronized with an external differential clock signal and generated from a clock signal delay adjusted by the DLL is output from the dedicated pad of the one semiconductor memory device. The other semiconductor memory device receives the flying lock clock signal from the dedicated pad.

Description

  The present invention relates to a semiconductor device, and more particularly to a clock synchronous semiconductor memory device.

  Recently, in a clock synchronous semiconductor memory device or the like, a semiconductor memory device incorporating a DLL (Delay Lock Loop) circuit has been mainstream, and in a module, the number of DLLs corresponding to the number of semiconductor memory devices to be mounted. As a result, the power consumption of the system is increased.

  A temperature rise (heat generation) due to an increase in current consumption leads to instability of the system.

  Accordingly, an object of the present invention is to provide a semiconductor memory device and a semiconductor device that reduce power consumption in a semiconductor device including a plurality of chips of a semiconductor memory device with a DLL circuit.

  In order to solve the above-described problems, the invention disclosed in the present application is generally configured as follows.

According to the present invention, the delay value corresponding to the delay information provided in the connection signal line that outputs the lock signal (LCLK) that is delay-synchronized with the external clock signal to the internal circuit of its own semiconductor memory device and connects between the semiconductor memory devices. Outputs a signal (referred to as a “flying lock clock signal”) (LIOCLK) that is delayed and synchronized with an external clock signal, which is a clock signal earlier than the lock signal (LCLK), to another semiconductor memory device. locked loop) and the circuit, the internal signal (MLCLK) of the DLL circuit, selects one of the flying lock clock signal input from another semiconductor storage device (LIOCLK), and outputs the lock signal (LCLK) A clock select circuit, wherein the DLL circuit is active in the lock clock select circuit. In the first state controlled by the above, the internal signal (MLCLK) is selected, and the lock clock select of the other semiconductor memory device in the second state in which the DLL circuit is mounted and the DLL circuit is controlled to be inactive. In the second state in which the flying lock clock signal is supplied to the circuit and the DLL circuit is controlled to be inactive, the other semiconductor memory device in the first state in which the DLL circuit is mounted and the DLL circuit is controlled to be active There is provided a semiconductor memory device that selects the flying lock clock signal supplied from, and generates the lock signal (LCLK) from the flying lock clock signal (LIOCLK) .

  According to the present invention, in a chip to which a flying lock clock signal is supplied from a chip on which the DLL circuit is operated via a dedicated pad, most of the DLL circuit does not operate, so that the current consumption of the DLL circuit is reduced. it can. As a result, current consumption can be reduced as a whole module.

  The above-described present invention will be described below with reference to the accompanying drawings in order to explain in more detail. The present invention relates to a semiconductor memory device stack module having a DLL (Delay Lock Loop) circuit or a multi-chip module (MCM) having a plurality of semiconductor memory devices. The semiconductor memory device has a dedicated pad (PAD) for sharing between the semiconductor memory device and another semiconductor memory device, operates the DLL of one semiconductor memory device, does not operate the DLL in the other semiconductor memory device, and operates one semiconductor From the dedicated pad of the storage device, a clock signal (referred to as a “flying lock clock signal”) that is delayed and synchronized with an external clock signal (CLK, CLKB), which is generated from a clock signal (CLK) that is delay-adjusted by DLL, Other semiconductor memory devices input the flying lock clock signal from a dedicated pad. Since most of the DLL circuit does not operate in a chip to which a flying lock clock signal is supplied from a chip in which the DLL circuit operates via a dedicated pad, the current consumption of the DLL circuit can be reduced. As a result, current consumption can be reduced as a whole module. Hereinafter, description will be made with reference to examples.

  1 and 2 are diagrams showing the configuration of an embodiment of the present invention. FIG. 1 shows a bonding state when a semiconductor memory device having a dedicated pad for DLL is stacked in two chips. FIG. 2 shows an internal configuration and operation of a semiconductor memory device having a dedicated pad (DPIO) for transferring a flying lock clock signal synchronized with an external differential clock signal (CLK, CLKB), which is generated from a DLL locked clock signal. It is a figure for demonstrating.

  Referring to FIG. 2, the flying lock clock (LIOCLK) is set to a dedicated pad (dedicated PAD) by a signal obtained from an initial setting or a separately provided bonding option pad (PAD) by an external command such as a mode register set. And a chip C1 set to be supplied to another chip, and a chip C2 set to capture a flying lock clock (LIOCLK) from the outside.

  The chip C1 and the chip C2 include a DLL circuit DL, an output circuit group DO, a DQ-pad group PQ, a dedicated pad DP, and a dedicated pad DPIO.

Although not particularly limited, in this embodiment, the DLL circuit DL is
As an input signal
Differential clock CLK, CLKB,
Output enable signal OE,
DLL enable signal DLLEN,
DLL reset signal DLLRST, and
MLCLK
Enter
LCLK as output signal, and
Output ELCLK,
A flying lock clock (LIOCLK) is input / output as an input / output signal, and a data output timing signal is generated.

  The CLK and CLKB signals are reference clock signals that are input differentially from the outside.

  The DLLEN signal is a signal for selecting whether to activate or deactivate the DLL set by an external mode register or the like.

  The DLLRST signal is a signal for resetting the DLL operation set by an external mode register or the like.

  The OE signal is an output enable signal for enabling data output.

  The LCLK signal is a clock used for data output.

  The ELCLK signal and the MLCLK signal are signals for acquiring wire delay information.

  The LIOCLK signal is a signal for passing a flying lock clock signal to another chip.

  The PD1 to PDs signals are data signals for data output.

The output circuit group DO is
The input signals are PD, OE, and LCLK;
The output signal is DOUT.
It consists of a group of output circuits that output data.

  The DQ-PAD (pad) group PQ is a pad to which the output signal of the output circuit is connected.

  The dedicated pad DP is provided to obtain delay information of the flying lock clock.

  The dedicated pad DPIO is a pad for inputting and outputting a flying lock clock.

  As connection information between the blocks, a flying lock clock signal generated from a signal locked by the DLL is input as LCLK of the output circuit group DO.

  A DOUT signal that is an output signal of the output circuit group DO is connected to the DQ-pad group PQ.

  The ELCLK signal that is an output signal of the DLL circuit DL and the MLCLK signal that is an input signal are connected to a dedicated pad DP, and the two dedicated pads DP are connected via a bonding wire.

  The LIOCLK signal that is an input / output signal of the DLL circuit DL is connected to the dedicated pad DPIO, and the dedicated pad DPIO of the chip C1 and the dedicated pad DPIO of the chip C2 are connected via a bonding wire.

  The chip connection form shown in FIG. 1 shows a bonding state when the semiconductor memory device having the DLL dedicated pad shown in FIG. 2 is stacked in two chips.

  As shown in FIG. 1, the chip (semiconductor memory device) C1 and the chip C2 are stacked, and B1 which is a bonding pad for connection with an external signal, and a chip PAD on the chips C1 and C2 Are connected by bonding wires.

  Further, the chip C1 and the chip C2 are dedicated pads DPIO for passing a flying lock clock which is generated from a DLL-locked clock signal and is delayed and synchronized with an externally input differential clock signal CLK and CLKB. Two dedicated pads DP for obtaining bonding wire delay information are provided, and the dedicated pads for passing the flying lock clock are connected between the chips C1 and C2 by bonding wires.

  In addition, a dedicated pad DP for acquiring bonding wire delay information (for example, a dedicated pad to which ECLK is connected) is a dedicated pad for acquiring bonding wire delay information in the same semiconductor memory device (dedicated PAD to which MLCLK is connected). Bonding wire is connected.

  FIG. 3 is a diagram showing an example of the configuration of the DLL circuit of this embodiment and the connection relationship with the dedicated pad.

  The configuration in FIG. 3 includes a DLL circuit and a dedicated pad group. The DLL circuit includes a clock first stage circuit DL0, a delay generation circuit DL1, a delay control circuit DL2, a lock clock select circuit DL3, an output circuit replica circuit DL4, and a phase determination circuit DL5.

  The clock first stage circuit DL0 amplifies the CLK and CLKB signals, which are input signals, by a differential amplifier circuit constituted by a current mirror circuit or the like and outputs the amplified signal as an RCLK signal.

  The delay generation circuit DL1 generates a signal ETCLK obtained by adding a delay determined by DLT [t: 1] (t is a positive integer determined by delay adjustment accuracy) to the RCLK signal.

  The delay control circuit DL2 outputs delay information data as a DLT [t: 1] signal according to the state of the DET that is the phase determination result signal.

The lock clock select circuit DL3 generates a signal that is a source of the clock signal LCLK supplied from the output circuit group.
When the DLL is active, the MLCLK signal,
When the DLL is inactive, the LIOCLK signal is selected. That is, when the DLL is inactive, the lock clock select circuit DL3 selects the LIOCLK signal input to the LIOCLK terminal (input / output terminal) from the other chip via the dedicated pad DPIO and outputs it as the LOCK signal and the RLCLK signal.

  The lock clock select circuit DL3 outputs the RLCLK signal when the DLL is active.

  The output circuit replica circuit DL4 outputs a MCLK signal with a delay equivalent to that of the output circuit with respect to the RLCLK signal.

  The phase determination circuit DL5 outputs the result of detecting the deviation between the edge of the MCLK signal and the cross position of the differential external clock signals CLK and CLKB as a DET signal.

  In this embodiment, a lock clock select circuit DL3 is newly provided (not present in the conventional configuration), and the output signal ETCLK of the delay generation circuit DL1 is connected to the output circuit replica circuit DL4 as an RLCLK signal.

  The dedicated pad group includes a dedicated pad DP to which the MLCLK and ELCLK signals are connected, and a dedicated pad DPIO to which the LIOCLK signal is connected. In the conventional configuration, this dedicated pad does not exist.

  The DLLEN signal input to the clock first stage circuit DL0, delay generation circuit DL1, delay control circuit DL2, lock clock select circuit DL3, and phase determination circuit DL5 is initialized by an external command such as a mode register set or separately. This is a signal obtained from the provided bonding option PAD. Although not particularly limited, when the DLL is activated, the DLLEN signal is set to High (“H”), and when the DLL is deactivated, the DLLEN signal is set to Low (“L”).

  In the DLL circuit, when the DLLEN signal is inactive at the low level, the operation of each circuit that inputs the DLLEN signal is stopped.

  The DLLRST signal input to the delay control circuit DL2 is a signal for resetting the delay information and returning it to the initial value.

  The OE signal input to the lock clock select circuit DL3 is an enable signal for enabling the LCLK signal input to the output circuit group.

FIG. 4 is a diagram showing a configuration example of the lock clock select circuit DL3 of the present embodiment. As a configuration,
An inverter J0 that inputs and inverts the MLCLK signal connected to the dedicated pad DP of FIG. 3 and outputs the MLCLKB signal;
An inverter J1 (inverted receiver of IOCLK signal) that inputs and inverts the LIOCLK signal connected to the dedicated pad DPIO of FIG. 3 and outputs the LIOCLKB signal;
A 2-input NAND circuit J2 that inputs DLLEN and ETCLK signals and outputs an ETCLKLB signal;
A 2-input NAND circuit J3 that inputs DLLEN and ETCLK signals and outputs an ETCLKEB signal;
An inverter J4 that inputs and inverts the DLLEN signal and outputs the DLLENB signal;
A two-input NAND circuit J5 that inputs SLCLK and OE signals and outputs an LCLKPB signal;
An inverter J6 that inputs and inverts the LCLKPB signal and outputs the LCLK signal;
A two-input NAND circuit J7 that inputs the SLCLK and DLLEN signals and outputs the RLCLKPB signal;
An inverter J8 that inputs the RLCLKPB signal and outputs the RLCLK signal;
An inverter J9 for load adjustment with ELCLK as an input;
Clock inverters (clocked inverters) J10 to J14;
It has.

  In the clock inverter J10, the MCLKB signal is connected as DT (input), the DLLENB signal as ENB (inverted signal of the enable signal EN), the DLLEN signal as EN, and the SLCLK signal as output OB.

  In the clock inverter J11, the LIOCLKB signal is connected as DT, the DLLEN signal as ENB, the DLLENB signal as EN, and SLCLK as OB.

  In the clock inverter J12, the ETCLKLB signal is connected as DT, the DLLENB signal as ENB, the DLLEN signal as EN, and LIOCLK as OB (connected to a dedicated pad). The clock inverter J12 and the NAND circuit J2 constitute a tristate normal output buffer of LIOCLK.

  In the clock inverter J13, the ETCLKEB signal is connected as DT, GND as ENB, power supply as EN, and ELCLK as OB.

  The clock inverter J14 is connected with GND as DT, power supply as ENB, GND as EN, and MLCLK as OB.

The clock inverters J10 to J14 have the same configuration,
A PMOS transistor Q1I (I = 1 to 5) having a source connected to a power supply and a gate connected to ENB;
A PMOS transistor Q2I (I = 1 to 5) having a source connected to the drain of the PMOS transistor Q1I (I = 1 to 5), a gate connected to the DT signal, and a drain connected to the output OB;
NMOS transistor Q3I (I = 1 to 5) having a drain connected to output OB and a gate connected to input DT;
An NMOS transistor Q4I (I = 1 to 5) having a source connected to GND, a gate connected to EN, and a drain connected to the source of the NMOS transistor Q3I (I = 1 to 5);
It has.

  FIG. 5 is a diagram showing another configuration example of the lock clock select circuit DL3 in the DLL circuit of this embodiment. Referring to FIG. 5, a replica delay element J15 of wiring, pads, and bonding wire portions, in which the input is the ELCLK signal and the output is the MLCLK signal, is added to the configuration of FIG. The other configuration is the same as that of FIG. The replica delay element J15 includes an ELCLK equivalent delay element K0, a pad equivalent delay element K1, a bonding wire equivalent delay element K2, a pad equivalent delay element K3, and an MLCLK wiring equivalent delay element K4 connected in series. Each circuit is composed of a circuit (an integrating circuit of a resistor and a MOS capacitor) for replicating the respective delays.

  Next, the operation of this embodiment will be described.

  In FIG. 2, the chip C1 supplies a flying lock clock to another chip C2 via a pad DPIO by an initial setting by an external command such as a mode register set or a signal obtained from a separately provided bonding option PAD. Is set to

  The chip C2 shows a case where it is set to take in the flying lock clock LIOCLK from the outside.

  The DLLEN signal in the chip C1 is set to a high level, and the DLLEN signal in the chip C2 is set to a low level.

  In this state, the DLL circuit DL of the chip C1 in which the DLLEN signal is High is in an active state, and performs an operation for phase-synchronizing the delay of data output with the external CLK and CLKB signals. It becomes a state.

  Further, a signal having the same homologous delay as the flying lock clock LIOCLK is output as the ELCLK signal.

  The ELCLK signal in the chip C1 is connected to the MLCLK signal via the bonding wire in the dedicated pad DP, and the MLCLK signal is input to the DLL circuit DL.

  On the other hand, the DLL circuit DL in the chip C2 in which the DLLEN signal is set to Low becomes inactive, and the ELCLK signal becomes Low in the DLL circuit (since DLLEN is Low, the output of the NAND circuit J3 is output in the clocked inverter J13). Becomes high, the transistor Q34 is turned on, and the ELCLK signal is at a low level.) Since the ELCLK signal is connected to the MLCLK signal via the dedicated pad DP, it is input to the DL of the DLL circuit as a low state.

  Further, the LIOCLK signal in the chip C2 becomes a high impedance state by the DLLEN signal (because DLLEN is Low, in the clocked inverter J12, EN is Low, DLLENB is High, and the clocked inverter J12 is turned off). Here, since the LIOCLK of the output signal in the chip C1 is connected to the LIOCLK signal of the chip C2 via the dedicated pads DPIO of the chips C1 and C2, the LIOCLK in the chip C2 is driven by the LIOCLK of the chip C1. It will be.

  The above-described chip connected by bonding is shown as a diagram of a bonding state when the semiconductor memory device having the DLL dedicated pad of FIG. 1 is stacked in two chips. The dedicated pad DP is bonded in the chip, and the dedicated pad DPIO is connected between the chips.

  The LIOCLK, MLCLK, and ELCLK signals in each chip are wired with the same load so that the wiring delays are equal.

If the delay due to the LIOCLK wiring load is TSL, the delay due to the MLCLK wiring load is TSM, and the delay due to the ELCLK wiring load is TSE,
TSL = TSM = TSE (1)
It becomes.

Further, in each chip, a bonding wire connecting between dedicated pads DP for obtaining bonding wire delay information (delay due to the load of the dedicated pad DP and the bonding wire is TW1),
The bonding wire that connects the LIOCLK signal between the chips via the dedicated pad DPIO (delay by the load is TW2)
Bonding is performed so that the delay times are equal.

    TW1 = TW2 (2)

With the above,
Delay from ELCLK output from the DLL circuit DL of the chip C1 to input to the DLL circuit DL as MLCLK via a bonding wire by a dedicated pad DP (dedicated pad DP for acquiring bonding wire delay information) (= TSE + TW1 + TSM)
The delay until the LIOCLK signal output from the chip C1 is input to the DLL circuit DL of the chip C2 as the LIOCLK of the chip C2 via the bonding wire connecting the dedicated pad DPIO of the chip C1 and the dedicated pad DPIO of the chip C2 ( = TSL + TW2 + TSL) are equal to each other.

That is, from the relational expressions (1) and (2),
TSE + TW1 + TSM = TSL + TW2 + TSL (3)
It becomes.

  In the chip C1, a signal generated from the MLCLK signal is selected as LCLK, and in the chip C2, a signal generated from the LIOCLK signal is selected and output as LCLK, so that the LCLK has the same waveform (transition timing etc.) in the chips C1 and C2. Can be the same).

  Next, a configuration for selecting a signal generated from the MLCLK signal in this chip as LCLK and a signal generated from the LIOCLK signal as LCLK will be described with reference to FIG.

  In FIG. 3, description will be made in a state where the DLL is in an active state and the phase of the edge of the output signal MCLK of the output circuit replica circuit DL4 and the cross position of the CLK and CLKB signals are locked.

  In this case, the delay control signal DL2 is adjusted so that the phase of the edge of the output signal MCLK of the output circuit replica circuit DL4 and the cross position of the CLK and CLKB signals are locked as described above. DLT [t: 1] is output to the delay generation circuit DL1. Based on this information, the delay generation circuit DL1 adds a delay to the input signal RCLK so that the phase of the MCLK edge and the cross position of the CLK and CLKB signals are locked. Generate.

  In this locked state, the RLCLK signal is earlier (phase advanced) than MCLK by the delay of the output circuit replica circuit DL4 having the same delay as the output circuit (delay amount is set to “TREP”). Signal.

Here, from the configuration example of the lock clock select circuit shown in FIGS. 3 and 4, the ETCLK signal is delayed from the ELCLK signal (ETCLK to ELCLK via the 2-input NAND circuit J3 and the clock inverter J13 in FIG. The ELCLK signal is input to the lock clock select circuit as the MLCLK signal via the dedicated pad DP, the bonding wire connecting the dedicated pads DP, and the dedicated pad in FIG. . This delay is
TSE + TW1 + TSM
It can be expressed as

  Further, the MLCLK signal is connected to the RLCLK signal through the inverter J0, the clock inverter J10, the two-input NAND circuit J7 and the inverter J8 in FIG.

  The delay from MLCLK to RLCLK in the lock clock select circuit is TMR.

The ETCLK signal becomes the LIOCLK signal (the delay from ETCLK to LIOCLK is “TEL”) via the 2-input NAND circuit J2 and the clock inverter J12 in FIG. 4, and the LIOCLK signal is as described above. Input / output terminal of the DLL circuit (lock clock select circuit) for inputting the LIOCLK signal of the DLL circuit of the chip C2 via the dedicated pad DPIO of the chip C1, the bonding wire connecting the dedicated pads DPIO, and the dedicated pad DPIO of the chip C2. DL3 input / output terminal). This delay is
TSL + TW2 + TSL
It becomes.

Further, the LIOCLK signal is connected to the RLCLK signal through the inverter J1, the clock inverter J11, the input NAND circuit J7 and the inverter J8 in the lock clock select circuit of FIG. The delay from LIOCLK to RLCLK in the lock clock select circuit is assumed to be “TLR”. In the delay value in FIG. 4 described above, since the configuration is the same,
TEE = TEL (4)
TMR = TLR (5)
Holds.

  The delay from the LIOCLK signal to LCLK (referred to as “TLL”) when the OE signal that enables the output is High is equal to the TLR of the delay because the circuit configuration is the same.

That is,
TMR = TLR = TLL (6)

  As described above, the configuration example 2 of the lock clock select circuit DL3 in FIG. 5 is a configuration in which the replica delay element J15 of the wiring, pad, and bonding wire portion is added to the configuration example 1 in FIG. The configuration of FIG. 5 is equivalent to the delay (equivalent to this) by the capacitance and resistance elements in which the ELCLK and MLCLK wirings, the dedicated pads DP, and the bonding wires connecting the dedicated pads DP shown in FIGS. J15 delay is made equal to TSE + TW1 + TSM).

  With such a configuration, there is an advantage that it is not necessary to provide ELCLK and MLCLK wirings, dedicated pads DP, and bonding wires connecting the dedicated pads DP. However, it is necessary to adjust the equivalent delay element in advance based on information on the material of the bonding wire and the length when bonded.

  Based on the above delay relationship, the operation of the configuration example 1 of the lock clock select circuit of FIG. 4 in the chip C1 in which the DLL enable signal DLLEN is set to High in FIG. 2 and is set to supply the flying lock clock LIOCLK. Indicates.

  The clock inverters J11 and J10 have a low level of the DLLEN signal at the high level and the low level of the reverse data of the DLLEN generated by the inverter J4, so that the clock inverters J11 and J10 have EN low at J11 and ENB high, respectively. The LIOCLKB signal of the input signal is not output as SLCLK. In J10, EN becomes High and ENB becomes Low, so that the input signal MLCLKB is output as the reverse data SLCLK signal.

  Since the input DLLEN signal of the two-input NAND circuit J7 is High in the SLCLK signal, the reverse data of the SLCLK signal is output as the RLCLKPB signal, and the reverse data of the RLCLKPB signal is output as the RLCLK signal by the inverter J8.

  Similarly, in the 2-input NAND circuit J5 to which the SLCLK signal is input, when the enable signal OE for enabling the output is High, the reverse data of the SLCLK signal is output as the LCLKPB signal, and the LCLKPB signal is output by the inverter J6. The reverse data is output as the LCLK signal and input as LCLK of the output circuit group in FIG.

  When the OE signal is Low, the output LCLKPB of the 2-input NAND circuit J5 is High, and the output LCLK of the inverter J6 is Low.

  Since the input DLLEN is High, the 2-input NAND circuit J3 outputs the reverse data of ETCLK as the ETCLKEB signal. In the clock inverter J13, EN is High and ENB is Low, so the reverse data of the ETCLKEB signal is ELCLK. Is output and connected to the dedicated pad DP of FIG.

  The inverter J9 connected to ELCLK is provided to apply the same load as the load generated by the inverter J1 connected to LIOCLK.

  The clock inverter J14 does not output the input GND level because EN is Low and ENB is High. This clock inverter J14 is an element provided for equalizing the load of LIOCLK by the clock inverter J12 and the load of MLCLK.

From the above operation, the delay TDLE from the ETCLK signal to the RLCLK signal in FIG. 4 in the chip C1 in which DLLEN is set to High (when OE is High, the delay from the ETCLK signal to LCLK is the same)
The delay (TEE) of the 2-input NAND circuit J3 and the clock inverter J13 in FIG.
A wiring delay (TSE) of the ELCLK signal;
A delay (TW1) of the bonding wire connecting the dedicated pads DP and DP;
MLCLK signal wiring delay (TSM);
Delay from MLCLK to RLCLK (TMR) by inverter J0, clock inverter J10, two-input NAND circuit J7, and inverter J8 including delay due to load of clock inverter J14 in FIG.
TDLE = TEE + TSE + TW1 + TSM + TMR (7)
It can be expressed as.

  When the OE signal is in the High state, the delay until the signal is transmitted from ETCLK to LCLK is the same as the delay until the signal is transmitted from ETCLK to RLCLK.

Therefore, the ETCLK signal in the chip C1 in the locked state is MCLK that is phase-synchronized with the external differential clock signals CLK and CLKB.
TREP + TDLE
The signal becomes faster.

  At the same time, since EN of the clock inverter J12 is High and ENB is Low, the LIOCLK signal is output as a signal having a delay TEL with respect to ETCLK.

  Next, FIG. 2 shows the operation of the configuration example 1 of the lock clock select circuit of FIG. 4 in the chip C2 in which the DLL enable signal DLLEN is set to Low and the flying lock clock is supplied.

  Since DLLEN is Low, the output signal DLLENB signal of the inverter J4 is High, and since the clock inverters J10 and J11 are respectively EN at Low and ENB is High at J10, the MLCLKB signal of the input signal is not output as SLCLK. In J11, EN becomes High and ENB becomes Low, so the input signal LIOCLKB is output as the reverse data SLCLK signal.

  Since the input DLLEN signal of the two-input NAND circuit J7 is Low in the SLCLK signal, the RLCLKPB signal is output as High, and the RLCLK signal output from the inverter J8 is output as Low.

  In the 2-input NAND circuit J5 to which the SLCLK signal is input, the reverse data of the SLCLK signal is output as the LCLKPB signal when the output enable signal OE for enabling the output is High, and the inverter J6 reverses the LCLKPB signal. Data is output as the LCLK signal and input as LCLK of the output circuit group in FIG.

  When the OE signal is Low, the output LCLKPB of the 2-input NAND circuit J5 is High, and the output LCLK of the inverter J6 is Low.

  In the 2-input NAND circuit J3, since the input DLLEN is Low, the output ETCLKEB is High, and the output of the clock inverter J13 is ELCLK Low.

  Since the ELCLK signal is input to the lock clock select circuit of FIG. 4 as MLCLK via the bonding wire connected to the dedicated pad DP, it is similarly at the Low level.

  In the 2-input NAND circuit J2, since the input DLLEN signal is Low, the output ETCLKLB is High.

  In the clock inverter J12 to which the ETCLKLB signal is input, since EN is Low and ENB is High, input data is not output, and the LIOCLK signal as an output signal is in a high impedance state.

  Here, the LIOCLK signal of the chip C1 in which DLLEN is set to High is in an output state, and the LIOCLK signal is passed through a bonding wire that connects the dedicated pad DPIO of the chip C1 and the dedicated pad DPIO of the chip C2. Since it is connected to the LIOCLK of the chip C2, the LIOCLK in the chip C2 is driven by the LIOCLK of the chip C1.

In this state, the delay TDLD from the ETCLK of the chip C1 to the LCLK of the chip C2 is
The delay (TEL) of the 2-input NAND circuit J2 and the clock inverter J12 in FIG.
LIOCLK signal wiring delay (TSL), delay due to bonding wire connecting dedicated pad DPIO of chip C1 and dedicated pad DPIO of chip C2 and dedicated pad (TW2),
Wiring delay (TSL) of the LIOCLK signal of the chip C2,
Delay from the LIOCLK to the LCLK by the inverter J1, the clock inverter J11, the input NAND circuit J5, and the inverter J6 including the delay due to the load of the clock inverter J12 in FIG. 4 in the chip C2 (TLL)
TDLD = TEL + TSL + TW2 + TSL + TLL (8)
It can be expressed as.

Here, the delay of TDLE (Equation (7)) and TDLD (Equation (8)) is expressed as TEE = TEL,
TSE = TSL,
TW1 = TW2,
TSM = TSL,
TMR = TLL
Than,
TDLE = TDLD (9)
And it can be seen that they are equal to each other.

  FIG. 6 is a timing diagram showing the timing relationship in the present embodiment.

  In the timing diagram of FIG. 6, the flying lock clock is supplied to another chip via a pad by a signal obtained from an initial setting by an external command such as a mode register set or a separately provided bonding option PAD. It is set (DLLEN = High), and the chip C2 shows a case where it is set to take in the flying lock clock from the outside (DLLEN = Low).

  Moreover, the case where the OE signal for enabling the output is in a high state is shown.

  From the timing diagram of FIG. 6 and the above description, the data output timing in the chip C2 supplied with the flying lock clock from the chip C1 is the same as that of the chip C1.

  Since the operation of the DLL circuit in this state of the chip C2 operates only a part of the lock clock select circuit DL3 of FIG. 3, the current consumption of the DLL circuit of the chip C2 can be greatly reduced.

  In the first embodiment, since the chips C1 and C2 have the same bonding connection relationship, the DLL states of the chip C1 and the chip C2 can be interchanged.

  In the conventional configuration, all the DLL circuits mounted on each semiconductor memory device are operating. The same applies to the laminated module.

  On the other hand, in this embodiment, in the stacked or multi-chip module, by utilizing the fact that adjacent semiconductor memory devices are close, only the DLL of any one of the semiconductor memory devices is between the adjacent semiconductor memory devices. And the number of active DLLs can be reduced relative to the number of mounted semiconductor memory devices by supplying a flying lock clock generated from a locked DLL circuit to a nearby chip. Can be reduced.

  FIG. 7 is a diagram showing the configuration of the second exemplary embodiment of the present invention. FIG. 7 shows n chips C1 to Cn (n is 2) of a semiconductor memory device having dedicated input / output pads for clock signal CLK synchronized with external CLK and CLKB generated from clock signal CLK locked by DLL. The above-mentioned connection configuration and the connection configuration from DLL to output are shown.

  The internal configuration of each chip is made up of CLKEN, CLKB, DLL activation signals DLLEN that are input from the outside, and signals that are phase-synchronized with OE, CLK, and CLKB signals for enabling output. LCLK, LOCLK1 to LOCLKn (flying lock clocks LOCLK1 to LOCLKn are also referred to as “LOCLK signal group”), and DLL circuits DL and DLL circuits having LICLK signals to which signals generated from DLL lock clocks are input from other chips The LCLK signal that is the output CLK of the output circuit, which is made from the signal that is phase-synchronized with CLK and CLKB, the OE signal that enables the output, and the PD that is the data signal to be output are input, and the output signal is the DQ-pad Output circuit group DO connected to PQ, output DQ-pad group PQ to which the signal output from the path group DO is connected, the LOCLK signal group of the flying lock clock output from the DLL circuit DL, and the flying lock clock connected to the LICLK signal input to the DLL circuit An input / output pad group PDL is used.

The chips C1 to Cm-1 and Cm + 1 to Cn MRS are set to be supplied with a flying lock clock by an external command, and the chip Cm is set to another chip by an external command such as MRS. Is set to feed (but
When n = 2, n = m and only the C1 chip is
When n = 3, m = 2,
When n> = 4, m <= n−1).

  In this case, the output dedicated pads LOu (u = 1 to m) of the chip Cm are connected to the input dedicated pads LIN of the chip by bonding wires.

  Here, when u = m, bonding is performed on the same chip.

  FIG. 8 is a diagram showing the configuration of the DLL circuit according to the second embodiment of the present invention and the connection relationship with the pads.

  The difference between FIG. 8 and the configuration shown in FIG. 3 (DLL circuit configuration and pad connection relationship diagram) is that the lock clock selector circuit DL3A in FIG. 8 is replaced with the lock clock selector circuit DL3 in FIG. In FIG. 8, a flying lock clock input / output pad group is provided instead of the dedicated pad group (DP, DPIO) of FIG.

  The following two points (A) and (B) are different as the connection information.

  (A) Flying lock clocks (LOCLK signal group) output from the lock clock selector circuit DL3A are output for the number of chips that want to share the flying lock clock generated from the clock signal locked by the DLL circuit. It is connected to the lock clock input / output pad group LOu.

  (B) In FIG. 3, the ELCLK signal is input as MLCLK to the DLL circuit via the bonding wire connecting the dedicated pads DP. In FIG. 8, the ELCLK signal is set to supply the flying lock clock. On the Cm chip, the LOCLKm signal is input to the DLL as LICLK via a bonding wire connecting the output pad LOm and the input pad LIN.

FIG. 9 is a diagram showing a configuration example of the lock clock select circuit DL3A of FIG. The configuration of FIG.
A two-input NAND circuit R1 having an LICLK signal and an OE signal as inputs and an output of the LCLKSB signal;
An inverter R2 having an LCLKSB signal as an input and an output of the LCLK signal;
A two-input NAND circuit R3 having the LICLK signal and the DLLEN signal as inputs and the output being a RLCLKSB signal;
An inverter R4 having an RLCLKSB signal as an input and an output of the RLCLK signal;
A two-input NAND circuit R5 that receives the DLLEN signal and the ETCLK signal and outputs an ENCLKB signal;
Inverters R6_1 to R6_n that receive the ENCLKB signal and output the LOCLK signal group;
It has.

  Next, the operation of the second embodiment of the present invention will be described. The chip Cm in FIG. 7 is set to supply the flying lock clock to the other chips C1 to Cm-1 and the other chips Cm + 1 to Cn via the PAD and the bonding wire by an external command such as MRS. , DLL becomes active (DLLEN = High state).

  Chips C1 to Cm-1 and Cm + 1 to Cn are set to be supplied with a flying lock clock from the chip Cm via pads and bonding wires, and the DLL becomes inactive (DLLEN = Low state). .

  In this state, when the DLL in the chip Cm is locked, the phase between the edge of MCLK and the cross position of CLK and CLKB which are external input signals is determined from the configuration of the DLL circuit of the chip Cm shown in FIG. It becomes synchronized. For this reason, the RLCLK signal is a signal earlier than MCLK by the delay (TREP) of the output circuit replica circuit DL4A.

In the DLL circuit in the chip Cm, since the DLLEN signal is High, the ETCLK signal input to the lock clock select circuit DL3A is
With respect to RLCLK, the delay of the two-input NAND circuit R5 and the inverter R6_m, which is a delay from the ETCLK signal to LOCLKm in FIG. 9 (the delay amount is “TELm”),
LOCLKm wiring delay (TSLOm) of FIG.
The output pad LOm to which LOCLKm is connected, the bonding wire to which the input pad LIN is connected, the output pad LOm, and the delay due to the load on the input pad LIN (the delay amount is “TBm”),
LICLK signal wiring delay (TSLIm) connected to the input pad LIN,
The sum of the delay of the inverter R4 from the LICLK to the RLCLK in FIG.
The signal becomes faster by the delay of.

  That is, the delay from the input of ETCLK to LCLK (the output of the lock clock select circuit DL3A) in the chip Cm is TDLEm.

  When the OE signal for enabling the output is High, the 2-input NAND circuit R1 from LICLK to LCLK is enabled, so the delay (TLLm) between the 2-input NAND circuit R1 and the inverter R2 is the same as the configuration in the delay of TLR2. Since it is the same, the delay is the same.

    TLLm = TLRm (11)

  That is, the delay from ETCLK to LCLK is also TDLEm.

On the other hand, the chips C1 to Cm-1 and the chips Cu of the chips Cm + 1 to Cn set so as to be supplied with the LOCLK signal of the flying lock clock from the ETCLK signal of the chip Cm (u is 1 to m-1, m + 1 to n). The delay TDLDu to LCLK in (a positive integer) is
The delay (TELu) of the 2-input NAND circuit R5 and the inverter R6_u in the lock clock select circuit of FIG.
A delay (TSLOu) to the flying lock clock input / output pad group PDL to which the LOCLK group is connected;
Delay due to load on the output pad LOu of the flying lock clock input / output pad group, the bonding wire connected to the input pad LIN of the flying lock clock input / output pad group of the chip Cu, the output pad LOu, and the input pad LIN The amount is “TBu”),
LICLK wiring delay (TSLIu) of FIG.
Delay (TLLLu) between the 2-input NAND circuit R1 and the inverter R2 in FIG.
Given by the sum of
TDLDu = TELu + TSLOu + TBu + TSLIu + TLLu (12)
It becomes.

  Here, since TELk (k = 1 to n) has the same configuration, it has the same delay value.

  The LOCLK signal group and the LICLK signal are wired so as to have the same wiring delay, and the delays of TSLOk (k = 1 to n) and TSLIk (k = 1 to n) are made the same.

  The delay of TBk (k = 1 to n) is equalized by bonding so that the delays due to bonding are equal.

  Since TLLk (k = 1 to n), which is the delay between the two-input NAND circuit R1 and the inverter R2 in FIG. Further, as described above, TLLk = TLRk.

From the above
TDLEm = TDLDk
(K = 1 to m-1, m + 1 to n) (13)
Thus, the timing of the LCLK signal in each chip can be made the same.

  In this embodiment, the DLL circuit is active in n chips in one chip. In this chip, the flying lock clock generated from the lock clock is supplied to other chips, so the power consumption increases. To do.

  On the other hand, since the DLL circuits of other chips are inactive, the power consumption of the DLL circuit can be greatly reduced because only a part of the lock clock select circuit is operating.

In the increase and decrease of power consumption,
Since the increase <reduction can be easily estimated from the ratio of the operation circuit, the configuration of this embodiment can greatly reduce the current consumption of the DLL in the entire module.

  In the second embodiment, since the bonding configuration is different from that of the first embodiment, the chip that supplies the flying lock clock after the bonding cannot be replaced.

  The present invention can be applied to a semiconductor device such as a DRAM (Dynamic RAM) and an SRAM (Static RAM) provided with a DLL.

  Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the configurations of the above-described embodiments, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, including modifications.

It is a figure which shows the bonding state at the time of two-chip lamination | stacking in the 1st Example of this invention. It is a figure which shows the connection structure of the semiconductor memory device of 1st Example of this invention, and a dedicated pad. It is a figure which shows the connection relation of the structure of the DLL circuit of 1st Example of this invention, and a dedicated pad. 1 is a diagram illustrating a configuration example of a lock clock select circuit according to a first exemplary embodiment of the present invention. FIG. It is a figure which shows another example of a structure of the lock clock select circuit of the 1st Example of this invention. It is a timing diagram which shows operation | movement of the 1st Example of this invention. It is a figure which shows the connection structure of the semiconductor memory device of 2nd Example of this invention, and a dedicated pad. It is a figure which shows the connection relation of the structure of the DLL circuit of 2nd Example of this invention, and a dedicated pad. It is a figure which shows the structural example of the lock clock select circuit of the 2nd Example of this invention.

Explanation of symbols

B1 Bonding pad (PAD)
C1, C2, Cm, Cn Chip DL DLL circuit DL0, DL0A Clock first stage circuit (CLK first stage circuit)
DL1, DL1A Delay generation circuit DL2, DL2A Delay control circuit DL3, DL3A Lock clock select circuit (lock CLK select circuit)
DL4, DL4A Output circuit replica circuit DL5, DL5A Phase determination circuit DO Output circuit group DP dedicated pad DPIO dedicated pad J0, J1, J4, J6, J8, J9 Inverter J2, J3, J5, J7 2-input NAND circuit J10-J14 clock Inverter J15 Replica delay element K0 ELCLK equivalent delay element K1 pad equivalent delay element K2 bonding wire equivalent delay element K3 pad equivalent delay element K4 MLCLK wiring equivalent delay element LIN input pad LO1-LOn output pad PQ output pad group (DQ-PAD group)
Q11-Q15, Q21-Q25 PchMOS transistors Q31-Q35, Q41-Q45 NchMOS transistors R1, R3, R5 2-input NAND circuit R2, R4, R6 Inverter circuit

Claims (19)

A lock signal (LCLK) that is delay-synchronized with an external clock signal is output to an internal circuit of its own semiconductor memory device, and a delay value corresponding to delay information provided in a connection signal line connecting the semiconductor memory devices is obtained as the lock signal ( A DLL (delay locked loop) circuit that outputs a signal (referred to as a “flying lock clock signal”) (LIOCLK) that is delayed and synchronized with an external clock signal that is a clock signal earlier than (LCLK) to another semiconductor memory device;
A lock clock select circuit that selects one of the internal signal (MLCLK) of the DLL circuit and the flying lock clock signal (LIOCLK) input from another semiconductor memory device, and outputs the lock signal (LCLK);
With
The lock clock select circuit is
In the first state in which the DLL circuit is controlled to be active, the internal signal (MLCLK) is selected, and another semiconductor memory device in the second state in which the DLL circuit is mounted and the DLL circuit is controlled to be inactive Supplying the flying lock clock signal to the lock clock select circuit of
In the second state in which the DLL circuit is controlled to be inactive, the flying lock clock signal supplied from another semiconductor memory device in the first state in which the DLL circuit is mounted and the DLL circuit is controlled to be active is selected Then, the semiconductor memory device is characterized in that the lock signal (LCLK) is generated from the flying lock clock signal (LIOCLK). A lock signal (LCLK) that is delay-synchronized with an external clock signal is output to an internal circuit of its own semiconductor memory device, and a delay value corresponding to delay information provided in a connection signal line connecting the semiconductor memory devices is obtained as the lock signal ( A DLL (delay locked loop) circuit that outputs a signal (referred to as a “flying lock clock signal”) (LIOCLK) that is delayed and synchronized with an external clock signal that is a clock signal earlier than (LCLK) to another semiconductor memory device;
A lock clock select circuit that selects one of the internal signal (MLCLK) of the DLL circuit and the flying lock clock signal (LIOCLK) input from another semiconductor memory device, and outputs the lock signal (LCLK);
Comprising first and second semiconductor memory devices each comprising:
The first semiconductor memory device supplies its own flying lock clock signal (LIOCLK) to the lock clock select circuit of the second semiconductor memory device,
The second semiconductor memory device deactivates the DLL circuit of the second semiconductor memory device, and the lock clock select circuit of the second semiconductor memory device receives the flying lock clock supplied from the first semiconductor memory device. A semiconductor memory device, wherein a signal (LIOCLK) is selected and the lock signal (LCLK) is generated from the flying lock clock signal (LIOCLK). A lock signal (LCLK) that is delay-synchronized with an external clock signal is output to an internal circuit of its own semiconductor memory device, and a delay value corresponding to delay information provided in a connection signal line connecting the semiconductor memory devices is obtained as the lock signal ( A DLL (delay locked loop) circuit that outputs a signal (referred to as a “flying lock clock signal”) (LIOCLK) that is delayed and synchronized with an external clock signal that is a clock signal earlier than (LCLK) to another semiconductor memory device;
A lock clock select circuit that selects one of the internal signal (MLCLK) of the DLL circuit and the flying lock clock signal (LIOCLK) input from another semiconductor memory device, and outputs the lock signal (LCLK);
A pad for supplying the flying lock clock signal to at least one other semiconductor memory device or inputting a flying lock clock signal supplied from a DLL circuit of the other semiconductor memory device;
With
The lock clock select circuit of the own semiconductor memory device in which the DLL circuit is controlled to be inactive is a flying lock clock signal input to the pad from another semiconductor memory device in which the DLL circuit is controlled to be active. And generating the lock signal (LCLK) from the flying lock clock signal.   4. The semiconductor memory device according to claim 1, wherein the deactivation of the DLL circuit deactivates a delay locked loop in the DLL circuit by a DLL control signal.   The flying lock clock signal is supplied to the other semiconductor memory device through the pad of the other semiconductor memory device connected to the pad by a bonding wire, or the pad of the other semiconductor memory device 4. The semiconductor device according to claim 3, wherein the state in which the flying lock clock signal is supplied from another semiconductor memory device through a pad connected by a bonding wire is selectable. Storage device.   The delay information by connection through the pad connecting the other semiconductor memory device is acquired in a replica configuration using a resistor and a capacitor, and is advanced by the delay with respect to the lock signal (LCLK). 4. The semiconductor memory device according to claim 1, wherein a clock signal is supplied to the other semiconductor memory device as the flying lock clock signal. The DLL circuit
From the DLL circuit, another clock signal (ELCLK) that is delayed and synchronized with an external clock signal that is a clock signal that is earlier than the lock signal (LCLK) by a delay value corresponding to the delay information is output from one pad. Input to the first terminal (MLCLK) for input of the DLL circuit through another pad connected by a bonding wire,
From the second input / output terminal (LIOCLK) of the DLL circuit, a flying lock clock signal supplied from the other semiconductor memory device is input from the pad via a wiring or generated by the DLL circuit The flying lock clock signal delayed and synchronized with the external clock signal is output to the pad via the wiring,
Input a DLL control signal for controlling the activation of the DLL,
When the DLL control signal is activated, a clock signal input to the first terminal is selected and output as a lock signal (LCLK) from the DLL circuit, and from the second terminal of the DLL circuit, A flying lock clock signal that is delay-synchronized with an external clock signal is output to the pad,
When the DLL control signal is inactivated, the output of the second terminal is set to a high impedance state, the flying lock clock signal input to the second terminal is selected, and the lock signal (LCLK from the DLL circuit is selected). The semiconductor memory device according to claim 3, further comprising: the lock clock select circuit that outputs the data as a signal. Another clock signal (ELCLK) delayed and synchronized with the external clock signal is output from the DLL circuit, reaches one pad via a wiring, and passes through another pad and wiring connected from the one pad by a bonding wire. A delay time until it is input to the first terminal (MLCLK) of the DLL circuit,
A flying lock clock signal that is output from the second terminal (LIOCLK) of the DLL circuit and that is delayed and synchronized with the external clock signal reaches the pad of the other semiconductor device via the wiring, the pad, and the bonding wire. 8. The semiconductor memory device according to claim 7, wherein a delay time until reaching the second terminal (LIOCLK) of the other semiconductor device is set to be equal to each other. . In the lock clock select circuit,
The basic signal (ETCLK), which is the output of the delay generation circuit that varies the delay of the external clock signal that is delay-synchronized with the external clock signal, is input to the lock clock select circuit, and then the lock signal (LCLK) of the DLL circuit is output. The delay time until
After the basic signal (ETCLK), which is the output of the delay generation circuit that varies the delay of the external clock signal synchronized with the external clock signal, is input to the lock clock select circuit, the DLL control signal is in an inactive state. 9. The semiconductor memory device according to claim 7, wherein the semiconductor memory device is set to be equal to a delay time until a lock signal (LCLK) of a DLL circuit of the other semiconductor device is output.   Until the other clock signal (ELCLK) is output from the DLL circuit and input from one pad to the first terminal (MLCLK) for input of the DLL circuit through another pad connected by a bonding wire 8. The semiconductor memory device according to claim 7, further comprising a replica delay element of a wiring, a pad, and a bonding wire portion. In the lock clock select circuit,
The basic signal (ETCLK), which is the output of the delay generation circuit that varies the delay of the external clock signal that is delay-synchronized with the external clock signal, is input to the lock clock select circuit, and then corresponds to the activated DLL control signal. The delay time until the lock signal (LCLK) of the DLL circuit is output is
After the basic signal (ETCLK) that is the output of the delay generation circuit that varies the delay of the external clock signal that is delay-synchronized with the external clock signal is input to the lock clock select circuit,
8. The semiconductor according to claim 7, wherein the DLL control signal is set to be equal to a delay until the lock signal (LCLK) of the DLL circuit of the other semiconductor device in the inactive state is output. Storage device. The DLL circuit receives an output signal of the lock clock select circuit directly or via a replica circuit of the output circuit, and detects a phase with an external clock signal;
A delay control circuit that receives the output of the phase determination circuit and generates a signal for controlling a delay time;
4. The semiconductor memory device according to claim 1, further comprising: a delay generation circuit that varies a delay of the external clock signal in accordance with a signal of the delay control circuit. 5. In each of the semiconductor devices having a multi-chip module configuration having a plurality of stacked modules or semiconductor memory devices of a semiconductor memory device each having a DLL (delay locked loop) circuit that delay-synchronizes a clock signal,
The DLL circuit of each of the semiconductor memory devices is
As a DLL circuit output signal, a lock signal (LCLK) delayed and synchronized with an external clock signal is output to an internal circuit of its own semiconductor memory device, and a delay corresponding to delay information provided in a connection signal line connecting the semiconductor memory devices A signal (hereinafter referred to as “flying lock clock signal”) (LIOCLK) that is delayed and synchronized with an external clock signal, which is a clock signal that is earlier than the lock signal (LCLK), is output to another semiconductor memory device;
Further, each of the semiconductor memory devices selects either the internal signal (MLCLK) of the DLL circuit of its own semiconductor memory device or the flying lock clock signal (LIOCLK) input from the other semiconductor memory device. A lock clock select circuit for outputting the lock signal (LCLK) as an output signal of a DLL circuit to an internal circuit of its own semiconductor memory device;
One semiconductor memory device in which a DLL circuit among the plurality of semiconductor memory devices is activated has the flying lock clock signal generated from the DLL circuit as at least one other semiconductor in which the DLL circuit is inactivated. While supplying to the memory device, the lock clock select circuit selects the internal signal (MLCLK) of its own DLL circuit as the lock signal (LCLK),
The lock clock select circuit of at least one other semiconductor memory device in which the DLL circuit is deactivated receives the flying lock clock signal supplied from one semiconductor memory device in which the DLL circuit is activated as the lock signal ( LCLK) ,
A semiconductor device characterized in that the number of active DLL circuits can be reduced with respect to the number of mounted semiconductor memory devices, and current consumption can be reduced as a whole module. In a semiconductor device having a multichip module configuration, each of which includes a plurality of stacked modules or semiconductor memory devices of a semiconductor memory device provided with a DLL (delay locked loop) circuit,
The DLL circuit of each semiconductor memory device outputs a lock signal (LCLK) delayed and synchronized with an external clock signal as an output signal of the DLL circuit to an internal circuit of its own semiconductor memory device, and connects the semiconductor memory devices. A signal (referred to as a “flying lock clock signal”) (LIOCLK) in which a delay value corresponding to delay information included in the connection signal line to be synchronized with an external clock signal which is a clock signal earlier than the lock signal (LCLK) is obtained. Output to other semiconductor memory devices,
Further, each of the semiconductor memory devices selects either the internal signal (MLCLK) of the DLL circuit of its own semiconductor memory device or the flying lock clock signal (LIOCLK) input from the other semiconductor memory device. A lock clock select circuit for outputting the lock signal (LCLK) as an output signal of a DLL circuit to an internal circuit of its own semiconductor memory device;
A pad dedicated to the DLL circuit for sharing the flying lock clock signal between one semiconductor memory device and another semiconductor memory device;
Selectively activating a DLL circuit of one semiconductor memory device;
In other semiconductor memory devices, the DLL circuit is selectively deactivated,
The flying lock clock signal generated by the DLL circuit is output from the pad of the one semiconductor memory device,
In the other semiconductor memory device, the flying lock clock signal is input from the pad,
The lock clock select circuit of the other semiconductor memory device selects the inputted flying lock clock signal and supplies it to the other semiconductor memory device as the lock signal (LCLK). . The DLL circuit outputs, from the DLL circuit, another clock signal (ELCLK) that is delayed and synchronized with an external clock signal that is a clock signal that is earlier than the lock signal (LCLK) by a delay value corresponding to the delay information. Then, input from one pad to the first terminal (MLCLK) for input of the DLL circuit through another pad connected by a bonding wire,
From the second input / output terminal (LIOCLK) of the DLL circuit, a flying lock clock signal supplied from the other semiconductor memory device is input from the pad via a wiring or generated by the DLL circuit The flying lock clock signal delayed and synchronized with the external clock signal is output to the pad via the wiring,
Input a DLL control signal for controlling the activation of the DLL,
When the DLL control signal is activated, a clock signal input to the first terminal is selected and output as a lock signal (LCLK) from the DLL circuit, and from the second terminal of the DLL circuit, A flying lock clock signal that is delay-synchronized with an external clock signal is output to the pad,
When the DLL control signal is inactivated, the output of the second terminal is set to a high impedance state, the flying lock clock signal input to the second terminal is selected, and the lock signal (LCLK from the DLL circuit is selected). The semiconductor device according to claim 14, further comprising: the lock clock select circuit that outputs the data as a signal. Another clock signal (ELCLK) delayed and synchronized with the external clock signal is output from the DLL circuit, reaches one pad via a wiring, and passes through another pad and wiring connected from the one pad by a bonding wire. A delay time until it is input to the first terminal (MLCLK) of the DLL circuit,
A flying lock clock signal that is output from the second terminal (LIOCLK) of the DLL circuit and that is delayed and synchronized with the external clock signal reaches the pad of the other semiconductor device via the wiring, the pad, and the bonding wire. 16. The semiconductor device according to claim 15, wherein a delay time until reaching the second terminal (LIOCLK) of the other semiconductor device is set to be equal to each other. In the lock clock select circuit of the DLL circuit,
The basic signal (ETCLK), which is the output of the delay generation circuit that varies the delay of the external clock signal that is delay-synchronized with the external clock signal, is input to the lock clock select circuit, and then the lock signal (LCLK) of the DLL circuit is output. The delay time until
After the basic signal (ETCLK), which is the output of the delay generation circuit that varies the delay of the external clock signal that is delay-synchronized with the external clock signal, is input to the lock clock select circuit, the other DLL control signal is inactive. 17. The semiconductor device according to claim 16, wherein the delay time until the lock signal (LCLK) of the DLL circuit of the semiconductor device is output is set to be equal.   Until the other clock signal (ELCLK) is output from the DLL circuit and input from one pad to the first terminal (MLCLK) for input of the DLL circuit through another pad connected by a bonding wire 16. The semiconductor device according to claim 15, further comprising a replica delay element of a wiring, a pad, and a bonding wire portion. In the lock clock select circuit of the DLL circuit,
The basic signal (ETCLK), which is the output of the delay generation circuit that varies the delay of the external clock signal that is delay-synchronized with the external clock signal, is input to the lock clock select circuit, and then corresponds to the activated DLL control signal. The delay time until the lock signal (LCLK) of the DLL circuit is output is
After the basic signal (ETCLK), which is the output of the delay generation circuit that varies the delay of the external clock signal that is delay-synchronized with the external clock signal, is input to the lock clock select circuit, the DLL control signal is in an inactive state. 16. The semiconductor device according to claim 15, wherein the semiconductor device is set to be equal to a delay until a lock signal (LCLK) of a DLL circuit of another semiconductor device is output.

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