TW201515547A - Semiconductor device - Google Patents

Abstract

[Problem] To provide a highly noise-resistant high-precision duty regulator circuit. [Solution] A semiconductor device comprises a plurality of clocked inverters (CV1, CV2, CV4, CV8) which are inserted into a clock signal propagation path and are mutually connected in parallel. Pull-up circuits (UP) of the clocked inverters (CV1, CV2, CV4, CV8) are respectively controlled in isolation by control signals (P11, P12, P14, P18) which are generated on the basis of a clock signal duty ratio. Pull-down circuits (DN) of the clocked inverters (CV1, CV2, CV4, CV8) are respectively controlled in isolation by control signals (N11, N12, N14, N18) which are generated on the basis of the clock signal duty ratio. With the present invention, it is possible to change the duty ratio of a transiting clock signal without making fine adjustments to the bias level, as the plurality of clocked inverters which are controlled in isolation from one another are connected in parallel.

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an energy ratio adjusting circuit that adjusts an energy ratio of a clock signal.

A typical DRAM (Dynamic Random Access Memory) of a semiconductor memory device is a DDR (Double Data Rate) type. The DDR type DRAM is required to correctly input the energy ratio of the clock signal to 50% from the rising edge and the falling edge of the clock signal. Therefore, the energy adjustment circuit is used. Many (refer to Patent Document 1).

There are various forms of circuits known for the energy rate adjustment circuit. For example, it is known that the switching rate of the clock signal is changed when the bias level of the transistor is finely adjusted, whereby the energy ratio of the clock signal is used as a variable rate adjustment circuit.

[Previous Technical Literature] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2008-210436

However, in the energy rate adjustment circuit in the form of micro-adjusting the bias level of the transistor, it is necessary to generate a multi-stage bias level with high accuracy, and the circuit configuration becomes complicated. Further, when the bias level is slightly changed by noise or the like, the energy ratio of the clock signal is greatly changed, and it is difficult to obtain high stability.

A semiconductor device according to one aspect of the present invention is characterized by comprising: an energy rate detecting circuit that generates a plurality of control signals by detecting an energy ratio of a clock signal, and a transmission channel inserted into the clock signal, which are connected in parallel with each other The plurality of first clocked inverters are independently controlled by the plurality of first clocked inverters via the plurality of control signals.

A semiconductor device according to another aspect of the present invention includes: a first signal node and a second signal node; and includes each input node, an output node, and a step of pulling up the output node according to a level of the input node a rising circuit, and a first clocked inverter that pulls down a plurality of first pull-down circuits of the output node according to a level of the input node, and the input node of the plurality of first clocked inverters is applied Commonly connected to the first signal node, wherein the output nodes of the plurality of first clocked inverters are connected in common to the second signal node, and the first rise of the plurality of first clocked inverters The circuit is selectively activated by any one of the plurality of first control signals, and the first pull-down circuit of the plurality of first clocked inverters is via any one of the plurality of second control signals And each is selectively activated.

According to the present invention, in the case of a plurality of clocked inverters that are independently controlled in parallel, it is possible to change the energy ratio of the clock signal that passes through without using the bias potential.

10‧‧‧Semiconductor device

11‧‧‧Memory cell array

12‧‧‧ line decoder

13‧‧‧ column decoder

14‧‧‧Sensor circuit

15‧‧‧Amplification circuit

20‧‧‧Access control circuit

21~24‧‧‧External terminals

25‧‧‧ clock receiver

30‧‧‧ Data input and output circuit

30a‧‧‧Output circuit

31‧‧‧data terminal

32‧‧‧ Data strobe terminal

40‧‧‧Power circuit

41, 42‧‧‧ power terminals

100‧‧‧DLL circuit

110‧‧‧delay line

111‧‧‧ coarse adjustment delay line

112‧‧‧ fine adjustment delay line

113‧‧‧ buffer

114‧‧‧clock tree

120‧‧‧Reproduction circuit

130‧‧‧ phase decision circuit

140‧‧‧delay line control circuit

150, 150A, 150B, 150C‧‧‧ energy rate adjustment circuit

151~154‧‧‧Energy Rate Adjustment Department

155‧‧‧Synthesis circuit

160‧‧‧Energy rate detection circuit

170‧‧‧DCC control circuit

171, 172‧‧‧ decoder

173‧‧‧Logical Circuit

181‧‧‧ Fuze circuit

182‧‧‧Test mode circuit

183‧‧‧Selector

A, B‧‧‧ transmission path

BL‧‧‧ bit line

CV1, CV2, CV4, CV8, CV2F, CV4F‧‧‧ clock inverter

DN‧‧‧ pull-down circuit

IVA1~IVA4, IVB1~IVB4‧‧‧ inverter circuit

MC‧‧‧ memory unit

MN11, MN11a, MN11b, MN12‧‧‧N-channel MOS transistor

MP11, MP11a, MP11b, MP12‧‧‧P channel MOS transistor

N1‧‧‧ input node

N2‧‧‧ output node

SA‧‧‧Sense Amplifier

SL, VL‧‧‧ power wiring

TG1~TG4‧‧‧Transmission gate pair

TGA1~TGA4, TGB1-TGB4‧‧‧ transmission gate pair

UP‧‧‧ rising circuit

WL‧‧‧ character line

figure 1

A block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention is shown.

figure 2

A block diagram showing the composition of the DLL circuit 100 is shown.

image 3

A block diagram showing the configuration of the energy rate adjustment circuit 150.

Figure 4

The circuit diagram of the energy rate adjustment unit 151.

Figure 5

A circuit diagram of the clocked inverter CV1 via the modification.

Figure 6

A block diagram of the circuit for generating the fuze signals FP, FN is shown.

Figure 7

A circuit diagram of the synthesizing circuit 155.

Figure 8

A block diagram showing the configuration of the DCC control circuit 170 is schematically shown.

Figure 9

In order to explain the relationship between the values of the bits b6 to b2 of the energy detection signal D1 and the driving ability, it is shown that the energy ratio is less than 50%.

Figure 10

In order to explain the relationship between the values of the bits b6 to b2 of the energy detection signal D1 and the driving ability, it is shown that the energy ratio exceeds 50%.

Figure 11

In order to explain the mode map of the adjustment amount by the energy rate adjustment units 151 to 154, the case where the energy ratio is less than 50% is displayed.

Figure 12

A waveform diagram showing the change in the energy ratio of the internal clock signal in the case where the energy ratio is less than 50%.

Figure 13

In order to explain the pattern of the adjustment amount by the energy rate adjustment units 151 to 154, the case where the energy ratio exceeds 50% is displayed.

Figure 14

A waveform diagram showing the change in the energy ratio of the internal clock signal in the case where the energy ratio exceeds 50%.

Figure 15

In order to explain the waveform diagram of the operation of the synthesizing circuit 155, (a) shows a waveform in which the energy ratio is less than 50%, and (b) shows a waveform in which the energy ratio exceeds 50%.

Figure 16

A block diagram showing the configuration of the energy ratio adjusting circuit 150A according to the first modification is shown.

Figure 17

A block diagram showing the configuration of the energy ratio adjusting circuit 150B according to the second modification is shown.

Figure 18

A block diagram showing the configuration of the energy ratio adjusting circuit 150C according to the third modification is shown.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to additional drawings.

Fig. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

The semiconductor device 10 DRAM according to the present embodiment includes a memory cell array 11 as shown in FIG. 1 . For the memory cell array 11, a plurality of word lines WL and WL which are mutually crossed are provided. The bit line BL of the number is arranged with the memory cell MC at the intersections. The selection of the word line WL is performed via the row decoder 12, and the selection of the bit line BL is performed via the column decoder 13. The bit lines BL are each connected to a corresponding sense amplifier SA in the sensing circuit 14, and the bit line BL selected by the column decoder 13 is connected to the amplifying circuit 15 by a sense amplifier SA.

The operations of the row decoder 12, the column decoder 13, the sensing circuit 14, and the amplifying circuit 15 are controlled via the access control circuit 20. The access control circuit 20 is supplied with an address signal ADD, a command signal CMD, an external clock signal CK, CKB, and the like via the external terminals 21 to 24. The external clock signals CK and CKB are mutually complementary signals. The access control circuit 20 controls the row decoder 12, the column decoder 13, the sensing circuit 14, the amplifying circuit 15, and the data input/output circuit 30 in accordance with the signals.

Specifically, the display command signal CMD is an active command, and the address signal ADD is supplied to the row decoder 12. In response to this, the row decoder 12 selects the word line WL displayed by the address signal ADD, whereby the corresponding memory cells MC are connected to the bit line BL. Thereafter, the access control circuit 20 activates the sensing circuit 14 at a specific time.

On the other hand, when the display command signal CMD is a read command or a write command, the address signal ADD is supplied to the column decoder 13. In response to this, the column decoder 13 connects the bit line BL displayed by the address signal ADD to the amplifying circuit 15. Through this, in the reading action At this time, the read data DQ read from the memory cell array 11 by the sense amplifier SA is output from the data terminal 31 to the outside through the amplifier circuit 15 and the data input/output circuit 30. Further, at the time of the write operation, the write data DQ supplied from the outside by the data terminal 31 and the data input/output circuit 30 is written to the memory cell MC by the amplifier circuit 15 and the sense amplifier SA. .

As shown in FIG. 1, the DLL circuit 100 is included in the access control circuit 20. The DLL circuit 100 receives the external clock signals CK, CKB, and generates a phase-controlled internal clock signal LCLK based on these. The DLL circuit 100 includes a delay line (DL) 110 that delays the internal clock signal LCLK, and an energy adjustment circuit (DCC) 150 that adjusts the energy ratio of the internal clock signal LCLK to 50%. The details of the DLL circuit 100 will be described later. The internal clock signal LCLK is supplied to the output circuit 30a included in the data input/output circuit 30. Thereby, the read data DQ and the data strobe signal DQS are output from the data terminal 31 and the data strobe terminal 32 in synchronization with the internal clock signal LCLK.

Each of these circuit components uses a specific internal voltage as an operating power source. These internal power sources are generated via the power supply circuit 40 shown in FIG. The power supply circuit 40 receives the external potential VDD and the ground potential VSS supplied from the power supply terminals 41 and 42, and generates internal voltages VPP, VPERI, VARY, and the like. The internal potential VPP is generated by boosting the external potential VDD, and the internal potentials VPERI, VARY are generated by stepping down the external potential VDD. to make.

The internal voltage VPP is a voltage mainly used in the row decoder 12. The row decoder 12 drives the word line WL selected in accordance with the address signal ADD to the VPP level, thereby turning on the cell transistor included in the memory cell MC. The internal voltage VARY is the voltage mainly used in the sensing circuit 14. When the sensing circuit 14 is activated, the read data is amplified by driving one of the bit line pairs to the VARY level and the other to the VSS level. The internal voltage VPERI is used as an operating voltage of a peripheral circuit that is mostly accessed by the control circuit 20 or the like. As the operating voltage of the peripheral circuits, when the internal voltage VPERI having a lower voltage than the external voltage VDD is used, the semiconductor device 10 is reduced in power consumption. FIG. 2 is a block diagram showing the configuration of the DLL circuit 100.

The DLL circuit 100 shown in FIG. 2 includes a delay line 110 that generates an internal clock signal LCLK when the internal clock signal PCLK1 is delayed. The internal clock signal PCLK1 passes through the signal of the energy rate adjustment circuit 150 from the internal clock signal PCLK0 output from the clock receiver 25 that receives the external clock signal CK, CKB. The delay line 110 has a configuration in which the adjustment pitch of the serial connection delay amount is a coarse adjustment delay line (CDL) 111 and a fine adjustment delay line (FDL) 112 in which the adjustment pitch of the delay amount is fine. The internal clock signal LCLK outputted from the delay line 110 is supplied to the output circuit 30a by the buffer 113 and the pulse tree 114, and as described above, as the output time of the predetermined read data DQ or the data strobe signal DQS. The time signal is used.

The internal clock signal LCLK is also supplied to the replica circuit 120. The replica circuit 120 has a circuit having substantially the same delay time as the circuit group formed by the buffer 113, the clock tree 114, and the output circuit 30a, and receives the internal clock signal LCLK to output the replica clock signal RCLK. Here, the output circuit 30a is configured to output the read data DQ or the data strobe signal DQS in synchronization with the internal clock signal LCLK, and the copy clock signal RCLK output from the replica circuit 120 and the read data DQ or The data strobe signal DQS is correctly synchronized. In the DRAM, the read data DQ or the data strobe signal DQS is necessary for the external clock signals CK, CKB to be correctly synchronized, and it is necessary to detect the offset between the two phases. And make corrections. The detection is performed by the phase determination circuit 130, and the determination result is output as the phase determination signal PD.

The phase determination signal PD is supplied to the delay line control circuit 140. The delay line control circuit 140 is a circuit that controls the delay amount of the delay line 110 in accordance with the phase determination signal PD. Specifically, the phase determination signal PD indicates that the phase of the replica clock signal RCLK is slower than the internal clock signal PCLK0, and the delay line control circuit 140 reduces the delay amount of the delay line 110. Conversely, the phase determination signal PD indicates that the phase of the replica clock signal RCLK is higher than the internal clock signal PCLK0, and the delay line control circuit 140 increases the delay amount of the delay line 110. Through such an operation, the phase of the replica clock signal RCLK is adjusted in accordance with the internal clock signal PCLK0, and the delay amount of the delay line 110 is adjusted. Copy the phase of the clock signal RCLK with the internal clock signal When PCLK0 coincides, the read data DQ or the data strobe signal DQS is correctly synchronized with respect to the external clock signals CK, CKB.

As shown in FIG. 2, the DLL circuit 100 includes an energy rate adjustment circuit 150 that adjusts the energy ratio. Although not particularly limited, in the present embodiment, the energy ratio adjusting circuit 150 is inserted before the delay line 110, and the energy rate ratio of the internal clock signal PCLK0 output from the clock receiver 25 is adjusted to generate an energy ratio ratio. Internal clock signal PCLK1. In the present invention, the insertion position of the energy rate adjustment circuit 150 is not limited thereto, and may be any place as long as it is inserted into the transmission channel of the internal clock signal, for example, it may be inserted after the delay line 110.

The energy ratio of the internal clock signal LCLK is detected via the energy detection circuit (DCD) 160. The detection position of the internal clock signal LCLK via the energy rate detecting circuit 160 is preferably closer than the output circuit 30a. In the present embodiment, the energy ratio of the internal clock signal LCLK passing through the clock tree 114 is detected. However, the present invention is not limited to this, and as shown by a broken line in FIG. 2, the energy ratio of the internal clock signal LCLK before passing through the clock tree 114 may be detected.

The energy rate detection signal D1 detected by the energy rate detecting circuit 160 is supplied to the DCC control circuit 170. As will be described later, the energy rate detection signal D1 is a binary signal formed by a plurality of bits. The DCC control circuit 170 receives the energy rate detection signal D1, generates an energy rate control signal D2 based thereon, and supplies it to the energy rate adjustment circuit 150. The energy rate adjustment circuit 150 causes the internal clock signal PCLK0 according to the energy rate control signal D2. The energy ratio change is outputted as the internal clock signal PCLK1.

FIG. 3 is a block diagram showing the configuration of the energy rate adjustment circuit 150.

As shown in FIG. 3, the energy rate adjustment circuit 150 is configured by four energy rate adjustment units 151 to 154 and a combination circuit 155. The energy rate adjustment units 151 and 152 are connected in series to constitute the transmission channel A. The energy rate adjustment units 153, 154 are also connected in series to constitute the transfer channel B. The transfer channel A and the transfer channel B are connected in parallel. Further, the internal clock signal PCLKA1 outputted from the transmission channel A and the internal clock signal PCLKB1 outputted from the transmission channel B are input to the synthesizing circuit 155, and output as the internal clock signal PCLK1.

The energy ratio adjusting sections 151 to 154 have the same circuit configuration, and achieve a function of changing the conversion ratio of one of the rising edge and the falling edge of each internal clock signal. The control signals that are different from each other are used to adjust the conversion rates of the energy rate adjusting units 151 to 154. Specifically, the energy ratio adjusting unit 151 uses the control signals P1 and N1, and the energy rate adjusting unit 152 uses the control signals P2 and N2, and the energy rate adjusting unit 153 uses the control signals P3 and N3 for the energy rate adjusting unit 154. Control signals P4, N4 are used. These control signals P1 to P4, N1 to N4 form part of the signal of the above-described energy rate control signal D2.

FIG. 4 is a circuit diagram of the energy rate adjustment unit 151.

As shown in FIG. 4, the energy ratio adjustment unit 151 includes six clocked inverters CV1, CV2, CV4, CV8, CV2F, and CV4F connected in parallel, and receives an internal clock signal PCLK0 to generate an internal clock. Signal PCLKA0. These clocked inverters have the same circuit configuration, and the configuration of the clocked inverter CV1 will be described as a representative here. The clocked inverter CV1 is connected to the power supply line VL to which the internal potential VPERI is supplied and the power supply line SL to which the ground potential VSS is supplied, and is connected in series in this order to the P-channel type MOS transistors MP11, MP12, and N. Channel type MOS transistors MN12, MN11 are constructed.

The gate electrodes of the transistors MP12 and MN12 are connected in common to form an input node n1 to which the internal clock signal PCLK0 is supplied. Further, the drains of the transistors MP12 and MN12 are connected in common to form an output node n2 to which the internal clock signal PCLK1 is output.

On the other hand, a control signal P11 to which a part of the control signal P1 is supplied is supplied to the gate electrode system of the transistor MP11. As a result, the control signal P11 is activated to a low level, and the clocked inverter CV1 is capable of pulling up the output node n2 according to the level of the input node n1. Conversely, when the control signal P11 is inactivated to a high level, the clocked inverter CV1 is in a state in which the output node n2 cannot be pulled up. In this manner, the transistors MP11 and MP12 connected in series constitute a riser circuit UP that is selectively activated by the control signal P11.

Similarly, a control signal N11 to which a portion of the control signal N1 is supplied is applied to the gate electrode system of the transistor MN11. As a result, the control signal N11 is activated to a high level, and the clocked inverter CV1 is capable of pulling down the output node n2 according to the level of the input node n1. Conversely, the control signal N11 is inactivated to a low level. The clock inverter CV1 is in a state in which the output node n2 cannot be pulled down. In this manner, the transistors MN11 and MN12 connected in series are configured to selectively activate the pull-down circuit DN via the control signal N11.

In this way, the clocked inverter CV1 can independently control the rising circuit UP and the pull-down circuit DN. This point is different from a general clock inverter.

The other clocked inverters CV2, CV4, CV8, CV2F, and CV4F have the same circuit configuration as the above-described clocked inverter CV1 except that there is a corresponding control signal for each input.

Here, the driving ability of the clocked inverters CV1, CV2, CV4, and CV8 is weighted as a multiplication of 2. Specifically, when the driving capability of the clocked inverter CV1 is 1 DC, the driving capacities of the clocked inverters CV2, CV4, and CV8 are 2 DC, 4 DC, and 8 DC, respectively. Accordingly, the pull-up capability can be controlled to 16 stages (0DC~15DC) according to the control signals P11, P12, P14, P18 constituting the control signal P1, and moreover, according to the control signals N11, N12 constituting the control signal N1. , N14, N18 and the pull-down capability is controlled to 16 stages (0DC~15DC). These control signals P1, N1 are generated by the DCC control circuit 170 in accordance with the energy rate detection signal D1 output from the energy rate detecting circuit 160.

However, it is difficult to make a transistor having a driving ability of less than 2 DC, as shown in FIG. 5, and the transistor MP11 is formed by two transistors connected in series, and MN11 is formed. can. In the example shown in FIG. 5, the two P-channel MOS transistors MP11a and MP11b constituting the transistor MP11 are driven. The dynamic capability is 2DC, and the driving ability of 1DC can be obtained from the case where these are connected in series. Similarly, the driving ability of the two N-channel MOS transistors MN11a and MN11b constituting the transistor MN11 is 2 DC, and the driving ability of 1 DC can be obtained by connecting them in series.

On the other hand, the clocked inverters CV2F and CV4F each have a driving capability of 2 DC and 4 DC in order to provide a fixed driving capability to the circuit of the energy ratio adjusting unit 151. Whether or not the clocked inverter CV2F, CV4F activation system can be selected via the fuze signals FP, FN. For example, in the case where only the clocked inverter CV2F is activated, the fuse signals FP12 and FN12 may be activated. Further, in the case where only the clocked inverter CV4F is activated, the fuse signals FP14 and FN14 may be activated.

For the clocked inverter CV2F, the CV4F does not need to control the rising circuit UP and the pull-down circuit DN independently, but can be commonly controlled in the same manner as a general clocked inverter. In this case, it is possible for the clocked inverters CV2F and CV4F to be activated to pull up and pull down, and for the inactivated clocked inverter CV2F, the CV4F output is in a high impedance state.

Figure 6 is a block diagram showing the circuit of FN for generating the fuze signal FP.

As shown in FIG. 6, the fuze signals FP, FN are stored in the fuze circuit 181. The fuze circuit 181 is a non-volatile memory circuit including an optical fuze element or an electrical fuze element (a write-once element). In the manufacturing stage, the program of the fuze signals FP, FN is performed. The fuze signals FP, FN outputted from the fuze circuit 181 are supplied to the energy ratio adjusting circuit 150 by the selector 183.

On the other hand, in the test action, the fuze signals FP, FN should be made variable, and the test mode circuit 182 is also provided, and the test mode circuit 182 can output any test fuze signals TFP, TFN, via the test. When the signal TEST is activated, it can be supplied to the energy rate adjustment circuit 150 by the selector 183.

In this way, whether or not the clock inverter CV2F is used, the CV4F is fixed except for the test operation. Accordingly, the switching between the pull-up capability and the pull-down capability by the energy rate adjustment unit 151 is always 16 stages. However, when the clock inverters CV2F and CV4F are used, the adjustment ratio of the pull-up capability and the pull-down capability of the energy rate adjustment unit 151 changes. For example, in the case where only the clocked inverter CV2F is used, the driving ability of the energy ratio adjusting unit 151 can be adjusted in the range of 2DC to 17DC, and the energy rate adjusting unit can be used in the case of using the clocked inverters CV2F and CV4F. The driving capability of 151 can be adjusted within the range of 6DC~21DC. In this case, in the former case, in the case where the adjustment ratio, that is, the ratio of the maximum drive capability to the minimum drive capability is 8.5 times (= 17/2), in the latter case, the adjustment rate is 3.5 times (= 21 / 6). The former is intended to greatly ensure the possible range of adjustment of the energy rate, for example, it is optimal for relatively low-speed products, and the latter is to refine the minimum adjustment interval of the energy rate, for example, for a relatively high-speed product. As described above, in the present embodiment, the adjustment range of the energy rate or the minimum adjustment pitch can be easily changed. By.

According to the configuration described above, the rising waveform of the internal clock signal PCLKA0 output from the energy rate adjusting unit 151 is controlled in accordance with the control signals P1 and FP, and the pull-down waveform is controlled in accordance with the control signals N1 and FN.

The other energy rate adjustment units 152 to 154 have the same circuit configuration as the above-described energy rate adjustment unit 151, in addition to the corresponding control signals. The energy rate adjustment unit 152 receives the internal clock signal PCLKA0 to generate the internal clock signal PCLKA1, and the energy rate adjustment unit 153 receives the internal clock signal PCLK0 to generate the internal clock signal PCLKB0, and the energy rate adjustment unit 154 receives the internal clock signal PCLKB0. The internal clock signal PCLKB1 is generated. Further, the internal clock signals PCLKA1 and PCLKB1 are supplied to the synthesizing circuit 155.

FIG. 7 is a circuit diagram of the synthesizing circuit 155.

As shown in FIG. 7, the synthesizing circuit 155 includes four inverter circuits IVA1 to IVA4 to which the internal clock signal PCLKA1 is input, and four inverter circuits IVB1 to IVB4 to which the internal clock signal PCLKB1 is input. Furthermore, the synthesizing circuit 155 is a pair of transmission gates TG1 to TG4 that are each turned on via the corresponding control signals IM1 to IM4, and the outputs of the inverter circuits IVA1 to IVA4, IVB1 to IVB4 are transmitted through a gate pair. The conduction sides of TG1 to TG4 are combined.

When specifically stated, the output nodes of the inverter circuits IVA1~IVA4 are short-circuited by the transmission gates TGA1~TGA4, and the output nodes of the inverter circuits IVB1~IVB4 are each transmitted through the gate pair. Short circuit by TGB1~TGB4. Further, the two transmission gate pairs (for example, TGA1 and TGB1) constituting the transmission gate pair TG1 to TG4 are electrically connected to each other via the corresponding control signals IM1 to IM4, and correspond to the control signals IM1 to IM4. It can control the synthesis ratio of the internal clock signal PCLKA1 and PCLKB1.

For example, if three of the transmission gate pairs TGA1 to TGA4 are turned on, and one of the transmission gate pairs TGB1 to TGB4 is turned on, the internal clock signal PCLKA1 can be synthesized by a synthesis ratio of 3:1. , PCLKB1, which generates the internal clock signal PCLK1. Alternatively, if two of the transmission gate pairs TGA1 to TGA4 are turned on, and two of the transmission gate pairs TGB1 to TGB4 are turned on, the internal clock signal PCLKA1 can be synthesized by a 1:1 synthesis ratio. , PCLKB1, which generates the internal clock signal PCLK1.

These control signals IM1 to IM4 also form part of the signal of the above-described energy rate control signal D2. Accordingly, the energy rate control signal D2 is included in the control signals P1 to P4, N1 to N4, and IM1 to IM4. As described above, the energy rate control signal D2 is generated via the DCC control circuit 170.

FIG. 8 is a block diagram schematically showing the configuration of the DCC control circuit 170.

The DCC control circuit 170 receives the energy rate detection signal D1 of, for example, 8 bits output from the energy rate detecting circuit 160, and generates an energy rate control signal D2 via decoding and logic calculation. Although not particularly limited, in the present embodiment, the energy detection signal D1 is 8-bit. The binary signal, in which the upper 6 bits b7 to b2 are used to generate the control signals P1 to P4, N1 to N4, and the lower 2 bits b1 and b0 are used to generate the control signals IM1 to IM4. In particular, the uppermost bit b7 is used as a signal indicating that the energy ratio is less than 50% or more than 50%. In this case, the value of the energy rate detection signal D1 is "01111111b" or less, and the energy ratio of the internal clock signal LCLK is less than 50%, and the value of the energy detection signal D1 is "10000000b" or more, and the internal clock signal LCLK is The energy ratio is over 50%.

As shown in FIG. 8, the DCC control circuit 170 includes a decoder 171 that decodes the bits b6 to b2 of the power rate detection signal D1, and a decoder 172 that decodes the bits b1 and b0 of the energy rate detection signal D1, according to the decoder 171. The output signal and the uppermost bit b7 of the energy detection signal D1 are logically calculated by the logic circuit 173. The logic circuit 173 is a case where the uppermost bit b7 is 0, that is, when the energy ratio of the internal clock signal LCLK is less than 50%, the value of the bit b6 to b2 is smaller, and the driving of the energy adjustment circuit 150 is driven. The ability to generate control signals P1~P4, N1~N4 is reduced. Conversely, the case where the uppermost bit b7 is 1, that is, for the case where the energy ratio of the internal clock signal LCLK is more than 50%, the value of the bit b6 to b2 is larger, and the driving ability of the energy adjustment circuit 150 is higher. The control signals P1 to P4 and N1 to N4 are generated to be smaller. On the other hand, the output of the decoder 172 is used as the control signals IM1 to IM4.

Here, the control signals P1, P3, N2, and N4 constitute the first control signal, and the uppermost bit b7 is 0, that is, internally. In the case where the energy ratio of the clock signal LCLK is less than 50%, the value is controlled in accordance with the actual energy ratio. In this case, the control signals P2, P4, N1, and N3 constituting the second control signal are fixed to the maximum value. These control signals P1, P3, N2, N4 are values that are related to each other. In the present embodiment, P1 = P3, N2 = N4, and P1, P3, N2, and N4 are mutually inverted signals, and these control signals P1 can be generated by deriving one type of control signal. , P3, N2, N4.

Similarly, the control signals P2, P4, N1, and N3 constitute the second control signal, and the uppermost bit b7 is 1, that is, in the case where the energy ratio of the internal clock signal LCLK is more than 50%, The actual energy ratio is controlled to control its value. In this case, the control signals P1, P3, N2, and N4 constituting the first control signal are fixed to the maximum value. As will be described later, these control signals P2, P4, N1, and N3 acquire mutually correlated values. In the present embodiment, P2 = P4, N1 = N3, and P2, P4 and N1, N3 are mutually inverted signals, and these control signals P2 can be generated by deriving one type of control signal. , P4, N1, N3.

9 and 10 are schematic diagrams for explaining the relationship between the values of the bits b6 to b2 of the energy detection signal D1 and the driving ability, and FIG. 9 shows a case where the energy ratio is less than 50%, and FIG. 10 shows that the energy ratio is More than 50% of the time.

The symbol 190 shown in Figs. 9 and 10 is a value of the bits b6 to b2 of the energy rate detection signal D1, and is a total of 32 types of values. For the case where the display energy ratio is less than 50%, the value of the display bit b6 to b2 is shown. Small, the rate is smaller than the state, and for the case where the display energy ratio is more than 50%, it is shown that the value of the bit b6 to b2 is larger, and the energy ratio is larger. In addition, the symbol 191 indicates the adjustment amount of the transmission channel A, and the symbol 192 indicates the adjustment amount of the transmission channel B.

Here, the adjustment amounts A2 to A17 and B2 to B17 correspond to the adjustment amounts of the above-described driving capacities 2DC to 17DC. However, the adjustment amounts A2 to A17 in the transmission path A are designed to reduce the driving capability by only 0.5 DC for the adjustment amounts B2 to B17 of the transmission path B.

The setting of the adjustment amount of the transmission channels A and B in response to the values of the bits b6 to b2 is performed as follows.

First, when the energy ratio is less than 50%, the values of the bits b6 to b2 are "10000b" indicated by the symbol 193 in Fig. 9, and the adjustment amount in the transmission channel A is set to correspond to A10. On the other hand, the transfer channel B is set to an adjustment amount B9 which is larger than the adjustment amount A10 by one pitch. Here, in the case where the energy ratio is less than 50%, it is necessary to adjust the driving ability of the power-up adjusting units 151 and 153 to the rising circuit UP via the control signals P1 and P3, and the driving capability of the pull-down circuit DN is The driving ability of the pull-down circuit DN is adjusted by the control signals N2, N4 for the energy rate adjusting sections 152, 154, and the driving capability of the rising circuit UP is fixed to the maximum value.

Then, in this example, as shown in Fig. 11 of the schematic diagram, the driving capacities of the rising circuits UP included in the energy rate adjusting units 151, 153 are set to 10 DC and 9 DC, respectively, and are included in the energy rate adjusting portions 152, 154. The driving ability of the pull-down circuit DN is set to 10 DC and 9 DC, respectively. For the other rising circuit UP and pull-down circuit DN, the maximum driving capability (17DC) is set. As a result, when the internal clock signal PCLK0 is input, the rising edge of the internal clock signals PCLKA0, PCLKB0 is passivated, and the inner edge signals PCLKA1, PCLKB1 are pulled down to become passivated.

Fig. 12 is a waveform diagram showing changes in the energy ratio of the internal clock signal in the case where the energy ratio is less than 50%. In Fig. 12, the waveform shown by the solid line is the actual waveform, and the waveform shown by the broken line is the waveform of the case where the energy ratio is 50%. This point is also the same for FIG. 14 which will be described later.

As described above, in the case where the display energy ratio is less than 50%, in the first-stage energy rate adjusting units 151 and 153, the rising capability is adjusted to be small, and the internal clock signals PCLKA0 and PCLKB0 are required in response to the rising capability. The rising edge is passivated. Here, in the case where the logical threshold value of the energy rate adjustment sections 152, 154 of the lower stage is set to the intermediate potential VM, in the energy rate adjustment sections 152, 154, the time when the input bit criterion is switched from the low level to the high level becomes slow. . This is equivalent to the case where the edge is slowed down below the internal clock signal PCLK0, and the energy ratio is expanded.

Further, in the lower energy rate adjustment units 152, 154, the pull-down capability is adjusted to be smaller. Therefore, the internal clock signals PCLKA1 and PCLKB1 are passivated under the pull-down capability in response to the pull-down capability. Here, the logic threshold of the synthesis circuit 155 of the lower stage is also set as the intermediate potential. In the case of the VM, in the synthesizing circuit 155, the time when the input bit criterion is switched from the high level to the low level becomes slower. This is equivalent to the case where the edge change is slower than the internal clock signal PCLK0, and the energy ratio is further expanded. Through this principle, the energy ratio is expanded to around 50%.

Next, when the energy ratio is more than 50%, the values of the bits b6 to b2 are "10000b" indicated by the symbol 193 in Fig. 9, and the adjustment amount in the transmission channel A is set to correspond to A9. On the other hand, the transfer channel B is set to an adjustment amount B9 which is larger than the adjustment amount A9 by one pitch. Here, in the case where the energy ratio is more than 50%, it is necessary to adjust the driving ability of the pull-down circuit DN to the energy rate adjusting units 151 and 153 via the control signals N1 and N3, and the driving ability of the rising circuit UP is The driving capacity of the rising circuit UP is adjusted by the control signals P2 and P4 for the energy rate adjusting units 152 and 154. The driving capability of the pull-down circuit DN is fixed to the maximum value.

Accordingly, in this example, as shown in Fig. 13 of the pattern diagram, the driving ability of the pull-down circuit DN included in the energy rate adjusting sections 151, 153 is set to 9 DC, and is included in the rise of the energy rate adjusting sections 152, 154. The driving capability of the circuit UP is set to 9DC. For the other rising circuit UP and pull-down circuit DN, the maximum driving capability (17DC) is set. As a result, when the internal clock signal PCLK0 is input, the internal clock signals PCLKA0, PCLKB0 are passivated while the edge is passivated, and the rising edges of the internal clock signals PCLKA1, PCLKB1 become blunt. Chemical.

Fig. 14 is a waveform diagram showing changes in the energy ratio of the internal clock signal in the case where the energy ratio exceeds 50%.

As described above, in the case where the display energy ratio is more than 50%, the pull-down capability is adjusted to be smaller in the initial energy rate adjustment units 151 and 153, and the internal clock signals PCLKA0 and PCLKB0 are required in response to the pull-down capability. The drop-down edge is passivated. Here, in the case where the logical threshold value of the energy rate adjustment sections 152, 154 of the lower stage is set to the intermediate potential VM, in the energy rate adjustment sections 152, 154, the time when the input bit criterion is switched from the high level to the low level becomes slow. . This is equivalent to the case where the rising edge of the internal clock signal PCLK0 is slow, and the energy ratio is reduced.

Further, in the lower energy rate adjustment units 152 and 154, the rising power is adjusted to be small, and the rising edge of the internal clock signals PCLKA1 and PCLKB1 is passivated in response to the rising capability. Here, the logic threshold value of the synthesis circuit 155 of the lower stage is also set to the intermediate potential VM. In the synthesis circuit 155, the time when the input bit criterion is switched from the low level to the high level becomes slow. This is equivalent to the case where the rising edge of the internal clock signal PCLK0 is changed slowly, and the energy ratio is further reduced. Through this principle, the energy ratio is reduced to around 50%.

In this manner, the logic circuit 173 included in the DCC control circuit 170 generates the control signals P1 to P4, N1 to N4 based on the values of the bits b7 to b2 of the energy rate detection signal D1, and controls the energy rate adjustment unit based thereon. When the driving capability of 151~154 is generated, two internal clock signals PCLKA1 and PCLKB1 are generated. As described above, the adjustment amount of the transmission channel A and the adjustment amount of the transmission channel B are only the difference of the driving capability of 0.5 DC, and the difference in the energy ratio of the internal clock signals PCLKA1 and PCLKB1 becomes the minimum pitch equivalent to the driving capability of 0.5 DC. . The internal clock signals PCLKA1, PCLKB1 having such a difference in energy rate are input to the synthesizing circuit 155.

Fig. 15 is a waveform diagram for explaining the operation of the synthesizing circuit 155. (a) shows a waveform in a case where the energy ratio is less than 50%, and (b) shows a waveform in a case where the energy ratio exceeds 50%.

For the case where the energy ratio is less than 50%, the internal clock signal PCLKA1, PCLKB1 lowers the edge of the internal clock signal PCLK0. Further, as shown in FIG. 15(a), the pull-down edge of the internal clock signal PCLKA1 has a delay equivalent to a driving capability of 0.5 DC for the pull-down edge of the internal clock signal PCLKB1. Such two internal clock signals PCLKA1, PCLKB1 are synthesized via the combining circuit 155, and any of the three intermediate phases M1, M2, M3 can be obtained in response to the values of the control signals IM1 to IM4.

On the other hand, in the case where the energy ratio exceeds 50%, the rising edge of the internal clock signals PCLKA1, PCLKB1 becomes slow for the internal clock signal PCLK0. Further, as shown in FIG. 15(b), the rising edge of the internal clock signal PCLKA1 has a delay equivalent to a driving capability of 0.5 DC for the rising edge of the internal clock signal PCLKB1. Synthesizing such two within the synthesis circuit 155 The partial clock signals PCLKA1 and PCLKB1 can acquire three intermediate phases M1, M2, and M3 in response to the values of the control signals IM1 to IM4.

The intermediate phase M1 to M3 shown in Fig. 15(a) shows the internal clock signal PCLK1 obtained by synthesizing the internal clock signals PCLKA1 and PCLKB1 with a synthesis ratio of 3:1, 1:1, 1:3. The drop edge. In addition, the intermediate phases M1 to M3 shown in FIG. 15(b) display the internal clocks obtained by synthesizing the internal clock signals PCLKA1 and PCLKB1 with a combination ratio of 3:1, 1:1, and 1:3. The rising edge of signal PCLK1. The selection of the synthesis ratio is based on the bits b1, b0 of the energy rate detection signal D1, and can be performed via the control signals IM1 to IM4.

However, in the case where the synthesis ratio is made 1:0, the waveform of the internal clock signal PCLK1 is determined only by the internal clock signal PCLKA1, and for the case where the synthesis ratio is made 0:1, only the internal clock signal is passed. The waveform of the internal clock signal PCLK1 is determined by PCLKB1. In this way, the synthesizing circuit 155 can directly output a waveform that is not an intermediate value, and the accuracy of the adjustment pitch of the energy ratio can be made 1/4 (the decomposition capability is four times).

In addition, when the energy ratio adjustment units 151 to 154 adjust the energy ratio 32 stages and the resolution is four times from the synthesis circuit 155, the energy rate adjustment circuit 150 of the present embodiment can secure the total 128 stages. Adjust the spacing. Here, for the case of an energy rate adjustment circuit in the form of assuming that the bias level of the micro-adjusting transistor is used, it is necessary to generate a bias potential of 128 degrees with high precision, and to compare the energy ratio with a slight noise. There will be a large error. In this regard, in In the present embodiment, the bias potential is not used, and the change in the energy-energy ratio from the completion of the digital control is high, and the noise tolerance is high, and the stability is adjusted.

Further, in the present embodiment, the energy ratio is adjusted from the first stage energy rate adjusting units 151 and 153 by controlling the driving ability of one of the P channel type and the N channel type MOS transistors, and in the next stage. In the energy ratio adjusting sections 152 and 154, when the driving ability of the other of the P-channel type and the N-channel type MOS transistor is controlled, the energy ratio is adjusted, and the P-channel MOS transistor is used even under the processing conditions and the like. The threshold value may be deviated from the critical value of the N-channel MOS transistor, and the adjustment ratio of the energy ratio may be offset.

FIG. 16 is a block diagram showing the configuration of the energy ratio adjusting circuit 150A according to the first modification.

The energy rate adjustment circuit 150A according to the first modification is different from the energy rate adjustment circuit 150 shown in FIG. 3 in that only the transmission channel A is used. Regardless of this, the synthesis circuit 155 is not used. According to the configuration, when the energy ratio adjusting circuit 150 shown in FIG. 3 is compared, the adjustment pitch becomes thicker, but the occupied area can be reduced. Further, similarly to the energy rate adjustment circuit 150 shown in FIG. 3, it is possible to offset the adjustment of the energy ratio due to the deviation of the threshold value.

Fig. 17 is a block diagram showing the configuration of the energy ratio adjusting circuit 150B according to the second modification.

The energy rate adjustment circuit 150B according to the second modification is based on the energy rate adjustment shown in FIG. 3 in the point where the energy rate adjustment units 152 and 154 are omitted. Circuit 150 is different. According to the configuration, although the adjustment deviation of the energy ratio due to the variation of the threshold value cannot be matched, the occupied area can be reduced, and the fine adjustment pitch similar to the energy rate adjustment circuit 150 shown in FIG. 3 can be obtained. .

FIG. 18 is a block diagram showing the configuration of the energy ratio adjusting circuit 150C according to the third modification.

The energy rate adjustment circuit 150C according to the third modification is different from the energy rate adjustment circuit 150 shown in FIG. 3 in that only the energy rate adjustment unit 151 is used. According to the related configuration, the circuit builder can be greatly simplified.

The above is a description of the preferred embodiments of the present invention, and the present invention is not limited to the embodiments described above, and various modifications may be made without departing from the scope of the invention. Insider.

For example, in the above embodiment, the control signals P1 to P4, N1 to N4 are generated based on the values of the bits b7 to b2 of the energy detection signal D1, and the control signals IM1 to IM4 are generated based on the values of the bits b1 and b0, but The bits used to generate these control signals P1 to P4, N1 to N4, and IM1 to IM4 are not limited thereto.

Further, in the above-described embodiment, the driving ability of the complex clock inverter included in each of the energy ratio adjusting units 151 to 154 has a weighting of 2, but this point is not essential in the present invention. Accordingly, when a plurality of clocked inverters having mutually the same driving ability are connected in parallel, the energy rate adjusting unit can be configured.

Further, in the above-described embodiment, although the driving ability of the inverter circuit included in the plurality of combining circuits 155 is not poorly set, it is possible to have a weighting of 2 for these driving capacities.

Further, in the above-described embodiment, the energy ratio of the internal clock signal is increased or decreased by 50%, but the target energy ratio is not limited to 50%. Moreover, it is not necessary to increase or decrease the energy ratio of the internal clock signal. For example, if it is clear that the energy ratio of the input internal clock signal is smaller than the target value, the ratio is not required. The reduction in function is only sufficient to increase the function. In this case, the pull-up circuit DN included in the energy rate adjusting unit 151, 153 and the rising circuit UP included in the energy rate adjusting units 152, 154 do not need to be able to adjust the driving ability, and may be fixed.

CV1, CV2, CV4, CV8, CV2F, CV4F‧‧‧ clock inverter

DN‧‧‧ pull-down circuit

MN11, MN12‧‧‧N channel MOS transistor

MP11, MP12‧‧‧P channel MOS transistor

N1‧‧‧ input node

N2‧‧‧ output node

SL, VL‧‧‧ power wiring

UP‧‧‧ rising circuit

FP12, FN12, FP14, FN14, FP, FN‧‧‧ fuze signals

P11, P12, P14, P18, P1‧‧‧ control signals

N11, N12, N14, N18, N1‧‧‧ control signals

VPERI‧‧‧ internal potential

VSS‧‧‧ Ground potential

151‧‧‧Energy Rate Adjustment Department

PCLK0‧‧‧ internal clock signal

Claims (20)

A semiconductor device comprising: an energy rate detecting circuit that generates a plurality of control signals by detecting an energy ratio of a clock signal, and a plurality of first clocks that are inserted in parallel with each other in a transmission channel of the clock signal In the inverter, the plurality of first clocked inverters are independently controlled by the plurality of control signals. The semiconductor device according to claim 1, wherein the plurality of first clocked inverters each include an input node, an output node, and a step of pulling up the output node according to a level of the input node. a rising circuit, and a first pull-down circuit that pulls down the output node according to a level of the input node, wherein at least one of the first rising circuit and the first pull-down circuit is via any one of the plurality of control signals corresponding thereto And selectively activated. The semiconductor device according to claim 2, wherein the plurality of control signals include a plurality of first control signals and a plurality of second control signals, each of which is included in the plurality of first clocked inverters The first rising circuit is selectively activated by any one of the plurality of first control signals corresponding thereto, and the first pull-down circuit included in each of the plurality of first clocked inverters is corresponding to the first pull-down circuit Any one of the plurality of second control signals is selectively activated. The semiconductor device according to claim 3, further comprising a second clocked inverter connected in series to the plurality of first clocked inverters and connected in parallel to each other, wherein the plurality of The 2 clock inverters are independently controlled by the aforementioned plurality of control signals. The semiconductor device according to claim 4, wherein the plurality of second clocked inverters each include an input node, an output node, and a step of pulling up the output node according to a level of the input node a rising circuit, and a second pull-down circuit that pulls down the output node according to a level of the input node, wherein each of the second rising circuits included in the plurality of second clocked inverters corresponds to the plurality of And selectively activating the control signal, wherein each of the second pull-down circuits included in the plurality of second clocked inverters is selectively selected via any one of the plurality of first control signals corresponding thereto Activated by the ground. The semiconductor device according to claim 5, further comprising a third clocked inverter connected in parallel to the plurality of first clocked inverters and connected in parallel to each other, and connected in series The third clock pulse inverter of the plurality of the plurality of fourth clocked inverters connected in parallel with each other, wherein the plurality of third clocked inverters are independently controlled via the plurality of control signals The fourth complex clock inverter of the foregoing plurality is controlled by the foregoing plurality of control signals The number is controlled independently. The semiconductor device according to claim 6, wherein the plurality of third clocked inverters each include an input node, an output node, and a step of pulling up the output node according to a level of the input node. a rising circuit, and a third pull-down circuit for pulling down the output node according to the level of the input node, wherein the fourth fourth clocked inverter comprises an input node, an output node, and a bit according to the input node a fourth rising circuit that pulls up the output node, and a fourth pull-down circuit that pulls down the output node according to the level of the input node, and each of the third rising of the third clocked inverter included in the plurality of The circuit is selectively activated by any one of the plurality of first control signals corresponding to the plurality of, and the third pull-down circuit included in each of the plurality of third clocked inverters is corresponding to the plurality of And selectively activating any one of the control signals, wherein the fourth rising circuit included in each of the plurality of fourth clocked inverters is via the second control corresponding to the plurality of Selectively activating any of the signals, and the fourth pull-down circuit included in each of the plurality of fourth clocked inverters is selectively added via any one of the plurality of first control signals corresponding thereto Activater. The semiconductor device according to claim 6 or claim 7, wherein the semiconductor device further includes a second clocked inverter from the plurality of And a synthesizing circuit that outputs the aforementioned clock signal and the aforementioned clock signal output from the fourth fourth clocked inverter. The semiconductor device according to any one of claims 1 to 3, further comprising a third clock pulse which is connected in parallel to the plurality of first clocked inverters and connected in parallel to each other And a synthesizing circuit for synthesizing the clock signal outputted from the first plurality of clocked inverters and the clock signal outputted from the third third clocked inverter; The 3-clock inverter is independently controlled by the aforementioned plurality of control signals. The semiconductor device according to claim 8, wherein the synthesizing circuit synthesizes the clock signal by a synthesis ratio based on a part of the plurality of control signals. A semiconductor device comprising: a first signal node; and a second signal node; and a first rising circuit including each input node, an output node, and a pull-up of the output node according to a level of the input node; And a first clocked inverter that pulls down a plurality of first pull-down circuits of the output node according to a level of the input node, wherein the input nodes of the plurality of first clocked inverters are commonly connected to the first a signal node, the aforementioned output node of the first plurality of clocked inverters Connected to the second signal node, the first rising circuit of the plurality of first clocked inverters is selectively activated by any one of a plurality of corresponding first control signals, and the plurality of The first pull-down circuit of the first clocked inverter is selectively activated by any one of the plurality of second control signals corresponding thereto. The semiconductor device according to claim 11, wherein the first clocked inverter included in at least two of the plurality of first clocked inverters has different driving capacities. The semiconductor device according to claim 11, wherein the first rising circuit includes first and second first conductivity type transistors connected in series, and the first pull-down circuit includes a series connection In the second and second conductivity type transistors, the control electrode of the first first conductivity type transistor is connected to the corresponding input node, and the control electrode of the first second conductivity type transistor is applied. And connected to the corresponding input node, and the control electrode of the second first conductivity type transistor is supplied with any one of the plurality of first control signals corresponding to the second plurality of conductivity types; The control electrode of the crystal is supplied with any one of the second plurality of control signals corresponding to the plurality. A semiconductor device according to claim 11, wherein At least one of the first rising circuits included in the plurality of first clocked inverters is inactivated via the plurality of first control signals, and is passed through the plurality of second control signals. The first pull-down circuit included in the plurality of first clocked inverters is activated, and is included in the first pull-down of the plurality of first clocked inverters via the plurality of second control signals. At least one of the circuits is inactivated, and the first rising circuit included in the plurality of first clocked inverters is activated as an activator via the plurality of second control signals. The semiconductor device according to claim 11, further comprising: a third signal node; and including each input node, an output node, and a second rise of the output node in accordance with a level of the input node a circuit, and a second clocked inverter that pulls down a plurality of second pull-down circuits of the output node according to a level of the input node, wherein the input nodes of the plurality of second clocked inverters are commonly connected to In the second signal node, the output node of the plurality of second clocked inverters is connected in common to the third signal node, and the second rising circuit of the plurality of second clocked inverters corresponds to Each of the plurality of second control signals is selectively activated, and the second pull-down circuit of the plurality of second clocked inverters is Each of the first plurality of control signals corresponding to the plurality of signals is selectively activated. The semiconductor device according to claim 15, wherein the first rising circuit included in the plurality of first clocked inverters is activated by the plurality of first control signals. The second pull-down circuit included in the plurality of second clocked inverters is activated by the first plurality of control signals, and is included in the first plurality of the plurality of second control signals via the plurality of second control signals. The first pull-down circuit of the pulse inverter is activated, and the second rising circuit included in the plurality of second clocked inverters is active as the second control signal through the plurality of second control signals. The person. The semiconductor device according to claim 16, further comprising: a fourth signal node and a fifth signal node, and including each input node, and an output node, and pulling up the aforementioned according to the level of the input node a third rising circuit of the output node, and a third clocked inverter that pulls down the complex of the third pull-down circuit of the output node according to the level of the input node, and each input node, and an output node, and according to the aforementioned input a fourth rising circuit of the output node and a fourth clocked inverter that pulls down the complex of the fourth pull-down circuit of the output node according to the level of the input node, the third of the plural The input node of the clocked inverter is commonly connected to the first signal node, The output nodes of the plurality of third clocked inverters are connected in common to the fourth signal node, and the input nodes of the plurality of fourth clocked inverters are connected in common to the fourth signal node. The output node of the fourth plurality of clocked inverters is connected in common to the fifth signal node, and the third rising circuit of the plurality of third clocked inverters corresponds to the first of the plurality of Any one of the control signals is selectively activated, and the third lowering circuit of the plurality of third clocked inverters is selectively activated by any one of the plurality of second control signals corresponding thereto. The fourth rising circuit of the plurality of fourth clocked inverters is selectively activated by any one of the plurality of second control signals, and the fourth of the plurality of fourth clocked inverters The 4 pull-down circuit is selectively activated by any one of the first plurality of control signals corresponding to the plurality of. The semiconductor device according to claim 17, further comprising: a synthesizing circuit that synthesizes a first signal appearing at the third signal node and a second signal existing at the fifth signal node. The semiconductor device according to claim 18, wherein the synthesis circuit combines the first and second signals by a composite ratio based on a plurality of third control signals. The semiconductor device according to any one of claims 11 to 19, further comprising: a non-volatile memory circuit for storing a fourth control signal, and an input node, an output node, and an input node according to the input node a fifth rising circuit of the output node, and a fifth clocked inverter that pulls down the fifth pull-down circuit of the output node according to the level of the input node, the fifth clocked inverter The input node is connected to the first signal node, and the output node of the fifth clocked inverter is connected to the second signal node, and the fifth rising circuit and the fifth pull-down circuit are connected to the second signal The fourth control signal is activated.