JP4626192B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a non-contact solid identification device equipped with an IC chip, and relates to a semiconductor device that is inexpensive, excellent in productivity, and suitable for obtaining good communication characteristics.

  2. Description of the Related Art In recent years, non-contact type individual identification systems using RFID (Radio Frequency Identification) tags have been attracting attention as a system for managing the entire life cycle of goods in all business categories of manufacturing, distribution, sales, and recycling. In particular, radio frequency RFID tags using UHF waves or microwaves are attracting attention due to the feature that a communication distance of several meters is possible with a structure in which an external antenna is attached to an IC chip. System construction is underway for the purpose of product history management.

  As a radio frequency type RFID tag using a microwave, for example, a tag using a TCP (Tape Carrier Package) type inlet developed by Hitachi, Ltd. and Renesas Technology Corp. is known.

In addition, as another inlet structure, for example, an IC chip in which one external electrode is formed on each of the front and back surfaces by Usami of Hitachi, Ltd., a dipole antenna is connected to each external electrode formed on each surface. A glass diode package structure has been developed (see Patent Document 1). Furthermore, when Usami et al. Mount an IC chip (hereinafter referred to as a double-sided electrode chip) on which the two external electrodes are formed on the front and back surfaces to an excitation slit type dipole antenna, the external electrode of the IC chip is sandwiched by the antenna. Has been developed (see Patent Document 2). The dipole antenna structure having the excitation slit can match the impedance of the antenna and the input impedance of the IC chip by changing the width and length of the slit, and can obtain good communication characteristics.
JP 2002-269520 A Japanese Patent Laid-Open No. 2004-127230

  In order to realize logistics and goods management of a large amount of goods with a non-contact type individual identification system using RFID tags, it is necessary to attach RFID tags to each of the goods. Low-cost and mass production of RFID is indispensable.

  However, when an IC chip in which two external electrodes for signal input / output are formed in the same plane is mounted on the excitation slit type dipole antenna, the two external electrodes of the IC chip are connected to the excitation slit. Since it is necessary to connect to each side, the two external electrodes of the IC chip are generally disposed at a position across the slit, and the IC chip and the antenna must be accurately aligned. Therefore, in the past, TAB (Tape Automated Bonding) method was used to mount the IC chips one by one on the antenna. However, this method requires time for handling such as vacuum suction from the dicing film and positioning with the antenna. There is such a problem. Further, when the IC chip is downsized, these problems are further increased, which hinders inexpensive and mass production.

  On the other hand, if the structure in which the two external electrodes of the double-sided electrode chip are sandwiched between the antennas is used, high-precision alignment between the IC chip and the antenna becomes unnecessary, and there is no hindrance to the downsizing of the chip. It is effective as a method for producing an inexpensive RFID tag.

  The problem with this method is that when conductive bumps that electrically connect the external electrodes on the circuit surface of the double-sided electrode chip and the antenna are formed in the semiconductor element region other than the external electrodes, the conductive bumps and the inside of the double-sided electrode chip There is an unnecessary electrical coupling with a circuit composed of the above semiconductor elements, and communication characteristics deteriorate due to generation of power loss, crosstalk noise, and the like. In particular, the analog circuit inside the double-sided electrode chip is susceptible to voltage changes and noise because it processes analog signals whose amplitude changes continuously, and when it is close to the bumps via an insulating film of several μm However, communication characteristics are inevitably degraded.

  The present invention has been made in view of the above, and provides an RFID tag that has a structure that is inexpensive and excellent in productivity using a double-sided electrode chip and that also has excellent communication characteristics.

  That is, the present invention is as follows.

  First, in a semiconductor device having an IC chip for wireless communication including a rectifier circuit portion, a clock circuit portion, a logic circuit portion, and a memory circuit portion and a transmission / reception antenna, the IC chip is on a circuit surface on which a semiconductor element is formed. A first external electrode formed on the first external electrode, a conductive bump formed on the first external electrode to electrically connect the first external electrode and the transmitting / receiving antenna, and the circuit surface A second external electrode formed on the opposing surface, and a first conductor and a second conductor constituting the transmitting / receiving antenna and connected to the first external electrode and the second external electrode, respectively. And the conductive bump is at least a region in the analog circuit portion including the rectifier circuit portion and the clock circuit portion that selectively excludes a region in which unnecessary electrical coupling may occur with the conductive bump. form Characterized in that it is.

  Second, in a semiconductor device having a wireless communication IC chip including a rectifier circuit portion, a clock circuit portion, a logic circuit portion, and a memory circuit portion and a transmission / reception antenna, the IC chip is on a circuit surface on which a semiconductor element is formed. A first external electrode formed on the first external electrode, a conductive bump formed on the first external electrode to electrically connect the first external electrode and the transmitting / receiving antenna, and on the circuit surface At least one conductive dummy bump that does not contribute to the electrical connection, a second external electrode formed on a surface facing the circuit surface, the transmission / reception antenna, and the first antenna A first conductor and a second conductor connected to the external electrode and the second external electrode, respectively, and the conductive bump and the conductive dummy bump include at least the rectifier circuit unit and Among the analog circuit section which includes a lock circuit, characterized in that the electrical unnecessary bond is formed selectively excluding area a region may occur between the conductive bump and said conductive dummy bumps.

  Third, in a semiconductor device having a wireless communication IC chip including a rectifier circuit portion, a clock circuit portion, a logic circuit portion, and a memory circuit portion and a transmission / reception antenna, the IC chip is on a circuit surface on which a semiconductor element is formed. A first external electrode formed on the first external electrode, a conductive bump formed on the first external electrode to electrically connect the first external electrode and the transmitting / receiving antenna, and on the circuit surface At least one non-conductive dummy bump formed on the second surface, a second external electrode formed on a surface opposite to the circuit surface, the transmission / reception antenna, and the first external electrode and the second external electrode. A first conductor and a second conductor respectively connected to the external electrodes, and the conductive bump includes at least the conductive circuit in the analog circuit unit including the rectifier circuit unit and the clock circuit unit. Wherein the electrical unwanted coupling is formed in a region selectively excluding an area that may occur between the sexual bumps.

  Fourth, in a semiconductor device having an IC chip for wireless communication including a rectifier circuit portion, a clock circuit portion, a logic circuit portion, and a memory circuit portion and a transmission / reception antenna, the IC chip is on a circuit surface on which a semiconductor element is formed. A first external electrode formed on the first external electrode, a conductive bump formed on the first external electrode to electrically connect the first external electrode and the transmitting / receiving antenna, and the circuit surface A second external electrode formed on the opposing surface, and a first conductor and a second conductor constituting the transmitting / receiving antenna and connected to the first external electrode and the second external electrode, respectively. And the thickness of the insulating film formed between the circuit surface of the IC chip and the conductive bump is 15 μm or more. Here, the thickness of the insulating film is preferably 10 μm or more, and more preferably 15 μm or more.

  Fifth, in the semiconductor device, the conductive bumps are made of gold, and the height thereof is in the range of 5 μm to 40 μm.

  Sixth, in the semiconductor device, electrical connection between the conductive bump and the first or second conductor constituting the transmission / reception antenna, and the second or second electrical electrode constituting the transmission / reception antenna. At least one of the electrical connection with the first conductor and the electrical connection between the first conductor and the second conductor constituting the transmission / reception antenna is made of a conductive adhesive or an anisotropic conductive adhesive. It is carried out through.

  Seventhly, in the semiconductor device, the second external electrode is formed of a processed surface of a Si base substrate of the IC chip.

  According to the semiconductor device of the present invention, the following effects can be obtained. A conductive bump is formed on the first external electrode formed in the circuit surface of the IC chip for wireless communication including the rectifier circuit portion, the clock circuit portion, the logic circuit portion, and the memory circuit portion, and faces the circuit surface. In a semiconductor device having a structure in which each electrode of a double-sided electrode chip having a second external electrode formed on the surface is sandwiched between first and second conductors constituting an antenna, conductive bumps on the first external electrode At least in the analog circuit portion including the rectifier circuit portion and the clock circuit portion, in a region excluding a region where unnecessary electrical coupling may occur with the conductive bump, or on the circuit surface and conductivity By setting the insulating film formed between the bumps to 15 μm or more, high-precision alignment between the IC chip and the antenna is unnecessary, and the analog circuit of the IC chip and the conductive bump Excellent inexpensive productivity electrical unwanted coupling can be suppressed between, it is possible to achieve good RFID tag inlet communication characteristics can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The semiconductor device according to the present embodiment includes a double-sided electrode chip having external electrodes on both sides of an IC chip, and a transmission / reception antenna composed of first and second conductors. FIG. 1 is an example of an RFID tag inlet that is a semiconductor device of the present embodiment, and shows a schematic view of an inlet in which a double-sided electrode chip is mounted on an excitation slit dipole antenna serving as a transmission / reception antenna, as viewed from above. The antenna is composed of a first conductor 21 and a second conductor 22, and these two conductors 21 and 22 are electrically connected by sandwiching the double-sided electrode chip 10 at the A part, and at the B part 2 Two conductors 21 and 22 are connected. An excitation slit 25 is formed in the first conductor 21, and the impedance of the antenna and the double-sided electrode chip 10 can be matched by changing the width and length of the excitation slit 25.

  FIG. 2 shows a schematic cross-sectional view of C-C ′ of FIG. 1. The double-sided electrode chip 10 includes a circuit surface 11 made of a semiconductor element, a first external electrode 12 formed in the circuit surface 11, a conductive bump 13 formed on the first external electrode 12, a circuit surface 11, It is comprised from the 2nd external electrode 14 formed in the surface which opposes. The double-sided electrode chip 10 includes a first conductor 21 and a second conductor 22 that constitute an antenna through the conductive particles 41 contained in the anisotropic conductive adhesive 40 by the conductive bumps 13 and the second external electrodes 14. Is connected to each. FIG. 2 shows a structure in which the conductive bump 13 of the double-sided electrode chip 10 is connected to the second conductor 22 and the second external electrode 14 is connected to the first conductor 21. Even if the top and bottom surfaces are inverted, the inlet performance remains unchanged. Moreover, although the 1st conductor 21 and the 2nd conductor 22 showed the structure currently supported by the 1st base base material 23 and the 2nd base base material 24, respectively, the base base materials 23 and 24 are not provided. Also good.

  If the structure shown by sandwiching and connecting the two external electrodes 13 and 14 of the double-sided electrode chip 10 with the antenna shown in FIGS. 1 and 2, high-precision alignment between the double-sided electrode chip 10 chip 10 and the antenna becomes unnecessary. In addition, since there is no hindrance to downsizing of the double-sided electrode chip 10, the production of an inexpensive RFID tag can be realized.

  FIG. 3 is a block diagram showing a circuit configuration example of the semiconductor device of this embodiment. An example of use of the semiconductor device of this embodiment is an RFID tag inlet, which includes an antenna 20, a rectifier circuit 50, a clock circuit 51, a logic circuit 52, a memory circuit 53, and the like. The electromagnetic wave input from the antenna 20 is rectified in the rectifier circuit 50 to generate a DC voltage. The clock circuit 51 extracts a clock from a signal that has been carried on an electromagnetic wave, and the logic circuit 52 controls writing and reading of data. The memory circuit 53 includes a counter, a decoder, a memory cell, and the like.

  Further, the internal circuit of the double-sided electrode chip 10 operates with an analog circuit such as a rectifier circuit 50 and a clock circuit 51 that operates by an analog signal whose amplitude continuously changes, and a digital signal obtained by converting the analog signal into 0 and 1. It is composed of digital circuits such as a logic circuit 52 and a memory circuit 53.

  When the internal circuit of the double-sided electrode chip 10 operates, if the internal circuit and the conductive bumps 13 are close to each other, unnecessary electrical coupling occurs between the two and power loss, crosstalk noise, etc. occur. The communication characteristics deteriorate. In particular, the analog circuit inside the double-sided electrode chip 10 is easily affected by a change in voltage and noise, and deterioration in communication characteristics is inevitable when it is close to the conductive bump 13 through an insulating film of several μm. In the semiconductor device of the present embodiment, in order to suppress the influence of this unnecessary electrical coupling, the conductive bumps 13 are selectively formed in a region excluding the analog circuit region that may cause the electrical unnecessary coupling. Alternatively, the insulating film formed between the internal circuit and the conductive bump 13 is made to be 15 μm or more.

  FIG. 4 shows a double-sided electrode chip in which conductive bumps and conductive dummy bumps are formed outside the circuit region as a first example of the embodiment of the double-sided electrode chip constituting the semiconductor device of the present embodiment. FIG. 4A is a plan view of the double-sided electrode chip 10 viewed from the surface of the conductive bump 13, and FIG. 4B is a cross-sectional view taken along the line D-D 'in FIG. The conductive bump 13 shown in FIG. 4 is formed on the first external electrode 12 in the circuit surface 11, and the first external via the opening formed on the first external electrode 12 of the insulating film 16. It is connected to the electrode 12. Further, in order to keep the parallelism between the double-sided electrode chip 10 and the antenna when connecting the antenna and the conductive bump 13, three conductive materials that do not contribute to the electrical connection between the internal circuit of the double-sided electrode chip 10 and the antenna. The dummy dummy bumps 15 are formed outside the circuit area. It can be seen from FIG. 4B that the internal circuit and the conductive bump 13 do not overlap with each other in terms of cross-sectional structure, and no electrical unnecessary coupling occurs.

  FIG. 10 described later shows an example of a conventional structure in which conductive bumps are formed in the entire circuit region for comparison. FIG. 10A is a plan view of the double-sided electrode chip 110 viewed from the surface of the conductive bump 118, and FIG. 10B is a cross-sectional view taken along the line I-I 'of FIG. The conductive bump 118 having the conventional structure shown in FIG. 10A is formed on almost the entire surface of the double-sided electrode chip 110, and is formed through the opening formed on the first external electrode 112 of the insulating film 116. 1 external electrode 113. 10B, the conductive bump 118 and the circuit surface 111 of the internal circuit such as the rectifier circuit unit 150, the clock circuit unit 151, the logic circuit unit 152, and the memory circuit 153 have a cross-sectional structure through an insulating film 116. It overlaps with. The insulating film of a general semiconductor chip is formed by sputtering and has a thickness of about 1 μm to several μm, which is very thin to block the correlation of electrical signals operating at high frequencies. Electrical unnecessary coupling occurs with the circuit.

  In FIG. 5, as a second example of the embodiment of the double-sided electrode chip constituting the semiconductor device of the present embodiment, the conductive bump is expanded from the first external electrode to a region that does not overlap the circuit region. 2 shows a double-sided electrode chip in which conductive dummy bumps are formed outside a circuit area and in a part of a logic circuit and memory circuit area including a digital circuit. FIG. 5A shows a plan view of the double-sided electrode chip 10 viewed from the surface of the conductive bump 13, and FIG. 5B shows a cross-sectional view of the E-E 'portion of FIG. 5A. The conductive bump 13 shown in FIG. 5 is formed so as to expand from the first external electrode 12 in the circuit surface 11 to a region that does not overlap the circuit region, and is formed on the first external electrode 12 of the insulating film 16. The first external electrode 12 is connected through the opened opening. Further, in order to maintain the parallelism between the double-sided electrode chip 10 and the antenna when connecting the antenna and the conductive bump 13, one conductive dummy bump that does not contribute to the connection between the internal circuit of the double-sided electrode chip 10 and the antenna. 15 is formed outside the circuit area and in a part of the area of the logic circuit and the memory circuit including the digital circuit.

  Since the conductive dummy bump 15 also has the same potential as that of the conductive bump 13 through the conductor constituting the antenna, it may cause unnecessary electrical coupling with the circuit surface 11 of the internal circuit through the insulating film 16. The effect is small if it is on a logic circuit and a memory circuit that operate according to the above.

  According to the second example shown in FIG. 5, first, the conductive bump 13 is enlarged to increase the connection area between the conductive bump 13 and the antenna, thereby reducing the connection resistance and improving the connection reliability. I can expect. Further, by expanding the conductive dummy bumps 15, the bump area combined with the conductive bumps 13 is increased. For example, the two conductors 21 and 22 constituting the antenna and the conductivity of the double-sided electrode chip 10 sandwiched between them are sandwiched between them. When connecting the second external electrode 14 formed by gold vapor deposition or the like over the entire surface of the bump 13 surface and the circuit surface with the anisotropic conductive adhesive, the two connection surfaces Since the difference in pressure-bonding pressure is reduced, a good connection state can be obtained.

  FIG. 6 shows, as a third example of the embodiment of the double-sided electrode chip constituting the semiconductor device of the present embodiment, a conductive bump formed on the first external electrode from the outside of the circuit area and a logic composed of a digital circuit. A double-sided electrode chip is shown which is enlarged to a part of the area of the circuit and the memory circuit and formed in a square shape. FIG. 6A is a plan view of the double-sided electrode chip 10 as viewed from the surface of the conductive bump 13, and FIG. 6B is a cross-sectional view taken along the line F-F 'of FIG. The conductive bump 13 shown in FIG. 6 is formed on the first external electrode 12 in the circuit surface 11 so as to be expanded to a region that does not overlap the circuit region and a part of the logic circuit and memory circuit region including the digital circuit. The first external electrode 12 is connected through an opening formed on the first external electrode 12 of the insulating film 16.

  According to the third example shown in FIG. 6, by expanding the conductive bump 13 around the double-sided electrode chip 10, the connection area between the bump and the antenna is increased more than the structure shown in the second example. Further, a reduction in connection resistance and an improvement in connection reliability can be expected. In addition, it is possible to maintain parallelism when connecting the double-sided electrode chip 10 and the antenna, for example, when connecting the antenna and the two connection surfaces of the double-sided electrode chip 10 together via an anisotropic conductive adhesive. A good connection state can also be obtained in that the difference in pressure-bonding pressure can be reduced.

  In FIG. 7, as a fourth example of the embodiment of the double-sided electrode chip constituting the semiconductor device of the present embodiment, the conductive bump is expanded from the first external electrode to a region that does not overlap the circuit region. A double-sided electrode chip is shown in which non-conductive dummy bumps are formed in part of a region including an analog circuit region. FIG. 7A is a plan view of the double-sided electrode chip 10 viewed from the surface of the conductive bump 13, and FIG. 7B is a cross-sectional view taken along the line G-G 'in FIG. The conductive bump 13 shown in FIG. 7 is formed so as to expand from the first external electrode 12 in the circuit surface to a region that does not overlap the circuit region, and is formed on the first external electrode 12 of the insulating film 16. The first external electrode 12 is connected through the opening. In order to maintain the parallelism between the double-sided electrode chip 10 and the antenna when the antenna and the conductive bump 13 are connected, the non-conductive dummy bump 17 is formed in a part of the region including the circuit region.

  According to the fourth example shown in FIG. 7, as in the second example shown in FIG. 5, by expanding the conductive bump 13, the connection area between the bump and the antenna is increased, and the connection resistance is reduced. Reduction and improvement in connection reliability can be expected. Further, if the non-conductive dummy bumps 17 are formed on the circuit surface of the double-sided electrode chip 10, the double-sided electrode chip 10 and the antenna are not generated without causing unnecessary electrical connection between the non-conductive dummy bumps 17 and the internal circuit of the double-sided electrode chip 10. The point that the parallelism when connecting the two can be kept, for example, the difference in pressure bonding pressure when the antenna and the two connection surfaces of the double-sided electrode chip 10 are collectively connected via the anisotropic conductive adhesive can be reduced. In this case, a good connection state can be obtained.

  FIG. 8 shows a double-sided electrode chip constituting a fifth example of the embodiment of the double-sided electrode chip constituting the semiconductor device of the present embodiment. FIG. 8A shows a plan view of the double-sided electrode chip 10 viewed from the surface of the conductive bump 13, and FIG. 8B shows a cross-sectional view taken along the line H-H 'in FIG. 8A. As shown in FIG. 8A, the conductive bumps 13 are formed on almost the entire surface of the double-sided electrode chip 10 including the analog circuit area from the first external electrode 12 in the same manner as the conventional conductive bumps 118 (FIG. 10). Has been. On the other hand, as shown in FIG. 8B, the insulating film 16 formed between the circuit surface 11 such as the rectifier circuit 50, the clock circuit 51, the logic circuit 52, and the memory circuit 53 and the conductive bump 13 is polyimide. It is formed with a thickness of 15 μm or more by coating with resin or the like.

  According to the fifth example shown in FIG. 8, a conductive bump is formed on almost the entire surface of the double-sided electrode chip 10 as in the conventional structure shown in FIG. The connection resistance can be reduced and the connection reliability can be improved, and the parallelism when the double-sided electrode chip 10 and the antenna are connected can be maintained. For example, the two connection surfaces of the antenna and the double-sided electrode chip 10 A good connection state can also be obtained in that the difference in pressure-bonding pressure when the two are connected together via an anisotropic conductive adhesive can be reduced. In addition, the insulating film interposed between the circuit surface 11 of the internal circuit and the conductive bump 13 is increased to 15 μm or more compared to the thickness of 1 μm to several μm of the conventional structure, so that an unnecessary electrical coupling between the two is achieved. Can be suppressed.

  In the first to fifth examples, either the surface of the conductive bump 13 or the surface of the second external electrode 14 of the double-sided electrode chip 10 is connected to the first conductor 21 constituting the antenna. Even if the electrode chip 10 rotates in the direction of the circuit surface, the performance as a semiconductor device does not change, and it is not necessary to arrange the double-sided electrode chip 10 in a specific direction, so the structure of the present embodiment realizes mass production. Preferred above.

  In the first to fifth examples, the connection part between the double-sided electrode chip 10 and the first and second two conductors 21 and 22 constituting the antenna and the connection part between the two conductors 21 and 22 constituting the antenna. At least one is formed via a conductive adhesive or an anisotropic conductive adhesive. The conductive adhesive contains a thermosetting matrix resin and granular, flake-like, or needle-like metal pieces. The anisotropic conductive adhesive contains matrix resin and conductive particles made of metal particles or organic resin particles having a metal layer formed on the surface. When the double-sided electrode chip 10 and the antenna or the two conductors 21 and 22 constituting the antenna are heat-bonded, the metal pieces or conductive particles 41 contained in the matrix resin 40 are in close contact with the conductors 21 and 22. Since it is fixed, a good electrical connection can be obtained. In particular, if an anisotropic conductive adhesive having a sufficient amount of resin to fill the periphery of the double-sided electrode chip 10 between the two conductors 21 and 22 constituting the antenna is used, the double-sided electrode chip simultaneously with the electrical connection. 10 sealing effects are obtained, which is suitable for realizing high reliability.

  In the first to fifth examples, of the first and second conductors 21 and 22 constituting the antenna, at least the first conductor 21 forming the excitation slit is made of aluminum or copper. It is preferable for realizing good antenna circuit workability and low cost by punching and punching.

  The two conductors 21 and 22 constituting the antenna may be a metal plate alone or a thin metal layer supported on a base substrate made of organic resin or paper. When the semiconductor device of this embodiment is used in the form of an RFID tag inlet, the conductors 21 and 22 are supported by base base materials 23 and 24 made of organic resin or paper to protect the antenna. This is preferable from the viewpoint of preventing short circuit. In particular, polyethylene terephthalate (PET) is suitable for realizing a low-cost inlet.

  That is, the semiconductor device of the present embodiment is a semiconductor device having an IC chip for wireless communication including a rectifier circuit unit 50, a clock circuit unit 51, a logic circuit unit 52, and a memory circuit unit 53, and a transmission / reception antenna. The double-sided electrode chip 10 includes a first external electrode 12 formed on a circuit surface 11 on which a semiconductor element is formed, and a first external electrode 12 for electrically connecting the first external electrode 12 and the transmitting / receiving antenna. Conductive bumps 13 formed on the external electrode 12, a second external electrode 14 formed on the surface facing the circuit surface 11, an antenna, and the first external electrode 12 and the first external electrode 12. A first conductor 21 and a second conductor 22 connected to two external electrodes 14, and the conductive bump 13 includes at least an analog circuit including the rectifier circuit unit 50 and a clock circuit unit 51. Of the portion, it is formed in a region that selectively excludes a region where unnecessary electrical coupling may occur with the conductive bump 13, or formed between the circuit surface 11 and the conductive bump 13. The semiconductor device is characterized in that the insulating film 16 is 15 μm or more.

  As described with reference to FIGS. 1 to 8, the double-sided electrode chip 10 has a structure in which the two-sided electrode chip 10 is sandwiched between the two conductors 21 and 22 and is formed on the circuit surface of the double-sided electrode chip 10. By suppressing unnecessary electrical coupling between the bumps 13 and the circuit surface 11 of the internal circuit, an RFID tag inlet having low cost, excellent productivity, and good communication characteristics can be realized.

  Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings. However, the present invention is not limited to these embodiments.

<Example 1>
Example 1 will be described with reference to a bump arrangement diagram of a double-sided electrode chip shown in FIG. 4 and a process diagram shown in FIG.

First, as shown in FIG. 4, the upper left external electrode 12 of the double-sided electrode chip 10 of 480 μm in length and width including the rectifier circuit 50, the clock circuit 51, the logic circuit 52, the memory circuit 53, the external electrodes 12 in the circuit plane, and the like is provided. Conductive bumps 13 of 65 μm each in vertical and horizontal directions are formed in the area on the formed circuit surface, and three conductive dummy bumps 15 of 65 μm in vertical and horizontal directions are formed in the area where the circuit is not formed at the four corners of the double-sided electrode chip. did. Each bump had a height of 15 μm and was formed by plating. (Fig. 9 (a))
Next, the base material which bonded the 1st conductor 21 and the polyethylene terephthalate base material 23 by aluminum foil is prepared, and the 1st circuit layer which etched the excitation slit to the predetermined dimension using the iron chloride solution is produced. did. The first conductor supported by the polyethylene terephthalate base material 23 constitutes an antenna. (Fig. 9 (b))
Next, an anisotropic conductive adhesive film (AC-2056T-45, Hitachi Chemical Co., Ltd.) containing conductive particles 41 in the matrix resin 40 at a predetermined position where the double-sided electrode chip 10 of the first conductor 21 is mounted. Co., Ltd.) was temporarily bonded. (Fig. 9 (c))
Next, the double-sided electrode chip 10 was temporarily fixed at a predetermined position on the anisotropic conductive adhesive film on the first conductor 21. (Fig. 9 (d))
Next, the conductive particles 41 are contained in the matrix resin 40 at predetermined positions on the aluminum foil surface of the second circuit layer made of the base material obtained by bonding the second conductor 22 made of aluminum foil and the polyethylene terephthalate base material 24 together. A second conductor 21 constituting an antenna is prepared by temporarily adhering an anisotropic conductive adhesive film (AC-2056T-45, manufactured by Hitachi Chemical Co., Ltd.), and the anisotropic conductive film surface is a double-sided electrode chip 10. The crimping head 60 on which the protrusions equal to the thickness of the double-sided electrode chip 10 were formed from above the second conductor 22 was aligned at a predetermined position. (Fig. 9 (e))
Next, the pressure-bonding head 90 was lowered and pressure-bonded for 20 seconds under the conditions of a temperature of 180 ° C. and a load of 2 N to obtain the structure shown in FIG.

  The RFID tag inlet obtained through the above steps is divided into an RFID tag reader (MRJ300, output 300 mW, manufactured by Hitachi Kokusai Electric) and an RFID tag reader antenna (circular one-patch linearly polarized antenna, manufactured by Hitachi Kokusai Electric). ) Was used to measure the communication distance, and a maximum communication distance of 260 mm was obtained.

<Example 2>
Example 2 will be described with reference to a bump arrangement diagram of a double-sided electrode chip shown in FIG. 5 and a process diagram shown in FIG.

First, as shown in FIG. 5, the external electrode 12 on the upper side of the double-sided electrode chip 10 of 480 μm in length and width including the rectifier circuit 50, the clock circuit 51, the logic circuit 52, the memory circuit 53, the external electrode 12 in the circuit plane, and the like. In the formed region and the region where the circuit is not formed, conductive bumps 13 made of gold having a length of 65 μm and width of 400 μm, a region where the circuit under the double-sided electrode chip 10 is not formed, a logic circuit and a memory circuit were formed. A concave conductive dummy bump 15 made of gold was formed in a part of the region having a length of 150 μm and a width of 400 μm. Each bump had a height of 15 μm and was formed by plating. (Fig. 9 (a))
Hereinafter, according to FIG. 9, an RFID tag inlet was manufactured in the same process as in the first embodiment except that the pressure bonding conditions were a temperature of 180 ° C., a load of 3.5 N, and a pressure bonding time of 20 seconds.

  When the communication distance of the inlet obtained in the above steps was measured using the same reader and antenna as in Example 1, a maximum communication distance of 255 mm was obtained.

<Example 3>
Example 3 will be described with reference to a bump arrangement diagram of a double-sided electrode chip shown in FIG. 6 and a process diagram shown in FIG.

First, as shown in FIG. 6, the external electrodes 12 on the upper side of the double-sided electrode chip 10 of 480 μm in length and width including the rectifier circuit 50, the clock circuit 51, the logic circuit 52, the memory circuit 53, the external electrodes 12 in the circuit surface, and the like. Gold-shaped conductive bumps 13 made of gold were formed in a region of 420 μm in length and 400 μm in width in the formed region, the region where the circuit was not formed, and the region where the logic circuit and the memory circuit were formed. The height of the bump was 15 μm and was formed by plating. (Fig. 9 (a))
Hereinafter, according to FIG. 9, an RFID tag inlet was manufactured in the same process as in the first embodiment except that the pressure bonding conditions were a temperature of 180 ° C., a load of 4.5 N, and a pressure bonding time of 20 seconds.

  When the communication distance of the inlet obtained in the above steps was measured using the same reader and antenna as in Example 1, a maximum communication distance of 255 mm was obtained.

<Example 4>
Example 4 will be described with reference to a bump arrangement diagram of a double-sided electrode chip shown in FIG. 7 and a process diagram shown in FIG.

  First, as shown in FIG. 7, the external electrode 12 on the upper side of the double-sided electrode chip 10 of 480 μm in length and width including the rectifier circuit 50, the clock circuit 51, the logic circuit 52, the memory circuit 53, the external electrodes in the circuit surface, and the like is formed. A conductive bump 13 of 65 μm in length and 400 μm in width was formed in the formed region and the region where no circuit was formed. The height of the bump was 15 μm and was formed by plating.

Next, an epoxy resin containing a spherical silicon dioxide filler in the range of 300 μm in length and 400 μm in width including the area where each circuit is formed at the bottom of the chip is potted using a dispenser, followed by conditions of 150 ° C. for 1 hour. And a non-conductive dummy bump 17 was formed. The maximum height of the non-conductive dummy bump 17 was 20 μm. (Fig. 9 (a))
Hereinafter, according to FIG. 9, an RFID tag inlet was manufactured in the same process as in Example 1 except that the pressure bonding conditions were a temperature of 180 ° C., a load of 4.5 N, and a pressure bonding time of 20 seconds.

  When the communication distance of the inlet obtained in the above steps was measured using the same reader and antenna as in the first example, a maximum communication distance of 260 mm was obtained.

<Comparative example>
A comparative example will be described with reference to a bump arrangement diagram of a double-sided electrode chip shown in FIG. 10 and a process diagram shown in FIG.

First, as shown in FIG. 10, the external electrode 112 on the upper side of the double-sided electrode chip 110 of 480 μm in length and width including the rectifier circuit 150, the clock circuit 151, the logic circuit 152, the memory circuit 153, the external electrodes in the circuit surface, and the like is formed. The conductive bumps 113 made of gold were formed in a range of 400 μm each in length and width including the formed region and the region where each circuit was formed. The height of the bump was 15 μm and was formed by plating. (Fig. 9 (a))
Hereinafter, according to FIG. 9, an RFID tag inlet was manufactured in the same process as in the first embodiment except that the pressure bonding conditions were a temperature of 180 ° C., a load of 4.5 N, and a pressure bonding time of 20 seconds.

  When the communication distance of the inlet obtained in the above steps was measured using the same reader and antenna as in Example 1, a maximum communication distance of 200 mm was obtained.

The results of the first to fourth embodiments and the comparative example are summarized in Table 1.

It is a top view which shows the structure of the semiconductor device of this Embodiment. It is sectional drawing which shows the structure of the semiconductor device of this Embodiment. It is a block diagram which shows the circuit structural example of the semiconductor device of this Embodiment. It is a figure which shows bump arrangement | positioning of the double-sided electrode chip | tip of the 1st example of this Embodiment. It is a figure which shows bump arrangement | positioning of the double-sided electrode chip | tip of the 2nd example of this Embodiment. It is a figure which shows bump arrangement | positioning of the double-sided electrode chip | tip of the 3rd example of this Embodiment. It is a figure which shows bump arrangement | positioning of the double-sided electrode chip | tip of the 4th example of this Embodiment. FIG. 10 is a diagram showing a bump arrangement of a double-sided electrode chip of a fifth example of the present embodiment. It is a figure for demonstrating the manufacturing process of the semiconductor device of this Embodiment. It is a figure which shows bump arrangement | positioning of the conventional double-sided electrode chip.

Explanation of symbols

10: Double-sided electrode chip 11: Internal circuit of double-sided electrode chip 12: First external electrode 13: Conductive bump 14: Second external electrode 15: Conductive dummy bump 16: Insulating film 17: Nonconductive dummy bump 18: Conductive Bump 20: Antenna 21: First conductor 22 constituting the antenna 22: Second conductor 23 constituting the antenna 23: Base substrate 24 supporting the first conductor 24: Base substrate 25 supporting the second conductor : Exciting slit 40 formed in the first conductor: Anisotropic conductive adhesive 41: Conductive particles 50: Rectifier circuit 51: Clock circuit 52: Logic circuit 53: Memory circuit 60: Crimp head

Claims (6)

In a semiconductor device having an IC chip for wireless communication having a circuit region including a rectifier circuit portion, a clock circuit portion, a logic circuit portion, and a memory circuit portion, and a transmission / reception antenna,
The IC chip includes a first external electrode formed on a circuit surface on which a semiconductor element is formed, and the first external electrode for electrically connecting the first external electrode and the transmitting / receiving antenna. A conductive bump formed thereon, a second external electrode formed on a surface opposite to the circuit surface, and the transmission / reception antenna and the first external electrode and the second external electrode, respectively. A first conductor and a second conductor to be connected;
The conductive bump selectively removes at least a region where an unnecessary electrical coupling may occur between the conductive bump and an analog circuit portion including the rectifier circuit portion and the clock circuit portion, and the circuit region. And a part of a digital circuit portion including the logic circuit portion and the memory circuit portion . The semiconductor device is formed around the analog circuit portion. In a semiconductor device having an IC chip for wireless communication having a circuit region including a rectifier circuit portion, a clock circuit portion, a logic circuit portion, and a memory circuit portion, and a transmission / reception antenna,
The IC chip includes a first external electrode formed on a circuit surface on which a semiconductor element is formed, and the first external electrode for electrically connecting the first external electrode and the transmitting / receiving antenna. A conductive bump formed thereon, at least one conductive dummy bump formed on the circuit surface that does not contribute to electrical connection, and a second external formed on the surface facing the circuit surface An electrode, and a first conductor and a second conductor constituting the transmitting / receiving antenna and connected to the first external electrode and the second external electrode, respectively,
The conductive bump and the conductive dummy bump have at least a region where an unnecessary electrical coupling may occur between the conductive bump and the conductive dummy bump in the analog circuit unit including the rectifier circuit unit and the clock circuit. It is formed in an area that is selectively removed, and is formed to be enlarged outside the circuit area and part of the digital circuit area including the logic circuit section and the memory circuit section so as to face each other across the circuit area. A semiconductor device characterized by that. In a semiconductor device having an IC chip for wireless communication having a circuit region including a rectifier circuit portion, a clock circuit portion, a logic circuit portion, and a memory circuit portion, and a transmission / reception antenna,
The IC chip includes a first external electrode formed on a circuit surface on which a semiconductor element is formed, and the first external electrode for electrically connecting the first external electrode and the transmitting / receiving antenna. A conductive bump formed thereon, at least one non-conductive dummy bump formed on the circuit surface, a second external electrode formed on a surface facing the circuit surface, and the transmission / reception A first conductor and a second conductor constituting an antenna and connected to the first external electrode and the second external electrode, respectively;
The conductive bump is formed at least in an analog circuit part including the rectifier circuit part and the clock circuit part, in a region that selectively excludes a region where unnecessary electrical coupling may occur with the conductive bump, The non-conductive dummy bump is formed outside the circuit area, in a digital circuit area including the logic circuit section and the memory circuit section , and in an area including the analog circuit section.   4. The semiconductor device according to claim 1, wherein the conductive bump is made of gold and has a height in a range of 5 μm to 40 μm.   5. The semiconductor device according to claim 1, wherein electrical connection between the conductive bump and the first or second conductor constituting the transmission / reception antenna, and the second external electrode and the transmission / reception are performed. At least one of the electrical connection with the second or first conductor constituting the antenna and the electrical connection between the first conductor and the second conductor constituting the transmitting / receiving antenna is a conductive adhesive. Alternatively, the semiconductor device is performed through an anisotropic conductive adhesive.   6. The semiconductor device according to claim 1, wherein the second external electrode is formed by a processed surface of a Si base substrate of the IC chip.

Images