JP4583587B2 - Power-on control system and power-on control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power-on control system and a power-on control method , and more particularly to a power-on control system and a power-on control method for an electronic device having a plurality of circuit blocks that operate at different power supply voltages.
[0002]
[Prior art]
Some electronic devices such as information processing devices and communication control devices perform power-on retry control when power-on fails. For example, in Japanese Patent Laid-Open No. 9-325834, if a predetermined command is output from a specific program within a set time after the information processing apparatus is turned on, the power-on state is continued and output within the set time. If not, it is assumed that the information processing apparatus has not been in a normal operating state, and the power supply is temporarily turned off. Then, after that, control is performed to turn on the power supply device again after a predetermined time has elapsed. Further, if a predetermined command is not output within the set time, the power-on state is continued for a predetermined energization time, and then the power is turned off and the next re-on control is performed.
[0003]
[Problems to be solved by the invention]
However, in such a conventional technique, the power-on sequence is the same every time, and it is impossible to control the power-on sequence and control the rising slope of the power when there are a plurality of power supply voltages. Due to critical factors such as variations in LSI characteristics and differences in usage environment, there is a problem that there is a possibility that the power will not start even after repeated power cycle.
[0004]
An object of the present invention is to provide a power-on control system and a power-on control method for an electronic device that are not affected by variations in the characteristics of components and usage environments.
[0005]
[Means for Solving the Problems]
According to the present invention, there is provided a power-on control system for an electronic device having a plurality of circuit blocks that operate with different power supply voltages.
Oite when the power is turned on again, the combination of parameters indicating a condition of a slope of rise of the parameter and the power supply voltage indicating the order of the power supply voltage is turned on, and controls so as to form a combination of different parameters from the last time the power is turned on the power-on control means only including,
The power-on control means sets the same combination of parameters between the power supply voltages when the power is first turned on, and performs power-on control when a signal indicating the rise of the circuit block has not arrived. power-control system and performing are obtained.
[0006]
According to the present invention, there is also provided a power-on control method for an electronic device having a plurality of circuit blocks that operate with different power supply voltages.
A power supply that controls the combination of the parameter indicating the power supply voltage turn-on order and the parameter indicating the slope condition of the power supply voltage rise with a combination of parameters different from the previous power-on. Including the input control step,
In the power-on control step, when the power is turned on for the first time, the combination of the parameters is set to be the same between the power supply voltages, and when the signal indicating the rise of the circuit block has not arrived, the power-on control step is performed. A power-on control method can be obtained .
[0007]
The operation of the present invention will be described. If the system startup OK command is not output from the device even after a predetermined time elapses after the first power-on, the power is turned off and the second power-on is performed after a certain time elapses. The combination of the power supply voltage input sequence and the power supply voltage rising slope (parameter combination) is changed from the first, and the power supply is turned on again. In this way, each time the power is turned on again, the combination of parameters is changed and the power is turned on.
[0008]
More specifically, if a system startup OK command is output from the device within a predetermined time after the electronic device such as a communication device is turned on, the power must be turned on and output within the predetermined time. For example, it is assumed that the apparatus has not started up in a normal state, and the power supply is temporarily turned off. And after a certain period of time, carry out the re-introduction of power by changing the combination of power-up parameters. By repetitively performing this power-on again while changing the combination of power-up parameters, it depends on critical factors such as the power-on voltage sequence, variations in LSI characteristics, and differences in the usage environment. Even if there is a failure in starting up the communication device, it is possible to reliably start up the communication device in a normal state by turning on the power again thereafter.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a system configuration diagram of a communication apparatus to which the present invention is applied. In FIG. 1, reference numeral 600 denotes a power control unit that controls power on / off, and reference numeral 700 denotes a communication control unit that is a target of power control. The power supply control unit 600 includes a power supply 301, a power switch (SW) 302 that turns on AC power, a primary power supply monitoring unit 303 that monitors the power supply voltage of the power supply 301, a device startup monitoring unit 100 that controls power on / off, An Nch-FET unit 304 that supplies + 5V power to the communication control unit 700, an FET control unit 200 that controls the FET, an Nch-FET unit 305 that supplies + 3V power to the communication control unit 700, and an FET control unit that controls the FET 220.
[0010]
The power supply on the power supply control unit 600 side inside the FET is called a primary side, and the power supply on the communication control unit 700 side outside is called a secondary side. The communication control unit 700 includes a + 5V system LSI unit 509 that is a + 5V system load, a + 3V system LSI unit 510 that is a + 3V system load, and an ACK return unit that returns a command to the power supply control unit 600 when the apparatus starts up in a normal state. 511.
[0011]
FIG. 2 is a configuration diagram of the apparatus start-up monitoring unit 100, the + 5V-type FET control unit 200, and the + 3V-type FET control unit 220, showing the features of the present invention. The device start-up monitoring unit 100 monitors whether a command is output from the communication control unit 700 within a predetermined time, and controls the device start-up control unit 102 that controls the turning off / on of the secondary power supply. The device start-up control unit The secondary power supply startup parameter generation unit 101 generates a power supply startup parameter of the secondary power supply according to an instruction 102.
[0012]
The + 5V system FET control unit 200 includes a DELAY (delay) unit 201 that delays the timing when the FET is turned on at the digital level, a DSEL (selection) unit 202 that selects whether the delay is necessary or not at the digital level, and the gate voltage of the FET. A FET booster driver 203 to be generated, a RUMP (slope) unit 204 for delaying an increase in the gate voltage of the FET at an analog level, and an ASEL unit 205 for selecting necessity / unnecessity of RUMP UP at an analog level.
[0013]
The + 3V system FET control unit 220 includes a DELAY unit 201 that delays the timing at which the FET is turned on at a digital level, a DSEL unit 202 that selects necessity / unnecessity of delay at the digital level, and an FET boost driver 203 that generates a gate voltage of the FET. The RUMP unit 204 delays the rise in the gate voltage of the FET at the analog level, and the ASEL unit 205 selects whether the RUMP UP is necessary / unnecessary at the analog level.
[0014]
Next, with respect to the actual operation of the embodiment of the present invention, the combination of the secondary power supply startup parameters of FIG. 6, the DELAY parameter waveform of FIG. 3, the RUMP parameter of FIG. The waveform will be described with reference to the secondary power-off / re-on flow in FIG.
[0015]
First, the power supply SW302 is turned on and AC100V is input to the power supply 301 (step S1). The power supply 301 starts outputting the + 5V output 504 and the + 3V output 505 on the primary side. The primary power supply monitoring unit 303 monitors this output voltage, and outputs a PWOK signal 401 when the voltage rises to a normal level (step S2). Upon receiving this WPOK signal 401, the apparatus startup monitoring unit 100 sets the secondary power supply startup parameters by the secondary power supply startup parameter generation unit 101. The parameter set here is parameter number 0 in FIG. That is, a parameter of no DELAY / no RUMP is set for the + 5V system, and no DELAY / RUMP is set for the + 3V system (step S3).
[0016]
After setting the parameters, the apparatus start-up control unit 102 outputs a FETON signal 407 to turn on the secondary power supply (step S4). Upon receiving the FETON signal 407, the + 5V FET control unit 200 executes the DELAY operation and the RUMP UP operation according to the parameter setting. The DSEL unit 202 selects no DELAY and outputs a D-FETON signal 207. The difference in delay with and without DELAY is shown in the DELAY parameter waveform of FIG.
[0017]
When there is no DELAY with respect to the input of the FETON signal 407, the D-FETON signal 207 is not delayed (W2 in FIG. 3). When DELAY is present, the delay set by the DELAY unit 201 is generated in the D-FETON signal 207 (W3 in FIG. 3).
[0018]
Upon receiving the D-FETON signal 207, the FET boost driver 203 generates a bias to be applied to the gate of the FET. The ASEL unit 205 selects no RUMP and outputs an A-FETON signal 408. The Nch-FET unit 304 supplies + 5V power to the secondary side according to the A-FETON signal 408.
[0019]
The difference in the rising slope of the secondary power supply with and without RUMP is shown in the RUMP parameter waveform of FIG. When there is no RUMP for the D-FETON signal 207, the rising edge of the A-FETON signal 408 becomes steep (W5 in FIG. 4). This A-FETON signal 408 is applied to the gate of the FET. Therefore, the rise of the secondary power supply also becomes steep (W6 in FIG. 4).
[0020]
When there is no RUMP, the rise of the A-FETON signal 408 is gentle (W7 in FIG. 4). This A-FETON signal 408 is applied to the gate of the FET. For this reason, the rise of the secondary power supply is also gradual (W8 in FIG. 4). In response to the FETON signal 407, the + 3V FET control unit 220 executes the DELAY operation and the RUMP operation according to the parameter setting. The DSEL unit 202 selects no DELAY and outputs a D-FETON signal 207.
[0021]
Upon receiving the D-FETON signal 207, the FET boost driver 203 generates a bias to be applied to the gate of the FET. The ASEL unit 205 selects no RUMP and outputs an A-FETON signal 409. The Nch-FET unit 305 supplies + 3V power to the secondary side according to the A-FETON signal 409. The power supply control unit 600 supplies the secondary side voltage to the communication control unit 700 as described above.
[0022]
Here, the apparatus startup control unit 102 waits for the SYSOK signal 402 from the communication control unit 700 (steps S5 and S6). The communication control unit 700 outputs a SYSOK signal 402 from the ACK return unit 511 when the apparatus starts up to a normal state. In the apparatus start-up monitoring unit 100, when this SYSOK signal 402 is output within a predetermined time, it is assumed that the apparatus has started up normally, the supply of secondary power is continued, and the apparatus shifts to an operating state (step S5). , S6, S10).
[0023]
However, if this SYSOK is not output within a predetermined time, it is considered that the apparatus has failed to start up, and the apparatus start-up control unit 102 stops outputting the FETON signal 407 (step S7). When the output of the FETON signal 407 is stopped, the D-FETON signal 207 and the A-FETON signals 408 and 409 are also stopped. Therefore, the power supply to the secondary side is stopped. As a result, the power supply on the secondary side is once cut off.
[0024]
The apparatus start-up control unit 102 waits for the secondary power supply to sufficiently discharge after stopping the output of the FET ON signal 407 (step S8), and then the secondary power supply start-up parameter generation unit 101 The INC signal 103 is output so as to increment the parameter number (that is, the parameter combination No., see FIG. 6). Receiving the INC signal 103, the secondary power supply startup parameter generation unit 101 sets the parameter number to +1 from the previous setting. The parameter number set here is “parameter number 1” in FIG. That is, a combination of parameters with no DELAY / no RUMP for the + 5V system and no DELAY / RUMP for the + 3V system is set (step S9).
[0025]
After setting the parameters, the apparatus start-up control unit 102 outputs a FETON signal 407 to turn on the secondary power supply (step S4). Thereafter, the secondary-side power supply is started up according to the parameters, and the apparatus start-up unit 102 waits for the SYSOK signal 402 (steps S5 and S6).
[0026]
The communication control unit 700 outputs a SYSOK signal 402 from the ACK return unit 511 when the apparatus starts up to a normal state. In the apparatus start-up monitoring unit 100, when this SYSOK signal 402 is output within a predetermined time, it is assumed that the apparatus has started up normally, the supply of secondary power is continued, and the apparatus shifts to an operating state (step S5). , S6, S10).
[0027]
However, if this SYSOK is not output within a predetermined time, it is considered that the apparatus has failed to start up, and the apparatus start-up control unit 102 stops outputting the FETON signal 407 (step S7). When the output of the FETON signal 407 is stopped, the D-FETON signal 207 and the A-FETON signals 408 and 409 are also stopped. For this reason, the power supply to the secondary side is stopped. As a result, the power supply on the secondary side is once cut off.
[0028]
The apparatus start-up control unit 102 waits for the secondary power supply to sufficiently discharge after stopping the output of the FET ON signal 407 (step S8), and then the secondary power supply start-up parameter generation unit 101 , and it outputs the INC signal 103 to increment the parameter number. Receiving the INC signal 103, the secondary power supply startup parameter generation unit 101 sets the parameter number to +1 from the previous setting. The parameter number set here is “parameter number 2” in FIG.
[0029]
That is, a parameter of DELAY absent / RUMP is set for the + 5V system, and no DELAY / RUMP is set for the + 3V system (step S9). After setting the parameters, the apparatus start-up control unit 102 outputs a FETON signal 407 to turn on the secondary power supply (step S4). Thereafter, the secondary-side power supply is started up according to the parameters, and the apparatus start-up unit 102 waits for the SYSOK signal 402 (steps S5 and S6).
[0030]
As described above, the apparatus start-up control unit 102 turns off the secondary power supply while changing the combination of the secondary power supply start-up parameters until the SYSOK signal 402 is output from the communication control unit 700 within a predetermined time. / Repeat the input. Through this series of operations, even if there is a failure to start up the communication device due to critical factors such as the order in which the power supply voltage is turned on, variation in LSI characteristics, and differences in the usage environment, communication is ensured by turning on the power again thereafter. It becomes possible to start up the apparatus in a normal state.
[0031]
As another embodiment of the present invention, the basic configuration is as described above, but the DELAY and RUMP parameters can be expanded from two patterns to N patterns. That is, the combination of the startup parameters of the secondary power source can be made in more detail and in a wide range (various types). It is also possible to expand the power supply voltage types from two types of + 5V and + 3V to N. As a result, the communication apparatus can be normally started up even if a more critical element such as use in a poor environment is added.
[0032]
【The invention's effect】
As described above, according to the present invention, when the apparatus does not start up normally, the secondary power supply is changed while changing the delay parameter at the digital level and the RUMP UP parameter at the analog level for starting up the secondary power supply. By turning off and on again, it is possible to reliably bring the communication device up to a normal state even if there are critical factors such as the order in which the power supply voltage is turned on, variations in LSI characteristics, and differences in the usage environment. There is an effect of becoming.
[Brief description of the drawings]
FIG. 1 is a system configuration diagram of an embodiment of the present invention.
2 is a configuration diagram of an apparatus start-up monitoring unit and an FET control unit in FIG. 1. FIG.
FIG. 3 is an example of a DELAY parameter waveform.
FIG. 4 is an example of a RUMP parameter waveform.
FIG. 5 is a flowchart of secondary power-off / re-on.
FIG. 6 is a diagram illustrating a combination example of secondary power supply startup parameters.
[Explanation of symbols]
100 Device Startup Monitoring Unit 101 Secondary Power Supply Startup Parameter Generation Unit 102 Device Startup Control Unit 200 FET Control Unit (+ 5V System)
201 DELAY section (digital level delay circuit)
202 DSEL section (digital level delay selection)
203 FET Boost Driver 204 RUMP Unit (Analog Level RUMP UP Circuit)
205 ASEL (Analog level RUMP UP selection)
220 FET controller (+ 3V system)
303 Primary power supply monitoring unit 304 Nch-FET unit (+ 5V system)
305 Nch-FET part (+ 3V system)
401 PWOK signal (primary power supply OK)
403 DELAY0 signal (+ 5V DELAY parameter)
404 DELAY1 signal (+ 3V system DELAY parameter)
405 RUMP0 signal (+ 5V RUMP parameter)
406 RUMP1 signal (+ 3V RUMP parameter)
509 + 5V LSI
510 + 3V LSI
511 ACK return unit 600 Power supply control unit 700 Communication control unit

Claims (2)

A power-on control system for an electronic device having a plurality of circuit blocks that operate with different power supply voltages,
Oite when the power is turned on again, the combination of parameters indicating a condition of a slope of rise of the parameter and the power supply voltage indicating the order of the power supply voltage is turned on, and controls so as to form a combination of different parameters from the last time the power is turned on the power-on control means only including,
The power-on control means sets the same combination of parameters between the power supply voltages when the power is first turned on, and performs power-on control when a signal indicating the rise of the circuit block has not arrived. A power-on control system characterized by performing . A power-on control method for an electronic device having a plurality of circuit blocks operating at different power supply voltages,
A power supply that controls the combination of the parameter indicating the power supply voltage turn-on order and the parameter indicating the slope condition of the power supply voltage rise with a combination of parameters different from the previous power-on. Including the input control step,
In the power-on control step, when the power is turned on for the first time, the combination of the parameters is set to be the same between the power supply voltages, and when the signal indicating the rise of the circuit block has not arrived, the power-on control step is performed. A power-on control method comprising:

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