JP4580488B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of polishing a semiconductor substrate.
[0002]
[Prior art]
With the recent miniaturization of semiconductor devices, element isolation using a shallow trench has attracted attention in place of element isolation using a silicon local oxidation (LOCOS) method. Hereinafter, element isolation using a shallow trench will be briefly described.
[0003]
An element formation region of the surface of the silicon substrate is covered with a mask pattern having a two-layer structure of a silicon oxide film and a silicon nitride film. Using this mask pattern as an etching mask, shallow grooves are formed on the surface of the silicon substrate. A silicon oxide film is formed on the silicon substrate to fill the shallow groove. At this time, if the filling is performed under the condition that the wide groove is filled with the silicon oxide film, the silicon oxide film tends to be thick on the wide element formation region and thin on the narrow element formation region.
[0004]
The silicon oxide film is polished to expose the silicon nitride film of the mask pattern and leave the silicon oxide film in the trench. The mask pattern is removed, and the element formation region of the silicon substrate is exposed. Through the steps so far, the plurality of element formation regions are electrically separated by silicon oxide embedded in the shallow trench. In this method, since the thickness of the silicon oxide film varies, a thick portion of the silicon oxide film tends to remain after polishing.
[0005]
If sufficient polishing is performed until the thick part of the silicon oxide film is completely removed, the upper surface of the silicon oxide film embedded in the shallow groove is bent downward, and so-called dishing occurs.
[0006]
In order to prevent polishing residue of the silicon oxide film, a method is known in which a thick portion of the silicon oxide film is partially removed before polishing. The partial removal of the silicon oxide film can be performed by covering other than the thick part with a resist pattern and dry etching the thick part of the silicon oxide film.
[0007]
[Problems to be solved by the invention]
In the method of removing the thick part of the silicon oxide film before polishing, a photolithography process and a dry etching process are newly added in order to partially remove the silicon oxide film. For this reason, it leads to an increase in manufacturing cost.
[0008]
An object of the present invention is to provide a method of manufacturing a semiconductor device using a polishing method that does not involve an increase in the photolithography process and hardly causes polishing residue.
[0009]
[Means for Solving the Problems]
According to one aspect of the invention,
Preparing a semiconductor substrate in which the surface waviness is measured, and the size of the waviness in which the waviness having a period equal to or greater than the first period is removed is inspected;
Forming a groove in the surface of the semiconductor substrate;
Filling the groove with a thin film made of a dielectric;
And polishing the thin film so that the thin film remains in the groove and the thin film on a region where the groove is not formed is removed .
[0010]
When a substrate that has passed the undulation inspection process is used, in-plane undulation of the film thickness after polishing the thin film can be reduced.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
It has been reported that the surface roughness of the silicon oxide film after polishing the silicon oxide film formed on the surface of the silicon substrate by a certain thickness is affected by the surface roughness of the underlying silicon substrate (C Shan Xu et al., “Effect of Silicon Front Surface Topography on Silicon Oxide Chemical Planarization”, ECS Letters, 1 (4) pp.181-183, 1998). The inventors of the present application thought that the undulation of the surface of the silicon substrate might affect the film thickness of the polished silicon oxide film. An evaluation experiment was conducted in order to clarify the relationship between the undulation of the surface of the silicon substrate and the variation in film thickness of the polished silicon oxide film. Before describing the examples of the present invention, evaluation experiments conducted by the present inventors will be described.
[0012]
First, two types of silicon substrates W1 and W2 obtained from different manufacturers were prepared, and irregularities on the surfaces of both were measured by an optical flatness measurement method. Here, a method is used in which the surface of the silicon substrate is irradiated with measurement light, and the tilt of the substrate surface is detected from fluctuations in the amount of reflected light when the silicon substrate is tilted back and forth and left and right. The measurement was performed on 420 points on one diameter of the silicon substrate surface.
[0013]
Of the undulations of the substrate surface thus measured, the undulation size is obtained by 6 times (6σ) the standard deviation of undulations obtained by removing the undulations of a certain period (upper limit value of the evaluation target undulation period). Evaluated. The reason why the magnitude of the waviness is evaluated by 6σ is that 6σ is considered to correspond to the maximum amplitude of the waviness.
[0014]
FIG. 1A shows the swell 6σ as a function of the upper limit value of the evaluation target swell period. The abscissa represents the upper limit value of the evaluation target undulation period in the unit “mm”, and the ordinate represents the undulation 6σ in the unit “μm”. Black circle symbols and white circle symbols in the figure indicate 6σ of undulations of the silicon substrates W1 and W2, respectively. In addition, the outer periphery vicinity area | region from the edge of a silicon substrate to 5 mm was excluded from the evaluation object .
[0015]
Assuming that the upper limit value of the evaluation target undulation period is x (mm) and the undulation 6σ is y (μm), the undulation 6σ of the silicon substrate W1 is substantially along a straight line of y = 0.0031x. Further, 6σ of the undulation of the silicon substrate W2 is substantially along a straight line of y = 0.004x.
[0016]
A silicon oxide film having a thickness of 1 μm was formed on the surfaces of the silicon substrates W1 and W2 by plasma enhanced chemical vapor deposition (PE-CVD). This silicon oxide film was polished for 60 seconds to flatten the surface. The average polishing amount at this time was 350 nm.
[0017]
The film thickness of the polished silicon oxide film was measured by an optical interference film thickness measurement method. The measurement location is almost the same as the location where the swell of the silicon substrate was measured.
[0018]
FIG. 1B shows 6σ of the undulation of the thickness of the silicon oxide film as a function of the upper limit value of the evaluation target undulation period. The horizontal axis represents the upper limit value of the evaluation target waviness cycle in the unit “mm”, and the vertical axis represents the 6σ of the waviness of the film thickness in the unit “μm”.
[0019]
The waviness of the silicon oxide film formed on the surface of the silicon substrate W1 with a period of 5 to 20 mm is smaller than that of the silicon substrate W2. From this result, it can be considered that the waviness on the surface of the silicon substrate having a period of 5 to 20 mm affects the waviness of the silicon oxide film after polishing.
[0020]
In FIG. 1A, only the swell in the direction along one diameter in the surface of the silicon substrate was evaluated. Next, the grounds on which the undulation in the direction along one diameter is representative of the undulation on the entire surface of the substrate will be described.
[0021]
The in-plane waviness of the silicon substrate was measured, and waviness with a waviness period of 20 mm or more was removed. The substrate surface was divided into a plurality of sites of a certain size, and the maximum value of the difference between the maximum value and the minimum value of the surface height (hereinafter referred to as the maximum amplitude of waviness) was determined for each site. . The maximum amplitude was obtained for each site size by varying the size of the site.
[0022]
FIG. 2 is a graph in which the largest maximum amplitude among the maximum amplitudes determined for each site is plotted as a function of the site diameter. The black circle symbol and the white circle symbol in the figure are measured values relating to the silicon substrates W1 and W2, respectively. As shown in FIG. 2, the maximum value of the maximum amplitude of the undulation of the silicon substrate W1 is smaller than that of the silicon substrate W2. This corresponds to the undulation results measured for a direction along one diameter in the surface of the silicon substrate. That is, by measuring the undulation in the direction along one diameter, it is possible to infer the state of in-plane undulation.
[0023]
Next, a result of forming a shallow trench type element isolation structure using the silicon substrates W1 and W2 will be described. First, a method for forming a shallow trench type element isolation structure will be described with reference to FIGS.
[0024]
As shown in FIG. 3A, a plurality of wide element formation regions 4 and a plurality of narrow element formation regions 5 are defined in the surface of a silicon substrate 1 having a diameter of 8 inches (about 20 cm). The wide element formation regions 4 are separated from each other by a wide element isolation region 6, and the narrow element formation regions 5 are separated from each other by a narrow element isolation region 7.
[0025]
A silicon oxide (SiO ₂ ) film 2 having a thickness of about 10 nm and a silicon nitride (SiN) film 3 having a thickness of about 100 to 250 nm are grown on the surface of the silicon substrate 1. Instead of the silicon nitride film 3, a silicon oxynitride (SiON) film may be used.
[0026]
As shown in FIG. 3B, the silicon oxide film 2 and the silicon nitride film 3 on the element isolation regions 6 and 7 are removed.
[0027]
As shown in FIG. 3C, the surface layer of the silicon substrate 1 is etched using the silicon nitride film 3 as an etching mask to form grooves 6a and 7a having a depth of 0.2 to 0.5 μm.
[0028]
As shown in FIG. 3D, the surface of the silicon substrate 1 exposed on the inner surfaces of the grooves 6a and 7a is thermally oxidized to form a silicon oxide film 10 having a thickness of 10 nm. A silicon oxide film 11 having a thickness of about 730 nm is deposited so as to cover the entire surface of the substrate. The silicon oxide film 11 is deposited by CVD using high-density plasma generated by inductive coupling or electron cyclotron resonance. As the source gas, for example, a gas obtained by diluting silane (SiH ₄ ) and oxygen (O ₂ ) with helium (He) is used. At this time, the flow rate of silane is 150 sccm, the flow rate of oxygen is 300 sccm, and the flow rate of helium is 400 sccm. The trenches 6 a and 7 a are filled with the silicon oxide film 11. The silicon oxide film 11 may be formed of phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), borosilicate glass (BSG), or the like.
[0029]
Unevenness appears on the surface of the silicon oxide film 11. The film thickness of the silicon oxide film 11 on the wide element formation region 4 is larger than the film thickness of the silicon oxide film 11 on the narrow element formation region 5. Further, the thickness t ₂ of the silicon oxide film 11 in the narrow groove 7a is larger than the thickness t ₁ of the silicon oxide film 11 in the wide groove 6a. For example, when the groove depth is 0.4 μm, the width of the narrow groove 7 a is 0.25 μm, and the thickness of the silicon oxide film 11 on the wide element formation region 4 is 730 nm, the thickness t ₂ is t ₁ . It becomes about 1.1 times.
[0030]
As shown in FIG. 4E, the first polishing is performed to planarize the surface of the silicon oxide film 11. In the first polishing, a relatively hard polishing cloth, for example, IC-1000 manufactured by Rodel, is used. The amount of compressive strain with respect to the compressive load of the polishing pad IC-1000 is about 0.02 μm · cm ² / g in a wet state. In addition, a slurry containing a hydroxyl group-containing dispersant or an amine-based dispersant containing abrasive grains made of a silica-based material or cesium oxide can be used as the slurry. Examples of such a slurry include Planerlite-6103 manufactured by Fujimi, SS-25 manufactured by Cabot, or Rodel 2371 manufactured by Rodel. When PLANERLITE-6103 or SS-25 is used, these are diluted with pure water.
[0031]
FIG. 5 shows a schematic cross-sectional view of the polishing apparatus. A polishing cloth 24 is attached to the upper surface of the base 25. The elastic member 20 is attached to the lower surface of the substrate holding base 21, and the substrate 1 to be polished is held on the lower surface thereof with the surface to be polished facing downward. The substrate holding base 21 is disposed at a position shifted from the support shaft 26 of the base 25. The support shaft 27 of the substrate holder 21 is parallel to the support shaft 26 of the base 25.
[0032]
The base 25 and the substrate holding base 21 are rotated about the support shafts 26 and 27, respectively, and the slurry is supplied onto the polishing cloth 24 from the slurry supply port 30. The supply amount of the slurry is, for example, 350 cc / min. Polishing is performed by lowering the substrate holder 21 and pressing the substrate 1 to be polished against the polishing pad 24. The elastic member 20 uniformly distributes the pressure applied to the surface to be polished within the substrate surface. The preferable range of the Young's modulus of the elastic member 20 is 1 × 10 ⁴ N / m ² to 1 × 10 ¹⁰ N / m ² , and the more preferable range is 1 × 10 ⁵ N / m ² to 1 × 10. ⁷ N / m ² .
[0033]
In the first polishing step, since a relatively hard polishing cloth is used, the polishing pressure applied to the thick silicon oxide film 11 on the wide element formation region 4 increases, and the portion is polished preferentially. In addition, it is preferable to use a polishing cloth having a compressive strain ratio to a compressive load of 0.06 μm · cm ² / g or less.
[0034]
As shown in FIG. 4F, the second polishing is performed using a polishing cloth softer than the polishing cloth used in the first polishing, for example, IC-1400 manufactured by Rodel. As the slurry, for example, SS-25 manufactured by Cabot Corp. diluted with pure water 1: 1 can be used. The supply amount of the slurry is, for example, 300 cc / min. Polishing is stopped when the silicon nitride film 3 is exposed.
[0035]
In the second polishing, since a soft polishing cloth is used, the difference between the pressure applied to the convex portion and the pressure applied to the concave portion is reduced. For this reason, the difference between the polishing rate of the convex portion and the polishing rate of the concave portion is reduced.
[0036]
The silicon oxide film 2 and the silicon nitride film 3 remaining on the element formation regions 4 and 5 are removed, and the surface of the silicon substrate 1 is exposed. In this way, a shallow trench type element isolation structure is formed.
[0037]
A shallow trench type element isolation structure was formed on the surfaces of the silicon substrates W1 and W2 by the method shown in FIGS. After the removal process of the silicon nitride film 3 shown in FIG. 4F, it was inspected whether or not the silicon nitride film 3 remained, and the substrate on which the silicon nitride film 3 remained was rejected. When the silicon substrate W1 was used, the defect rate was 0%, whereas when the silicon substrate W2 was used, the defect rate was 35%.
[0038]
In the case where the silicon substrate W2 is used, among the thick portions of the silicon oxide film 11 shown in FIG. 3D, those located in the portions that are lowered due to the waviness of the substrate surface are not easily polished. In particular, since the first polishing is performed using a hard polishing cloth, the silicon oxide film 11 located at a low portion is hardly polished.
[0039]
Since the second polishing is performed using a soft polishing cloth, the thick portion of the silicon oxide film 11 on the element formation region 4 left by the first polishing is not completely removed. If the silicon oxide film 11 remains on the element formation region 4, the silicon nitride film 3 therebelow is not removed and remains to the end.
[0040]
Since the surface of the silicon substrate W1 is small, insufficient polishing of the thick portion of the silicon oxide film 11 is unlikely to occur in the first polishing. For this reason, when the silicon substrate 11 is used, it is considered that the defect rate is small.
[0041]
In the conventional method, the thick portion of the silicon oxide film 11 is removed in advance from the state shown in FIG. The method described with reference to FIGS. 3 and 4 does not require this photolithography process, and thus the number of processes can be reduced.
[0042]
Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. First, before entering the wafer process, the surface waviness of the silicon substrate is inspected. If the manufacturer of the silicon substrate and the manufacturer of the semiconductor device are different, the swell inspection may be performed by any manufacturer. A silicon substrate in which waviness exceeds a reference value is rejected, and a silicon substrate having waviness below the reference value is accepted. Except for the unacceptable silicon substrate, a shallow trench type element isolation structure is formed on the surface of the acceptable silicon substrate by the method described with reference to FIGS. Since the silicon substrate having a large waviness is removed in advance, the defect occurrence rate of the shallow trench type element isolation structure can be reduced.
[0043]
For example, in the step of inspecting undulation, when the upper limit value of the evaluation target undulation period is x (mm) and the 6σ of undulation is y (μm), the upper limit value of the evaluation target undulation period is in the range of 5 mm to 20 mm. What satisfies y ≦ 0.0031x may be accepted and those not satisfying may be rejected. This is equivalent to the standard deviation σ (μm) of the undulation being 0.00052x or less in the range of the upper limit value 5 mm to 20 mm of the evaluation target undulation period. When this standard is used, the above-described silicon substrate W1 is accepted and the silicon substrate W2 is rejected.
[0044]
In the embodiment, the swell was evaluated at a plurality of points within the range of 5 mm to 20 mm. However, when viewing FIG. 1A, the upper limit value of the evaluation target swell period is one point within the range of 7 mm to 20 mm. Even if the swell is evaluated, it can be seen that the silicon substrates W1 and W2 can be distinguished. Note that the criterion for determining whether the standard deviation σ is acceptable is not limited to 0.00052x, and may be a criterion that does not reduce the yield in subsequent processes.
[0045]
Further, in the step of inspecting the undulation, as explained in FIG. 2, the substrate surface is divided into a plurality of sites, the maximum amplitude of the undulation is obtained for each site, and the maximum value of the obtained maximum amplitude is determined as a reference. You may compare with the value.
[0046]
Next, another pass / fail judgment method in the swell inspection process will be described with reference to FIG.
[0047]
FIG. 6A shows 6σ of the surface waviness of the silicon substrate W1 as a function of the upper limit value of the evaluation target waviness period. The triangle symbol, the circle symbol, and the square symbol in the figure indicate 6σ of the swell when the vicinity of the outer periphery from the edge of the substrate to 5 mm, 30 mm, and 50 mm is excluded from the evaluation target. It can be seen that there is a difference in swell 6σ in the range where the upper limit value of the evaluation target swell period is 20 mm to 40 mm.
[0048]
FIG. 6B shows 6σ of the waviness of the film thickness after polishing of the silicon oxide film formed on the surface of the silicon substrate W1 as a function of the upper limit value of the waviness period to be evaluated. The triangle symbol, the circle symbol, and the square symbol in the figure indicate 6σ of the swell when the vicinity of the outer periphery from the edge of the substrate to 5 mm, 30 mm, and 50 mm is excluded from the evaluation target. When the region from the outer periphery to 30 mm and 50 mm is excluded, 6σ shows a maximum value when the upper limit value of the evaluation target undulation period is around 25 mm. This seems to be an apparent problem by frequency analysis.
[0049]
When the upper limit value of the evaluation target undulation period is in the range of 20 mm to 40 mm, if the width of the region excluded from the evaluation target is different, the swell 6σ is also greatly different. This is considered to be because the waviness with a period of 20 to 40 mm exists in the vicinity of the outer periphery of the original silicon substrate.
[0050]
From this result, it is considered that waviness with a waviness period in the range of 20 mm to 40 mm also affects waviness of the film thickness after polishing of the silicon oxide film formed on the silicon substrate surface. According to the experiment results of the inventors of the present application, it was confirmed that the preferable value of 6σ of the surface waviness is 0.1 μm or less in the range where the upper limit value of the waviness period to be evaluated is 20 mm to 40 mm. That is, when the upper limit value of the evaluation target undulation cycle is in the range of 20 mm to 40 mm, a suitable value of 6 σ of the surface undulation should be 0.1 μm or less. This is equivalent to the standard deviation σ of the swell being 0.017 μm or less.
[0051]
In the above-described embodiment, 6σ is obtained by changing the upper limit value of the evaluation target undulation cycle within the range of 20 mm to 40 mm, but the upper limit value of the evaluation target undulation cycle may be set to one within the range of 20 mm to 40 mm. Good. In this case, the standard deviation of the waveform from which the waviness of the period equal to or higher than the upper limit value of the predetermined evaluation object waviness period is removed is obtained. If the obtained standard deviation is 0.017 μm or less, the semiconductor substrate may be accepted. Note that the standard deviation standard is not limited to 0.017 μm, and may be a standard that does not reduce the yield in subsequent processes.
[0052]
In the above-described embodiment, the embodiment has been described taking as an example the case where a shallow trench type element isolation structure is formed on the surface of a silicon substrate, but the same effect can be expected when a semiconductor substrate other than silicon is used. Moreover, not only when forming a shallow trench type element isolation structure, but also when a dielectric film, a semiconductor film, or a conductor film is deposited on the surface of a semiconductor substrate, and the deposited film is polished in advance, the substrate surface By checking the waviness of the film, the waviness of the film thickness of the film that has been deposited and then polished can be reduced.
[0053]
The above embodiment may be more generalized as follows. First, the surface of the semiconductor substrate is represented by one virtual plane using the least square method. Frequency analysis is performed on the undulation waveform on the surface of the semiconductor substrate with reference to the virtual plane. From this frequency analysis result, it is possible to determine whether or not the semiconductor substrate is acceptable. When the undulation is two-dimensional, the substrate surface may be represented by one virtual straight line using the least square method, and the undulation waveform of the surface may be obtained using this virtual straight line as a reference.
[0054]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0055]
【The invention's effect】
As described above, according to the present invention, a substrate with less undulation is used. As a result, the yield of products can be improved.
[Brief description of the drawings]
FIG. 1 is a graph showing 6σ of surface waviness of a silicon substrate and 6σ of film thickness waviness of a silicon oxide film formed and polished on the substrate.
FIG. 2 is a graph showing the maximum value of the maximum amplitude for each site of the undulation of the surface of the silicon substrate.
FIG. 3 is a sectional view (No. 1) of a substrate for explaining a method of forming a shallow trench type element isolation structure used in an embodiment.
FIG. 4 is a sectional view (No. 2) of the substrate for explaining a method of forming the shallow trench type element isolation structure used in the embodiment.
FIG. 5 is a schematic sectional view of a polishing apparatus.
FIG. 6 is a graph showing 6σ of surface waviness of a silicon substrate and 6σ of film thickness waviness of a silicon oxide film formed and polished on the substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxide film 3 Silicon nitride film 4 Wide element formation area 5 Narrow element formation area 6 Wide element isolation area 7 Narrow element isolation areas 10 and 11 Silicon oxide film 20 Elastic member 21 Substrate holding base 24 Polishing cloth 25 Base 26, 27 Support shaft 30 Slurry supply port

Claims (5)

Preparing a semiconductor substrate in which the surface waviness is measured, and the size of the waviness in which the waviness with a period equal to or greater than the first period is removed is inspected
Forming a groove in the surface of the semiconductor substrate;
Filling the groove with a thin film made of a dielectric;
Polishing the thin film so that the thin film remains in the groove and the thin film on a region where the groove is not formed is removed . In the polishing step, a first polishing step for polishing using a first polishing cloth, and a first polishing step for polishing using a polishing cloth softer than the first polishing cloth after the first polishing step. The method for manufacturing a semiconductor device according to claim 1 , further comprising a second polishing step. Preparing the semiconductor substrate comprises:
Measuring the undulation of the surface of the semiconductor substrate before inspection;
Obtaining a standard deviation of the waveform from which the waviness of the first period or more is removed;
Comparing the determined standard deviation with a standard value of the standard deviation, and determining whether the semiconductor substrate before inspection is acceptable;
Preparing the pre-inspection semiconductor substrate determined to be acceptable as the semiconductor substrate;
The manufacturing method of the semiconductor device of Claim 1 or 2 containing this. In the step of determining pass / fail, when the first period is 7 mm or more and 20 mm or less, the obtained standard deviation is σ (μm), and the first period is x (mm), σ is The method for manufacturing a semiconductor device according to claim 3, wherein the pre-inspection semiconductor substrate of 0.00052x or less is accepted. Preparing the semiconductor substrate comprises:
A step of representing a surface of a semiconductor substrate before inspection by one virtual plane or one virtual line using a least square method;
Frequency analysis of the undulation waveform of the surface of the semiconductor substrate before inspection based on the virtual plane or virtual line;
A step of determining pass / fail of the pre-inspection semiconductor substrate based on a result of frequency analysis;
Preparing the pre-inspection semiconductor substrate determined to be acceptable as the semiconductor substrate;
The manufacturing method of the semiconductor device of Claim 1 or 2 containing this.

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