JP4558273B2 - 低誘電率技術における銅のバイア - Google Patents
低誘電率技術における銅のバイア Download PDFInfo
- Publication number
- JP4558273B2 JP4558273B2 JP2002556914A JP2002556914A JP4558273B2 JP 4558273 B2 JP4558273 B2 JP 4558273B2 JP 2002556914 A JP2002556914 A JP 2002556914A JP 2002556914 A JP2002556914 A JP 2002556914A JP 4558273 B2 JP4558273 B2 JP 4558273B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- copper
- liner
- depositing
- copper interconnect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 239000010949 copper Substances 0.000 title claims abstract description 54
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 239000010410 layer Substances 0.000 claims abstract description 65
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 abstract description 11
- 238000005275 alloying Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000000463 material Substances 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910004353 Ti-Cu Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005382 thermal cycling Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910017945 Cu—Ti Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 240000008042 Zea mays Species 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001721 carbon Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
- Chemically Coating (AREA)
Description
Claims (4)
- 集積回路中に銅の相互接続を形成する方法であって、
(a)基板上に第1の銅相互接続層を堆積させ、パターン形成するステップと、
(b)前記第1の銅相互接続層上にSiLK(ダウケミカル社の登録商標)層を含む第1の低誘電率層間誘電体層を堆積させるステップと、
(c)前記第1の低誘電率層間誘電体層を貫通して、前記第1の銅相互接続層の表面で停止する、1組のバイアを形成するステップと、
(d)前記1組のバイア内の前記第1の低誘電率層間誘電体層および前記第1の銅相互接続層の表面にTiの第1のライナ層を堆積させるステップであって、前記TiにNの蒸気を徐々に加えるステップをさらに含み、前記第1のライナ層が層の上部に向かってNの勾配が増大するTi(N)から形成される、前記第1のライナ層を堆積させるステップと、
(e)前記1組のバイア内の前記第1のライナ層上にCVD TiNの第2のライナ層を堆積させるステップと、
(f)前記1組のバイア内の前記第2のライナ層上にTaおよびTaNから成る群から選択される第3のライナ層を堆積させるステップと、
(g)前記第3のライナ層上に第2の銅相互接続層を堆積させ、パターン形成するステップと、
を含む方法。 - 前記ステップ(b)ないし(g)を繰り返して、前記第2の銅相互接続層の上に1組の相互接続層を形成するステップをさらに含む、請求項1に記載の方法。
- 前記低誘電率層間誘電体層は前記SiLK層と前記第1の銅相互接続層の間にSiN層を含む、請求項1に記載の方法。
- 前記基板は表面に誘電体層が設けれたSi基板からなる、請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/759,015 US6383929B1 (en) | 2001-01-11 | 2001-01-11 | Copper vias in low-k technology |
PCT/US2001/049138 WO2002056342A2 (en) | 2001-01-11 | 2001-12-19 | Copper vias in low-k technology |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004525504A JP2004525504A (ja) | 2004-08-19 |
JP4558273B2 true JP4558273B2 (ja) | 2010-10-06 |
Family
ID=25054057
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002556914A Expired - Fee Related JP4558273B2 (ja) | 2001-01-11 | 2001-12-19 | 低誘電率技術における銅のバイア |
Country Status (10)
Country | Link |
---|---|
US (1) | US6383929B1 (ja) |
EP (1) | EP1397830B1 (ja) |
JP (1) | JP4558273B2 (ja) |
KR (1) | KR100562630B1 (ja) |
CN (1) | CN1256760C (ja) |
AT (1) | ATE457081T1 (ja) |
AU (1) | AU2002241651A1 (ja) |
DE (1) | DE60141254D1 (ja) |
TW (1) | TWI245365B (ja) |
WO (1) | WO2002056342A2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6569751B1 (en) * | 2000-07-17 | 2003-05-27 | Lsi Logic Corporation | Low via resistance system |
US7327033B2 (en) * | 2004-08-05 | 2008-02-05 | International Business Machines Corporation | Copper alloy via bottom liner |
US7361930B2 (en) * | 2005-03-21 | 2008-04-22 | Agilent Technologies, Inc. | Method for forming a multiple layer passivation film and a device incorporating the same |
US7279411B2 (en) * | 2005-11-15 | 2007-10-09 | International Business Machines Corporation | Process for forming a redundant structure |
US7902613B1 (en) * | 2008-01-28 | 2011-03-08 | Cadence Design Systems, Inc. | Self-alignment for semiconductor patterns |
CN102623437B (zh) * | 2012-04-06 | 2017-05-31 | 上海集成电路研发中心有限公司 | 硅通孔结构及其制造方法 |
US8835305B2 (en) | 2012-07-31 | 2014-09-16 | International Business Machines Corporation | Method of fabricating a profile control in interconnect structures |
US9881798B1 (en) | 2016-07-20 | 2018-01-30 | International Business Machines Corporation | Metal cap integration by local alloying |
US9905459B1 (en) * | 2016-09-01 | 2018-02-27 | International Business Machines Corporation | Neutral atom beam nitridation for copper interconnect |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07283219A (ja) * | 1994-04-13 | 1995-10-27 | Sanyo Electric Co Ltd | 半導体装置および半導体装置の製造方法および半導体装 置の製造装置 |
US6475912B1 (en) * | 1998-06-01 | 2002-11-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield |
US6245662B1 (en) * | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
US6080669A (en) * | 1999-01-05 | 2000-06-27 | Advanced Micro Devices, Inc. | Semiconductor interconnect interface processing by high pressure deposition |
US6221757B1 (en) | 1999-01-20 | 2001-04-24 | Infineon Technologies Ag | Method of making a microelectronic structure |
US6146517A (en) * | 1999-05-19 | 2000-11-14 | Infineon Technologies North America Corp. | Integrated circuits with copper metallization for interconnections |
US6303490B1 (en) * | 2000-02-09 | 2001-10-16 | Macronix International Co., Ltd. | Method for barrier layer in copper manufacture |
JP2001274160A (ja) * | 2000-03-24 | 2001-10-05 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
-
2001
- 2001-01-11 US US09/759,015 patent/US6383929B1/en not_active Expired - Fee Related
- 2001-12-19 EP EP01988335A patent/EP1397830B1/en not_active Expired - Lifetime
- 2001-12-19 DE DE60141254T patent/DE60141254D1/de not_active Expired - Lifetime
- 2001-12-19 JP JP2002556914A patent/JP4558273B2/ja not_active Expired - Fee Related
- 2001-12-19 WO PCT/US2001/049138 patent/WO2002056342A2/en active IP Right Grant
- 2001-12-19 AT AT01988335T patent/ATE457081T1/de not_active IP Right Cessation
- 2001-12-19 AU AU2002241651A patent/AU2002241651A1/en not_active Abandoned
- 2001-12-19 CN CNB018218954A patent/CN1256760C/zh not_active Expired - Fee Related
- 2001-12-19 KR KR1020037009001A patent/KR100562630B1/ko not_active IP Right Cessation
-
2002
- 2002-01-08 TW TW091100149A patent/TWI245365B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6383929B1 (en) | 2002-05-07 |
KR20030071798A (ko) | 2003-09-06 |
WO2002056342A3 (en) | 2004-01-08 |
AU2002241651A1 (en) | 2002-07-24 |
EP1397830B1 (en) | 2010-02-03 |
ATE457081T1 (de) | 2010-02-15 |
WO2002056342A2 (en) | 2002-07-18 |
DE60141254D1 (de) | 2010-03-25 |
KR100562630B1 (ko) | 2006-03-20 |
TWI245365B (en) | 2005-12-11 |
CN1256760C (zh) | 2006-05-17 |
CN1545726A (zh) | 2004-11-10 |
EP1397830A4 (en) | 2009-03-11 |
EP1397830A2 (en) | 2004-03-17 |
JP2004525504A (ja) | 2004-08-19 |
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