JP4556125B2 - Encoding apparatus and method, decoding apparatus and method, image processing system, recording medium, and program - Google Patents

Description

The present invention relates to an encoding apparatus and method, a decoding apparatus and method, an image processing system , a recording medium, and a program, and in particular, an encoding apparatus and method, a decoding apparatus and method, and an image that prevent unauthorized copying using an analog signal. The present invention relates to a processing system , a recording medium, and a program.

  2. Description of the Related Art In recent years, digital recording / reproducing apparatuses that record content such as television programs on a recording medium such as an HD (hard disk) or a DVD (Digital Versatile Disk) with a digital signal have been rapidly spread.

  With the widespread use of digital recording and playback devices that use HD and DVD as recording media, viewers can easily record TV programs and the like on recording media with high quality.

  On the other hand, with the widespread use of digital recording and playback devices, there is also an aspect that it becomes easier to illegally copy content such as TV programs and movies sold on DVDs.

  FIG. 1 shows an example of the configuration of an image processing system that reproduces content recorded on a recording medium, displays the content on a display, and records the reproduced content on another recording medium.

  In FIG. 1, an image processing system 1 reproduces an image signal of content recorded on a recording medium such as an optical disc such as a DVD, and outputs an analog image signal Van obtained as a result. A display 12 that displays the analog image signal Van as an image, and a recording device 13 that records the analog image signal Van on a recording medium such as an optical disk using the analog image signal Van output from the playback device 11.

  The playback device 11 includes a decoding unit 21 and a D / A (Digital-to-Analog) conversion unit 22. The decoding unit 21 decodes an encoded digital image signal read from a recording medium (not shown) and supplies the resulting digital image signal to the D / A conversion unit 22. The D / A conversion unit 22 converts the digital image signal supplied from the decoding unit 21 into an analog signal, and outputs an analog image signal Van obtained as a result.

  The display 12 is composed of, for example, a CRT (Cathode-Ray Tube), an LCD (Liquid Crystal Display), or the like, and displays the analog image signal Van from the D / A converter 22 as an image. As a result, the user can view an image corresponding to the image signal recorded on the recording medium.

  The analog image signal Van output from the playback device 11 is also supplied (input) to the recording device 13.

  The recording device 13 includes an A / D (Analog-to-Digital) conversion unit 31, an encoding unit 32, and a recording unit 33, and records an input analog image signal Van on a recording medium (not shown) such as an optical disk. To do.

  An analog image signal Van output from the playback device 11 is input to the A / D converter 31. The A / D converter 31 converts the input analog image signal Van into a digital signal and supplies the resulting digital image signal Vdg to the encoder 32. The encoding unit 32 encodes the digital image signal Vdg from the A / D conversion unit 31 and supplies the encoded digital image signal Vcd obtained as a result to the recording unit 33. The recording unit 33 records the encoded digital image signal Vcd on a recording medium.

  In the image processing system 1 configured as described above, an image signal can be recorded on a recording medium different from the reproduced recording medium by using the analog image signal Van output from the reproducing device 11. In other words, the content (image signal) may be illegally copied using the analog image signal Van output from the playback device 11.

  Conventionally, in order to prevent unauthorized copying using such an analog image signal Van, when copyright protection is performed, the analog image signal Van is output after being scrambled or output of the analog image signal Van It has been proposed to prohibit (see, for example, Patent Document 1).

  In addition, a noise information generation unit is provided in either or both of the compression / decoding unit on the reproduction side and the compression / encoding unit on the recording side, and noise information that cannot be identified at the time of image reproduction is embedded in the digital video data. Thus, although copying itself is possible, a digital video apparatus has been proposed in which an image deteriorates remarkably when repeated a plurality of times, thereby substantially limiting the number of copies (see, for example, Patent Document 2).

  However, the method of scrambling the analog image signal Van and outputting it, or prohibiting the output of the analog image signal Van as in Patent Document 1 described above can prevent unauthorized copying, but the display 12 is normal. There arises a problem that the image cannot be displayed.

  Further, as in the above-described Patent Document 2, in the method of embedding noise information in the reproduction side compression decoding unit or the recording side compression encoding unit, a noise information generation unit and a circuit for embedding the noise information are required, and the circuit scale is increased. There is a problem that increases.

  Therefore, a method for preventing unauthorized copying using an analog image signal without causing inconvenience such as an image not being displayed or an increase in circuit scale has been proposed by the present applicant (for example, (See Patent Document 3).

JP 2001-245270 A Japanese Patent Laid-Open No. 10-289522 Japanese Patent Application Laid-Open No. 2004-289685

  In the method described in Patent Document 3, attention is paid to analog noise such as a phase shift of a digital image signal obtained by A / D conversion of the analog image signal, and the digital image signal is encoded focusing on the analog noise. By doing this, it is impossible to copy while maintaining good quality without degrading the quality of the image before copying, thereby preventing unauthorized copying using analog image signals, but the distribution of digital content In recent years, the proposal of another method for preventing unauthorized copying as described above has been demanded.

  The present invention has been made in view of such a situation, and makes it possible to prevent unauthorized copying using an analog signal.

The encoding apparatus according to the present invention sorts each pixel in accordance with block dividing means for dividing the first image included in the input image data into a plurality of blocks, and the pixel value of each pixel constituting the block. together, sorting order information indicating the sorting results when sorting, and a sort order calculating means for calculating the maximum value and the minimum value of the pixel values of the pixels constituting the block from the maximum and minimum values, the magnitude of the pixel values Based on the sort order information, the pixel value generating means for generating the predicted pixel value of each pixel constituting the block and the predicted pixel value generated by the pixel value generating means are sorted according to the sort order information. reverse sorting means for inversely sorted before spatial phase of each pixel constituting are sorted, the difference calculating a difference data between the predicted pixel value of the pixel value and the inverse-sorting of the pixels constituting the block A data calculating means, characterized in that it comprises an encoding means for encoding the differential data.

  The encoding device can further include noise adding means for adding noise to the input image data.

  The encoding means can encode the difference data by performing DCT (Discrete Cosine Transform) conversion on the difference data and quantizing the DCT coefficient obtained as a result.

The pixel value generation means can calculate a straight line using the maximum value and the minimum value, and let the pixel value obtained by the straight line be the predicted pixel value of each pixel constituting the block .

The pixel value obtained by a straight line can be a pixel value on the straight line .

The input image data includes the second image . When the second image is divided into a plurality of blocks, storage means for storing the sort order information of each of the plurality of blocks of the second image, and the sort order calculation A sort order extraction means for extracting the sort order information closest to the sort order information calculated by the means from the sort order information stored in the storage means, and the reverse sort means is extracted by the sort order extraction means. Based on the sort order information, the predicted pixel value generated by the pixel value generating means can be reverse-sorted into the spatial phase before each pixel constituting the block is sorted.

Sorting order information, the maximum and minimum values, and by the encoding means may further include output means for outputting the difference data encoded.

The second image can be the top image of the input image data .

The encoding method of the present invention sorts each pixel in accordance with a block division step for dividing the first image included in the input image data into a plurality of blocks, and the size of the pixel value of each pixel constituting the block. together, sorting order information indicating the sorting results when sorting, and a sort order calculating a maximum value and the minimum value of the pixel values of the pixels constituting the block from the maximum and minimum values, the magnitude of the pixel values Based on the sort order information, the pixel value generation step that generates the predicted pixel value of each pixel that constitutes the block and the predicted pixel value that is generated in the pixel value generation step are sorted according to the sort order information. reverse sorting step for inversely sorted before spatial phase of each pixel is sorted constituting the difference between the predicted pixel value of the pixel value after the inverse sorting of the pixels constituting the block And the difference data calculating step of calculating data, characterized in that it comprises an encoding step of encoding the differential data.

According to a first recording medium of the present invention , a computer is caused to divide a first image included in input image data into a plurality of blocks according to a block dividing step and a pixel value of each pixel constituting the block. as well as sorting each pixel, sort order information indicating the sorting results when sorting, and a sort order calculating a maximum value and the minimum value of the pixel values of the pixels constituting the block from the maximum and minimum values The pixel value generation step for generating the predicted pixel value of each pixel constituting the block, sorted according to the size of the pixel value, and the predicted pixel value generated in the pixel value generation step are used as the sort order information. based on the inverse sorting step for inversely sorted before spatial phase of each pixel constituting the block is sorted, the pixel value reverse sorting of the pixels constituting the block And differential data calculation step of calculating the difference data between the predicted pixel value of a computer-readable recording medium recording a program for executing an encoding step of encoding the differential data.

According to a first program of the present invention, a computer divides a first image included in input image data into a plurality of blocks, and a block division step according to the pixel value of each pixel constituting the block. as well as sorting the pixel, sort order information indicating the sorting results when sorting, and a sort order calculating a maximum value and the minimum value of the pixel values of the pixels constituting the block from the maximum and minimum values, Based on the sort order information, the pixel value generation step for generating the predicted pixel value of each pixel constituting the block, sorted according to the size of the pixel value, and the predicted pixel value generated in the pixel value generation step Te, reverse sorting step for inversely sorted before spatial phase of each pixel constituting the block is sorted, the pixel values of the pixels constituting the block opposite saw And differential data calculation step of calculating the difference data between the predicted pixel value after the difference data is a program for executing an encoding step of encoding.

In the encoding apparatus and method, the first recording medium, and the first program of the present invention, the first image included in the input image data is divided into a plurality of blocks, and the pixel value of each pixel constituting the block with each pixel according to the size it is sorted in the sort order information representative of the sort result when sorted, and the maximum value and the minimum value of the pixel values of the pixels constituting the block are calculated. Then, from the maximum value and the minimum value, the predicted pixel value of each pixel constituting the block, which is sorted according to the size of the pixel value, is generated, and the generated predicted pixel value is based on the sort order information. The pixels constituting the block are reverse-sorted into the spatial phase before sorting , and difference data between the pixel value of each pixel constituting the block and the predicted pixel value after reverse sorting is calculated and encoded.

When the decoding apparatus of the present invention sorts each pixel according to the size of the pixel value of each pixel constituting one block, for one block among a plurality of blocks into which the first image is divided sorting order information indicating the sorting result, the maximum value and the minimum value of the pixel values of pixels constituting one block, and the prediction pixel of each pixel constituting the first block is generated using the maximum value and the minimum value An acquisition means for acquiring encoded difference data in which difference data between a value and a pixel value is encoded, and one block that is sorted according to the size of the pixel value from the maximum value and the minimum value Pixel value generating means for generating a predicted pixel value for each pixel; and reverse sorting means for reversely sorting the predicted pixel values generated by the pixel value generating means into a spatial phase before sorting based on the sort order information; , encoding difference Differential data decoding means for decoding the data to the difference data, characterized in that it comprises adding means for adding the prediction pixel value obtained as a difference data and the inverse sorting decoded by the differential data decoding means.

  The decoding apparatus can further include noise adding means for adding noise to the output of the adding means.

  The differential data decoding means dequantizes the encoded differential data, and performs inverse DCT (Discrete Cosine Transform) transformation on the dequantized encoded differential data, thereby decoding the encoded differential data into differential data. Can be made.

The pixel value generation means can calculate a straight line using the maximum value and the minimum value, and let the pixel value obtained by the straight line be the predicted pixel value of each pixel constituting the block .

Sort order information indicating a sorting result when each pixel is sorted according to the size of the pixel value of each pixel constituting each block of a plurality of blocks obtained by dividing a second image different from the first image Sort order extraction for extracting sort order information of one block out of a plurality of blocks obtained by dividing the second image stored in the storage means based on the storage means for storing and the sort order information of one block And the reverse sort means sorts the predicted pixel values generated by the pixel value generation means based on the sort order information of the blocks of the second image extracted by the sort order extraction means. You can reverse sort to the previous spatial phase.

The second image can be the top image of the input image data .

In the decoding method of the present invention, when each pixel is sorted according to the size of the pixel value of each pixel constituting one block of one block among a plurality of blocks into which the first image is divided sorting order information indicating the sorting result, the maximum value and the minimum value of the pixel values of pixels constituting one block, and the prediction pixel of each pixel constituting the first block is generated using the maximum value and the minimum value An acquisition step for acquiring encoded difference data in which difference data between a value and a pixel value is encoded, and one block that is sorted according to the size of the pixel value from the maximum value and the minimum value A pixel value generation step for generating a predicted pixel value for each pixel, and a reverse sort step for reversely sorting the predicted pixel value generated in the pixel value generation step into the spatial phase before the sorting based on the sort order information. Include a flop, and differential data decoding step of decoding the encoded difference data in the difference data, an adding step of adding the prediction pixel value of the differential data and after the inverse sorting decoded by the processing of the differential data decoding step It is characterized by.

A second recording medium of the present invention causes a computer, for one block of the plurality of blocks in which the first image is divided, according to the size of the pixel values of the pixels constituting the first block sorting order information indicating the sorting result when sorting the pixels, constituting the maximum value and the minimum value of the pixel values of pixels constituting one block, and one block is generated using the maximum value and the minimum value An acquisition step of acquiring encoded difference data in which difference data between a predicted pixel value and a pixel value of each pixel is encoded, and the maximum value and the minimum value are sorted according to the size of the pixel value, A pixel value generation step for generating a predicted pixel value of each pixel constituting one block, and a predicted pixel value generated in the pixel value generation step is reversed to a spatial phase before sorting based on the sort order information. Addition for adding the inverse sorting step of over preparative, and differential data decoding step of decoding the encoded difference data in the difference data, and the prediction pixel value obtained as a difference data and the inverse sorting decoded by the processing of the differential data decoding step A computer-readable recording medium on which a program for executing the steps is recorded .

According to the second program of the present invention, each of the plurality of blocks into which the first image is divided is stored in the computer according to the magnitude of the pixel value of each pixel constituting one block. sorting order information indicating the sorting result when sorting the pixel, the maximum value and the minimum value of the pixel values of pixels constituting one block, as well as constitute a block is generated using the maximum value and the minimum value An acquisition step of acquiring encoded difference data in which difference data between a predicted pixel value and a pixel value of each pixel is encoded, and the maximum value and the minimum value are sorted according to the size of the pixel value. A pixel value generation step for generating a predicted pixel value of each pixel constituting the block, and the predicted pixel value generated in the pixel value generation step as a spatial phase before sorting based on the sort order information. Reverse sorting step of sorting, adding step of adding the difference data decoding step of decoding the encoded difference data in the difference data, and the prediction pixel value obtained as a difference data and the inverse sorting decoded by the processing of the differential data decoding step Is a program for executing

In the decoding apparatus and method, the second recording medium, and the second program of the present invention, each pixel constituting one block of one block among a plurality of blocks into which the first image is divided Sort order information indicating the sorting result when each pixel is sorted according to the size of the pixel value, using the maximum and minimum values of the pixel values of the pixels constituting one block , and the maximum and minimum values Encoded difference data obtained by encoding difference data between the predicted pixel value and the pixel value of each pixel constituting one block generated in this way is acquired. Then, a predicted pixel value of each pixel constituting one block, which is sorted according to the size of the pixel value, is generated from the maximum value and the minimum value, and the generated predicted pixel value is included in the sort order information. Based on this, reverse sorting is performed on the spatial phase before sorting, the encoded differential data is decoded into differential data, and the decoded differential data and the predicted pixel value after reverse sorting are added.

The encoding unit of the first image processing system according to the present invention includes a block dividing unit that divides the first image included in the input image data into a plurality of blocks, and a pixel value of each pixel constituting the block. as well as sorting each pixel according, sort order information indicating the sorting results when sorting, and a sort order calculating means for calculating the maximum value and the minimum value of the pixel values of the pixels constituting the block, the maximum and minimum The pixel value generating means for generating the predicted pixel value of each pixel constituting the block, sorted according to the size of the pixel value from the value, and the predicted pixel value generated by the pixel value generating means based on the information, the inverse sorting means for inversely sorted before spatial phase of each pixel constituting the block is sorted, and the predicted pixel value of the pixel value after the inverse sorting of the pixels constituting the block And differential data calculation means for calculating the partial data, and having a coding means for coding the difference data.

In the first image processing system of the present invention, the first image included in the input image data is divided into a plurality of blocks, and each pixel is sorted according to the size of the pixel value of each pixel constituting the block. Rutotomoni, sort order information indicating the sorting result when sorted, and the maximum value and the minimum value of the pixel values of the pixels constituting the block are calculated. Then, from the maximum value and the minimum value, the predicted pixel value of each pixel constituting the block, which is sorted according to the size of the pixel value, is generated, and the generated predicted pixel value is based on the sort order information. The pixels constituting the block are reverse-sorted into the spatial phase before sorting , and difference data between the pixel value of each pixel constituting the block and the predicted pixel value after reverse sorting is calculated and encoded.

The decoding unit of the second image processing system according to the present invention depends on the size of the pixel value of each pixel constituting one block of one block among a plurality of blocks obtained by dividing the first image. sorting order information indicating the sorting result when sorting the pixels Te, the maximum value and the minimum value of the pixel values of pixels constituting one block, and one block is generated using the maximum value and the minimum value The acquisition means for acquiring encoded difference data obtained by encoding the difference data between the predicted pixel value and the pixel value of each of the constituent pixels, and the maximum value and the minimum value are sorted according to the size of the pixel value. A pixel value generating unit that generates a predicted pixel value of each pixel constituting one block, and a predicted pixel value generated by the pixel value generating unit, based on the sort order information; Reverse sort reverse And over DOO means, and differential data decoding means for decoding the encoded difference data in the difference data, that and an addition means for adding the prediction pixel value obtained as a difference data and the inverse sorting decoded by the differential data decoding means Features.

In the second image processing system of the present invention, each of the blocks of the plurality of blocks into which the first image is divided is set according to the magnitude of the pixel value of each pixel constituting one block. sorting order information indicating the sorting result when sorting the pixel, the maximum value and the minimum value of the pixel values of pixels constituting one block, as well as constitute a block is generated using the maximum value and the minimum value Encoded difference data obtained by encoding difference data between a predicted pixel value and a pixel value of each pixel is acquired. Then, a predicted pixel value of each pixel constituting one block, which is sorted according to the size of the pixel value, is generated from the maximum value and the minimum value, and the generated predicted pixel value is included in the sort order information. Based on this, reverse sorting is performed on the spatial phase before sorting, the encoded differential data is decoded into differential data, and the decoded differential data and the predicted pixel value after reverse sorting are added.

  According to the present invention, unauthorized copying using an analog signal can be prevented.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. It does not deny the existence of an invention that is added by correction.

The encoding device according to claim 1 (for example, the recording unit 141 in FIG. 2)
Block dividing means (for example, the blocking circuit 162 in FIG. 3) for dividing the first image included in the input image data into a plurality of blocks;
Sorting each pixel according to the size of the pixel value of each pixel constituting the block, sorting order information indicating the sorting result when sorting , and the maximum pixel value of the pixels constituting the block And a sort order calculating means for calculating the minimum value (for example, the sort order calculating circuit 163 in FIG. 3),
Pixel value generation means (for example, the prediction circuit 1 in FIG. 3) that generates the predicted pixel value of each pixel constituting the block, sorted according to the size of the pixel value, from the maximum value and the minimum value.
71)
Reverse sort means for reversely sorting the predicted pixel values generated by the pixel value generation means into a spatial phase before each pixel constituting the block is sorted based on the sort order information (for example, FIG. 3). Reverse sort circuit 172) ,
Difference data calculation means (for example, a subtracter 165 in FIG. 3) for calculating difference data between the pixel value of each pixel constituting the block and the predicted pixel value after reverse sorting ;
Coding means for coding the difference data (for example, block coding circuit 166 in FIG. 3).

The encoding device according to claim 2 is:
The image processing apparatus further includes noise adding means for adding noise to the input image data (for example, the A / D conversion unit 151 in FIG. 2 or the noise addition unit 291 in FIG. 25).

The encoding device according to claim 6 is:
The input image data includes a second image,
A storage means (e.g., a frame buffer 214 of FIG. 14) for storing said when the second image is divided into a plurality of blocks, said plurality of blocks each of the sorting order information of the second image,
Sort order extraction means (for example, sort order matching circuit 211 in FIG. 14) for extracting sort order information closest to the sort order information calculated by the sort order calculation means from the sort order information stored in the storage means; Further comprising
The reverse sort means (for example, the reverse sort circuit 212 in FIG. 14) , based on the sort order information extracted by the sort order extraction means, outputs the predicted pixel value generated by the pixel value generation means to the block It is characterized by reverse sorting to the spatial phase before sorting each pixel that constitutes.

The encoding device according to claim 7 is:
The sorting order information, the maximum and minimum values, and output means for outputting the difference data encoded by said encoding means (e.g., the data combining circuit 167 in FIG. 3) and further comprising a.

The encoding method according to claim 9 is:
A block division step for dividing the first image included in the input image data into a plurality of blocks (for example, step S1 in FIG. 11);
Sorting each pixel according to the size of the pixel value of each pixel constituting the block, sorting order information indicating the sorting result when sorting , and the maximum pixel value of the pixels constituting the block And a sort order calculating step for calculating a minimum value (for example, the process of step S2 in FIG. 11),
A pixel value generation step (step S3 in FIG. 11) for generating predicted pixel values of each pixel constituting the block, sorted according to the size of the pixel value, from the maximum value and the minimum value. When,
A reverse sorting step for reversely sorting the predicted pixel values generated in the pixel value generating step into a spatial phase before each pixel constituting the block is sorted based on the sort order information (for example, FIG. 11 In step S4),
A difference data calculation step for calculating difference data between the pixel value of each pixel constituting the block and the predicted pixel value after reverse sorting (for example, the process of step S5 in FIG. 11);
And an encoding step for encoding the difference data (for example, the process of step S6 in FIG. 11).

The recording medium program according to claim 10 and the specific example of each step of the program according to claim 11 are the same as the specific example in the embodiment of the invention of each step of the encoding method according to claim 9. is there.

The decoding device according to claim 12 is provided.
The sort result when each pixel is sorted according to the size of the pixel value of each pixel constituting the one block for one block among a plurality of blocks into which the first image is divided Sort order information,
A maximum value and a minimum value of pixel values of pixels constituting the one block;
And obtaining means for obtaining encoded difference data obtained by encoding difference data between a predicted pixel value of each pixel constituting the one block generated using the maximum value and the minimum value and the pixel value ( For example, the data decomposition circuit 182) of FIG.
Pixel value generation means (for example, a prediction circuit 191 in FIG. 12) that generates a predicted pixel value of each pixel constituting the one block, sorted according to the size of the pixel value, from the maximum value and the minimum value. )When,
Reverse sort means (for example, reverse sort circuit 192 in FIG. 12) for reverse sorting the predicted pixel values generated by the pixel value generation means into the spatial phase before sorting based on the sort order information;
Differential data decoding means (for example, block decoding circuit 184 in FIG. 12) for decoding the encoded differential data into the differential data;
And adding means (for example, an adder 185 in FIG. 12) for adding the difference data decoded by the difference data decoding means and the predicted pixel value after reverse sorting .

The decoding device according to claim 13 is provided.
It further comprises noise adding means (for example, the D / A converter 156 in FIG. 2 or the noise adding section 293 in FIG. 27) for adding noise to the output of the adding means.

The decoding device according to claim 16 comprises:
Sorting order information indicating the sorting result of when the first image and a second image different from the plurality of divided blocks in each sorting the pixels according to the size of the pixel values of the pixels constituting the block Storage means for storing (for example, the frame buffer 214 of FIG. 14);
Sort order extracting means for extracting sort order information of one block among a plurality of blocks obtained by dividing the second image stored in the storage means based on the sort order information of the one block ( For example, it further includes a sort order matching circuit 211) of FIG.
The reverse sort means (for example, the reverse sort circuit 212 in FIG. 14) is generated by the pixel value generation means based on the sort order information of the block of the second image extracted by the sort order extraction means. The predicted pixel values are reverse-sorted into the spatial phase before sorting.

The decoding method according to claim 18 comprises:
The sort result when each pixel is sorted according to the size of the pixel value of each pixel constituting the one block for one block among a plurality of blocks into which the first image is divided Sort order information,
A maximum value and a minimum value of pixel values of pixels constituting the one block;
And an acquisition step of acquiring encoded difference data in which difference data between a predicted pixel value of each pixel constituting the one block generated using the maximum value and the minimum value and the pixel value is encoded ( For example, the process of step S21 in FIG.
A pixel value generation step (for example, step S22 in FIG. 13) that generates predicted pixel values of each pixel constituting the one block, sorted according to the size of the pixel value, from the maximum value and the minimum value. Processing) and
A reverse sorting step for reversely sorting the predicted pixel values generated in the pixel value generating step into a spatial phase before sorting based on the sort order information (for example, the process of step S23 in FIG. 13);
A differential data decoding step (for example, the process of step S24 in FIG. 13) for decoding the encoded differential data into the differential data;
An addition step (for example, step S25 in FIG. 13) of adding the difference data decoded by the difference data decoding step and the predicted pixel value after reverse sorting .

The recording medium program according to claim 19 and the specific example of each step of the program according to claim 20 are the same as the specific example in the embodiment of the invention of each step of the decoding method according to claim 18. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a block diagram showing a configuration example of an embodiment of an image processing system to which the present invention is applied.

  In FIG. 2, an image processing system 101 reproduces an image signal recorded on a recording medium 121 such as an optical disc such as a DVD and outputs an analog image signal Van1 obtained as a result. A display 112 that displays the analog image signal Van1 as an image and a recording device 113 that records the image signal on a recording medium 122 such as an optical disk using the analog image signal Van1 output from the playback device 111 are configured.

  The playback device 111 includes a decoding unit 131 and a D / A (Digital-to-Analog) conversion unit 132. The decoding unit 131 decodes (decodes) the encoded digital image signal read from the recording medium 121, and supplies the resulting decoded digital image signal Vdg 0 to the D / A conversion unit 132. The D / A conversion unit 132 converts the decoded digital image signal Vdg0 supplied from the decoding unit 131 into an analog signal, and outputs an analog image signal Van1 obtained as a result.

  Here, the analog image signal Van1 output from the playback device 111 (the D / A conversion unit 132 thereof) is a signal distortion (hereinafter referred to as analog distortion) that naturally occurs when the decoded digital image signal Vdg0 is converted into an analog signal. Is referred to as). For example, analog distortion includes distortion caused by removing high-frequency components when converted to an analog signal by the D / A converter 132, and the phase of the signal when converted to an analog signal by the D / A converter 132. There are distortions and the like caused by shifting. Note that methods for evaluating image deterioration (image quality) due to analog distortion include S / N (Signal-to-Noise) evaluation, visual evaluation (visual deterioration evaluation), and the like.

  The display 112 is configured by, for example, a CRT (Cathode-Ray Tube), an LCD (Liquid Crystal Display), or the like, and displays an image corresponding to the analog image signal Van1 from the D / A conversion unit 132. As a result, the user can view an image corresponding to the image signal recorded on the recording medium 121.

  The analog image signal Van1 (input image data) output from the playback device 111 is also supplied (input) to the recording device 113.

  The recording device 113 encodes the analog image signal Van1 from the reproduction device 111 into an encoded digital image signal Vcd1 and records it on the recording medium 122, and the encoding recorded on the recording medium 122 In order to confirm an image when the digital image signal Vcd1 is decoded and displayed on the display, a reproduction unit 142 (decoding device) that reproduces the encoded digital image signal Vcd1 and an image reproduced by the reproduction unit 142 The display 143 is configured to display.

  The recording unit 141 includes an A / D (Analog-to-Digital) conversion unit 151, an encoding unit 152, and a medium recording unit 153. The input analog image signal Van1 is converted into a digital signal and encoded. The encoded digital image signal Vcd1 is recorded on the recording medium 122. As a result, copying using the analog image signal Van1 from the playback device 111 is performed.

  An analog image signal Van1 output from the playback device 111 is input to the A / D converter 151. The A / D converter 151 converts the input analog image signal Van1 into a digital signal, and supplies the resulting digital image signal Vdg1 to the encoder 152.

  The encoding unit 152 encodes the digital image signal Vdg1 from the A / D conversion unit 151, and supplies the encoded digital image signal Vcd1 obtained as a result to the medium recording unit 153 and the reproduction unit 142 (decoding unit 155 thereof). To do. The medium recording unit 153 records the encoded digital image signal Vcd1 from the encoding unit 152 on the recording medium 122.

  As described above, the playback unit 142 is configured to display the encoded digital image signal Vcd1 recorded on the recording medium 122 when it is decoded and displayed on a display by a predetermined playback device (for example, the playback device 111). This is for confirming the image. Therefore, the playback unit 142 includes a decoding unit 155 and a D / A conversion unit 156 having the same configurations as the decoding unit 131 and the D / A conversion unit 132 of the playback device 111, respectively.

  The decoding unit 155 decodes (decodes) the encoded digital image signal Vcd1 from the encoding unit 152, and supplies the decoded digital image signal Vdg2 obtained as a result to the D / A conversion unit 156. The D / A converter 156 converts the decoded digital image signal Vdg2 supplied from the decoder 155 into an analog signal, and outputs the resulting analog image signal Van2 to the display 143.

  The display 143 is configured by, for example, a CRT (Cathode-Ray Tube), an LCD (Liquid Crystal Display), or the like, and displays an image corresponding to the analog image signal Van2 from the D / A conversion unit 156. Thereby, the user can confirm (view) an image when the encoded digital image signal Vcd1 recorded on the recording medium 122 is reproduced.

  In the recording apparatus 113 configured as described above, the encoded digital image signal Vcd1 is recorded on the recording medium 122 using the analog image signal Van1 from the reproducing apparatus 111, and the code recorded on the recording medium 122 is recorded. It is possible to confirm an image when the digitized digital image signal Vcd1 is reproduced on a predetermined reproduction device (for example, the reproduction device 111) and displayed on the display 112. Note that the encoding unit 152 or the decoding unit 155 processes the digital image signal Vdg1 or the encoded digital image signal Vcd1 input to each unit in units of frames.

  In the image processing system 101 of FIG. 2, an analog image signal output from the playback unit 142 is displayed on the display 112 when the playback device 111 plays back the recording medium 122 recorded (copied) by the recording device 113. The image quality (for example, the S / N ratio) of the image (based on the same analog image signal as Van2) is displayed on the display 112 when the copy source recording medium 121 is played back by the playback device 111 (by the analog image Van1). The image quality is significantly degraded from the image quality.

  Therefore, in the following, encoding and decoding are performed such that when an image signal is copied using the analog image signal Van1 output from the playback device 111, the image quality of the reproduced image signal is deteriorated. The encoding unit 152 and decoding unit 155 to be performed will be described in detail.

  FIG. 3 is a block diagram illustrating a configuration example of the first embodiment of the encoding unit 152 of the recording device 113 in FIG. 2.

  The encoding unit 152 includes an input terminal 161, a blocking circuit 162, a sort order calculation circuit 163, a predicted pixel value generation circuit 164, a subtractor 165, a block encoding circuit 166, a data synthesis circuit 167, and an output terminal 168. ing.

  The digital image signal Vdg1 from the A / D converter 151 (FIG. 2) is supplied to the blocking circuit 162 via the input terminal 161. The digital image signal Vdg1 is a signal corresponding to an image configured by a predetermined number of pixels such as 640 × 480 pixels (vertical × horizontal), for example, in which each pixel constituting the frame has a predetermined pixel value. .

  The blocking circuit 162 divides an image composed of a predetermined number of pixels into a plurality of blocks BL, and supplies them to the sort order calculation circuit 163 and the subtracter 165. Thereby, in the block forming circuit 162 and thereafter, each of the plurality of blocks BL divided by the block forming circuit 162 is set as the target block BLc, and the process is performed on the target block BLc. In the present embodiment, it is assumed that the size of the block BL is, for example, 8 × 8 pixels (horizontal direction × vertical direction).

  The sort order calculation circuit 163 rearranges the pixels constituting the target block BLc in descending order of pixel values. More specifically, the sort order calculation circuit 163 supplies the pixels constituting the target block BLc arranged in the raster order when supplied from the block forming circuit 162 in the order of increasing pixel values (hereinafter referred to as sort order). ) And the maximum value Vcdmax and the minimum value Vcdmin of the pixel values of the pixels constituting the target block BLc (parameters representing the feature amounts of the pixels constituting the target block BLc) are calculated. In addition, the sort order calculation circuit 163 has each pixel rearranged in the sort order where it exists in the spatial phase before the rearrangement (hereinafter referred to as the original spatial phase as appropriate) (that is, in the raster order). The sort order information Vcds representing that is calculated.

  The sort order calculation circuit 163 supplies the maximum value Vcdmax and the minimum value Vcdmin of the pixel values of the pixels constituting the target block BLc to the prediction circuit 171 and the data synthesis circuit 167, and the sort order information Vcds of the target block BLc is an inverse sort circuit. 172 and the data synthesis circuit 167.

  The predicted pixel value generation circuit 164 includes a prediction circuit 171 and an inverse sort circuit 172, and calculates the target block BLc from the maximum value Vcdmax and minimum value Vcdmin of the pixel values of the pixels constituting the target block BLc and the sort order information Vcds. The pixel value of each pixel that constitutes is calculated (generated).

  In the following, the pixel value of each pixel constituting the target block BLc calculated by the predicted pixel value generation circuit 164 is referred to as a predicted pixel value, and the target block BLc based on the digital image signal Vdg1 input from the input terminal 161 is configured. The pixel value of each pixel is referred to as an input pixel value.

  The prediction circuit 171 is supplied with the maximum value Vcdmax and the minimum value Vcdmin of the pixel values of the pixels constituting the block of interest BLc from the sort order calculation circuit 163. The prediction circuit 171 calculates a straight line using the maximum value Vcdmax and the minimum value Vcdmin, and supplies the pixel value obtained by the straight line to the inverse sort circuit 172 as a predicted pixel value of each pixel constituting the target block BLc. . Note that the predicted pixel values obtained here are sorted according to the size of the pixel values.

  Based on the sort order information Vcds from the sort order calculation circuit 163, the reverse sort circuit 172 rearranges the predicted pixel values from the prediction circuit 171 into the original spatial phase (raster order) (the spatial phase before the sorting). Reverse sort). Then, the inverse sort circuit 172 supplies the predicted pixel values rearranged to the original spatial phase (arranged in the spatial phase before being sorted) to the subtracter 165.

  The subtractor 165 calculates difference data for each pixel constituting the target block BLc and supplies the difference data to the block encoding circuit 166. That is, the subtracter 165 subtracts the predicted pixel value from the reverse sort circuit 172 from the input pixel value from the blocking circuit 162 for each pixel constituting the block of interest BLc, and calculates the difference data obtained as a result of the block code. To the circuit 166.

  The block encoding circuit 166 encodes the difference data of each pixel constituting the target block BLc from the subtracter 165. That is, the block encoding circuit 166 performs DCT conversion on the difference data of each pixel constituting the target block BLc supplied from the subtracter 146, and quantizes the DCT coefficient obtained as a result. Further, the block coding circuit 166 performs entropy coding (variable length coding) using, for example, a Huffman code on the quantized DCT coefficient, and supplies the encoded data Vcdo obtained as a result to the data synthesis circuit 167. . Note that the block encoding circuit 166 performs encoding to remove high-frequency components, as will be described later.

  The data synthesis circuit 167 includes the maximum value Vcdmax, the minimum value Vcdmin, and the sort order information Vcds from the sort order calculation circuit 163 and the encoded data Vcdo from the block encoding circuit 166 for a plurality of blocks BL constituting one frame. And is supplied (output) to the output terminal 168 as an encoded digital image signal Vcd1.

  The output terminal 168 outputs the encoded digital image signal Vcd1 supplied from the data synthesis circuit 167.

  The processing of the encoding unit 152 will be further described with reference to FIGS. 4 to 10.

  FIG. 4 shows an example in which the blocking circuit 162 divides an image corresponding to the digital image signal Vdg1 into a plurality of blocks BL.

  In the blocking circuit 162, for example, an image having a predetermined number of pixels such as 640 × 480 pixels is divided into a plurality of blocks BL of 8 × 8 pixels as shown in FIG. Each of the plurality of blocks BL is set as a target block BLc. Note that circles (◯) in FIG. 4 represent each pixel constituting the image.

  5 and 6 are diagrams for explaining the maximum value Vcdmax and minimum value Vcdmin of the pixels constituting the block of interest BLc and the sort order information Vcds calculated by the sort order calculation circuit 163. FIG.

  The target block BLc in which each pixel is arranged in the raster order is supplied from the blocking circuit 162 to the sort order calculation circuit 163. Therefore, when the pixel value of each pixel constituting the target block BLc is plotted with the horizontal axis representing the position of each pixel represented in the order of raster order 0 to 63 and the vertical axis representing the input pixel value of the pixel, for example, FIG. 5 As shown on the left side.

  The sort order calculation circuit 163 rearranges (sorts) the pixels constituting the target block BLc in descending order of input pixel values. In this case, as can be seen from the graph on the right side of FIG. 5 where the horizontal axis is the sort order (0 to 63) of each pixel and the vertical axis is the input pixel value of the pixel, the 0th input pixel value in the sort order is The maximum input pixel value Vcdmax in BLc is set, and the 63rd input pixel value in the sort order is the minimum input pixel value Vcdmin in the target block BLc.

  Further, the sort order calculation circuit 163 calculates sort order information Vcds indicating where each pixel rearranged in the sort order exists in the spatial phase before the rearrangement (that is, in the raster order). In FIG. 5, the sort order information Vcds is provided so that the order (sort order) after sorting the pixels is stored at the position of each pixel constituting the target block BLc.

  For example, the pixel at the upper left corner of the block of interest BLc surrounded by a square in the sort order information Vcds of FIG. 5 is associated with a sort order of “40”, and the position in the original spatial phase. This indicates that the sorting order of the pixels in the above is 40th. In addition, the sorting order of “0” is placed in the fourth pixel to the right and the second pixel below from the pixel at the upper left corner of the block of interest BLc, which is circled in the sorting order information Vcds of FIG. Are associated with each other, indicating that the sort order of the pixel at that position is 0th in the original spatial phase. That is, it represents that a pixel surrounded by a circle is a pixel having the maximum value Vcdmax of the pixel values of the pixel constituting the target block BLc.

  Accordingly, each pixel constituting the target block BLc rearranged in the sort order can be returned to the original spatial phase (raster order) by using the sort order information Vcds as shown in FIG.

  The prediction circuit 171 calculates a straight line using the maximum value Vcdmax and the minimum value Vcdmin obtained by sorting the pixels constituting the target block BLc, and calculates the pixel value of each pixel constituting the target block BLc obtained by the straight line. The predicted pixel value is used.

  That is, as shown in FIG. 7, the prediction circuit 171 sets the horizontal axis as the sort order (0 to 63) of each pixel constituting the target block BLc, and the vertical axis indicates the input of each pixel constituting the target block BLc. When the pixel value is used, the maximum value Vcdmax is assigned to the 0th predicted pixel value in the sort order, and the minimum value Vcdmin is assigned to the 63rd predicted pixel value in the sort order. Further, the prediction circuit 171 sets the pixel values on the straight line connecting the two points of the maximum value Vcdmax point and the minimum value Vcdmin point to each of the predicted pixel values of the 1st to 62nd pixels in the sort order.

That is, the prediction pixel value P _Si in the sorting order Si in the prediction circuit 171 is obtained by the following equation.

P _Si = {Vcdmax × (N-1-Si) + Vcdmin × Si} / (N-1)

  Here, N represents the total number of pixels of the block of interest BLc (here, 64).

In FIG. 7, since Vcdmax = 238 and Vcdmin = 167, for example, the predicted pixel values P ₀ , P ₁ ,..., P ₆₂ , P _{63 in the} sort order 0, 1,. Is as follows.

P ₀ = {238 × (63-0) + 167 × 0} / 63 = 238
P ₁ = {238 × (63-1) + 167 × 1} / 63 = 237
・
P ₆₂ = {238 × (63−62) + 167 × 62} / 63 = 168
P ₆₃ = {238 × (63−63) + 167 × 63} / 63 = 167

  The predicted pixel value of each pixel constituting the target block BLc calculated as described above is supplied to the reverse sort circuit 172.

  As shown in FIG. 8, the reverse sort circuit 172 rearranges the predicted pixel values from the prediction circuit 171 into the original spatial phase (raster order) based on the sort order information Vcds from the sort order calculation circuit 163.

  The two-dimensional waveform shown on the lower side of FIG. 8 is a predicted pixel value of each pixel constituting the target block BLc in which the predicted pixel values according to the sort order from the prediction circuit 171 are rearranged in the original spatial phase (raster order). (Hereinafter referred to as a predicted waveform). Here, the X axis represents the horizontal position of the pixel constituting the target block BLc, the Y axis represents the vertical position of the pixel constituting the target block BLc, and the Z axis is calculated by the prediction circuit 171. Represents the predicted pixel value. In the two-dimensional waveform on the lower side of FIG. 8, for example, the pixel at the upper left corner of the sort order information Vcds is arranged at the lower left corner (coordinate (0, 0)), and the target block BLc is The arrangement of the constituent pixels is different from the arrangement of the sort information Vcds shown in the upper right of FIG.

  The predicted pixel value of each pixel constituting the target block BLc rearranged in the original spatial phase by the reverse sort circuit 172 is supplied to the subtracter 165.

  Then, as shown in FIG. 9, the subtracter 165 subtracts the predicted pixel value from the input pixel value output from the blocking circuit 162 for each pixel constituting the block of interest BLc to obtain difference data. The difference data of each pixel constituting the target block BLc is supplied to the block encoding circuit 166. Hereinafter, the two-dimensional waveform represented by the input pixel value of each pixel constituting the target block BLc shown on the upper left side of FIG. 9 is referred to as an input waveform, and each pixel constituting the target block BLc shown on the lower side of FIG. A two-dimensional waveform represented by the difference data is referred to as a difference waveform.

  The block encoding circuit 166 encodes the difference data supplied from the subtracter 165 and supplies the encoded data Vcdo to the data synthesis circuit 167.

  That is, the block encoding circuit 166 performs DCT (Discrete Cosine Transform) conversion on the difference data of each pixel constituting the target block BLc supplied from the subtracter 165, and quantizes the DCT coefficient obtained as a result. To do. Here, when the DCT coefficient is quantized, the block encoding circuit 166 performs quantization using, for example, a quantization table for removing high frequency components as shown in FIG.

  Further, the block encoding circuit 166 performs entropy encoding (variable length encoding) using, for example, a Huffman code on the quantized DCT coefficient, and supplies the encoded data Vcdo obtained as a result to the data synthesis circuit 167. .

  Next, the encoding process of the encoding unit 152 in FIG. 3 will be described with reference to the flowchart in FIG. 11.

  First, in step S <b> 1, the blocking circuit 162 includes a plurality of images each composed of 8 × 8 pixels corresponding to the digital image signal Vdg <b> 1 supplied from the A / D converter 151 via the input terminal 161. Are supplied to the sort order calculation circuit 163 and the subtracter 165.

  In step S <b> 2, the sort order calculation circuit 163 sets one pixel BL of the plurality of blocks BL supplied from the blocking circuit 162 as the target block BLc, and sets each pixel constituting the target block BLc to a pixel value having a large pixel value. Sort in order. In step S2, the sort order calculation circuit 163 calculates the maximum value Vcdmax and minimum value Vcdmin of the pixel values of the pixels constituting the target block BLc, and the sort order information Vcds of the target block BLc. The calculated maximum value Vcdmax and minimum value Vcdmin are supplied to the prediction circuit 171 and the data synthesis circuit 167, and the sort order information Vcds is supplied to the reverse sort circuit 172 and the data synthesis circuit 167.

  In step S <b> 3, the prediction circuit 171 calculates a predicted pixel value for each pixel constituting the block of interest BLc by a straight line using the maximum value Vcdmax and the minimum value Vcdmin, and supplies the predicted pixel value to the reverse sort circuit 172.

  In step S4, the reverse sort circuit 172 calculates the predicted pixel value from the prediction circuit 171 based on the sort order information Vcds from the sort order calculation circuit 163 for each pixel constituting the target block BLc, based on the original spatial phase ( Sort (raster order) (reverse sort).

  In step S5, the subtractor 165 subtracts the predicted pixel value from the reverse sort circuit 172 from the input pixel value from the blocking circuit 162 for each pixel constituting the target block BLc, and thereby obtains the input pixel value and the predicted pixel. Difference data from the value is calculated and supplied to the block encoding circuit 166.

  In step S6, the block encoding circuit 166 encodes the difference data of each pixel constituting the target block BLc supplied from the subtractor 146, and supplies the encoded data Vcdo obtained as a result to the data synthesis circuit 167. . That is, in step S6, the block encoding circuit 166 performs DCT conversion on the difference data of each pixel constituting the target block BLc supplied from the subtractor 146, and quantizes the DCT coefficient obtained as a result. . Further, the block coding circuit 166 performs entropy coding (variable length coding) using, for example, a Huffman code on the quantized DCT coefficient, and supplies the encoded data Vcdo obtained as a result to the data synthesis circuit 167. .

  In step S <b> 7, the encoding unit 152 has processed all the blocks BL constituting the one-frame image supplied from the A / D conversion unit 151, i.e., all the blocks BL of the one-frame image are the target block. It is determined whether or not the above-described steps S2 to S6 have been performed as BLc.

  If it is determined in step S7 that all the blocks BL have not been processed, the process returns to step S2, and the block BL that has not been processed is set as the target block BLc. And the process of step S2 thru | or S7 is repeated with respect to the attention block BLc.

  On the other hand, if it is determined in step S7 that all blocks BL have been processed, the process proceeds to step S8, where the data synthesis circuit 167 outputs the encoded digital image signal Vcd1 for one frame via the output terminal 168. .

  After the process of step S8, the process proceeds to step S9, where the encoding unit 152 determines whether there is still an image of the frame to be processed, that is, whether the image of the frame to be processed next is supplied from the A / D conversion unit 151. judge.

  If it is determined in step S9 that there is still an image of a frame to be processed, the process returns to step S1 and the subsequent processing is repeated.

  On the other hand, if there is no image of the frame to be processed in step S9, that is, if the image of the frame to be processed next is not supplied from the A / D conversion unit 151, the processing ends.

  FIG. 12 is a block diagram illustrating a configuration example of the first embodiment of the decoding unit 155 of the recording device 113 in FIG.

  The decoding unit 155 includes an input terminal 181, a data decomposition circuit 182, a predicted pixel value generation circuit 183, a block decoding circuit 184, an adder 185, a block decomposition circuit 186, and an output terminal 187.

  The encoded digital image signal Vcd1 is supplied to the data decomposition circuit 182 from the encoding unit 152 via the input terminal 181.

  The data decomposing circuit 182 converts the encoded digital image signal Vcd1 into the maximum value Vcdmax and the minimum value Vcdmin (parameter) of the pixel values of each pixel constituting the block BL and the sort order of each of the plurality of blocks BL constituting one frame. The information Vcds and the encoded data Vcdo are each decomposed and acquired. Then, the data decomposition circuit 182 supplies the maximum value Vcdmax, the minimum value Vcdmin, and the sort order information Vcds of each of the plurality of blocks BL to the prediction pixel value generation circuit 183, and a code obtained by encoding the difference data of each pixel. The encrypted data Vcdo is supplied to the block decoding circuit 184.

  As a result, the prediction pixel value generation circuit 183 (prediction circuit 191 and inverse sort circuit 192), block decoding circuit 184, adder 185, and block decomposition circuit 185 after the data decomposition circuit 182 are similar to the encoding unit 152. The processing is performed with each of the plurality of blocks BL as the target block BLc.

  The predicted pixel value generation circuit 183 includes a prediction circuit 191 and an inverse sort circuit 192 that are similar to the prediction circuit 171 and the reverse sort circuit 172 of the prediction pixel value generation circuit 164 of the encoding unit 152 in FIG. From the maximum value Vcdmax and minimum value Vcdmin of the pixel values of the pixels constituting the target block BLc supplied from 182 and the sort order information Vcds, each of the constituents of the target block BLc arranged in the spatial phase before sorting A pixel value (predicted pixel value) of the pixel is calculated (generated).

  That is, the maximum value Vcdmax and the minimum value Vcdmin of the pixel values of the pixels constituting the target block BLc are supplied from the data decomposition circuit 182 to the prediction circuit 191. As described with reference to FIG. 7, the prediction circuit 191 calculates a straight line using the maximum value Vcdmax and the minimum value Vcdmin, and uses the pixel value obtained by the straight line as a predicted pixel value to the inverse sort circuit 192. Supply. Note that the predicted pixel values obtained by the prediction circuit 191 are sorted according to the size of the pixel values.

  The reverse sort circuit 192 rearranges the predicted pixel values from the prediction circuit 191 into the original spatial phase (raster order) based on the sort order information Vcds from the data decomposition circuit 182 (to the spatial phase before sorting). Reverse sort). Then, the inverse sort circuit 192 supplies the predicted pixel value rearranged in the original spatial phase to the adder 185.

  The block decoding circuit 184 decodes the encoded data Vcdo from the data decomposition circuit 182. That is, the block decoding circuit 184 configures the block of interest BLc by inversely quantizing the encoded data Vcdo from the data decomposition circuit 182 and performing inverse DCT transform on the inversely quantized encoded data Vcdo. Difference data for each pixel is calculated and supplied to the adder 185.

  The adder 185 adds the difference data from the block decoding circuit 184 and the predicted pixel value from the reverse sort circuit 192 for each pixel constituting the target block BLc, and adds each pixel constituting the target block BLc. Get the output pixel value. Then, the adder 185 supplies the output pixel value of each pixel constituting the target block BLc to the block decomposition circuit 186.

  The block decomposition circuit 186 returns the output pixel value of each pixel constituting the target block BLc supplied from the adder 185 to the position (raster order) on the frame before the division into a plurality of blocks BL. One frame is composed of a plurality of blocks BL. Then, the block decomposition circuit 186 supplies the decoded digital image signal Vdg2 as an image for one frame to the output terminal 187. The output terminal 187 outputs the decoded digital image signal Vdg2 from the block decomposition circuit 186 (to the D / A converter 156 (FIG. 2)).

  Next, the decoding process of the decoding unit 155 of FIG. 12 will be described with reference to the flowchart of FIG.

  First, in step S21, the data decomposing circuit 182 uses the encoded digital image signal Vcd1 supplied via the input terminal 181 for each of the pixels constituting the block BL of the plurality of blocks BL constituting one frame. The maximum value Vcdmax and minimum value Vcdmin of pixel values, sort order information Vcds, and encoded data Vcdo are each decomposed and acquired. In step S21, the data decomposition circuit 182 supplies the maximum value Vcdmax, the minimum value Vcdmin, and the sort order information Vcds of each of the plurality of blocks BL to the prediction pixel value generation circuit 183, and blocks the encoded data Vcdo. This is supplied to the decryption circuit 184.

  In step S22, one block BL of the plurality of blocks BL is set as the target block BLc. In step S22, the prediction circuit 191 calculates a straight line using the maximum value Vcdmax and the minimum value Vcdmin of the pixel values of each pixel constituting the target block BLc, and calculates a predicted pixel value from the straight line. This is supplied to the reverse sort circuit 192.

  In step S23, the reverse sort circuit 192 rearranges the predicted pixel values of the pixels constituting the target block BLc to the original spatial phase (raster order) based on the sort order information Vcds of the target block BLc (reverse sort). To do). In step S <b> 23, the inverse sort circuit 192 supplies the predicted pixel value rearranged to the original spatial phase to the adder 185.

  In step S24, the block decoding circuit 184 decodes the encoded data Vcdo of the block of interest BLc (performs inverse quantization and inverse DCT transform), and calculates difference data of each pixel constituting the block of interest BLc. The block decoding circuit 184 supplies the calculated difference data to the adder 185.

  In step S25, the adder 185 adds the difference data from the block decoding circuit 184 and the predicted pixel value from the reverse sort circuit 192 for each pixel constituting the target block BLc, and performs block decomposition as an output pixel value. Supply to circuit 186.

  In step S <b> 26, the block decomposition circuit 186 returns the output pixel value of each pixel constituting the target block BLc supplied from the adder 185 to a position on the frame before being divided into the plurality of blocks BL.

  In step S27, the decoding unit 155 determines whether or not processing has been performed for all the blocks BL constituting one frame, that is, whether or not all the blocks BL of the image of one frame have been set as the target block BLc. If it is determined in step S27 that all the blocks BL of one frame image have not been processed, the process returns to step S22, and the block BL that has not yet been set as the target block BLc is set as the target block BLc, and steps S22 to S27 are performed. The process is repeated.

  On the other hand, if it is determined in step S27 that all the blocks BL of the image of one frame have been processed, the process proceeds to step S28, and the block decomposition circuit 186 outputs the decoded digital image signal Vdg2 for one frame to the output terminal 187. (To the D / A converter 156).

  In step S29, the decoding unit 155 determines whether there is still an image of a frame to be processed, that is, whether an image of a frame to be processed next is supplied from the encoding unit 152.

  If it is determined in step S29 that there is still a frame image to be processed, the process returns to step S21, and the subsequent processing is repeated.

  On the other hand, in step S29, if there is no image of the frame to be processed, that is, if the image of the frame to be processed next is not supplied from the encoding unit 152, the processing ends.

  FIG. 14 is a block diagram illustrating a configuration example of the second embodiment of the encoding unit 152 of the recording device 113 in FIG. 2.

  In FIG. 14, portions corresponding to the configuration of the first embodiment of the encoding unit 152 illustrated in FIG. 3 are denoted with the same reference numerals, and description thereof is omitted.

  That is, the encoding unit 152 in FIG. 14 is configured in the same manner as the encoding unit 152 in FIG. 3 except that a prediction pixel value generation circuit 201 is provided instead of the prediction pixel value generation circuit 164 in FIG. ing.

  The predicted pixel value generation circuit 201 includes a prediction circuit 171, a sort order matching circuit 211, a reverse sort circuit 212, a data extraction circuit 213, and a frame buffer 214.

  The prediction circuit 171 receives the maximum value Vcdmax and the minimum value Vcdmin of the pixels constituting the target block BLc from the sort order calculation circuit 163 when each of the plurality of blocks BL constituting one frame is the target block BLc. Supplied. The prediction circuit 171 calculates a straight line using the maximum value Vcdmax and the minimum value Vcdmin, and supplies the pixel value obtained by the straight line to the inverse sort circuit 212 as a predicted pixel value of each pixel constituting the target block BLc. .

  Sort order information Vcds is supplied from the sort order calculation circuit 163 to the sort order matching circuit 211. When the frame having the target block BLc is the first frame (hereinafter referred to as the first frame), the sort order matching circuit 211 uses the sort order information Vcds supplied from the sort order calculation circuit 163 as it is, and the reverse sort circuit 212. And supplied to the data synthesis circuit 167. As will be described later, the sort information Vcds of all the blocks BL constituting the head frame is stored in the frame buffer 214, and index information Vcdi is attached as an index representing the block BL.

  On the other hand, when the frame having the target block BLc is not the first frame, the sort information matching circuit 211 supplies the sort information Vcds of all the blocks BL constituting the first frame and the sort order calculation circuit supplied from the frame buffer 214. From the sort information Vcds from 163, matching of the sort order is performed.

  That is, the sort order matching circuit 211 selects the closest sort order (represented by the sort information Vcds from the sort order calculation circuit 163) of the target block BLc (for all blocks BL of the first frame supplied from the frame buffer 214). The index representing the block BL having the extracted sort order is extracted from the sort order of all the blocks BL of the first frame (represented by the sort information Vcds) and supplied to the reverse sort circuit 212 and the data synthesis circuit 167 as index information Vcdi. Here, as a method for calculating the block BL of the first frame with the closest sort order, for example, the sum of the absolute differences of the values of the sort order information Vcds between the target block BLc and the block BL of the first frame is minimized. The block BL of the first frame is set as the closest block BL in the sort order.

  When the frame having the target block BLc is the first frame, the reverse sort circuit 212 calculates the predicted pixel value from the prediction circuit 171 based on the sort order information Vcds (index information Vcdi) from the sort order matching circuit 211. , Rearrange to the original spatial phase (raster order) (resort to the spatial phase before sorting).

  On the other hand, when the frame having the target block BLc is not the first frame, the reverse sort circuit 212 extracts the sort order information Vcds of the block BL indicated by the index information Vcdi from the sort order matching circuit 211 from the frame buffer 214. Then, the reverse sort circuit 212 rearranges (reverse sorts) the predicted pixel values from the prediction circuit 171 into the original spatial phase (raster order) based on the extracted sort order information Vcds.

  Then, the reverse sort circuit 212 supplies the predicted pixel value rearranged in the original spatial phase to the subtracter 165.

  When the frame having the target block BLc is the first frame, the data extraction circuit 213 outputs the encoded digital image signal Vcd1 (the maximum value Vcdmax of the pixel values of each pixel constituting the target block BLc and the output terminal 168). The sort order information Vcds of the target block BLc is extracted from the minimum value Vcdmin, the sort order information Vcds of the target block BLc, and the encoded data Vcdo of the target block BLc.

  The data extraction circuit 213 supplies the extracted sort order information Vcds of each block BL of the first frame to the frame buffer 214, and index information Vcdi is attached as an index representing the block BL. The data extraction circuit 213 does not perform the subsequent processing after supplying the sort information Vcds of all the blocks BL of the first frame to the frame buffer 214. That is, the data extraction circuit 213 performs no processing on the encoded digital image signal Vcd1 output from the data synthesis circuit 167 for frames other than the first frame.

  The frame buffer 214 stores sort order information Vcds for each of a plurality of blocks BL constituting one frame (first frame) supplied from the data extraction circuit 213, and sort order matching circuit 211 and reverse sort circuit as necessary. 212.

  Next, the encoding process of the encoding unit 152 in FIG. 14 will be described with reference to the flowchart in FIG.

  Since the processing of steps S41 to S43 is the same as the processing of steps S1 to S3 in FIG. 11, the description thereof is omitted.

  In step S44, the sort order matching circuit 211 determines whether the image of the frame having the block of interest BLc is the image of the first frame. If it is determined in step S44 that the image of the frame having the target block BLc is the image of the first frame, the process proceeds to step S45, where the sort order matching circuit 211 supplies the sort order information Vcds supplied from the sort order calculation circuit 163. Are supplied (output) to the reverse sort circuit 212 and the data synthesis circuit 167 as they are.

  After the process of step S45, the process proceeds to step S46, and the reverse sort circuit 212 converts the predicted pixel value from the prediction circuit 171 into the original space based on the sort order information Vcds (index information Vcdi) from the sort order matching circuit 211. Sort by phase (raster order) (reverse sort).

  In step S47, the subtractor 165 subtracts the predicted pixel value from the reverse sort circuit 172 from the input pixel value from the blocking circuit 162 for each pixel constituting the target block BLc, thereby predicting the input pixel value. Difference data from the pixel value is calculated and supplied to the block encoding circuit 166.

  In step S48, the block encoding circuit 166 encodes the difference data of each pixel constituting the target block BLc supplied from the subtracter 146, and outputs the encoded data Vcdo obtained as a result to the data synthesis circuit 167.

  In step S49, the data extraction circuit 213 supplies the encoded digital image signal Vcd1 (the maximum value Vcdmax and the minimum value Vcdmin of the pixel values of each pixel constituting the target block BLc, the sort order of the target block BLc) supplied to the output terminal 168. The sort order information Vcds of the block of interest BLc is extracted from the information Vcds and the encoded data Vcdo of the block of interest BLc).

  In step S50, the frame buffer 214 stores the sort order information Vcds of the target block BLc supplied from the data extraction circuit 213, and attaches index information Vcdi as an index representing the block BL (the data extraction circuit 213 receives the target The sort order information Vcds of the block BLc is stored in the frame buffer 214, and index information Vcdi is added as an index representing the block BL).

  On the other hand, if it is determined in step S44 that the target block BLc currently processed is not the first frame, the process proceeds to step S51, and the sort information matching circuit 211 configures the first frame supplied from the frame buffer 214. Sort order matching is performed from the sort information Vcds of all the blocks BL and the sort information Vcds of the target block BLc from the sort order calculation circuit 163.

  That is, the sort order matching circuit 211 extracts the sort order closest to the sort order of the block of interest BLc from the sort orders of all the blocks BL of the first frame, and displays an index representing the block BL having the extracted sort order as index information. This is supplied as Vcdi to the reverse sort circuit 212 and the data synthesis circuit 167.

  In step S52, the reverse sort circuit 212 extracts the sort order information Vcds of the block BL represented by the index information Vcdi from the sort order matching circuit 211 from the frame buffer 214. Then, the reverse sort circuit 212 rearranges (reverse sorts) the predicted pixel values from the prediction circuit 171 into the original spatial phase (raster order) based on the extracted sort order information Vcds.

  In step S <b> 53, the subtractor 165 calculates difference data between the input pixel value and the predicted pixel value and supplies the difference data to the block encoding circuit 166 in the same manner as in step S <b> 47 described above.

  In step S54, the block encoding circuit 166 encodes the difference data of each pixel constituting the block of interest BLc supplied from the subtractor 146, similarly to the processing in step S48 described above, and the encoded data obtained as a result. Vcdo is output to the data synthesis circuit 167.

  After the process of step S50 or S54, the process proceeds to step S55, in which the encoding unit 152 has processed all the blocks BL constituting one frame image supplied from the A / D conversion unit 151, that is, one frame. It is determined whether or not the above-described steps S42 to S54 have been performed with all blocks BL of the image as the target block BLc.

  If it is determined in step S55 that all the blocks BL have not been processed, the process returns to step S42, and the block BL that has not been processed is set as the target block BLc. And the process of step S42 thru | or S54 is repeated with respect to attention block BLc.

  On the other hand, if it is determined in step S55 that all the blocks BL have been processed, the process proceeds to step S56, where the encoding unit 152 determines that there is still an image of a frame to be processed, that is, an image of a frame to be processed next. It is determined whether it is supplied from the A / D converter 151 or not.

  If it is determined in step S56 that there is still a frame image to be processed, the process returns to step S41, and the subsequent processing is repeated.

  On the other hand, in step S56, when there is no image of the frame to be processed, that is, when the image of the frame to be processed next is not supplied from the A / D conversion unit 151, the processing ends.

  In the encoding unit 152 (first embodiment) in FIG. 3, the sort information Vcds of the block BL is output from the output terminal 168 as one of the encoded digital image signals Vcd1 for all the blocks BL of all the frames. On the other hand, the encoding unit 152 (second embodiment) in FIG. 14 outputs the sort information Vcds of the block BL from the output terminal 168 for the block BL of the head frame, but the frames other than the head frame. For the block BL, the index information Vcdi representing the block BL of the first frame with the closest sort order is output from the output terminal 168, so that the information amount of the encoded digital image signal Vcd1 output from the output terminal 168 can be reduced. .

  FIG. 16 is a block diagram illustrating a configuration example of the second embodiment of the decoding unit 155 of the recording device 113 in FIG. 2. That is, FIG. 15 is a block diagram illustrating a configuration example of a decoding unit 155 corresponding to the encoding unit 152 of FIG.

  In FIG. 16, portions corresponding to the configuration of the first embodiment of the decoding unit 155 illustrated in FIG. 12 are denoted with the same reference numerals, and description thereof is omitted.

  That is, the decoding unit 155 of FIG. 16 has the same configuration as the decoding unit 155 of FIG. 12 except that a prediction pixel value generation circuit 221 is provided instead of the prediction pixel value generation circuit 183 of FIG. ing.

  The predicted pixel value generation circuit 221 includes a prediction circuit 191, a sort order extraction circuit 231, a frame buffer 232, and an inverse sort circuit 233.

  The prediction circuit 191 is supplied from the data decomposition circuit 182 with the maximum value Vcdmax and the minimum value Vcdmin of the pixel value when each of the plurality of blocks BL constituting one frame is the target block BLc. As described with reference to FIG. 7, the prediction circuit 191 calculates a straight line using the maximum value Vcdmax and the minimum value Vcdmin, and predicts the pixel value obtained by the straight line from each pixel constituting the target block BLc. The pixel value is supplied to the reverse sort circuit 233.

  If the frame having the block of interest BLc is the first frame, the sort order extraction circuit 231 supplies the sort order information Vcds supplied from the data decomposition circuit 182 to the reverse sort circuit 233 and also supplies it to the frame buffer 232. Then, index information Vcdi is added as an index representing the block BL.

  If the frame having the block of interest BLc is not the first frame, the sort order extraction circuit 231 sorts the sort order information Vcds of the block BL (of the first frame) specified by the index information Vcdi supplied from the data decomposition circuit 182. Are extracted from the frame buffer 232 and supplied to the reverse sort circuit 233.

  The frame buffer 232 supplies sort order information Vcds of each block BL of one frame (first frame) supplied from the sort order extraction circuit 231 (pixels of each pixel constituting the block BL of each of the plurality of blocks BL of the first frame). The result of sorting the pixels according to the magnitude of the value) and the index information Vcdi representing the block BL are stored and supplied to the sort order extraction circuit 231 as necessary.

  Based on the sort order information Vcds from the sort order extraction circuit 231, the reverse sort circuit 233 rearranges the predicted pixel values from the prediction circuit 191 into the original spatial phase (raster order) (the spatial phase before sorting). Reverse sort). Then, the inverse sort circuit 233 supplies the predicted pixel value rearranged in the original spatial phase to the adder 185.

  Next, the decoding process of the decoding unit 155 of FIG. 16 will be described with reference to the flowchart of FIG.

  In FIG. 17, steps S61, S62, and S67 to S73 are the same as steps S21 to S29 in FIG.

  In step S62, the prediction circuit 191 calculates a straight line using the maximum value Vcdmax and the minimum value Vcdmin from the data decomposition circuit 182, and calculates the predicted pixel value of each pixel constituting the target block BLc from the straight line. In step S63, the sort order extraction circuit 231 determines whether the image of the frame having the block of interest BLc is the image of the first frame.

  If it is determined in step S63 that the block of interest BLc is the image of the first frame, the process proceeds to step S64, where the sort order extraction circuit 231 uses the sort order information Vcds supplied from the data decomposition circuit 182 as the reverse sort circuit 233. And to the frame buffer 232.

  In step S65, the frame buffer 232 stores the sort order information Vcds of the block BL (of the first frame) supplied from the sort order extraction circuit 231 and attaches index information Vcdi as an index representing the block BL (sort The order extraction circuit 231 stores the sort order information Vcds of the block BL in the frame buffer 232 and attaches the index information Vcdi as an index representing the block BL).

  On the other hand, if it is determined in step S63 that the image of the frame having the block of interest BLc is not the image of the first frame, the process proceeds to step S66, where the sort order extraction circuit 231 includes the index information Vcdi supplied from the data decomposition circuit 182. The sort order information Vcds of the block BL (of the first frame) designated by the above is extracted from the frame buffer 232 and supplied to the reverse sort circuit 233.

  As described above, since the block BL of the frame other than the first frame is reverse-sorted using the index information Vcdi indicating the block BL of the first frame with the closest sort order, the sort order information of the blocks BL constituting each frame The encoded digital image signal Vcd1 can be decoded with a smaller amount of information than when Vcds is sent as it is.

  Next, referring to the flowchart of FIG. 18, the image signal is recorded (copied) on the recording medium 122 by using the analog image signal Van1 output from the reproduction device 111 by the recording device 113 of FIG. A recording confirmation process for confirming an image on the display 143 when the encoded digital image signal Vcd1 recorded on the recording medium 122 is decoded and displayed on the display in a predetermined reproducing apparatus will be described.

  First, in step S91, the A / D conversion unit 151 converts the input analog image signal Van1 into a digital signal, and supplies the resulting digital image signal Vdg1 to the encoding unit 152.

  In step S92, the encoding unit 152 encodes the digital image signal Vdg1 from the A / D conversion unit 151, and the encoded digital image signal Vcd1 obtained as a result is decoded by the medium recording unit 153 and the decoding unit 142 (decoding unit thereof). 155).

  In step S93, the medium recording unit 153 records the encoded digital image signal Vcd1 from the encoding unit 152 on the recording medium 122.

  In step S94, the decoding unit 155 decodes the encoded digital image signal Vcd1 from the encoding unit 152, and supplies the resulting decoded digital image signal Vdg2 to the D / A conversion unit 156. Note that the processes of steps S93 and S94 can be executed in parallel.

  In step S95, the D / A converter 156 converts the decoded digital image signal Vdg2 supplied from the decoder 155 into an analog signal, and outputs the resulting analog image signal Van2 to the display 143.

  In step S96, the display 143 displays an image corresponding to the analog image signal Van2 from the D / A conversion unit 156.

  As described above, the analog image signal Van1 with analog distortion reproduced and output by the reproduction device 111 is A / D converted into the digital image signal Vdg1, and the digital image signal Vdg1 is encoded to be recorded on the recording medium 122. To be recorded. That is, copying based on the analog image signal Van1 accompanied by analog distortion is performed.

  Here, the analog image signal Van1 with analog distortion output from the playback device 111 is a signal that is output after the encoded digital image signal recorded on the recording medium 121 is decoded by the decoding unit 131. . That is, the analog image signal Van1 with analog distortion output from the playback device 111 is a signal that has been subjected to the first encoding and decoding.

  Also, the encoded digital image signal Vcd1 copied based on the analog image signal Van1 subjected to the first encoding and decoding and recorded on the recording medium 122 is reproduced (decoded) by the reproducing device 111, When output, the analog image signal to be output from the playback device 111 is a signal that has been subjected to the second encoding and decoding in the same manner as the analog image signal Van2 output from the playback unit 142. .

  The decoded digital image signal Vdg2 subjected to the second encoding and decoding is a signal reproduced from the copy source recording medium 121, and is a decoded digital image subjected to the first encoding and decoding. Compared with the image signal Vdg0, the image quality is greatly deteriorated.

  Therefore, with reference to FIG. 19 to FIG. 24, the deterioration of the image quality of the second encoding and decoding with respect to the first encoding and decoding will be described.

  The left side of FIG. 19 shows the differential waveform of the predetermined block BL before the first encoding, and the right side of FIG. 19 shows the differential waveform after decoding after encoding the differential waveform of the block BL. Show. That is, the differential waveform shown on the right side of FIG. 19 indicates the differential waveform (difference data of each pixel constituting the block BL) after the first encoding and decoding.

  In the first encoding and decoding, as shown in FIG. 19, no significant change (distortion) is observed in the differential waveform of the block BL. Therefore, in the first encoding and decoding, although slight distortion due to encoding distortion (quantization distortion) occurs, basically the digital image signal does not deteriorate. In other words, this means that when the digital image signal is copied using the encoding unit 152 and the decoding unit 155 (131), the image quality is not deteriorated (the image quality is prevented from being deteriorated). Can also be said).

  The difference waveform of the block BL after decoding shown in the upper right side of FIG. 20 that is the same as the left side of FIG. 19 is the prediction waveform of the block BL (upper left side of FIG. 20) by the prediction pixel value generation circuit 183 (201) in the decoding unit 155. ) And the adder 185 and output as an output waveform (lower side in FIG. 20). The output waveform of the block BL shown in the lower side of FIG. 20 corresponds to the decoded digital image signal Vdg0 of the block BL output from the decoding unit 131 of the playback device 111.

  In the playback device 111, the decoded digital image signal Vdg0 is output as an analog image signal Van1 accompanied by analog distortion when converted into an analog signal. Then, in the recording device 113, the digital image signal Vdg1 obtained by converting the analog image signal Van1 into a digital signal is encoded by the encoding unit 152.

  The encoding unit 152 performs the same encoding as the first encoding, but the sort order information Vcds () is calculated by the sort order calculating circuit 163 based on the analog distortion and the first encoding distortion of the digital image signal Vdg1. Sort order) is significantly different from the first sort order information Vcds (sort order).

  FIG. 21 shows the prediction based on the maximum value Vcdmax and the minimum value Vcdmin of the pixels constituting the block BL obtained by the sort order calculation circuit 163 and the sort order information Vcds of the block BL in the second encoding. It is the figure which showed the processing result of the pixel value generation circuit 164 (201).

  In the sort order information Vcds of the block BL shown in FIG. 21, for example, a pixel with the sort order “1” is arranged to the left of the “39” -th pixel with the sort order indicated by the dotted circle. A pixel with the sort order “2” is arranged on the right side of the “39” pixel with the sort order indicated by the dotted dotted line. This indicates that the “39” -th pixel in the sort order and the pixels on both sides are greatly different in sort order. There is a correlation between the pixel value of a certain pixel and the pixel values of pixels in the vicinity of the pixel, and generally there is little significant change in the sort order. However, the sort order information Vcds (sort order) in the second encoding becomes significantly different from the first sort order information Vcds (sort order) due to the analog distortion and the first encoding distortion. As shown in the pixel, a pixel having a large difference from the sorting order of neighboring pixels is generated. In the sort order information Vcds of FIG. 21, for example, the “43” -th pixel indicated by the dotted dotted line and the “4” -th pixel also differ from the sort order of neighboring pixels. It is a large pixel. Thereby, the prediction waveform generated in the prediction pixel value generation circuit 164 of the encoding unit 152 is a waveform having a jagged high frequency component as shown in the lower side of FIG.

  The predicted waveform shown in the upper right side of FIG. 22 that is the same as the lower side of FIG. 21 is subtracted from the input waveform of the block BL (upper left side of FIG. 22) to obtain the differential waveform of the block BL (lower side of FIG. 22). The difference waveform obtained by subtracting the predicted waveform from the input waveform is similarly a waveform having a high frequency component because the high frequency component of the predicted waveform remains.

  However, since the encoding in the block encoding circuit 166 of the encoding unit 152 performs the encoding to remove the high-frequency component as described above, as shown in FIG. When the differential waveform (left side of FIG. 23) is encoded and further decoded, the differential waveform of the block BL after decoding is a waveform that is greatly distorted (high-frequency components are removed) as shown on the right side of FIG. It becomes.

  Therefore, as shown in FIG. 24, in the second decoding, the prediction waveform of the block BL (upper left side in FIG. 24) and the difference waveform of the decoded block BL (upper right side in FIG. 24) are added. The output waveform of the block BL to be obtained is also a greatly distorted waveform. That is, compared with the output waveform of the first block BL shown in FIG. 20, the output waveform of the second block BL (lower side in FIG. 24) is a greatly distorted waveform, and the image quality is deteriorated.

  As described above, the decoded digital image signal Vdg2 subjected to the second encoding and decoding, which is a signal reproduced from the copied recording medium 122, is a signal reproduced from the recording medium 121 that is the copy source. Compared with the decoded digital image signal Vdg0 subjected to the first encoding and decoding, the image quality is greatly deteriorated.

  In the case of the second embodiment of the encoding unit 152 or the decoding unit 155, the sort order information Vcds is extracted from the frame buffer 214 or 232 to perform encoding or decoding. The sort order information Vcds stored in the frame buffer 214 or 232 is the sort order information of the first frame. Even in the first frame, the sort order information Vcds in the second encoding is the sort order in the first encoding. Since it is greatly different (distorted) from the information Vcds, the distorted sort order information Vcds is used even in a frame other than the first frame that refers to the information Vcds, resulting in a greatly distorted output waveform.

  When the analog image signal Van1 output from the playback device 111 is a signal that has been encoded and decoded for the second time, the signal reproduced from the next copied recording medium 122 is the third time. The analog image signal Van2 is encoded and decoded, and the image is further deteriorated. That is, every time encoding and decoding are repeated, the image quality of the image signal recorded on the recording medium 122 deteriorates.

  Therefore, according to the recording / reproducing apparatus 113, copying using an analog image signal while maintaining good image quality becomes impossible, and the image quality of the image corresponding to the second and subsequent encoded and decoded image signals is not possible. Can be prevented from being illegally copied using an analog image signal.

  In the image processing system 101 of FIG. 2, special processing (such as deterioration of image quality) is performed on the analog image signal Van1 in order to prevent illegal copying by degrading image quality using analog distortion that occurs naturally. not going. Therefore, a special circuit or the like (means) for preventing unauthorized copying is not required, and the problem that the configuration becomes complicated (the circuit scale increases) does not occur. In the image processing system 101 in FIG. 2, an example using analog distortion generated when the D / A conversion unit 132 of the playback device 111 converts the decoded digital image signal Vdg0 into an analog signal has been described. Similar effects on analog distortion generated in the transmission path from the A conversion unit 132 to the A / D conversion unit 151 or analog distortion generated in the A / D conversion unit 151 (significant deterioration in image quality of the decoded digital image signal Vdg2) It becomes.

  Further, in the image processing system 101 in FIG. 2, in addition to the naturally occurring analog distortion, noise (analog noise) that intentionally generates analog distortion is added to the analog image signal Van1 output from the playback device 111. It is also possible to make it.

  FIG. 25 is a block diagram illustrating a configuration example of another embodiment of an image processing system to which the present invention has been applied.

  In FIG. 25, portions corresponding to those of the image processing system 101 of FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

  That is, the image processing system 101 in FIG. 25 is configured in the same manner as the image processing system 101 in FIG. 2 except that the recording unit 141 of the recording apparatus 113 is newly provided with a noise adding unit 291.

  The analog image signal Van1 output from the playback device 111 is input to the noise adding unit 291 of the recording device 1. The noise adding unit 291 adds noise to the input analog image signal Van1 and supplies it to the A / D conversion unit 151.

  With reference to the flowchart of FIG. 26, the recording confirmation process by the recording device 113 of FIG. 25 will be described.

  First, in step S <b> 101, the noise adding unit 291 adds noise to the analog image signal Van <b> 1 from the playback device 111 and supplies the analog image signal Van <b> 1 to the A / D conversion unit 151.

  In steps S102 to S107, processing similar to that in steps S81 to S86 in FIG. 18 is performed. That is, the A / D conversion unit 151 converts the analog image signal Van1 with a larger analog distortion into a digital signal by adding noise, and the encoding unit 152 converts the digital image signal Vdg1 into the encoded digital image. It is encoded into the signal Vcd1. Then, the encoded digital image signal Vcd1 is recorded on the recording medium 122. The encoded digital image signal Vcd1 is decoded into a decoded digital image signal Vdg2, further converted into an analog signal (analog image signal Van2), and displayed on the display 143 as an image.

  As described above, the recording apparatus 113 in FIG. 25 encodes not only the naturally occurring analog distortion but also the analog image signal Van1 in which the analog distortion is generated by intentionally adding noise (with analog distortion). To do. In this case, the second and subsequent encodings and decodings further deteriorate the image quality, and illegal copying using analog image signals can be prevented.

  When noise is intentionally added to the analog image signal, the reproduction apparatus 111 may output the analog image signal Van1 after adding the noise.

  That is, FIG. 27 is a block diagram showing a configuration example of still another embodiment of the image processing system to which the present invention is applied.

  In FIG. 27, portions corresponding to those of the image processing system 101 in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

  In other words, in the image processing system 101 of FIG. 27, the noise adding unit 292 is newly provided in the reproducing device 111, and correspondingly, the reproducing unit 142 of the recording device 113 having the same configuration as the reproducing device 111 is provided. 2 is configured in the same manner as the image processing system 101 in FIG. 2 except that the noise adding unit 293 is provided.

  An analog image signal reproduced from the recording medium 121 is supplied from the D / A conversion unit 132 to the noise adding unit 292 of the reproduction device 111. The noise adding unit 292 adds noise to the analog image signal from the D / A conversion unit 132 and outputs the resulting analog image signal Van1 to the display 112 and the recording device 113.

  Similarly, in the reproduction unit 142 of the recording device 113, the analog image signal is supplied from the D / A conversion unit 156 to the noise addition unit 293. The noise addition unit 293 adds noise to the analog image signal from the D / A conversion unit 156 and outputs the resulting analog image signal Van2 to the display 143.

  With reference to the flowchart of FIG. 28, the recording confirmation processing by the recording device 113 of FIG. 27 will be described.

  In steps S121 to S125, processing similar to that in steps S81 to S85 in FIG. 18 is performed. That is, the A / D conversion unit 151 converts the analog image signal Van1 from the playback device 111 into a digital signal, and the encoding unit 152 encodes the digital image signal Vdg1 into the encoded digital image signal Vcd1. Then, the encoded digital image signal Vcd1 is recorded on the recording medium 122. The encoded digital image signal Vcd1 is decoded into a decoded digital image signal Vdg2, and further converted into an analog signal.

  Then, after the process of step S125, the process proceeds to step S126, where the noise adding unit 293 adds noise to the analog image signal from the D / A conversion unit 156, and outputs the resulting analog image signal Van2 to the display 143. .

  In step S127, the display 143 displays an image based on the analog image signal Van2 from the noise adding unit 293, and ends the process.

  As described above, the analog image signal Van1 is not only analog distortion that occurs naturally, but also intentionally added noise, so even if there is even more analog distortion, the analog image with good image quality maintained Copying using an image signal is impossible. In other words, illegal copying using an analog image signal (analog signal) can be prevented by further remarkably degrading the image quality of the image corresponding to the second and subsequent encoded and decoded image signals.

  In the block coding circuit 166 of FIG. 3 (FIG. 14) described above, a code that removes high-frequency components by performing DCT conversion on the residual data of each pixel of the block of interest BLc supplied from the subtractor 146. However, the block encoding circuit 166 may employ other DST (Discrete sine Transform) transformation, FFT (Fast Fourier Transform) transformation, or the like as long as it removes high frequency components. In this case, in the block decoding circuit 184 of FIG. 12 (FIG. 16), decoding corresponding to the block encoding circuit 166 is performed.

  In the embodiment described above, each of the plurality of blocks BL constituting one frame is sequentially processed as the target block BLc. However, all the blocks BL in one frame may be processed in parallel. . Further, the encoding unit 152 and the decoding unit 155 process the image in units of frames, but are not limited to units of frames. For example, the processing may be performed in parallel in units of fields or in units of a plurality of frames.

  A series of processes such as the recording confirmation process, the encoding process, and the decoding process described above can be executed by dedicated hardware or can be executed by software. When a series of processing is performed by software, for example, the series of processing can be realized by causing a (personal) computer as shown in FIG. 29 to execute a program.

  29, a CPU (Central Processing Unit) 301 executes various processes according to a program stored in a ROM (Read Only Memory) 302 or a program loaded from a storage unit 308 to a RAM (Random Access Memory) 303. To do. The RAM 303 also appropriately stores data necessary for the CPU 301 to execute various processes.

  The CPU 301, ROM 302, and RAM 303 are connected to each other via a bus 304. An input / output interface 305 is also connected to the bus 304.

  The input / output interface 305 includes an input unit 306 including a keyboard, a mouse, and an input terminal, a display including a CRT (Cathode Ray Tube) and an LCD (Liquid Crystal display), an output terminal, and an output unit 307 including a speaker. A storage unit 308 configured by a hard disk or the like, a communication unit 309 configured by a terminal adapter, an ADSL (Asymmetric Digital Subscriber Line) modem, a LAN (Local Area Network) card, and the like are connected. The communication unit 309 performs communication processing via various networks such as the Internet.

  A drive 310 is also connected to the input / output interface 305, and a magnetic disk (including a floppy disk), an optical disk (including a compact disk-read only memory (CD-ROM) DVD Digital Versatile Disk), a magneto-optical disk (MD (Including Mini-Disk) or a removable medium (recording medium) 321 such as a semiconductor memory is appropriately mounted, and a computer program read from the medium is installed in the storage unit 308 as necessary.

  29, the CPU 301 that executes the program, for example, has an A / D converter 151, an encoder 152, a decoder 155 (decoder 131), and a D / A converter 156 (D / A converter) in FIG. The drive 310 corresponds to the medium recording unit 153 corresponding to the conversion unit 132). The display 143 corresponds to the output unit 307.

  In the present specification, the steps described in the flowcharts are executed in parallel or individually even if they are not necessarily processed in time series, as well as processes performed in time series in the described order. It also includes processing.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

It is a block diagram which shows an example of a structure of the conventional image processing system. It is a block diagram which shows the structural example of one Embodiment of the image processing system to which this invention is applied. FIG. 3 is a block diagram illustrating a configuration example of a first exemplary embodiment of an encoding unit 152 in FIG. 2. It is a figure explaining the process of the blocking circuit 162. FIG. It is a figure explaining the process of the sort order calculation circuit. It is a figure explaining the process of the sort order calculation circuit. It is a figure explaining the process of the prediction circuit. FIG. 10 is a diagram for describing processing of an inverse sort circuit 172. It is a figure explaining the process of the subtractor 165. FIG. It is a figure which shows the example of the quantization table in the block encoding circuit 166. 12 is a flowchart for describing an encoding process of an encoding unit 152. FIG. 3 is a block diagram illustrating a configuration example of a first embodiment of a decoding unit 155 in FIG. 2. FIG. 40 is a flowchart for describing a decoding process of the decoding unit 155. FIG. It is a block diagram which shows the structural example of 2nd Embodiment of the encoding part 152 of FIG. 12 is a flowchart for describing an encoding process of an encoding unit 152. It is a block diagram which shows the structural example of the decoding part 155 of FIG. FIG. 40 is a flowchart for describing a decoding process of the decoding unit 155. FIG. 3 is a flowchart for explaining a recording confirmation process of the recording apparatus 113 in FIG. 2. It is a figure explaining the degradation of the image quality by the encoding and decoding of the 2nd time. It is a figure explaining the degradation of the image quality by the encoding and decoding of the 2nd time. It is a figure explaining the degradation of the image quality by the encoding and decoding of the 2nd time. It is a figure explaining the degradation of the image quality by the encoding and decoding of the 2nd time. It is a figure explaining the degradation of the image quality by the encoding and decoding of the 2nd time. It is a figure explaining the degradation of the image quality by the encoding and decoding of the 2nd time. It is a block diagram which shows the structural example of other embodiment of the image processing system to which this invention is applied. It is a flowchart explaining the recording confirmation process by the recording device 113 of FIG. FIG. 22 is a block diagram illustrating a configuration example of still another embodiment of an image processing system to which the present invention has been applied. It is a flowchart explaining the recording confirmation process by the recording device 113 of FIG. It is a block diagram which shows the structural example of one Embodiment of the computer to which this invention is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 Image processing system, 113 Recording apparatus, 141 Recording part, 142 Playback part, 152 Encoding part, 155 Decoding part, 161 Input terminal, 162 Blocking circuit, 163 Sort order calculation circuit, 164 Predictive pixel value generation circuit, 165 Subtractor, 166 block encoding circuit, 167 output terminal, 171 prediction circuit, 172 reverse sort circuit, 181 input terminal, 182 data decomposition circuit, 183 prediction pixel value generation circuit, 184 block decoding circuit, 185 adder, 186 block Decomposition circuit, 187 output terminal, 201 prediction pixel value generation circuit, 211 sort order matching circuit, 212 reverse sort circuit, 213 data extraction circuit, 214 frame buffer, 221 prediction Pixel value generation circuit, 231 sort order extraction circuit, 232 frame buffer, 233 reverse sort circuit, 291 to 293 noise addition unit

Claims (22)

Block dividing means for dividing the first image included in the input image data into a plurality of blocks;
Sorting each pixel according to the size of the pixel value of each pixel constituting the block, sorting order information indicating the sorting result when sorting , and the maximum pixel value of the pixels constituting the block And a sort order calculating means for calculating a minimum value ,
Pixel value generating means for generating a predicted pixel value of each pixel constituting the block, sorted according to the size of the pixel value from the maximum value and the minimum value;
Reverse sort means for reversely sorting the predicted pixel values generated by the pixel value generation means into a spatial phase before each pixel constituting the block is sorted based on the sort order information;
Difference data calculating means for calculating difference data between a pixel value of each pixel constituting the block and the predicted pixel value after reverse sorting ;
An encoding device comprising: encoding means for encoding the difference data. The encoding apparatus according to claim 1, further comprising noise adding means for adding noise to the input image data. The encoding means performs DCT (Discrete Cosine Transform) transformation on the difference data, and quantizes the DCT coefficient obtained as a result, thereby encoding the difference data. The encoding device described in 1. The pixel value generation means calculates a straight line using the maximum value and the minimum value, and uses a pixel value obtained by the straight line as a predicted pixel value of each pixel constituting the block. The encoding device according to 1. 5. The encoding apparatus according to claim 4 , wherein the pixel value obtained by the straight line is a pixel value on the straight line . The input image data includes a second image ,
Storage means for storing the when the second image is divided into a plurality of blocks, said plurality of blocks each of the sorting order information of the second image,
Sort order extraction means for extracting the sort order information closest to the sort order information calculated by the sort order calculation means from the sort order information stored in the storage means ,
The reverse sorting means uses the predicted pixel value generated by the pixel value generating means based on the sort order information extracted by the sort order extracting means before sorting each pixel constituting the block. The encoding apparatus according to claim 1, wherein reverse sorting is performed on the spatial phase. The second image is a head image of the input image data.
  The encoding apparatus according to claim 6. The sorting order information, the maximum and minimum values, as well as the coding apparatus according to claim 1, characterized by further comprising output means for outputting the difference data encoded by the encoding means. A block dividing step of dividing the first image included in the input image data into a plurality of blocks;
Sorting each pixel according to the size of the pixel value of each pixel constituting the block, sorting order information indicating the sorting result when sorting , and the maximum pixel value of the pixels constituting the block And a sort order calculating step for calculating the minimum value ,
A pixel value generating step for generating predicted pixel values of the respective pixels constituting the block, which are sorted according to the size of the pixel value from the maximum value and the minimum value;
A reverse sorting step that reversely sorts the predicted pixel values generated in the pixel value generation step into a spatial phase before each pixel constituting the block is sorted based on the sort order information;
A difference data calculation step of calculating difference data between a pixel value of each pixel constituting the block and the predicted pixel value after reverse sorting ;
And a coding step for coding the difference data. On the computer,
A block dividing step of dividing the first image included in the input image data into a plurality of blocks;
Sorting each pixel according to the size of the pixel value of each pixel constituting the block, sorting order information indicating the sorting result when sorting , and the maximum pixel value of the pixels constituting the block And a sort order calculating step for calculating the minimum value ,
A pixel value generating step for generating predicted pixel values of the respective pixels constituting the block, which are sorted according to the size of the pixel value from the maximum value and the minimum value;
A reverse sorting step that reversely sorts the predicted pixel values generated in the pixel value generation step into a spatial phase before each pixel constituting the block is sorted based on the sort order information;
A difference data calculation step of calculating difference data between a pixel value of each pixel constituting the block and the predicted pixel value after reverse sorting ;
An encoding step for encoding the difference data;
The computer-readable recording medium which recorded the program for performing this . On the computer,
A block dividing step of dividing the first image included in the input image data into a plurality of blocks;
Sorting each pixel according to the size of the pixel value of each pixel constituting the block, sorting order information indicating the sorting result when sorting , and the maximum pixel value of the pixels constituting the block And a sort order calculating step for calculating the minimum value ,
A pixel value generating step for generating predicted pixel values of the respective pixels constituting the block, which are sorted according to the size of the pixel value from the maximum value and the minimum value;
A reverse sorting step that reversely sorts the predicted pixel values generated in the pixel value generation step into a spatial phase before each pixel constituting the block is sorted based on the sort order information;
A difference data calculation step of calculating difference data between a pixel value of each pixel constituting the block and the predicted pixel value after reverse sorting ;
An encoding step for encoding the difference data;
A program for running The sort result when each pixel is sorted according to the size of the pixel value of each pixel constituting the one block for one block among a plurality of blocks into which the first image is divided Sort order information,
A maximum value and a minimum value of pixel values of pixels constituting the one block;
And obtaining means for obtaining encoded difference data obtained by encoding difference data between the predicted pixel value of each pixel constituting the one block generated using the maximum value and the minimum value and the pixel value; ,
Pixel value generation means for generating a predicted pixel value of each pixel constituting the one block, sorted according to the size of the pixel value from the maximum value and the minimum value;
Reverse sorting means for reversely sorting the predicted pixel values generated by the pixel value generating means into a spatial phase before sorting based on the sort order information;
Differential data decoding means for decoding the encoded differential data into the differential data;
A decoding apparatus comprising: an addition unit that adds the difference data decoded by the difference data decoding unit and the predicted pixel value after reverse sorting . The decoding device according to claim 12, further comprising noise adding means for adding noise to the output of the adding means. The differential data decoding means dequantizes the encoded differential data, and performs inverse DCT (Discrete Cosine Transform) transform on the dequantized encoded differential data, thereby converting the encoded differential data into the differential The decoding device according to claim 12, wherein the decoding device decodes the data. The pixel value generation means calculates a straight line using the maximum value and the minimum value, and uses a pixel value obtained by the straight line as a predicted pixel value of each pixel constituting the block. 12. The decoding device according to 12. Sorting order information indicating the sorting result of when the first image and a second image different from the plurality of divided blocks in each sorting the pixels according to the size of the pixel values of the pixels constituting the block Storage means for storing
Sort order extracting means for extracting sort order information of one block among a plurality of blocks into which the second image stored in the storage means is divided based on the sort order information of the one block; Further comprising
The reverse sorting unit is configured to convert the predicted pixel value generated by the pixel value generating unit based on the sort order information of the block of the second image extracted by the sort order extracting unit before being sorted. The decoding apparatus according to claim 12, wherein reverse sorting is performed on the spatial phase. The decoding apparatus according to claim 16 , wherein the second image is a head image of the input image data . The sort result when each pixel is sorted according to the size of the pixel value of each pixel constituting the one block for one block among a plurality of blocks into which the first image is divided Sort order information,
A maximum value and a minimum value of pixel values of pixels constituting the one block;
And obtaining the encoded difference data obtained by encoding the difference data between the predicted pixel value of each pixel constituting the one block generated using the maximum value and the minimum value and the pixel value; ,
A pixel value generation step for generating a predicted pixel value of each pixel constituting the one block, which is sorted according to the size of the pixel value from the maximum value and the minimum value;
A reverse sorting step for reversely sorting the predicted pixel values generated in the pixel value generating step into a spatial phase before sorting based on the sort order information;
A differential data decoding step for decoding the encoded differential data into the differential data;
A decoding method comprising: an adding step of adding the difference data decoded by the processing of the difference data decoding step and the predicted pixel value after reverse sorting . On the computer,
The sort result when each pixel is sorted according to the size of the pixel value of each pixel constituting the one block for one block among a plurality of blocks into which the first image is divided Sort order information,
A maximum value and a minimum value of pixel values of pixels constituting the one block;
And obtaining the encoded difference data obtained by encoding the difference data between the predicted pixel value of each pixel constituting the one block generated using the maximum value and the minimum value and the pixel value; ,
A pixel value generation step for generating a predicted pixel value of each pixel constituting the one block, which is sorted according to the size of the pixel value from the maximum value and the minimum value;
A reverse sorting step for reversely sorting the predicted pixel values generated in the pixel value generating step into a spatial phase before sorting based on the sort order information;
A differential data decoding step for decoding the encoded differential data into the differential data;
An addition step of adding the difference data decoded by the processing of the difference data decoding step and the predicted pixel value after reverse sorting ;
The computer-readable recording medium which recorded the program for performing this . On the computer,
The sorting result when each pixel is sorted according to the size of the pixel value of each pixel constituting the one block of one of the plurality of blocks into which the first image is divided is represented. Sort order information,
A maximum value and a minimum value of pixel values of pixels constituting the one block;
And obtaining the encoded difference data obtained by encoding the difference data between the predicted pixel value of each pixel constituting the one block generated using the maximum value and the minimum value and the pixel value; ,
A pixel value generation step for generating a predicted pixel value of each pixel constituting the one block, which is sorted according to the size of the pixel value from the maximum value and the minimum value;
A reverse sorting step for reversely sorting the predicted pixel values generated in the pixel value generating step into a spatial phase before sorting based on the sort order information;
A differential data decoding step for decoding the encoded differential data into the differential data;
An addition step of adding the difference data decoded by the processing of the difference data decoding step and the predicted pixel value after reverse sorting ;
A program for running An encoding unit that encodes input image data and a decoding unit that decodes encoded input image data, and when the input image data is repeatedly encoded and decoded, the image quality corresponding to the input image data In an image processing system that deteriorates,
The encoding unit includes:
Block dividing means for dividing the first image included in the input image data into a plurality of blocks;
Sorting each pixel according to the size of the pixel value of each pixel constituting the block, sorting order information indicating the sorting result when sorting , and the maximum pixel value of the pixels constituting the block And a sort order calculating means for calculating a minimum value ,
Pixel value generating means for generating a predicted pixel value of each pixel constituting the block, sorted according to the size of the pixel value from the maximum value and the minimum value;
Reverse sort means for reversely sorting the predicted pixel values generated by the pixel value generation means into a spatial phase before each pixel constituting the block is sorted based on the sort order information;
Difference data calculating means for calculating difference data between a pixel value of each pixel constituting the block and the predicted pixel value after reverse sorting ;
An image processing system comprising: encoding means for encoding the difference data. An encoding unit that encodes input image data and a decoding unit that decodes encoded input image data, and when the input image data is repeatedly encoded and decoded, the image quality corresponding to the input image data In an image processing system that deteriorates,
The decoding unit
The sort result when each pixel is sorted according to the size of the pixel value of each pixel constituting the one block for one block among a plurality of blocks into which the first image is divided Sort order information,
A maximum value and a minimum value of pixel values of pixels constituting the one block;
And obtaining means for obtaining encoded difference data obtained by encoding difference data between the predicted pixel value of each pixel constituting the one block generated using the maximum value and the minimum value and the pixel value; ,
Pixel value generation means for generating a predicted pixel value of each pixel constituting the one block, sorted according to the size of the pixel value from the maximum value and the minimum value;
Reverse sorting means for reversely sorting the predicted pixel values generated by the pixel value generating means into a spatial phase before sorting based on the sort order information;
Differential data decoding means for decoding the encoded differential data into the differential data;
An image processing system comprising: addition means for adding the difference data decoded by the difference data decoding means and the predicted pixel value after reverse sorting .

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