JP4555956B2 - Memory system, memory controller, and refresh operation control method for memory controller - Google Patents

Description

  The present invention relates to a memory system including a memory device that requires a memory cell refresh operation, a memory controller that controls a memory device that requires a memory cell refresh operation, and a memory controller that controls a memory device that requires a memory cell refresh operation. The present invention relates to a refresh operation control method.

  For example, Patent Document 1 discloses a method and apparatus for dynamically adjusting the refresh rate of a memory module according to the state of a computer system.

  The apparatus of Patent Literature 1 is used for detecting a change in at least one of a system state, a means for detecting a change in at least one of the system states to be monitored, a means for detecting a change in at least one of the system states to be monitored. Correspondingly, there are provided judging means for determining the optimum refresh rate in the current state of the computer system and means for setting the refresh rate to the judged optimum refresh rate.

According to the apparatus of Patent Document 1, unlike the case where the refresh rate cannot be changed, the refresh rate can be set to the optimum refresh rate. Thereby, according to the apparatus of patent document 1, it is not necessary to design a cooling system excessively in consideration of rebooting of a computer system, for example. Therefore, in the apparatus of Patent Document 1, it is possible to avoid an increase in cost due to excessive setting of environmental facilities (such as a cooling system) related to the computer system.
JP 2006-120144 A

  By the way, in order to meet the demand for miniaturization and high performance, recent memories employ an MCP (Multi-Chip-Package) structure or a POP (Package-On-Package) structure in which a plurality of memories are mounted. .

  In a DRAM (Dynamic Random Access Memory), a refresh operation for holding data at a predetermined cycle is required in order to prevent the data of the memory cells written in the DRAM from disappearing over time.

  However, in a DRAM, the data retention time is shortened as the temperature rises, so that it is required to frequently perform a refresh operation as the temperature rises.

  Therefore, in the MCP structure in which the DRAM and another memory different from the DRAM are mounted, when the temperature of the DRAM rises due to the heat released from the other memory, the time for the DRAM to hold data is shortened. For this reason, as the temperature of the DRAM rises, it becomes difficult to prevent the data from disappearing, and the performance of the refresh operation of the DRAM may be deteriorated.

  Further, the means for monitoring a plurality of system states (temperature detection elements and the like) disclosed in Patent Document 1 cannot be added in an MCP (multi-chip package) device or a POP (package-on-package) device. In a device structure in which a plurality of chip dies are mounted (for example, stacked) on one resin or the like, it is structurally difficult to incorporate the monitoring means, and the temperature and power consumption of the mounting device are determined by the monitoring means itself. It becomes a vicious circle that is further added by the power consumption and the amount of heat.

  The present invention has been proposed in view of such a situation, and the refresh operation of one memory is affected by the influence of heat released from another memory different from the one of the plurality of memories. It is an object of the present invention to provide a memory system, a memory controller, and a refresh operation control method for the memory controller that can prevent inferior performance.

Memory controller according to a first aspect of the invention, the memory controller connected to a plurality of memory including memory requiring refresh operation for data retention of the memory cell in a predetermined cycle, one need pre Symbol refresh operation memory request signal recognizing request recognition portion and the a operation cycle setting unit for setting a refresh operation cycle of one memory, the operating cycle of the device requesting access to different other memory and the memory setting unit, the main Motome認 if識部said memory request signal is outputted recognize an access request signal to the other memory, the second refresh operation is the refresh operation cycle after reception of said access request signal The first refresh operation cycle that is the refresh operation cycle before receiving the access request signal Shortened, if the request recognition portion recognizes the memory request signal is a terminate signal to deactivate the other memory, and wherein said second refresh operation cycle, return to the first refresh operation cycle To do.

According to the memory controller of the first aspect of the invention, in order to cope with an increase in the amount of heat released from the other memory by executing the operation corresponding to the access request to the other memory, the operation cycle setting unit Thus, the refresh operation cycle after receiving the access request can be made different from the refresh operation cycle before receiving the access request.
Therefore, according to the memory controller of the first aspect of the present invention, even when the amount of heat released from another memory increases and the time during which one memory holds the stored contents changes, The refresh operation cycle can be set to a refresh operation cycle necessary for one memory to hold the stored contents.
Therefore, according to the memory controller of the first aspect of the invention, the memory content of one memory can be prevented from disappearing by setting the refresh operation cycle necessary for one memory to hold the memory content. it can. For this reason, it is possible to prevent the performance of the refresh operation of one memory from being deteriorated due to the influence of heat released from another memory.

Memory system according to the invention of claim 8, in a memory system having a plurality of memory including refresh operation is required memory for data retention of the memory cell in a predetermined cycle, the refresh operation is one required memory comprising a Rume memory controller to control an access request to a different other memory access request and the refresh operation is one memory required to, the memory controller may request to access the other memory The second refresh operation cycle that is the refresh operation cycle after reception is made shorter than the first refresh operation cycle that is the refresh operation cycle before reception of the access request to the other memory, and the access to the other memory is performed. In response to the deactivation of the request, the second refresh operation cycle is changed to the first refresh operation cycle. And returning.

According to the memory system of the eighth aspect of the invention, in order to cope with an increase in the amount of heat released from the other memory by executing the operation corresponding to the access command to the other memory, the operation of the memory controller The cycle setting unit can make the refresh operation cycle after access different from the refresh operation cycle before access.
Therefore, according to the memory system of the eighth aspect of the invention, the refresh operation after access is performed even when the amount of heat released from another memory increases and the time for which one memory holds the stored contents changes. The cycle can be set to a refresh operation cycle necessary for one memory to hold the stored contents.
Therefore, according to the memory system of the eighth aspect of the invention, the memory content of one memory can be prevented from disappearing by setting the refresh operation cycle necessary for the memory to retain the memory content. it can. For this reason, it is possible to prevent the performance of the refresh operation of one memory from being deteriorated due to the influence of heat released from another memory.

A refresh operation control method for a memory controller according to a fourteenth aspect of the invention is a refresh operation control method for a memory controller connected to a plurality of memories including a memory that requires a refresh operation for maintaining data in memory cells at a predetermined cycle. in, change the memory request signal and recognizes step 1, the refresh operation cycle of the previous SL one memory of the device requesting access to different other memory and the refresh operation in the one memory needed Luz Step 2 is a second refresh operation cycle after receiving the access request signal when the memory request signal recognized in Step 1 is an access request signal to the other memory. A refresh operation cycle is defined as the refresh operation before receiving the access request signal. If the memory request signal recognized in step 1 is a signal for deactivating the other memory, the second refresh operation cycle is set to be shorter than the first refresh operation cycle, which is a cycle. It is characterized by returning to the operation cycle .

According to the refresh operation control method for a memory controller according to the invention of claim 14 , in order to cope with an increase in the amount of heat released by another memory by executing an operation corresponding to access to the other memory, By the operation cycle setting step 2, the refresh operation cycle of one memory after accessing another memory can be made different from the refresh operation cycle of one memory before accessing another memory.
Therefore, according to the refresh operation control method of a memory controller according to the invention of claim 14 , even when the amount of heat released by another memory increases and the time for which one memory holds the stored contents changes, The refresh operation cycle of one memory after access to another memory can be set to a refresh operation cycle necessary for one memory to hold the stored contents.
Therefore, according to the refresh operation control method for a memory controller according to the fourteenth aspect of the present invention, the memory content of one memory is erased by setting the refresh operation cycle necessary for the memory to retain the memory content. Can be prevented. For this reason, it is possible to prevent the performance of the refresh operation of one memory from being deteriorated due to the influence of heat released from another memory.

  According to the memory system, the memory controller, and the refresh operation control method of the memory controller of the present invention, it is possible to prevent the performance of the refresh operation of one memory from being deteriorated due to the influence of heat released from another memory.

<Embodiment>
An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit block diagram of the memory system 1 of the present embodiment. The memory system 1 includes a synchronous DRAM controller 10 (SDRAM controller 10), a synchronous DRAM 20 (SDRAM 20), and a synchronous flash memory 30 (SNVM 30).

  The SDRAM 20 and the SNVM 30 are combined with each other in a laminated structure, and are configured with an MCP (multi-chip package) device disclosed in FIG. Further, an SDRAM controller 10 is incorporated as the MCP chip 2 (another functional chip die). On the other hand, the SDRAM 20 (chip 1) component 1 sealed with resin or the like, the SNVM 30 (chip 3) sealed with another resin or the like, and the SDRAM controller 10 (chip 2) are combined in a laminated structure to form a resin or the like. The component 2 encapsulated in (1) is composed of a POP (package on package) device disclosed in FIG. It should be noted that the SDRAM controller 10 as an active component, the SDRAM 20 and the SNVM 30 as passive components, and the placement locations (assignment to the chips 1 to 3) in the MCP / POP are arbitrary. However, it is desirable that the SDRAM 20 and the SNVM 30 having a high operating frequency and large power consumption are distributedly arranged with other functional chips (chip 2) interposed therebetween.

  In the memory system 1, the SDRAM 20 and the SNVM 30 are connected to the SDRAM controller 10 through the same control lines (CLK, CKE, RAS #, CAS #, WE #, AD, DQ), and the same command system (read and write commands). The SDRAM controller 10 controls.

  In the memory system 1, the SDRAM controller 10, the SDRAM 20, and the synchronous flash memory 30 are commonly connected to each other with a metal material having a low resistance and a high thermal conductivity (50 to 400 W / mK) through a control signal line. . Various clock signals, various command signals, address signals, and data signals are inputted to and outputted from the SDRAM 20 and the synchronous flash memory 30 in common.

  In the SDRAM 20 and the synchronous flash memory 30, the clock signal CLK, the enable clock signal CKE, the row address select signal RAS #, the column address select signal CAS #, the write enable signal WE #, the address signal AD, and the data signal DQ are stored in the low resistance. Thus, input / output is commonly performed on the metal material having high thermal conductivity.

  Chip select signal CS1 # is input to SDRAM 20. The chip select signal CS2 # is input to the synchronous flash memory 30.

  The SDRAM 20 and the SNVM 30 connected by the same control line (CLK, CKE, RAS #, CAS #, WE #, AD, DQ) having a low resistance and high thermal conductivity share heat generated by the mutual operation in a short time. This is because heat is shared through the same control line that is shared and connected in the MCP device (FIG. 12) and the POP device (FIG. 13). When the data retention characteristics of the memory cells of the SDRAM 20 depend on thermal elements, even if the SDRAM 20 is not operating (only a refresh operation with a predetermined period of time), heat is shared in a short time by the high-speed operation of the SNVM 30, and the memory of the SDRAM 20 The data retention characteristics of the cell deteriorate. The case where the amount of heat generated in the MCP device or POP device is the largest is when the SDRAM 20 and the SNVM 30 operate simultaneously. For example, data is communicated between the SDRAM 20 and the SNVM 30 in response to a command from the SDRAM controller 10.

  The memory system 1 in FIG. 1 includes a request recognition unit 11, an arithmetic algorithm processor 12, and an operation cycle setting unit 13 in the SDRAM controller 10. The request recognition unit 11 has a function of recognizing a memory request signal for data access of the SDRAM 20 and the SNVM 30 placed under the control of the SDRAM controller 10 from the CPU. The request recognition unit 11 outputs an SD request signal when accessing the SDRAM 20, and outputs an SNVM request signal when accessing the SNVM 30. The arithmetic algorithm processor 12 issues a communication rule in a predetermined routine according to specifications (command type, latency, burst length, address, data, etc.) for performing communication with each memory. The operation cycle setting unit 13 manages refresh of the memory cells of the SDRAM 20. Specifically, when the SDRAM controller 10 issues a refresh command to the SDRAM 20 at a predetermined cycle, or when the SDRAM controller 10 issues the predetermined cycle setting information as mode register information to the SDRAM 20 having a self-refresh function, the operation cycle setting unit 13 manages refresh management information. As such management information, the operation cycle setting unit 13 outputs a refresh request signal to the arithmetic algorithm processor 12.

The SD / SNVM request signal (SD request signal, SNVM request signal) of the request recognition unit 11 is connected to the arithmetic algorithm processor 12. The SNVM request signal is input to the operation cycle setting unit 13. The refresh request signal from the operation cycle setting unit 13 is input to the arithmetic algorithm processor 12. The termination signal of the arithmetic algorithm processor 12 is input to the operation cycle setting unit 13.
The operation of these signals will be described.
When the request recognition unit 11 recognizes the memory request signal from the CPU to the SNVM 30, the request recognition unit 11 outputs the SNVM request signal to the arithmetic algorithm processor 12 and the operation cycle setting unit 13. The operation cycle setting unit 13 that manages the refresh of the memory cells of the SDRAM 20 changes the current refresh management information and outputs a refresh request signal to the arithmetic algorithm processor 12. Specifically, the refresh cycle of the SDRAM 20 is changed to a short cycle in response to an increase in the amount of heat generated in the MCP / POP that will be generated in the near future when the SNVM 30 is accessed.
By the refresh of the short cycle, the memory cell of the SDRAM 20 can hold data with high reliability irrespective of the heat increase in the package device due to the heat generated by the SNVM 30.
The arithmetic algorithm processor 12 outputs a termination signal to the operation cycle setting unit 13 when access to the SNVM 30 is completed according to the specification / communication rule. The operation cycle setting unit 13 performs a process of returning the refresh cycle of the SDRAM 20 changed to the short cycle to the original cycle in accordance with the termination signal.

  Note that the SDRAM controller 10 does not necessarily need to set the access (step N-1 or step N + 1) for changing the refresh cycle of the SDRAM 20 immediately before / after the access to the SNVM 30 (step N). The reason is disclosed by time adjustment described later. That is, as soon as access to the SNVM 30 occurs, the present invention discloses that the frequency change processing of the SDRAM 20 is performed immediately (without delay) before and after.

4 to 8 are timing charts showing a control method of the SDRAM controller 10. FIG. 4 is a timing chart showing a control method when the SDRAM controller 10 issues a refresh command to the SDRAM 20 at a predetermined cycle.
FIG. 5 is a timing chart showing a control method when the SDRAM controller 10 issues the predetermined cycle setting information as mode register information to the SDRAM 20 having a self-refresh function.
FIG. 6 is a timing chart showing a control method when the SDRAM controller 10 issues the predetermined cycle setting information as mode register information to the SDRAM 20 having an active command with a precharge function (Active with autoprecharge command).
FIG. 7 is a timing chart showing a control method in the case where the DRAM controller 10 issues the predetermined cycle setting information as mode register information to the SDRAM 20 having a precharge command.
FIG. 8 shows that the SDRAM controller 10 issues the predetermined cycle setting information as mode register information to the SDRAM 20 in response to a terminate command which is a command for interrupting or terminating the activation state of the SNVM 30 to the SDRAM 20 having a self-refresh function. It is a timing chart which shows the control method in the case.
The timing chart of FIG. 4 will be described.
After power-on, the SDRAM controller 10 manages the refresh of the memory cells of the SDRAM 20 in a predetermined refresh operation cycle (16 μs). An SDRAM refresh command is issued to the SDRAM 20 every 16 μs. When there is an SDRAM access command in response to a request from the CPU, the arithmetic algorithm processor 12 adjusts the priority with the SDRAM refresh command.
When there is an access request to the SNVM 30 by a request from the CPU, the SDRAM controller 10 issues a synchronous flash memory access command (active command) to the SNVM 30. From this time, the refresh management of the memory cells of the SDRAM 20 is changed. The time is changed from the predetermined refresh operation cycle (16 μs) to the second refresh operation cycle (8 μs). During communication between the SDRAM controller 10 and the SNVM 30, the SDRAM 20 issues an SDRAM refresh command each time the second refresh operation period (8 μs) comes. When the DRAM controller 10 issues a precharge command for ending communication with the SNVM 30, the refresh management of the memory cell of the SDRAM 20 is changed. The time is changed from the second refresh operation cycle (8 μs) to a predetermined refresh operation cycle (16 μs).

The timing chart of FIG. 5 will be described. Description of the same parts as those in FIG. 4 is omitted.
FIG. 5 is a timing chart showing a control method when the SDRAM controller 10 issues the predetermined cycle setting information as mode register information to the SDRAM 20 having a self-refresh function.
After power-on, the SDRAM controller 10 also sets a refresh operation cycle during the initialization sequence of the SDRAM 20 that performs latency setting and mode register setting. This is set in the mode register of the SDRAM 20 by a refresh operation cycle setting command. The SDRAM 20 performs background processing (predetermined refresh operation period (16 μs)) by itself in accordance with the register setting. The SDRAM controller 10 only performs register management.
When there is an access request to the SNVM 30 by a request from the CPU, the SDRAM controller 10 changes the mode register value of the SDRAM 20 to the second refresh operation cycle (8 μs) by a refresh operation cycle setting command. Immediately thereafter, a synchronous flash memory access command (active command) is issued. During communication between the SDRAM controller 10 and the SNVM 30, the SDRAM 20 performs self-refreshing in the second refresh operation cycle (8 μs).
When the SDRAM controller 10 issues a precharge command for ending the communication with the SNVM 30, the mode register value of the SDRAM 20 is immediately changed to a predetermined refresh operation cycle (16 μs) by a refresh operation cycle setting command. The refresh management of the memory cell of the SDRAM 20 is changed.

The active command or the precharge command and the refresh operation cycle setting command (mode register setting command) may be reversed in order. The arithmetic algorithm processor 12 optimally determines the context.
As a specific example, when the SDRAM controller 10 gives priority to the access of the SNVM 30, an activation command (active command) for activating the memory bank and the word line of the SNVM 30 is issued, and then a refresh operation cycle setting command ( Mode register setting command) and then an activation command (read command or write command) for activating the column line of the SNVM 30 with a predetermined latency. In this case, the time from the active command being the “time from the predetermined refresh operation cycle (16 μs) to the second refresh operation cycle (8 μs) being set” until the mode register setting command is issued is a predetermined time. It corresponds to adjustment.

The timing chart of FIG. 6 will be described. Description of the same parts as those in FIG. 5 is omitted.
In FIG. 6, when there is an access request to the SNVM 30 by a request from the CPU, the SDRAM controller 10 issues an active command with a precharge function (Active with autoprecharge command). The SDRAM controller 10 immediately changes the mode register value of the SDRAM 20 to the second refresh operation cycle (8 μs) by the refresh operation cycle setting command before issuing the active command with a precharge function. The predetermined time adjustment is determined according to the address depth requested by the CPU to access the SNVM 30 and the specifications (latency, burst length) when the arithmetic algorithm processor 12 communicates with the SNVM 30.

The timing chart of FIG. 7 will be described. Description of the same parts as those in FIG. 5 is omitted.
FIG. 7 shows that after the SDRAM controller 10 issues a precharge command for ending communication with the SNVM 30, the mode register value of the SDRAM 20 is set to a predetermined refresh operation cycle (16 μs) by a refresh operation cycle setting command after a predetermined time adjustment. Change to The predetermined time adjustment is determined according to the time until the MCP / POP device is brought down.

The timing chart of FIG. 8 will be described. Description of the same parts as those in FIG. 5 is omitted.
FIG. 8 shows the SDRAM controller 10 in response to a terminate command which is a command for interrupting or terminating the activation state of the SNVM 30 instead of the precharge command (FIG. 5) for terminating the communication with the SNVM 30. It is a timing chart which shows the control method in the case of issuing predetermined period setting information as mode register information.
After the SDRAM controller 10 issues a terminate command, the mode register value of the SDRAM 20 is immediately changed to a predetermined refresh operation cycle (16 μs) by a refresh operation cycle setting command. The refresh management of the memory cell of the SDRAM 20 is changed. The interruption includes interruption of SNVM30 burst read / burst write, interruption of SNVM30 program / erase processing (suspend command), and the like. When the reactivation command (resume command) is issued from the SDRAM controller 10 to the SNVM 30 again after the interruption, the SDRAM controller 10 issues a refresh operation cycle setting command immediately before and after the reactivation command. The mode register value is changed to the second refresh operation cycle (8 μs).

FIG. 9 is a circuit block diagram of the SDRAM controller 10.
Specifically, FIG. 2 is a circuit block diagram of the SDRAM controller 10 having a function in which the SDRAM controller 10 issues a refresh command to the SDRAM 20 at a predetermined cycle.
The SDRAM controller 10 includes a request recognition unit 100, a refresh management unit 101, a timer 102 and a timer setting value change unit (operation cycle setting unit) 110, an arithmetic algorithm processor 103, a command generation unit 104, and an address generation unit. 105, a data generation unit 106, and a memory interface unit 107. The request recognition unit 100 has a function of recognizing a memory request signal for data access of the SDRAM 20 and the SNVM 30 placed under the control of the SDRAM controller 10 from the CPU. The request recognition unit 100 outputs an SD request signal when accessing the SDRAM 20, and outputs an SNVM request signal when accessing the SNVM 30. The arithmetic algorithm processor 103 issues a communication rule in a predetermined routine in accordance with specifications (command type, latency, burst length, address, data, etc.) for performing communication with each memory. The refresh management unit 101 includes a timer 102 that measures the refresh operation cycle of the SDRAM 20 and a timer setting value change unit (operation cycle setting unit) 110 that sets the timer, and performs an operation every predetermined refresh operation cycle (16 μs). A refresh request is made to the algorithm processor 103. Further, the setting value of the timer 102 of the timer setting value changing unit (operation cycle setting unit) 110 is changed in response to a request from the arithmetic algorithm processor 103. The command generation unit 104, the address generation unit 105, and the data generation unit 106 generate predetermined commands, addresses, and data according to instructions from the arithmetic algorithm processor 103. The memory interface unit 107 transmits predetermined commands, addresses, and data to the SDRAM 20 and the SNVM 30. A circuit block that receives data from the SDRAM 20 and the SNVM 30 and transmits the data to the CPU is not shown.

The SD / SNVM request signal (SD request signal, SNVM request signal) of the request recognition unit 100 is connected to the arithmetic algorithm processor 103. The SNVM request signal is input to the operation cycle setting unit 110 in the refresh management unit 101. The operation cycle setting unit 110 is connected to the timer 102. A refresh request signal from the refresh management unit 101 is input to the arithmetic algorithm processor 103. The termination signal of the arithmetic algorithm processor 103 is input to the operation cycle setting unit 110 in the refresh management unit 101.
The operation of these signals will be described.
When the request recognition unit 100 recognizes the memory request signal from the CPU to the SNVM 30, the request recognition unit 100 outputs the SNVM request signal to the operation algorithm processor 103 and the operation cycle setting unit 110 in the refresh management unit 101. The refresh management unit 101 that manages refresh of the memory cells of the SDRAM 20 changes the refresh management information corresponding to the output of the timer 102 that continues to operate after power-on, and every refresh operation cycle (8 μs) whose cycle has been changed. A refresh request signal is output to the arithmetic algorithm processor 12. The arithmetic algorithm processor 12 instructs the command generator to generate a refresh command in accordance with the refresh request signal.

FIG. 10 is a circuit block diagram of the SDRAM controller 10.
Specifically, it is a circuit block diagram of the SDRAM controller 10 having a function in which the SDRAM controller 10 issues the predetermined cycle setting information as mode register information to the SDRAM 20 having a self-refresh function. Differences from FIG. 9 will be described, and description of common parts will be omitted.
A mode register 201 instead of the refresh management unit 101, a mode register value changing unit (operation cycle setting unit) 210 instead of the timer setting value changing unit (operation cycle setting unit) 110, and a mode register signal instead of the refresh request signal are disclosed. Is done. The refresh management unit 101 and the timer 102 are provided on the SDRAM 20 side described later.
The SNVM request signal is input to the mode register value changing unit (operation cycle setting unit) 210 in the mode register 201. The mode register signal of the mode register 201 is input to the arithmetic algorithm processor 103. The termination signal of the arithmetic algorithm processor 103 is input to the mode register value changing unit (operation cycle setting unit) 210 in the mode register signal.

FIG. 10 is a circuit block diagram of the SDRAM controller 10.
Specifically, it is a circuit block diagram of the SDRAM controller 10 having a function in which the SDRAM controller 10 issues the predetermined cycle setting information as mode register information to the SDRAM 20 having a self-refresh function. Differences from FIG. 9 will be described, and description of common parts will be omitted.
A mode register 201 instead of the refresh management unit 101, a mode register value changing unit (operation cycle setting unit) 210 instead of the timer setting value changing unit (operation cycle setting unit) 110, and a mode register signal instead of the refresh request signal are disclosed. Is done. The refresh management unit 101 and the timer 102 are provided on the SDRAM 20 side described later.
The SNVM request signal is input to the mode register value changing unit (operation cycle setting unit) 210 in the mode register 201. The mode register signal of the mode register 201 is input to the arithmetic algorithm processor 103. The termination signal of the arithmetic algorithm processor 103 is input to the mode register value changing unit (operation cycle setting unit) 210 in the mode register signal.
The operation of these signals will be described.
When the request recognition unit 100 recognizes the memory request signal from the CPU to the SNVM 30, the request recognition unit 100 outputs the SNVM request signal to the arithmetic algorithm processor 103 and the mode register value change unit (operation cycle setting unit) 210 in the mode register 201. The mode register 201 that manages the refresh of the memory cells of the SDRAM 20 changes the refresh operation cycle management information (16 μs) set during the initialization sequence of the SDRAM 20 after the power is turned on, and uses the changed refresh operation cycle management information (8 μs). The result is output to the arithmetic algorithm processor 103 as a mode register signal. The arithmetic algorithm processor 103 instructs the command generation unit 104 to generate a mode register setting command in accordance with the changed mode register signal. A register code indicating the changed refresh operation cycle management information (8 μs) is issued from the address generation unit 105 or the data generation unit 106.
Further, the mode register 201 re-changes the refresh operation cycle management information (8 μs) in response to the terminate signal. The refresh operation cycle management information (8 μs) is re-changed, and the re-changed refresh operation cycle management information (16 μs) is output to the arithmetic algorithm processor 103 as a mode register signal. The arithmetic algorithm processor 103 instructs the command generation unit 104 to generate a mode register setting command according to the changed mode register signal. Note that the register code indicating the re-changed refresh operation cycle management information (16 μs) is issued from the address generator 105 or the data generator 106.

FIG. 2 is a circuit block diagram of the SDRAM 20 corresponding to FIG. 9 (SDRAM controller 10) and FIG. 4 (a timing chart showing a control method when the SDRAM controller 10 issues a refresh command to the SDRAM 20 at a predetermined cycle).
As shown in FIGS. 1 and 2, the SDRAM 20 includes a command determination circuit 21, a refresh control circuit 23, a refresh address counter 26, and a memory cell 24.

  The command determination circuit 21 includes a command decoder circuit 21A. The command decoder circuit 21A receives the clock signal CLK and the various signals SIGNALS. The various signals SIGNALS are an enable clock signal CKE, a row address select signal RAS #, a column address select signal CAS #, and a write enable signal WE #. The command determination circuit 21 recognizes the refresh command issued by the SDRAM controller 10 by the command decoder circuit 21 A, and outputs a refresh request signal to the refresh control circuit 23.

  The refresh control circuit 23 receives a refresh request signal and generates a refresh address by the refresh address counter 26 in response to the refresh request signal. The refresh control circuit 23 outputs a memory cell control signal to the memory cell 24 together with the refresh address.

  The memory cell 24 refreshes the memory cell (recharge injection for data retention) according to the refresh address and the memory cell control signal.

FIG. 11 is a timing chart showing a control method when FIG. 10 (SDRAM controller 10) and FIG. 5 to FIG. 8 (SDRAM controller 10 issue the predetermined period setting information as mode register information to SDRAM 20 having a self-refresh function. 2 is a circuit block diagram of the SDRAM 20 corresponding to (chart). Differences from FIG. 2 will be described, and description of common parts will be omitted.
As shown in FIG. 11, the SDRAM 20 includes a mode register 22, a refresh management unit 27, and a timer 25.

  The command determination circuit 21 includes a command decoder circuit 21A. The command decoder circuit 21A receives the clock signal CLK and the various signals SIGNALS. The various signals SIGNALS are an enable clock signal CKE, a row address select signal RAS #, a column address select signal CAS #, and a write enable signal WE #. The command determination circuit 21 recognizes the mode register setting command issued by the SDRAM controller 10 by the command decoder circuit 21 A, and outputs a mode register setting signal to the mode register 22.

The mode register 22 is connected to the command decoder circuit 21A by a mode register setting signal. The mode register 22 receives a data signal DQ indicating a register code which is refresh operation cycle management information.
The mode register 22 takes in the refresh operation cycle management information according to the mode register setting signal and outputs the refresh operation cycle information signal to the refresh management unit 27.

  The refresh manager 27 is connected to the mode register 22 by a refresh operation cycle information signal. The refresh management unit 27 includes a timer 25 that measures the refresh operation cycle of the memory cell 24. The refresh management unit 27 outputs a refresh request signal to the refresh control circuit 23 for each refresh operation cycle (8 μs or 16 μs) corresponding to the refresh operation cycle information, for the output of the timer 25 that continues to operate after power-on.

  The refresh control circuit 23 receives a refresh request signal and generates a refresh address by the refresh address counter 26 in response to the refresh request signal. The refresh control circuit 23 outputs a memory cell control signal to the memory cell 24 together with the refresh address.

  The memory cell 24 refreshes the memory cell (recharge injection for data retention) according to the refresh address and the memory cell control signal.

  Next, the operation of the memory system 1 will be described. FIG. 3 shows an operation of the SDRAM controller 10 when a signal for accessing the SDRAM 20 and the synchronous flash memory 30 is transmitted from the SDRAM controller 10 including the change of the refresh operation cycle.

  In START, after the power is turned on, the refresh cycle is managed in a first refresh operation cycle (16 μs) which is a predetermined refresh operation cycle. Specifically, after power-on, the SDRAM controller 10 also sets a refresh operation cycle (first refresh operation cycle (16 μs)) during the initialization sequence of the SDRAM 20 that performs latency setting and mode register setting. This is set in the mode register 22 of the SDRAM 20 by a refresh operation cycle setting command (mode register setting command). Thereafter, the SDRAM 20 performs background processing (predetermined refresh operation cycle (16 μs)) by itself in accordance with the register setting. The SDRAM controller 10 only performs register management.

  In step 10 (S10), when there is an access request to the SNVM 30 by a request from the CPU, a second refresh operation cycle (8 μs) setting process for the SDRAM 20 is executed. In the second refresh operation cycle (8 μs) setting process, the SDRAM controller 10 outputs a mode register setting command to the mode register 22 of the SDRAM 20. A data signal DQ indicating a register code which is a mode register setting command and refresh operation cycle management information is a signal for instructing to set the refresh operation cycle to a cycle shorter than the initial setting value (16 μs) (8 μs). . The SDRAM 20 performs a refresh operation in which charges are reinjected into the capacitor of the memory cell 24 connected to the word line in accordance with the second refresh operation cycle (8 μs). The subsequent refresh operation cycle of the SDRAM 20 is shorter than the refresh operation cycle at the time of initial setting (START).

In step 20 (S20), an SNVM30 activation command issuance process is executed. In the SNVM 30 activation command issuing process, various access commands including a read command and a write command for the SNVM 30 are issued.
Data communication is performed between the SDRAM controller 10 and the SNVM 30 in accordance with the SNVM 30 activation command.

In step 30 (S30), SNVM30 deactivation command issuance processing is executed. In the SNVM 30 deactivation command issuance processing, various deactivation commands including the precharge command for the above-described SNVM 30 and the suspend command and termination command that are interruption processing are issued.
In accordance with the SNVM 30 deactivation command, the data communication between the SDRAM controller 10 and the SNVM 30 ends.

  In step 40 (S40), a first refresh operation cycle (16 μs) setting process for the SDRAM 20 is executed in response to the deactivation of the SNVM 30. In the first refresh operation cycle (16 μs) setting process, the SDRAM controller 10 outputs a mode register setting command to the mode register 22. A data signal DQ indicating a register code which is a mode register setting command and refresh operation cycle management information is a signal for instructing a setting to return the refresh operation cycle to the initial setting value (16 μs). The SDRAM 20 performs the refresh operation according to the first refresh operation cycle (16 μs). The subsequent refresh operation cycle of the SDRAM 20 is longer than the refresh operation cycle (8 μs) in step 10 (S10).

Next, the operation of another memory system 1 will be described. FIG. 14 shows the operation of the SDRAM controller 10 when a signal for accessing the SDRAM 20 and the synchronous flash memory 30 is transmitted from the SDRAM controller 10 including the cycle change of the refresh operation.
Differences from FIG. 3 will be described, and description of common parts will be omitted.

In step 200 (S200), an activation command issuing process with SNVM30 precharge function is executed. The activation command with a precharge function means “including an SNVM30 deactivation process automatically following the end of the activation process time for activating the SNVM30 by an access command for activating the SNVM30”. It is a command. Specifically, in the activation command issuing process with a precharge function, various access commands including a read command and a write command for the above-mentioned SNVM 30 are issued to respond to a request for a predetermined burst length and an address depth from the CPU. As soon as the data communication to be completed is completed, the SNVM 30 itself has a function to automatically deactivate the access command.
Data communication is performed between the SDRAM controller 10 and the SNVM 30 in accordance with the SNVM 30 activation command. Then, as soon as communication of a predetermined amount of data is completed, the SNVM 30 automatically starts an inactivation process inside.

  In step 300 (S300), the SDRAM controller 10 executes a refresh cycle control process. In the refresh cycle control process, the SDRAM controller 10 executes a first refresh operation cycle (16 μs) setting process for the SDRAM 20 after a predetermined time adjustment corresponding to the automatic deactivation process of the SNVM 30 itself. to manage. The predetermined time defines the time until the refresh operation cycle is returned from the current set value (8 μs) to the initial set value (16 μs). The specific time setting is set to a time obtained by further adding the time from the activation command with precharge function to the start time of the deactivation process or the heat generation due to the activation operation of the SNVM 30. Also good.

  In step 400 (S400), after a predetermined time adjustment, a first refresh operation cycle (16 μs) setting process is executed. In the first refresh operation cycle (16 μs) setting process, the SDRAM controller 10 outputs a mode register setting command to the mode register 22 of the SDRAM 20. A data signal DQ indicating a register code which is a mode register setting command and refresh operation cycle management information is a signal for instructing a setting to return the refresh operation cycle to the initial set value (16 μs). The SDRAM 20 performs the refresh operation according to the first refresh operation cycle (16 μs). The subsequent refresh operation cycle of the SDRAM 20 is longer than the refresh operation cycle (8 μs) in step 100 (S100).

Note that step 300 (S300) may be added to step 100 (S100). In this case, the various commands issued by the SDRAM controller 10 are in the order of the SNVM 30 active command and the SDRAM 20 mode register setting change command. The predetermined time adjustment between the SNVM 30 active command and the SDRAM 20 mode register setting change command is SNVM 30. Is set to the time from when the heat is activated until the heat in the package heats up. The time until the heat-up is a time until the memory cell of the SDRAM 20 reaches a temperature threshold at which data cannot be held unless the refresh operation cycle is changed. That is, the SNVM 30 is activated in response to the activation command of the SNVM 30, and the mode register setting change command of the SDRAM 20 is issued corresponding to the predetermined adjustment time until the predetermined temperature threshold is reached by the activation operation. The memory cell of the SDRAM 20 is refreshed in the second refresh operation cycle (8 μs) that is shorter than the changed first refresh operation cycle (16 μs).
In other words, the SNVM 30 is activated in response to the activation command of the SNVM 30 and the deactivation command of the SNVM 30 or the auto precharge (automatic deactivation processing of the SNVM 30 is performed before the predetermined adjustment time is reached. ), The mode register setting change command of the DRAM 20 is not issued. This is because the temperature of the SDRAM 20 in the MCP / POP does not reach the temperature threshold.

  In the present embodiment, the SDRAM 20 corresponds to one memory of the present invention. The synchronous flash memory 30 corresponds to another memory of the present invention.

  In the present embodiment, the second refresh operation cycle (8 μs) setting process (S10 / S100) causes the refresh operation cycle to be shorter (8 μs) than the initial setting value (first refresh operation cycle (16 μs)). Is set. Therefore, the second refresh operation cycle (8 μs) setting process (S10 / S100) for setting the refresh operation cycle corresponds to the operation cycle setting unit of the present invention. Further, the timer set value changing unit 110 and the mode register value changing unit 210 in the SDRAM controller 10 correspond to the operation cycle setting unit of the present invention.

  In the present embodiment, the second refresh operation cycle (8 μs) setting process (S10 / S100) causes the refresh operation cycle to be shorter (8 μs) than the initial setting value (first refresh operation cycle (16 μs)). Setting to 1 corresponds to step 2 of the operation cycle setting of the present invention.

  In the present embodiment, the refresh operation cycle (second refresh operation cycle (8 μs)) is returned to the initial set value (16 μs) by the first refresh operation cycle (16 μs) setting process (S40 / S400). . Accordingly, the first refresh operation cycle (16 μs) setting process (S40 / S400) for setting the refresh operation cycle corresponds to the operation cycle setting unit of the present invention. Further, the timer set value changing unit 110 and the mode register value changing unit 210 in the SDRAM controller 10 correspond to the operation cycle setting unit of the present invention.

  In the present embodiment, the refresh operation cycle (second refresh operation cycle (8 μs)) is returned to the initial setting value (16 μs) by the first refresh operation cycle (16 μs) setting process (S40 / S400). This corresponds to step 2 of the operation cycle setting of the present invention.

  In the present embodiment, the SDRAM controller 10 issues an activation command (active command), then immediately issues a refresh operation cycle setting command (mode register setting command) for the SDRAM 20, and then activates the SNVM 30 with a predetermined latency. (Read command or write command) is issued. The time from the active command until the mode register setting command is issued corresponds to a predetermined time adjustment.

  In the present embodiment, adding step 300 (S300) to step 100 (S100) and sequentially setting the active command of SNVM 30 and the mode register setting change command of SDRAM 20 corresponds to a predetermined time adjustment.

  In the present embodiment, until the refresh operation cycle is returned from the current set value (second refresh operation cycle (8 μs)) to the initial set value (first refresh operation cycle (16 μs)) by the refresh cycle control process (S300). The time is adjusted. Therefore, the refresh cycle control process (S300) for adjusting the time until the refresh operation cycle is returned to the initial setting value corresponds to the time adjustment unit in the arithmetic algorithm processor of the present invention. A signal returned to the first refresh operation period (16 μs) corresponding to the precharge command, the terminate command, or the active command with precharge function (Active with autoprecharge command) corresponds to a terminate signal.

  In the present embodiment, adjusting the time until the refresh operation cycle returns from the current set value (second refresh operation cycle (8 μs)) to the initial set value (first refresh operation cycle (16 μs)) This corresponds to the time adjustment step of the invention.

<Effect of embodiment>
The main effects are disclosed from this embodiment.
According to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the amount of heat released from the synchronous flash memory 30 is increased by executing the operation corresponding to the access request to the synchronous flash memory 30. To cope with this, the refresh operation cycle of the SDRAM 20 is changed from the refresh operation cycle before the access request.
Therefore, according to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the refresh operation cycle after the access request is set to the refresh operation cycle necessary for accumulating charges in the capacitor of the memory cell 24. It becomes possible to set.
Therefore, according to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the amount of heat released from the synchronous flash memory 30 increases, and the sustain time during which charges are accumulated in the capacitor of the memory cell 24 of the SDRAM 20 Even when the voltage changes, it is possible to prevent the charge from disappearing from the capacitor of the memory cell 24 by setting the period of the refresh operation necessary for reaccumulating the charge in the capacitor of the memory cell 24.
For this reason, it is possible to prevent the performance of the refresh operation of the SDRAM 20 from being deteriorated due to the influence of the amount of heat released by the synchronous flash memory 30.

According to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the refresh operation cycle of the SDRAM 20 processed in conjunction with the flash memory access command issuing process (S20 / S200) is the second refresh. By the operation cycle (8 μs) setting process (S10 / S100), the cycle (16 μs) before the access request can be shortened (8 μs).
Therefore, according to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, by making the refresh operation cycle after the access access request shorter than the refresh operation cycle (16 μs) before the access access request, After an access access request, the refresh operation can be performed frequently.
Therefore, according to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the amount of heat released from the synchronous flash memory 30 increases, and the sustain time during which charges are accumulated in the capacitor of the memory cell 24 of the SDRAM 20 Even when the time is shortened, it is possible to prevent the charge from disappearing from the capacitor of the memory cell 24 by frequently performing the refresh operation.

According to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the second refresh operation cycle (8 μs) is determined by the termination signal indicating deactivation of the synchronous flash memory 30, and the first refresh operation cycle. (16 μs).
Therefore, according to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the refresh operation cycle of the SDRAM 20 is returned to the returned first refresh operation cycle (16 μs) in accordance with the deactivation of the synchronous flash memory 30. ) Can perform a refresh operation.
Therefore, according to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the amount of heat released from the synchronous flash memory 30 is reduced, and the sustain time for accumulating charges in the capacitor of the memory cell 24 of the SDRAM 20 Is extended in the first refresh operation cycle (16 μs) after the refresh operation is returned, it is possible to prevent the charge from disappearing from the capacitor of the memory cell 24 with low power consumption.

According to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the SDRAM controller 10 issues an active command of the SNVM 30, and then immediately receives a refresh operation cycle setting command (mode register setting command) of the SDRAM 20. After that, the read command or write command of the SNVM 30 is issued with a predetermined latency. As a result, the refresh operation cycle setting command (mode register setting command) of the SDRAM 20 can be issued without an access delay of the SNVM 30.
Further, by adding step 300 (S300) to step 100 (S100), the SNVM 30 is activated in response to the activation command of the SNVM 30, and before the predetermined adjustment time is reached, the SNVM 30 deactivation command or In the case of the auto precharge (automatic deactivation process of SNVM 30), the mode register setting change command of the SDRAM 20 is not issued. As a result, when the temperature of the SDRAM 20 in the MCP / POP does not reach the temperature threshold value, it is possible to suppress the issuing of the refresh operation cycle setting command (mode register setting command) of the SDRAM 20, and in accordance with the amount of heat released by the flash memory 30, It is possible to optimally control the refresh operation cycle after issuing the access command.

According to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, the refresh cycle control corresponds to the time until the synchronous flash memory 30 becomes inactive or the time until heat down after the inactivation. By the processing (S300), it is possible to appropriately adjust the time until the cycle of the refresh operation after issuing the access command is returned from the current set value to the initial set value.
Therefore, according to the memory system 1, the SDRAM controller 10, and the refresh control method thereof according to the present embodiment, the time until the refresh operation cycle after the access command is issued is returned from the current set value to the initial set value is appropriately adjusted. As a result, after the temperature of the SDRAM 20 drops corresponding to the amount of heat released from the synchronous flash memory 30, the refresh operation cycle that has been changed short can be returned to the initial setting value.
Therefore, according to the memory system 1, the SDRAM controller 10, and the refresh control method thereof according to the present embodiment, the refresh operation cycle that has been changed to a short time is returned to the initial set value in response to the temperature drop of the SDRAM 20.
For this reason, the refresh operation can be continued with the optimum power consumption according to the cycle of the refresh operation necessary for reaccumulating the charge in the capacitor of the memory cell 24 of the SDRAM 20 and adapted to the temperature of the SDRAM 20.
Thereby, it is possible to prevent the charge from disappearing from the capacitor of the memory cell 24.

  According to the memory system 1, the SDRAM controller 10 and the refresh control method thereof according to the present embodiment, simultaneous activation of the SDRAM 20 and the synchronous flash memory 30 that generate the largest amount of heat (for example, data transfer between the SDRAM 20 and the synchronous flash memory 30). ) At times, data retention of the SDRAM 20 is guaranteed with current consumption for optimal refresh.

According to the memory system 1 and the SDRAM controller 10 of the present embodiment, the heat generation amount of the synchronous flash memory 30 is the device structure that most affects the SDRAM 20 shared in the same package. At this time, the data retention of the SDRAM 20 is Guaranteed by optimal current consumption.
Further, with respect to the plurality of terminals included in the synchronous flash memory 30 and the SDRAM 20, the more the number of terminals that are connected in the same manner between the synchronous flash memory 30 and the SDRAM 20, the shorter the amount of heat generated in the synchronous flash memory 30. The heat is transferred and the total amount of heat is shared together. At this time, data retention of the SDRAM 20 is ensured with an optimum current consumption.

  The present invention is not limited to the embodiment described above, and can be implemented by appropriately changing a part of the configuration without departing from the spirit of the invention. For example, in the above-described refresh cycle control process (S300), the time / time until the cycle of the refresh operation is changed from the initial set value to a short set value in consideration of the condition that the heat generation in the MCP is expected to be maximized. You may define time until it returns from the present setting value to an initial setting value. As an example of the condition where the heat generation of the MCP is expected to be maximized, data is transferred from the synchronous flash memory in the MCP to the SDRAM in the same MCP, and both memories mounted in the MCP execute an access operation. It is assumed that

  Further, in place of the SNVM request signal input to the operation cycle setting unit 13, the signal may be changed to a signal limited to conditions under which both the SDRAM 20 and the SNVM 30 operate. This is an example of a condition in which the heat generation of the MCP is expected to be maximized, and it can cope with the most severe condition of the temperature in the MCP in consideration of the refresh characteristic of the memory cell 24 of the SDRAM 20.

  Unlike the above-described embodiment, the refresh cycle control process (S30) illustrated in FIG. 3 may be omitted, and the refresh cycle may be changed by the SDRAM controller 10 after the access command is issued.

  Further, the refresh cycle of the nonvolatile memory in the same MCP may be changed instead of refreshing the SDRAM in the MCP. Specifically, the nonvolatile memory includes charge retention characteristics (floating gate structure or NROM structure flash memory), resistance retention characteristics (ReRAM), phase change characteristics (PRAM) and magnetic properties of a memory cell that is a nonvolatile storage unit. In consideration of the retention characteristics, the refresh cycle of the nonvolatile memory in the MCP corresponds to the active / inactive access of other functional chip dies in the same MCP. The controller that collectively controls the memory and the other function chip die changes or extends the refresh operation cycle of the nonvolatile memory before and after the activation / deactivation access command is issued to the function chip die.

The present invention can also be applied to a device in which a plurality of SDRAM chip dies are packaged together.
Specifically, the controller for controlling the first SDRAM and the second SDRAM collectively changes or extends the refresh operation cycle of the second SDRAM before and after the activation / inactivation access command is issued to the first SDRAM.

  Further, the present invention can be applied to a device having a POP structure instead of a device having an MCP structure.

Further, between the second refresh operation cycle (8 μs) setting process (S10 / S100) and the flash memory access command issuing process (S20 / S200), the communication process or memory to other devices controlled by the memory controller This includes communication processing steps between the controller and the CPU.
That is, in contrast to the process of accessing the synchronous flash memory 30 (S20 / S200), the refresh cycle setting change process (S10 / S100) to the SDRAM 20, which is the preprocess of the present invention, is relatively a preprocess step. I just need it. Similarly, between the first refresh operation cycle (16 μs) setting process (S40 / S400) and the flash memory access command issuing process (S20 / S200), the communication process to other devices controlled by the memory controller or This includes communication processing steps between the memory controller and the CPU. That is, in contrast to the process of accessing the synchronous flash memory 30 (S20 / S200), the refresh cycle setting change process (S40 / S400) to the SDRAM 20, which is the post-process of the present invention, is a relatively post-process step. I just need it.

It is a circuit block diagram of a memory system. 1 is a circuit block diagram of an SDRAM provided in a memory system. It is a flowchart explaining operation | movement of the SDRAM controller with which a memory system is provided. It is a 1st time chart explaining operation of an SDRAM controller. It is a 2nd time chart explaining operation | movement of an SDRAM controller. It is a 3rd time chart explaining operation | movement of an SDRAM controller. It is a 4th time chart explaining operation | movement of an SDRAM controller. It is a 5th time chart explaining operation | movement of an SDRAM controller. It is a circuit block diagram of an SDRAM controller. FIG. 5 is another circuit block diagram of the SDRAM controller. It is another circuit block diagram of SDRAM with which a memory system is provided. It is a figure explaining the package structure with which a memory system is provided. It is a figure explaining the other package structure with which a memory system is provided. It is a flowchart explaining other operation | movement of the SDRAM controller with which a memory system is provided.

1 memory system 10 SDRAM controller 20 SDRAM
30 Synchronous flash memory 11, 100 Request recognition unit 12, 102 Operation algorithm processor 13, 110, 210 Operation cycle setting unit 22, 201 Mode register 23 Refresh control circuit 24 Memory cell 25, 102 Timer 26 Refresh address counter 27, 101 Refresh Management Department

Claims (16)

In a memory controller connected to a plurality of memories including a memory that requires a refresh operation for maintaining data of memory cells in a predetermined cycle,
A memory request signal recognizing request recognition portion of the device requesting access to different other memory as one of the memory required before Symbol refresh operation,
And a duty cycle setting section for setting a refresh operation cycle of said one memory,
The operation cycle setting unit includes:
Wherein if the memory request signal is an access request signal to the other memory requirements Motome認識部 recognizes, the second refresh operation cycle is the refresh operation cycle after reception of the access request signal, said access Shorter than the first refresh operation cycle, which is the refresh operation cycle before receiving the request signal,
The memory controller , wherein the second refresh operation cycle is returned to the first refresh operation cycle when the memory request signal recognized by the request recognition unit is a terminate signal that deactivates the other memory. . The memory controller according to claim 1 , further comprising a time adjustment unit that adjusts a time from the predetermined cycle to the setting of the second refresh operation cycle. A time adjustment unit that adjusts a time until the second refresh operation cycle is returned to the predetermined cycle is provided, and a termination signal that is an output signal of the time adjustment unit is input to the operation cycle setting unit. The memory controller according to claim 1 . Wherein the operation cycle setting unit, wherein the access request signal of the access request signal to another memory to said one memory requirements Motome認識部recognizes is inputted, the operation cycle setting section in accordance with these signals the memory controller according to any one of claims 1 to 3, wherein changing the setting value. The memory controller, the memory controller according to any one of claims 1 to 4, wherein the at least two memory of the plurality of memories are connected to a device that is stacked and mounted on the same package. The memory controller according to claim 5 , wherein the memory controller is connected to a composite device on which the devices are stacked. Command control terminals, address terminals, and data terminals of the one memory and the other memory are commonly connected to the memory controller,
The memory controller according to any one of claims 1 to 6, wherein said memory controller controls the same command system in the one memory and the other memory. In a memory system having a plurality of memory including a memory requiring refresh operation for data retention of the memory cell at a predetermined period,
Wherein comprising a Rume memory controller to control an access request to a different other memory refresh operation and an access request to one of memory required and the refresh operation in the one memory required,
The memory controller is,
The second refresh operation cycle that is the refresh operation cycle after receiving the access request to the other memory is set to be greater than the first refresh operation cycle that is the refresh operation cycle before receiving the access request to the other memory. A memory system characterized in that the second refresh operation cycle is returned to the first refresh operation cycle in response to deactivation of an access request of the other memory. The memory system of claim 8, wherein the obtaining Bei time adjustment unit that adjusts the time from the first refresh operation cycle until set to the second refresh operation cycle. The memory system of claim 8, wherein the obtaining Bei time adjustment unit that adjusts the time of the second refresh operation cycle to return to the first refresh operation cycle. 11. The memory system according to claim 8 , wherein the memory system includes a device in which at least two of the plurality of memories are stacked and mounted in the same package. The memory system according to claim 11 , wherein the memory system is connected to a composite device in which the devices are stacked and mounted. Command control terminals, address terminals, and data terminals of the one memory and the other memory are commonly connected to the memory controller,
13. The memory system according to claim 8, wherein the memory controller controls the one memory and the other memory with the same command system. In a refresh operation control method for a memory controller connected to a plurality of memories including a memory that requires a refresh operation for maintaining data of memory cells in a predetermined cycle,
And recognizing 1 memory request signal from a device requesting access to different other memory and the refresh operation in the one memory required,
Equipped with automatic answering Step 2 to change the refresh operation cycle of the previous SL one memory,
In the step 2, when the memory request signal recognized in the step 1 is an access request signal to the other memory, a second refresh operation cycle, which is the refresh operation cycle after receiving the access request signal, Shorter than the first refresh operation cycle, which is the refresh operation cycle before receiving the access request signal,
When the memory request signal recognized in the step 1 is a signal for deactivating the other memory, the second refresh operation cycle is returned to the first refresh operation cycle. Operation control method. 15. The refresh operation control method for a memory controller according to claim 14 , further comprising a time adjustment step of adjusting a time until the first refresh operation cycle is set to the second refresh operation cycle. 15. The refresh operation control method for a memory controller according to claim 14 , further comprising a time adjustment step of adjusting a time until the second refresh operation cycle is returned to the first refresh operation cycle.

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