JP4910117B2 - Stacked memory device - Google Patents

Description

The present invention relates to a stacked memory equipment.

  For example, Patent Document 1 discloses a method and apparatus for dynamically adjusting the refresh rate of a memory module according to the state of a computer system.

  The apparatus of Patent Literature 1 is used for detecting a change in at least one of a system state, a means for detecting a change in at least one of the system states to be monitored, a means for detecting a change in at least one of the system states to be monitored. Correspondingly, there are provided judging means for determining the optimum refresh rate in the current state of the computer system and means for setting the refresh rate to the judged optimum refresh rate.

  According to the apparatus of Patent Document 1, unlike the case where the refresh rate cannot be changed, the refresh rate can be set to the optimum refresh rate. Thereby, according to the apparatus of patent document 1, it is not necessary to design a cooling system excessively in consideration of rebooting of a computer system, for example. Therefore, in the apparatus of Patent Document 1, it is possible to avoid an increase in cost due to excessive setting of environmental facilities (such as a cooling system) related to the computer system.

  The device of Patent Document 2 uses a tape including a metal core between the first chip and the second chip so that heat generated from the first and second chips inside the multichip package can be efficiently released to the outside. Means.

  According to the device of Patent Document 2, a highly integrated DRAM element in which the first and second chips are operated at high speed, and a metal core having excellent heat transfer characteristics for heat generated from the second chip, which is the upper layer chip. It can be discharged to the heat transfer path connected to the ground bonding part, the substrate, and the solder ball through the tape containing the MCP, so that the thermal performance of the MCP is improved (the refresh characteristic deteriorates due to the temperature rise in the MCP). Can be prevented).

JP 2006-120144 A JP 2003-332524 A

  By the way, in order to meet the demand for miniaturization and high performance, recent memories employ an MCP (Multi-Chip-Package) structure or a POP (Package-On-Package) structure in which a plurality of memories are mounted. .

  In a DRAM (Dynamic Random Access Memory), a refresh operation for holding data at a predetermined cycle is required in order to prevent the data of the memory cells written in the DRAM from disappearing over time.

  However, in a DRAM, the data retention time is shortened as the temperature rises, so that it is required to frequently perform a refresh operation as the temperature rises.

  Therefore, in the MCP structure in which the DRAM and another memory different from the DRAM are mounted, when the temperature of the DRAM rises due to the heat released from the other memory, the time for the DRAM to hold data is shortened. For this reason, as the temperature of the DRAM rises, it becomes difficult to prevent the data from disappearing, and the performance of the refresh operation of the DRAM may be deteriorated.

  Further, a plurality of system state monitoring means (temperature detection elements and the like) disclosed in Patent Document 1 are added in an MCP (Multi-Chip-Package) device or a POP (Package-On-Package) device. Can not. In a device structure in which a plurality of chip dies are mounted (for example, laminated) with a resin or the like, it is structurally difficult to incorporate the monitoring means, and the power consumption of the monitoring means itself depends on the temperature and power consumption of the device. That amount of heat is added. For this reason, it becomes difficult for the monitoring unit to accurately monitor a plurality of system states excluding the power consumption and the amount of heat of the monitoring unit itself.

  Further, the tape including the metal core disclosed in Patent Document 2 causes an increase in cost due to a new material. In addition, the flexibility of the layout of a large number of wirings on the substrate of the second chip, which is the upper chip, is hindered, and the yield is reduced due to an electrical short between the wirings and the metal tape. The problem that the second chip that is the upper layer chip and the first chip that is the lower layer chip directly share heat is not disclosed. Further, it is difficult to guarantee refresh for data retention for the middle layer chip between the upper layer chip and the lower layer chip without using a tape including a metal core.

  And the said patent document 2 is not disclosing the subject and solution in the structure where two chip die | dyes were connected by heat resistance connection by connection with low resistance and high thermal conductivity. Specifically, the lower layer chip operates due to the deterioration of the refresh characteristics of the lower layer chip due to the lower layer chip receiving the operation heat of the upper layer chip, or due to the operation heat generation of the upper layer chip operating at a higher frequency than the lower layer chip. It does not assume a structure and its thermal environment including connection conditions such as deterioration of refresh characteristics of the lower layer chip by receiving an operation heat generation of the upper layer chip larger than the heat generation. The same applies to the case where the upper layer chip generates a large operating heat in response to a command from the controller in an idle or power-down state (only the self-refresh operation) when the lower layer chip is not accessed from the controller.

The present invention has been proposed in view of such a situation, and the refresh operation of the first memory is influenced by the influence of heat released from another memory different from the first memory among the plurality of memories. and to provide a stacked memory equipment capable of preventing the poor performance.

  In the stacked memory device according to the first aspect of the present invention, a plurality of memories including a first memory that requires a refresh operation of a memory cell at a predetermined cycle and a non-volatile second memory are stacked on a mother substrate. In the stacked memory device, the first memory and the memory may be provided by an insulator disposed between the first memory and the second memory, and an electrical connection body having a thermal conductivity higher than a thermal conductivity of the insulator. A second memory is connected in common with heat, and the first memory is arranged on the mother board in the lowest layer of the plurality of stacked memories, and the second memory is arranged in the upper layer. To do.

According to the stacked memory device of the first aspect of the present invention, the first memory that requires the refresh operation of the memory cells at a predetermined cycle is disposed in the lowermost layer of the plurality of memories stacked on the mother substrate. A second memory in which the first memory and the second memory are connected by heat sharing with an electrical connection body having high thermal conductivity is disposed in the upper layer. Further, a third memory of a plurality of stacked memories in which the first memory and the second memory are not commonly connected is arranged in an intermediate layer between the first memory at the lowest layer and the second memory at the upper layer. Has been.
Therefore, according to the stacked memory device of the first aspect of the present invention, the area where the heat released by the second memory is released from the mother substrate via the first memory connected in a heat sharing manner is set to the first. The lower surface of the memory can be secured over the area facing the mother substrate. Thereby, the thermal conductivity of the mother substrate with respect to the second memory can be increased, and the heat released by the second memory can be easily moved toward the mother substrate.
Therefore, according to the stacked memory device of the first aspect of the present invention, the temperature of the first memory requiring the refresh operation is increased by facilitating the transfer of the heat released from the second memory toward the mother substrate. This prevents the stored contents held in the first memory from disappearing due to the temperature rise of the first memory. As a result, the performance of the refresh operation of the first memory that is heat-sharing connected to the second memory by the electrical connection body having high thermal conductivity under the influence of the heat released from the second memory is prevented. be able to.

  According to the stacked memory device of the present invention, the heat released by the second memory can be easily moved toward the mother substrate, so that the refresh operation in which the heat connection is performed by the electrical connection body having high thermal conductivity. Can be prevented from rising, and the stored contents held in the first memory can be prevented from disappearing due to the temperature rise of the first memory. Accordingly, it is possible to prevent the performance of the refresh operation of the first memory from being deteriorated due to the influence of the heat released from the other memory that is thermally connected to the first memory by the electrical connection body having high thermal conductivity. be able to.

<Embodiment 1>
Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 is an example of a stacked memory device of the present invention. The semiconductor device 1 includes a mother substrate 10, a synchronous DRAM 20 (SDRAM 20) that is a volatile memory, a NAND memory 30 that is a nonvolatile memory, and a synchronous flash memory 40 (SNVM 40) that is a nonvolatile memory. Yes. In the semiconductor device 1, the memories 20, 30 and 40 are combined to form an MCP. The SDRAM 20 and the SNVM 40 communicate with an SDRAM controller (not shown), and the NAND memory 30 communicates with a NAND memory controller (not shown). The memory system 1 includes a semiconductor device 1, an SDRAM controller, and a NAND memory controller.

  The SDRAM 20 and the SNVM 40 operate at the same high frequency / or the frequency at which the SNVM 40 is higher than the SDRAM 20, and the NAND memory 30 operates at a low frequency lower than the operating frequency of the SDRAM 20 and the SNVM 40. The amount of heat generated by these operations generally depends on the frequency. Therefore, the heat generation amount of the SNVM 40 is larger than the heat generation amount of the NAND memory 30.

In the memory system 1, the SDRAM controller, SDRAM 20 and SNVM 40 are connected between the three by the same control line (system clock signal, other various clock signals, various command signals, address signals and data signals) excluding the chip select signal. Commonly connected. The SDRAM controller controls the SDRAM 20 and the SNVM 40 with the same command system (for example, read and write commands).
The commonly connected control lines are commonly connected to each other with a metal material having a low resistance and a high thermal conductivity (for example, 50 to 400 W / mK which is a metal system) in the memory system 1 or the semiconductor device 1. ing.

  The SDRAM controller, SDRAM 20 and SNVM 40 share the heat generated by the mutual operation in a short time. In particular, heat is shared through the commonly connected control lines in the MCP device and the POP device. When the data retention (maintenance) characteristic of the memory cell of the SDRAM 20 depends on a thermal element, even if the SDRAM 20 is not operated according to a command from the SDRAM controller (only a self-refresh operation), the SNVM 40 heats due to the high-speed operation of the SNVM 40. The heat is transferred and shared to the SDRAM 20 in a short time by the commonly connected control lines, and the data retention characteristics of the memory cells of the SDRAM 20 deteriorate. The case where the amount of heat generated in the MCP device or the POP device is the largest is when the SDRAM 20 and the SNVM 40 operate simultaneously. For example, data communication is performed between the SDRAM 20 and the SNVM 40 according to a command from the SDRAM controller.

  In other words, the most severe environment of the device of the present application includes a structure including a connection that receives the operation heat generation of the SNVM 40 in which the SDRAM 20 is connected in heat sharing by a low resistance and high thermal conductivity connection in addition to its own operation heat generation and its thermal environment. It is.

  In FIG. 1, bonding wire connection electrodes 11 and 12 are formed on the upper surface of a mother substrate 10. Solder balls 15 are attached to the lower surface of the mother substrate 10.

  The SDRAM 20 is bonded to the upper surface of the mother substrate 10 with an adhesive layer 50. The adhesive layer 50 is formed by filling a thermosetting epoxy resin between the upper surface of the mother substrate 10 and the lower surface of the SDRAM 20. The above refresh operation is performed on the SDRAM 20. The SDRAM 20 has a self-refresh function (a function for autonomously performing a refresh operation according to a timer in the SDRAM 20 according to refresh cycle information given from the SDRAM controller).

  The NAND memory 30 is bonded to the upper surface of the SDRAM 20 by the adhesive layer 51 formed between the upper surface of the SDRAM 20 and the lower surface of the NAND memory 30.

  The SNVM 40 is bonded to the upper surface of the NAND memory 30 by the adhesive layer 51 formed between the upper surface of the NAND memory 30 and the lower surface of the SNVM 40.

  In the semiconductor device 1, the SDRAM 20, the NAND memory 30, and the SNVM 40 are integrated by the adhesive layer 50 and each adhesive layer 51. Each of the memories 20, 30 and 40 is stacked on the mother substrate 10.

  In the semiconductor device 1, the SDRAM 20 is located in the lowest layer among the memories 20, 30, and 40 stacked over three layers. The SNVM 40 is located in the uppermost layer among the memories 20, 30, 40 stacked over the three layers. A NAND memory 30 is located between the SDRAM 20 and the SNVM 40.

  The SDRAM 20 includes a lead wire connection electrode 25. Each lead wire connection electrode 25 performs wire bonding with the bonding wire connection electrode 11 of the mother substrate 10 by using an Au (gold) wire 61.

  The SNVM 40 includes a lead wire connection electrode 45. Each lead wire connection electrode 45 performs wire bonding with the bonding wire connection electrode 11 of the mother substrate 10 by using the Au wire 62. The lead wire connection electrode 25 of the SDRAM 20 and the lead wire connection electrode 45 of the SNVM 40 are electrically connected to the same solder ball 15 and / or commonly bonded to the same bonding wire connection electrode 11. That is, the SDRAM 20 and the SNVM 40 are heat-shared by the electrical connection body having high thermal conductivity in the semiconductor device 1 that is an MCP. This is because the SDRAM 20 and the SNVM 40 are passive devices that operate in response to a command from a common SDRAM controller.

  The NAND memory 30 includes a lead wire connection electrode 35. Each lead wire connection electrode 35 performs wire bonding with the bonding wire connection electrode 12 of the mother substrate 10 by using the Au wire 63. Each lead wire connection electrode 35 is wire-bonded to a bonding wire connection electrode 12 different from the bonding wire connection electrode 11 described above. That is, in the NAND memory 30 in the semiconductor device 1 that is an MCP, the SDRAM 20 and the SNVM 40 are not thermally shared by an electrical connection body having high thermal conductivity. This is because the NAND memory 30 is a passive device that operates in response to a command from a NAND memory controller different from the SDRAM controller.

  In the semiconductor device 1, the Au wires 61 to 63, the memories 20, 30, and 40 and the adhesive layers 50 and 51 are sealed with a mold resin 70, respectively.

  In the present embodiment, as described above, the SDRAM 20 thermally connected to the SNVM 40 by the electrical connection body having high thermal conductivity is disposed on the upper surface of the mother substrate 10 with the adhesive layer 50 interposed therebetween. For this reason, the area discharged from the mother substrate 10 via the adhesive layer 50 can be ensured over the area where the lower surface of the SDRAM 20 faces the mother substrate 10. That is, in two chips that share heat with a control line that is commonly connected to each other with a metal material having high thermal conductivity, the SDRAM 20 can prevent deterioration of the refresh characteristics of the DRAM 20 from heat generated by the SNVM 40.

  The area discharged from the mother substrate 10 through the adhesive layer 50 is secured over the area where the lower surface of the SDRAM 20 faces the mother substrate 10, thereby increasing the value of the thermal conductivity of the mother substrate 10 with respect to the SNVM 40 ( Assist). Thereby, the value of the thermal resistance of the mother board 10 with respect to the SNVM 40 can be further reduced.

  In the present embodiment, as described above, the SDRAM 20 is located in the lowest layer among the memories 20, 30, and 40 stacked over three layers. On the other hand, the SNVM 40 is located in the uppermost layer among the memories 20, 30, 40 stacked over three layers.

  The SDRAM 20 located at the lowermost layer is disposed away from the SNVM 40 located at the uppermost layer.

  In the present embodiment, as described above, the SNVM 40 is disposed on the upper surface of the NAND memory 30 with the adhesive layer 51 interposed therebetween. In other words, the SNVM 40 and the SDRAM 20 that are heat-sharingly connected by an electrical connection body having high thermal conductivity has a sandwich structure in which the NAND memory 30 is sandwiched. Regarding the influence of heat on the NAND memory 30 of the SNVM 40, the heat released by the SNVM 40 is the heat of the adhesive layer 51 between the NAND memory 30 and the SNVM 40 and the heat of the adhesive layer 51 between the NAND memory 30 and the SDRAM 20. It is transmitted to the NAND memory 30 according to the resistance value. This is because both electrical signals are not commonly connected within the MCP.

  The value of the thermal conductivity of the Au wire 63 (for example, 50 W / mK to 400 W / mK which is a metal type) is the value of the thermal conductivity of each adhesive layer 51 (for example, polyimide, silicone, epoxy type thermal conductivity). It is larger than 0.2 W / mK to 0.8 W / mK) which is an adhesive. For this reason, the value of the thermal resistance of the Au wire 63 is smaller than the value of the thermal resistance of each adhesive layer 51. Therefore, both the heat transferred to the NAND memory 30 via the SNVM 40 having the sandwich structure through the adhesive layer 51 and the heat transferred to the NAND memory 30 from the SNVM 40 via the SDRAM 20 are both Au wire. Through 63, it becomes easy to be transmitted to the mother board 10. Thereby, the heat dissipation effect of SNVM40 increases. In other words, in a stacked memory device having a sandwich structure composed of two chip dies that are connected in heat sharing with high thermal conductivity and three chip dies sandwiched between them and other chip dies that are not connected in heat sharing, they are generated in the two chip dies. The heat thus produced has a synergistic effect that the heat dissipation is assisted through the other chip die sandwiched between them.

  This feature is that the SNVM 40 and SDRAM 20 in which the electrical signals of each other are shared and connected with high thermal conductivity are arranged between the two chip dies, and the mother substrate 10 has high thermal conductivity different from the signal lines of the SNVM 40 and SDRAM 20. The NAND memory 30 including the signal line connected to the can be used as a heat sink. In other words, the chip of the NAND memory 30 that operates at a low frequency and / or is in an inactive state eliminates a new material and a special structure as a heat dissipation means of the SDRAM 20 that shares heat with the SNVM 40 that operates at a high frequency that is a sandwich structure. Can be combined.

  In the present embodiment, the SDRAM 20 is an example of the first memory of the present invention. The SNVM 40 is an example of the second memory of the present invention. The NAND memory 30 is an example of a third memory of the present invention. The adhesive layers 50 and 51 are an example of the insulator of the present invention.

  In the present embodiment, the bonding wire connection electrode 11 or the solder ball 15 is an example of an electrode terminal in which the first memory and the second memory of the present invention are commonly connected. The bonding wire connection electrode 12 is an example of another electrode terminal of the present invention.

<Effect of Embodiment 1>
In the semiconductor device 1 of the present embodiment, the SDRAM 20 that requires a refresh operation is located in the lowest layer among the memories 20, 30, and 40 stacked on the mother substrate 10 in three layers, and has high thermal conductivity. An SNVM 40 (40) connected to the SDRAM 20 (20) by heat sharing by an electrical connection body is located in the upper layer.
Therefore, according to the semiconductor device 1 of the present embodiment, the area where the heat released by the SNVM 40 is released from the mother substrate 10 via the heat sharing SDRAM 20, and the lower surface of the SDRAM 20 faces the mother substrate 10. Over the area to be secured. Thereby, the thermal conductivity of the mother substrate 10 with respect to the SNVM 40 can be increased, and the heat released by the SNVM 40 can be easily moved toward the mother substrate 10.
Therefore, according to the semiconductor device 1 of the present embodiment, the heat released from the SNVM 40 is easily moved toward the mother substrate 10, thereby suppressing the temperature of the SDRAM 20 from rising. The charge accumulated in the capacitor of the memory cell of the SDRAM 20 can be prevented from disappearing. Accordingly, it is possible to prevent the performance of the refresh operation of the SDRAM 20 thermally connected by the electrical connection body having high thermal conductivity with the SNVM 40 from being affected by the heat released from the SNVM 40.

In the semiconductor device 1 of the present embodiment, the operating frequency of the SNVM 40 is higher than or the same as the operating frequency of the SDRAM 20.
Therefore, according to the semiconductor device 1 of the present embodiment, the amount of heat generated by the operation of the SNVM 40 is greater / or the same as the amount of heat generated by the operation of the SDRAM 20.
Therefore, according to the semiconductor device 1 of the present embodiment, it is possible to suppress an increase in the temperature of the SDRAM 20 due to the influence of heat released from the SNVM 40. In particular, when the SDRAM 20 is not accessed from the outside (that is, when only the internal refresh operation for holding data is performed), the temperature of the SDRAM 20 rises due to the influence of heat released by the SNVM 40. That can be suppressed.

In the semiconductor device 1 of the present embodiment, the SNVM 40 (40) that is connected in heat sharing with the SDRAM 20 (20) is located in the uppermost layer of the memories 20, 30, and 40 stacked on the mother substrate 10 in three layers. In the intermediate layer, the NAND memory 30 (30) in which the SDRAM 20 and the SNVM 40 are not commonly connected is located.
Therefore, according to the semiconductor device 1 of the present embodiment, the SDRAM 20 is disposed away from the SNVM 40 located in the uppermost layer among the memories 20, 30, 40 stacked in three layers, and the NAND memory 30 Can be used as the heat sink of the SDRAM 20 and the SNVM 40 connected in a heat sharing manner.
Therefore, according to the semiconductor device 1 of the present embodiment, it is possible to suppress an increase in the temperature of the SDRAM 20 due to the influence of heat released from the SNVM 40.

According to the semiconductor device 1 of the present embodiment, in the SDRAM 20, the NAND memory 30 and the SNVM 40 stacked over three layers, a bonding wire connection electrode different from the bonding wire connection electrode 11 is between the SDRAM 20 and the SNVM 40. 12, a NAND memory 30 wire-bonded to is disposed.
Therefore, according to the semiconductor device 1 of the present embodiment, the heat that the SNVM 40 emits through the Au wire 63 that is connected to the lead wire connection electrode 35 of the NAND memory 30 and has excellent thermal conductivity is used as the bonding wire connection electrode 12 and This can be transmitted to the mother board 10. Thereby, the heat sink effect of the NAND memory 30 can be maximized. In particular, when the NAND memory 30 controlled by a memory controller different from the memory controller of the SDRAM 20 / SNVM 40 is in an inactive state, the temperature of the SDRAM 20 is prevented from rising due to the influence of heat released by the SNVM 40. be able to.

In the semiconductor device 1 of the present embodiment, the operating frequency of the SNVM 40 is higher than the operating frequency of the NAND memory 30.
Therefore, according to the semiconductor device 1 of the present embodiment, the amount of heat generated by the operation of the SNVM 40 is larger than the amount of heat generated by the operation of the NAND memory 30.
Therefore, according to the semiconductor device 1 of the present embodiment, the heat sink effect of the NAND memory 30 can be maximized.

<Embodiment 2>
A second embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a schematic cross-sectional view of the semiconductor device 2 of the second embodiment. Here, the same configurations as those of the first embodiment are denoted by the same reference numerals, and the description thereof is simplified. The semiconductor device 2 includes a mother substrate 10, synchronous DRAMs 20A and 20B (SDRAMs 20A and SDRAM 20B) that are volatile memories, NAND memories 30A and 30B that are nonvolatile memories, and a synchronous flash memory 40 that is a nonvolatile memory ( SNVM40). In the semiconductor device 2, the MCP is configured as in the semiconductor device 1 of the first embodiment. The SDRAM 20A, the SDRAM 20B, and the SNVM 40 are commonly connected to each other with a metal material having a low resistance and a high thermal conductivity, and share heat. The NAND memories 30A and 30B are commonly connected to each other with a metal material having a low resistance and a high thermal conductivity, and share heat.

  The SDRAM 20 </ b> A is bonded to the upper surface of the mother substrate 10 by the adhesive layer 50. The above-described refresh operation is performed on the SDRAM 20A. The SDRAM 20A has a self-refresh function.

  The NAND memory 30A is bonded to the upper surface of the SDRAM 20A by the adhesive layer 51 formed between the upper surface of the SDRAM 20A and the lower surface of the NAND memory 30A.

  The SDRAM 20B is bonded to the upper surface of the NAND memory 30A by the adhesive layer 51 formed between the upper surface of the NAND memory 30A and the lower surface of the SDRAM 20B. The above refresh operation is performed on the SDRAM 20B. The SDRAM 20B has a self-refresh function.

  The NAND memory 30B is bonded to the upper surface of the SDRAM 20B by the adhesive layer 51 formed between the upper surface of the SDRAM 20B and the lower surface of the NAND memory 30B.

  The SNVM 40 is bonded to the upper surface of the NAND memory 30B by the adhesive layer 51 formed between the upper surface of the NAND memory 30B and the lower surface of the SNVM 40.

  In the semiconductor device 2, the memories 20 </ b> A, 30 </ b> A, 20 </ b> B, 30 </ b> B, and 40 are integrated by the adhesive layer 50 and the adhesive layers 51. The memories 20A, 30A, 20B, 30B, and 40 are stacked on the mother board 10.

  In the semiconductor device 2, the SDRAM 20A is located in the lowermost layer of each of the memories 20A, 30A, 20B, 30B, and 40 stacked over five layers. The SNVM 40 is located in the uppermost layer of each of the memories 20A, 30A, 20B, 30B, and 40 stacked over five layers. An SDRAM 20B is disposed at a position closer to the SNVM 40 located at the uppermost layer than the SDRAM 20A located at the lowermost layer.

  In the semiconductor device 2, the NAND memory 30A is located between the SDRAM 20A and the SDRAM 20B. A NAND memory 30B is located between the SDRAM 20B and the SNVM 40.

  Each lead wire connection electrode 25 of the SDRAM 20 </ b> A performs wire bonding with the bonding wire connection electrode 11 by using the Au wire 61. Each lead wire connection electrode 25 of the SDRAM 20B performs wire bonding with the bonding wire connection electrode 11 by using an Au wire 65.

  Each lead wire connection electrode 35 of the NAND memory 30 </ b> A performs wire bonding with the bonding wire connection electrode 12 by using the Au wire 63. Each lead wire connection electrode 35 of the NAND memory 30 </ b> B performs wire bonding with the bonding wire connection electrode 12 by using an Au wire 66.

  In the present embodiment, like the SDRAM 20 of the first embodiment, the SDRAM 20A is disposed on the upper surface of the mother substrate 10 with the adhesive layer 50 interposed therebetween. For this reason, as described above, the value of the thermal conductivity of the mother substrate 10 with respect to the SDRAM 20A can be increased. As a result, the heat released by the SNVM 40 can be easily moved toward the mother substrate 10.

  In contrast, the SDRAM 20B is disposed between the NAND memory 30A and the NAND memory 30B. Therefore, the SDRAM 20B is sandwiched between the NAND memory 30A and the NAND memory 30B, which are heating elements.

  For this reason, in the SDRAM 20B, the temperature rises easily due to the influence of heat released from the NAND memories 30A and 30B. In addition, the distance from the SDRAM 20B to the mother substrate 10 is longer (far) than the distance from the SDRAM 20A to the mother substrate 10. For this reason, the thermal conductivity of the SDRAM 20B with respect to the mother substrate 10 is smaller than the thermal conductivity of the SDRAM 20A with respect to the mother substrate 10. Therefore, the heat dissipation effect of SDRAM 20B is inferior to that of SDRAM 20A.

  In the present embodiment, the SDRAM 20A is an example of a first memory according to the present invention. The SDRAM 20B is an example of another first memory of the present invention. SNVM 40 is a second example of the present invention.

  FIG. 3 is a circuit block diagram of the SDRAM controller 80. The SDRAM controller 80 is connected to each of the memories 20A, 20B, and 40 from outside the semiconductor device 2. The SDRAM controller 80 issues period setting information to the SDRAMs 20A and 20B as mode register information.

  The SDRAM controller 80 includes a request recognition unit 100, an arithmetic algorithm processor 103, a command generation unit 104, an address generation unit 105, a data generation unit 106, a memory interface unit 107, a first mode register 201, a second mode register 201, and a second mode register 201. And a mode register 202.

  The request recognition unit 100 recognizes a memory request signal transmitted from a CPU (Central Processing Unit). The memory request signal is used for data access to each of the memories 20A, 30A, 20B, 30B, and 40.

  The request recognition unit 100 outputs an SD request signal when accessing the SDRAMs 20A and 20B. The request recognition unit 100 outputs an SNVM request signal when accessing the SNVM 40.

  The arithmetic algorithm processor 103 issues a communication rule with a predetermined routine in accordance with specifications (command type, latency, burst length, address, data, etc.) for communication with each of the memories 20A, 20B, and 40.

  The first mode register 201 manages refresh of the memory cell of the SDRAM 20A. The first mode register 201 includes a first mode register value setting unit (first operation cycle setting unit) 210. The SNVM request signal is input to the first mode register value setting unit 210.

  The first mode register 201 outputs a first mode register signal S1 to the arithmetic algorithm processor 103.

  The second mode register 202 manages refresh of the memory cell of the SDRAM 20B. The second mode register 202 includes a second mode register value setting unit (second operation cycle setting unit) 220. The SNVN request signal is input to the second mode register value setting unit 220.

  The second mode register 202 outputs the second mode register signal S2 to the arithmetic algorithm processor 103.

  The command generation unit 104 generates a predetermined command control signal in response to a command from the arithmetic algorithm processor 103. The address generator 105 generates a predetermined address signal in response to a command from the arithmetic algorithm processor 103. The data generator 106 generates a predetermined data signal in response to a command from the arithmetic algorithm processor 103.

  The memory interface unit 107 transmits the command control signal, the address signal, and the data signal to the memories 20A, 20B, and 40, respectively. Note that a circuit block diagram for transmitting data from the memories 20A, 20B, and 40 to the CPU is not shown.

  The SDRAM controller 80 operates as described below. When the request recognition unit 100 recognizes the memory request signal for the SNVM 40, the request recognition unit 100 outputs the SNVM request signal to the arithmetic algorithm processor 103, the first mode register value setting unit 210 and the second mode register value setting unit 220.

  The first mode register 201 controls the first refresh operation cycle management from the basic refresh operation cycle management information (32 μs) set in the arithmetic algorithm processor 103 during the initialization sequence of the SDRAM 20A after the power is turned on as the first mode register signal S1. Management information to be changed to information (16 μs) is output.

  The arithmetic algorithm processor 103 instructs the command generator 104 to generate a mode register setting command in accordance with the first mode register signal S1. A register code indicating the first refresh operation cycle management information (16 μs) is issued by the address generator 105 or the data generator 106.

  The second mode register 202 uses the basic refresh operation cycle management information (32 μs) to the second refresh operation cycle management information (8 μs) set in the arithmetic algorithm processor 103 during the initialization sequence of the SDRAM 20B as the second mode register signal S2. The management information to be changed to is output. In the present embodiment, the cycle (8 μs) of the second refresh operation of the SDRAM 20B is set to a cycle shorter than the cycle (16 μs) of the first refresh operation of the SDRAM 20A.

  The arithmetic algorithm processor 103 instructs the command generation unit 104 to generate a mode register setting command according to the second mode register signal S2. A register code indicating the second refresh operation cycle management information (8 μs) is issued by the address generator 105 or the data generator 106.

  FIG. 4 is a circuit block diagram of the SDRAM 20A. The SDRAM 20A includes a command determination circuit 21, a mode register 22, a refresh control circuit 23, a memory cell 24, and a refresh management unit 25.

  The command determination circuit 21 includes a command decoder circuit 21A. The command decoder circuit 21A receives a clock signal CLK and various signals SIGNALS. The various signals SIGNALS are a chip select signal CS, a row address select signal RAS #, a column address select signal CAS #, and a write enable signal WE #.

  The command decoder circuit 21A recognizes the mode register setting command generated by the SDRAM controller 80. Thereafter, the command decoder circuit 21 </ b> A outputs a mode register setting signal to the mode register 22.

  The data signal DQ is input to the mode register 22. The data signal DQ includes a register code that is the first refresh operation cycle management information.

  The mode register 22 takes in the first refresh operation cycle management information in accordance with the mode register setting signal. Thereafter, the mode register 22 outputs a first refresh operation cycle information signal to the refresh manager 25.

  The refresh management unit 25 includes a timer 27. The timer 27 measures the refresh operation cycle of the memory cell 24. The refresh management unit 25 outputs a first refresh request signal to the refresh control circuit 23 every refresh operation cycle (here, 16 μs) in correspondence with the first refresh operation cycle management information.

  The refresh control circuit 23 includes a refresh address counter 26. The refresh address counter 26 generates a first refresh address in response to the first refresh request signal.

  The refresh control circuit 23 outputs a memory cell control signal to the memory cell 24 together with the first refresh address.

  In accordance with the first refresh address and the memory cell control signal, the memory cell 24 is refreshed (recharge injection for data retention).

  The SDRAM 20B also includes a command determination circuit 21, a mode register 22, a refresh control circuit 23, a memory cell 24, and a refresh management unit 25, as in the SDRAM 20A (see FIG. 4).

  In the SDRAM 20B, the data signal DQ (the second refresh operation cycle management information) is input to the mode register 22.

  In the SDRAM 20B, the mode register 22 takes in the second refresh operation cycle management information in accordance with the mode register setting signal. Thereafter, the mode register 22 outputs a second refresh operation cycle information signal to the refresh management unit 25.

  The refresh management unit 25 outputs a second refresh request signal to the refresh control circuit 23 every refresh operation cycle (here, 8 μs) in association with the second refresh operation cycle management information.

  The refresh address counter 26 generates a second refresh address in response to the second refresh request signal.

  The memory cell 24 is refreshed according to the second refresh address and the memory cell control signal.

  In the present embodiment, an example of the memory system of the present invention includes an SDRAM controller 80, SDRAMs 20A, 20B, and SNVM 40. The SDRAM controller 80 may be included in the semiconductor device 2 or may be included in a plurality of semiconductor devices sealed with different resins stacked as shown in FIG. 5 described later.

  In the present embodiment, the refresh operation cycle (16 μs) is an example of the first refresh operation cycle of the present invention. The refresh operation cycle (8 μs) is an example of the second refresh operation cycle of the present invention. The refresh operation cycle (32 μs) set during the initialization sequence of the SDRAM 20A after power-on is an example of the basic refresh operation cycle of the present invention.

  In the present embodiment, the first mode register value setting unit 210 is an example of a first operation cycle setting unit of the present invention. The second mode register value setting unit 220 is an example of a second operation cycle setting unit of the present invention. The first mode register value setting unit 210 and the second mode register value setting unit 220 are examples of the operation cycle setting unit of the present invention.

  In the present embodiment, the first mode register value setting unit 210 sets the refresh operation cycle (16 μs) for the SDRAM 20A to a cycle longer than the refresh operation cycle (8 μs) for the SDRAM 20B. It is an example of a setting step.

  In the present embodiment, the second mode register value setting unit 220 sets the refresh operation cycle (8 μs) for the SDRAM 20B to a cycle shorter than the refresh operation cycle (16 μs) for the SDRAM 20A. It is an example of a setting step.

<Effect of Embodiment 2>
In the semiconductor device 2 of this embodiment, the thermal conductivity of the SDRAM 20 </ b> B with respect to the mother substrate 10 is lower than the thermal conductivity of the SDRAM 20 </ b> A with respect to the mother substrate 10. Thereby, the heat dissipation effect of SDRAM20B is inferior to the heat dissipation effect of SDRAM20A. For this reason, in order to prevent the charge accumulated in the capacitor of the memory cell 24 of the SDRAM 20B from being lost, it is necessary to perform the refresh operation of the SDRAM 20B more frequently than the refresh operation of the SDRAM 20A.
In the semiconductor device 2 of the present embodiment, the first mode register value setting unit 210 and the second mode register value setting unit 220 allow the refresh operation cycle (16 μs) for the SDRAM 20A located in the lowermost layer to be more effective than the SDRAM 20A. The refresh operation cycle (8 μs) for the SDRAM 20B disposed at a position closer to the SNVM 40 located at the uppermost layer than the SDRAM 20A is set to a different cycle.
Therefore, according to the semiconductor device 2 and its refresh operation control method of the present embodiment, as described above, even when the refresh operation of the SDRAM 20B needs to be performed more frequently than the refresh operation of the SDRAM 20A, A refresh operation cycle for the SDRAM 20B can be set by the second mode register value setting unit 220 separately from the refresh operation cycle for the SDRAM 20A.
Thus, in the semiconductor device 2 and the refresh operation control method thereof according to the present embodiment, the refresh operation cycle (8 μs) for the SDRAM 20B is a cycle sufficient to prevent the charge accumulated in the capacitor of the memory cell 24 of the SDRAM 20B from being lost. It becomes possible to set to.

In the semiconductor device 2 of the present embodiment, the SDRAM 20A, SDRAM 20B, and SNVM 40 are heat-sharing connected by an electrical connection body having high thermal conductivity, and operate in response to a command from a common SDRAM controller. Thus, when the SNVM 40 is accessed, the first refresh operation cycle management information (16 μs), the second refresh operation cycle, from the basic refresh operation cycle management information (32 μs) set during the initialization sequence according to the heat radiation effects of the SDRAM 20A and SDRAM 20B. Change to management information (8 μs).
Therefore, according to the SDRAM controller and the refresh operation control method of the present embodiment, the optimum refresh operation cycle that can prevent the charge accumulated in the capacitors of the memory cells 24 of the SDRAM 20A and SDRAM 20B from disappearing. Can be set.

In the semiconductor device 2 of this embodiment, the thermal conductivity of the SDRAM 20 </ b> B with respect to the mother substrate 10 is lower than the thermal conductivity of the SDRAM 20 </ b> A with respect to the mother substrate 10. Thereby, the heat dissipation effect of SDRAM20B is inferior to the heat dissipation effect of SDRAM20A. Therefore, the time required for the charge accumulated in the capacitor of the memory cell 24 of the SDRAM 20B to disappear due to the temperature rise of the SDRAM 20B is the time required for the charge accumulated in the capacitor of the memory cell 24 of the SDRAM 20A to disappear. It is shorter than that.
In the semiconductor device 2 of this embodiment, the second mode register value setting unit 220 sets the refresh operation cycle (8 μs) for the SDRAM 20B, which has a lower heat dissipation effect than the SDRAM 20A, to a cycle shorter than the refresh operation cycle (16 μs) for the SDRAM 20A. is doing.
Therefore, according to the semiconductor device 2 and the refresh operation control method thereof according to the present embodiment, the SDRAM 20B in addition to the SDRAM 20A is stored in the capacitor of the memory cell 24 of the SDRAM 20B in consideration of the temperature rise of the SDRAM 20B. It is possible to set an optimal refresh operation cycle that can prevent the charge from being lost.

  The present invention is not limited to the embodiment described above, and can be implemented by appropriately changing a part of the configuration without departing from the spirit of the invention. For example, the operation cycle setting unit of the present invention may be a setting unit that combines the functions of the first mode register value setting unit 210 and the second mode register value setting unit 220. If the basic refresh operation cycle management information (32 μs) of the memory 20A has a margin, the second refresh operation cycle management information (16 μs) is changed by changing only the second mode register 202 in response to the memory request signal to the SNVM 40. Management information to be changed may be output. This is because the heat dissipation effect of the SDRAM 20A is superior to the heat dissipation effect of the SDRAM 20B. Further, unlike the above-described embodiment, the refresh operation of the SDRAM memory cell may be executed by a refresh command issued every predetermined period (for example, 8 μs or 16 μs).

Unlike the embodiment described above, the adhesive layers 50 and 51 may be formed of an adhesive having good thermal conductivity instead of the thermosetting epoxy resin.
Unlike the above-described embodiment, instead of the bonding wires, TAB or other connection means may be used to form electrical connections between the chips or to the mother board.

Unlike the semiconductor device (MCP) of the first embodiment described above, the present invention can be applied to another semiconductor device (POP) of the first embodiment of FIG. In FIG. 5, the adhesive layers 50 and 51 are not shown. With reference to the mother substrate 10, the chip 1, the chip 2, and the chip 3 are configured in a stacked relationship. The wire bonding of each of the chip 2 and the chip 3 is commonly connected to the ball 110 of the mother substrate 30 and is connected to the chip 1 on the mother substrate 20 via the mother substrate 20. The ball 210 is a signal line that connects the chip 1 on the mother board 20 and a device such as a CPU (not shown) on the mother board. As in the first embodiment, the heat generated by the operation of the chip 3 is directly shared with the chip 2 through a metal material with high thermal conductivity (wire bonding, metallized metal wiring on the mother substrate 30). . As in the first embodiment, the chip 2 that requires a refresh operation for data retention improves the heat dissipation efficiency of the chip 2 itself, thereby preventing the refresh characteristics from deteriorating. The heat of the mother board 30 is dissipated to the mother board 10 through all the balls 110 provided on the mother board 30, the mother board 20, and all the balls 210 provided on the mother board 20.
Further, the heat generated with the chip 3 is directly shared with the chip 1 through a metal material having high thermal conductivity (wire bonding, ball 110, metallized metal wiring on the mother substrate 20). As described above, the chip 1 improves the heat dissipation efficiency of the chip 1 itself, so that the heat generated with the chip 3 is dissipated to the mother substrate 10 through the mother substrate 20 and all the balls 210 provided on the mother substrate 20. Let
Note that the mother substrate 20 and the chip 1 stacked thereon, and the mother substrate 30 and the chip 2 and chip 3 stacked thereon may be reversely stacked based on the mother substrate 10.
Further, as in the first embodiment, a NAND memory may be arranged in an intermediate layer between the chip 2 and the chip 3 and a NAND memory controller may be arranged in an upper layer of the chip 1. These effects are the same as those of the first embodiment.

  In the present embodiment, the chip 2 (SDRAM) is an example of the first memory of the present invention. Chip 3 (synchronous flash memory) is an example of the second memory of the present invention. Chip 1 (SDRAM controller) is an example of the first functional chip of the present invention. The mother substrates 10, 20, and 30 are examples of the mother substrate of the present invention and are examples of the insulator of the present invention.

  In the present embodiment, the ball connection electrode 110 is an example of an electrode terminal in which the first memory and the second memory of the present invention are commonly connected. The ball connection electrode 120 is an example of another electrode terminal of the present invention.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. FIG. 10 is a circuit block diagram of an SDRAM controller connected to the semiconductor device of the second embodiment. FIG. 6 is a circuit block diagram of an SDRAM provided in a semiconductor device of Embodiment 2. FIG. 6 is a schematic configuration diagram of another semiconductor device according to the first embodiment.

1, 2 Semiconductor device 10 Mother substrate 11, 12 Bonding wire connection electrode 20 SDRAM
24 memory cell 30 NAND memory 40 synchronous flash memory 80 SDRAM controller 210 first mode register value setting unit 220 second mode register value setting unit

Claims (6)

In a stacked memory device in which a plurality of memories including a first memory that requires a refresh operation of a memory cell at a predetermined cycle and a second memory that is nonvolatile are stacked on a mother substrate,
Comprising an insulator disposed between the said first memory a second memory,
The first memory and the second memory are commonly connected by an electrical connection body having a thermal conductivity higher than the thermal conductivity of the insulator,
The first memory is disposed on the mother board in the lowest layer of the plurality of stacked memories, and the second memory is disposed in the upper layer ,
In an intermediate layer between the first memory in the lowermost layer and the second memory in the upper layer, the third memory of the plurality of stacked memories in which the first memory and the second memory are not commonly connected. A stacked memory device, wherein a memory is arranged .   The stacked memory device of claim 1, wherein an operating frequency of the second memory is higher than or equal to an operating frequency of the first memory. The operating frequency of the second memory is stacked memory device according to claim 1, wherein the higher than the operating frequency of the third memory. 2. The stacked memory according to claim 1 , wherein the third memory is connected to the electrode terminal of the mother board by an electrical connection body having a thermal conductivity higher than that of the insulator. apparatus. The stacked memory device includes a memory controller that controls the first memory and the second memory,
An insulator disposed between the memory and the memory controller;
According to any one of claims 1 to 4, characterized in that said memory and said memory controller by a higher thermal conductivity than the thermal conductivity is electrical connection body of the insulator are connected in common Multilayer memory device. The first memory and the second memory are mounted on a first mother board,
The memory controller is mounted on a second mother board,
An insulator disposed between the memory and the memory controller;
The memory and the memory controller are commonly connected between the first mother board and the second mother board by an electrical connection body having a thermal conductivity higher than that of the insulator. The stacked memory device according to claim 5 .

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