JP4555446B2 - Electronic equipment - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an electronic device, and more particularly to an electronic device in which processing corresponding to a key operation is performed by a plurality of processors.
[0002]
[Prior art]
An example of a conventional electronic device of this type is Japanese Patent Publication No. 1-20464 [G06F15 / 16, 3/02] published on April 17, 1989. In this conventional technology, a keyboard is connected to the master processor, keyboard data is supplied to the slave processor via the master processor, and keyboard data can be supplied to both the master processor and the slave processor by a single keyboard unit. is there.
[0003]
[Problems to be solved by the invention]
However, with such a conventional technique, the system can be simplified, but the input cannot be diversified. In other words, none of the processors could enter keys other than the keyboard.
[0004]
Therefore, a main object of the present invention is to provide an electronic device that allows various inputs.
[0005]
[Means for Solving the Problems]
  A first invention is a first processor for executing a first process.The second2nd processor which performs 2 processingA plurality of first keys connected to the first processor,And connected to the second processorMultiple secondKey, the first process isRequest processing for requesting the second processor to set at least one of the plurality of second keys as a specific keyThe second process includesKey operation determination processing to determine whether or not a specific key is operated,andFirst specific signal generation processing for generating a specific signal to be given to the first processor when a specific key is operatedIncludingOnly,The first processor executes a first process in response to an operation of the first key, and executes a specific function process in the first process when a specific signal is input during the execution of the first process.It is an electronic device.
[0007]
[Action]
  According to the first invention,Multiple first keys are connectedThe first processor executes the first process,Multiple secondThe second processor to which the key is connected executes the second process.The request process included in the first process requests the second processor to set at least one of the plurality of second keys as the specific key. The key operation determination process included in the second process isDetermine whether a specific key has been operated,The first specific signal generation processA specific key is operatedShould be given to the first processorGenerate a specific signal. The first processor isThe first process is executed according to the operation of the first key, and during the execution of the first processSpecific signalIs input, in the first processSpecific functionprocessingRun.
[0008]
In one aspect of the present invention, a specific function is assigned to a specific bit of a register. The specific signal is a signal for setting a predetermined value in a specific bit of the register, and the first processor executes a specific function when the specific bit of the register indicates a predetermined value. Preferably, the first processor notifies the second processor of key information indicating a specific key and bit information indicating a specific bit. At this time, the second processor determines whether or not the specific key is operated based on the key information, and sets a predetermined value in the specific bit of the register based on the bit information.
[0009]
  In another aspect of the present invention, the first process is a game process that is executed as necessary, and the second process is a telephone process that is always executed. At this time, the specific function is related to the game processing,SecondThe key is associated with phone processing when game processing is not being performed. Preferably, the specific function is a pause function that pauses a game that is being executed, and the second processor also generates a specific signal when detecting an incoming call.
[0016]
【The invention's effect】
  According to the first invention, connected to the second processorSecondWhen a key is operated, a specific function is performed in the first processorSpecific function processing to executeIs executed. In other words, the first processorSpecific function processing performed byWas connected to the second processorSecondIt is executed according to the operation of the key, and thereby diversification of key input can be realized.
[0018]
The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.
[0019]
【Example】
Referring to FIG. 1, a mobile communication terminal with game function 10 of this embodiment includes a main body 12 formed in an elongated rectangular parallelepiped shape. An antenna 14 projects from the upper surface of the main body 12, and a speaker 16, a color LCD 18, a game activation key 20, a game key 22, a telephone key 24, and a microphone 26 are disposed on the front surface of the main body 12.
[0020]
The game key 22 includes a cross key 22a for instructing the main character developing the game to move in a predetermined direction (for example, forward, backward, direction change, jump, etc.), and a predetermined behavior (for example, acquisition of an item or target) A button 22b and B button 22c for instructing the Further, as the telephone key 24, there are a hook key 24a, a hold key 24b, a numeric key 24c indicating "0" to "9", a * key 24d, and a # key 24e.
[0021]
In the incoming call waiting state, an incoming call waiting screen as shown in FIG. According to FIG. 2, today's date and current time and the game character related to the production of the applicant are displayed at the center of the screen, and a character indicating the reception state and the remaining battery level is displayed at the top of the screen. When the operator performs a dial operation using the hook key 24a and the numeric key 24c while waiting for an incoming call, the dialed telephone number is displayed on the LCD 18 and a calling process for the other party is performed. When the other party performs an incoming operation for this call, a protocol is established and a call can be made. On the other hand, when there is an incoming call from the other party, the incoming message and the telephone number of the caller are displayed on the LCD 18 and a ring tone is output from the speaker 48 (see FIG. 7) provided on the back of the main body 12. Here, when the operator operates the hook key 24a, the output of the ringing tone is stopped and the protocol is established with the caller to be in a call ready state.
[0022]
When the operator operates the game activation key 20 while waiting for an incoming call, the telephone mode is switched to the game mode. First, a menu screen as shown in FIG. 3 is displayed. When the operator selects a desired game (for example, Super Mario DX) from this menu screen, the selected game is started. The display on the LCD 18 is updated to a game screen as shown in FIG. 4, and BGM is output from the speaker 48 on the back. The game proceeds in response to the operation of the game key 22 described above, and sound effects are output from the speaker 48 as necessary.
[0023]
In this embodiment, in the game mode, the * key 24d functions as a start key and the # key 24e functions as a select key (another telephone key may function as a start key or a select key). For this reason, the game in progress is interrupted / resumed according to the operation of the * key 24d. In other words, if the * key 24d is pressed while the game is in progress, the state shifts to a pause state, the game screen stops moving, and the BGM output is interrupted. * When the key 24d is pressed again, the pause state is released, the game screen starts moving, and the output of BGM is resumed.
Further, on the above-described menu screen or a screen for prompting the player to select, the cursor on the screen is moved by operating the # key 24e.
[0024]
While the game is in progress, incoming call detection is always performed. When there is an incoming call, the movement of the game screen stops and the output of BGM is stopped. That is, the game is paused in response to the incoming call. Further, a ringtone is output from the speaker 48 instead of BGM, and the display on the LCD 18 is updated to an incoming call screen as shown in FIG.
According to FIG. 5, the tone (tone) of the game screen is changed, and an incoming message “Incoming” and the telephone number of the caller are displayed on the game screen. Also at this time, the output of the ringtone is stopped by the operation of the hook key 24a, the protocol is established, and a call is ready. When the call ends, the tone is restored and the game screen shown in FIG. 4 is displayed again.
[0025]
However, the pause state continues even after the call ends, and the pause state is canceled in response to the operation of the * key 24d. That is, when a call is received, the game is paused without operating the * key 24d, but the paused state is canceled by operating the * key 24d. * By releasing the pause state by operating the key 24d, the game screen starts to move and the output of BGM is resumed as described above.
[0026]
When it becomes necessary to register the player's name in the middle or at the start of the game, a player name input screen as shown in FIGS. 6A and 6B is displayed on the LCD 18. At this time, the player name is displayed in the name input frame on the screen by operating the numeric key 24c. That is, each of the numeric keys 24c is assigned 50 hiragana, whole “°”, and “ten” “ten”, and the operation of the numeric keys 24c performs a desired name input process.
[0027]
Specifically, the inside of the main body 12 is configured as shown in FIG. The game activation key 20 and the telephone key 24 are directly connected to a CPU (telephone CPU) 28 for telephone processing. The antenna 14 is connected to the telephone CPU 28 via the transmission / reception circuit 32, and the speaker 16 and the microphone 26 are connected to the telephone CPU 28 via the audio codec 30. The speaker 48 is connected to the telephone CPU 28 via the adder 46. The SRAM 34 and the flash memory 36 are connected to the telephone CPU 28 via an 8-bit bus 38. The flash memory 36 stores a telephone processing program (telephone program) and telephone directory data, and the SRAM 34 is used as a work RAM when processing the telephone program.
[0028]
On the other hand, the game key 22, the LCD 18, the SRAM 42, and the external terminal S are directly connected to a game processing CPU (game CPU) 40, and a speaker 48 is connected via an adder 46 and an amplifier 44. The SRAM 42 is used as an external work RAM when processing a game processing program (game program).
[0029]
In addition to the exchange of data via the 8-bit bus 38, an interrupt request and direct exchange of communication data are performed between the telephone CPU 28 and the game CPU 40. Communication data is also exchanged with an external device (not shown) connected through the external connection terminal S.
[0030]
The game CPU 40 is configured as shown in FIG. As the processor, there are a game CPU core 50, a sound processing unit (SPU) 64, an image processing unit (PPU) 78, and an LCD controller 84. The internal memory is provided in the system ROM 52, flash memory 54, work RAM 56, color palette RAM 68, registers 70 and 80, VRAMs 72 and 74, OAM (Object Attribute Memory) 76, frame memories 86 and 88, and key controller 82. There is a game key register 1 (see FIG. 9).
In addition to the processor and the internal memory, a UART 58 and a UART selector 60 are provided for exchanging the above communication data with the telephone CPU 28 or an external device, and an external SRAM I / F 62 is provided for accessing the SRAM 42 shown in FIG.
[0031]
The memory that the game CPU core 50 can access includes the system ROM 52, flash memory 54, work RAM 56, SRAM 42, color palette RAM 68, register 70, VRAM 72 and 74, OAM 76, game CPU control register 80d provided in the register 80, FIFO register 80e. And an interrupt register 80g (see FIG. 13) and a game key register 1 (see FIG. 9) provided in the key controller 82.
[0032]
The memory accessible by the PPU 78 is a color palette RAM 68, a register 70, VRAMs 72 and 74, and an OAM 76.
[0033]
The memories that can be accessed by the LCD controller 84 are frame memories 86 and 88, and a frame memory register 80a, an output control register 80b, and a palette control register 80c (see FIG. 13) provided in the register 80.
[0034]
Note that the SPU 64 can access a sound ROM (not shown), but a detailed description of the audio processing is omitted.
[0035]
The memory mapping seen from the game CPU core 50 is shown in FIG. 12, the system ROM 52 is assigned to “00000000h” to “0199999999h”, the SRAM 42 is assigned to “02000000h” to “0299999999h”, and the work RAM 56 is assigned to “03000000h” to “0399999999h”. Further, various registers (70, 80d, 80e, 80g, game key register 1) are assigned to “04000000h” to “0499999999h”, and a color palette RAM 68 is assigned to “05000000h” to “0599999999h”. Further, VRAMs 72 and 74 are assigned to “06000000h” to “06999999h”, OAM 76 is assigned to “07000000h” to “0799999999h”, and a game program (image) is assigned to “08000000h” to “0819999999h”.
[0036]
Also, the browser program and the monitor program stored in the flash memory 54 are assigned to “10000000h” to “Xh−1”, and the game program stored in the flash memory 54 is assigned to “Xh” to “Xh + 00199999h”. The backup stored in the flash memory 54 is assigned to Xh + 00200000h ”to“ 10400000h ”. The game CPU core 50 accesses each memory using such an address.
[0037]
Specifically describing each memory, the system ROM 52 stores a boot program for the game CPU core 50, a recovery program when the flash memory 54 is destroyed, and the like. The flash memory 54 stores the backup, game program, browser program, and monitor program as described above. The game program is downloaded from a server provided on the Internet and storing a large number of game programs. That is, if a desired game program is selected by connecting to the server using the telephone function, the selected game program is downloaded to the flash memory 54 via the telephone CPU 28. The work RAM 56 and the SRAM 42 temporarily store data obtained during the processing of the above-described program.
[0038]
The VRAM 72 stores background image data indicating a stationary character (stationary character), the VRAM 74 stores object image data indicating a character with motion (motion character), and an OAM (Object Attribute Memory) 76 Stores the motion character's attributes. For example, when the game screen shown in FIG. 4 is displayed, the background image data stored in the VRAM 72 includes still character data such as trees, mountains, and the ground. The object image data stored in the VRAM 74 includes motion character data such as a hero who jumps in the air, a mushroom that moves on the ground, and a block that floats in the air and finely moves from below.
[0039]
The color palette RAM 68 stores palette data for coloring still characters and moving characters, and the register 70 holds setting values for designating image modes and applying special effects to the screen.
[0040]
Referring to FIG. 13, frame memory register 80a holds address data and image data of frame memories 86 and 88. Specifically, the X address and Y address of the frame memory 86 and binary image data for one dot (= 1 bit) to be written at this address (X, Y), and the X address and Y address of the frame memory 88 and this Color image data for one dot (= 8 bits) to be written at the address (X, Y) is set. The setting for the frame memory register 80a is performed by the telephone CPU. In the telephone mode, the address data and image data of both the frame memories 86 and 88 are set by the telephone CPU 28, and only the address data and image data of the frame memory 86 are set by the telephone CPU 28 in the game mode.
[0041]
The output control register 80b is a register for controlling the output of image data from the LCD controller 84 to the LCD 18. In this register, composition start line data, composition end line data, image start line data, and LCD control data are set. The As shown in FIGS. 16 and 17, areas 1 and 2 are formed on the display screen, an image based on the image data drawn in the frame memory 86 is displayed in area 1, and the frame memory 86 and area 2 are displayed in area 2. A composite image based on the respective image data drawn in 88 is displayed. The synthesis start line designation data and the synthesis end line designation data indicate the start position and end position of area 2, respectively.
The image start line data is data that designates from which line in the frame memory 88 the reading of the color image data is to be started. By updating the image start line data every predetermined number of lines, it is possible to scroll the color image.
[0042]
Specifically, the LCD control data is represented by 8 bits as shown in FIG. The 0th bit (= LCNT0) is a mode selection flag, “0” indicates a telephone mode, and “1” indicates a game mode. The first bit (= LCNT1) is a flag for controlling the output / stop of the image based on the binary image data drawn in the frame memory 86. “0” indicates stop and “1” indicates output. The second bit (= LCNT2) is a flag for controlling whether or not to blend this color image when displaying an image based on the color image data drawn in the frame memory 88. “0” indicates normal. , “1” indicates blending. The fourth bit and the third bit (= LCNT4, 3) are flags for controlling the output and tone (gradation) of the image based on the color image data drawn in the frame memory 88, and “00” is the output stop, “01” indicates a tone-down, “10” indicates a unity tone, and “11” indicates a tone-up. The fifth bit (= LCNT5) is a flag for controlling display on / off of the LCD 18. “0” indicates display off, and “1” indicates display on.
The sixth and seventh bits are not used in this embodiment.
[0043]
The palette control register 80 c is a register for designating an image color based on the binary image data written in the frame memory 86. For area 1 that is not a composite area, palette data 0 for determining the background color and palette data 1 for determining the character color are set. In contrast, only the palette data 1 for determining the character color is set for the second area, which is the composite area, and the background is always a transparent color.
[0044]
The game CPU control register 80d has only a game CPU activation flag.
The game CPU activation flag is set to “1” in response to the operation of the game activation key 20, and is set to “0” in response to the operation of the hold key 24b. “1” indicates a game mode, and “0” indicates a telephone mode.
[0045]
The FIFO register 80e is a register for temporarily holding data exchanged between the game CPU 40 and the telephone CPU 28 in the game mode. Specifically, it consists of two FIFO registers 1 and 2, each having a capacity of 64 × 16 bits. Since the telephone CPU 28 of this embodiment is an 8-bit CPU, only 8 bits of the 16-bit setting data are used. However, if the FIFO registers 1 and 2 are set to 16 bits, a 16-bit telephone CPU can be handled.
[0046]
The FIFO register 1 is used for data transfer from the game CPU 40 to the telephone CPU 28, and the FIFO register 2 is used for data transfer from the telephone CPU 28 to the game CPU 40. For this reason, writing to the FIFO register 1 is performed only by the game CPU 40, and reading from the FIFO register 1 is performed only by the telephone CPU 28. Further, writing to the FIFO register 2 is performed only by the telephone CPU 28, and reading from the FIFO register 2 is performed only by the game CPU 40. The FIFO registers 1 and 2 are used in the assigning process of the start function and select function to the * key 24d and the # key 24e, and the player name input process.
[0047]
The game key register 80 f is a register that holds data related to game operations, and includes game key registers 2 and 3. The game key register 1 is provided in the key controller 80 as described above, and any of the game key registers 1 to 3 is formed of 8 bits as shown in FIG. The A button 22b is assigned to the 0th bit (= K0, KI0, KO0), the B button 22c is assigned to the 1st bit (= K1, KI1, KO1), and the 2nd to 5th bits (= K2). To K5, KI2 to KI5, and KO2 to KO5) are assigned the upward direction, the downward direction, the left direction, and the right direction of the cross key 22a. Also, a start key (* key 24d) is assigned to the sixth bit (= K6, KI6, KO6), and a select key (# key 24e) is assigned to the seventh bit.
[0048]
When the A button 22b is operated, the 0th bit is updated from “0” to “1”, and when the B button 22c is operated, the 1st bit is updated from “0” to “1”. The second bit is updated from “0” to “1” when the cross key 22a is operated upward, and the third bit is updated from “0” to “1” when the cross key 22a is operated downward. . The fourth bit is updated from “0” to “1” when the cross key 22a is operated leftward, and the fifth bit is updated from “0” to “1” when the cross key 22a is operated rightward. Is done. Further, when the * key 24d is operated, the sixth bit is updated from “0” to “1”, and when the # key 24e is pressed, the seventh bit is updated from “0” to “1”.
[0049]
The interrupt register 80g is a register that temporarily holds an interrupt request exchanged between the game CPU 40 and the telephone CPU 28. An interrupt request issued from the game CPU 40 to the telephone CPU 28 is set in the interrupt register 1, and an interrupt request issued from the telephone CPU 28 to the game CPU 40 is set in the interrupt register 2. Note that both the interrupt from the telephone CPU 28 to the game CPU 40 and the interrupt from the game CPU 40 to the telephone CPU 28 are used in the assignment process of the start function and the select function to the * key 24d and the # key 24e, and the player name input process. The
[0050]
The key controller 82 and its surroundings are configured as shown in FIG. In the game mode, as described above, the * key 24d functions as a start key, and the # key 24e functions as a select key. When the operator operates the * key 24d or the # key 24e, the predetermined bit of the telephone key register 28b is updated to “1”. The telephone CPU core 28a determines which key is operated from the set value of the telephone key register 28b. When the * key 24d is operated, the sixth bit of the game key register 3 is operated and the # key 24e is operated. If so, the seventh bit of the game key register 3 is updated to “1”.
[0051]
In the game key register 1, a logical sum of a numerical value corresponding to the operation of the game key 22 and a numerical value output from the game key register 3 is set. The game CPU core 50 inputs a set value of the game key register 1 and performs a game process according to the input set value. Therefore, not only the operation of the game key 22 but also the operation of the * key 24d and the # key 24e are reflected in the game process.
[0052]
The set value of the game key register 1 is also given to the game key register 2, and the set values of the game key registers 1 and 2 always match. Therefore, the set value of the game key register 2 changes according to the operation of the game key 22. The telephone CPU core 28a determines whether or not the A button 22b is operated from the set value of the game key register 2 when the player name is input, and performs processing according to the determination result.
[0053]
Returning to FIG. 8, the PPU 78 performs processing on the image data stored in the VRAMs 72 and 74 according to the palette data in the palette RAM 68 and the set value of the register 70, and 8-bit color image data subjected to such processing. Are output to the LCD controller 84 together with the address data. However, the background image data and the object image data are drawn in the VRAMs 72 and 74 only in the game mode, and the PPU 78 transfers the color image data and the address data to the LCD controller 84 only in the game mode.
[0054]
The LCD controller 84 is specifically configured as shown in FIG. LCNT0 of the LCD control data set in the output control register 80b is given to the selector 84b, LCNT1 is given to the read controller 84f, LCNT4 and 3 are given to the tone control circuit 84g, and LCNT2 and 5 are image synthesis circuit 84h. Given to. The synthesis start line data and the synthesis end line data set in the output control register 80b are given to the image synthesis circuit 84h, and the image start line data is given to the read controller 84c.
[0055]
Further, the area 1 pallet data 0, the area 1 pallet data 1 and the area 2 pallet data 1 set in the pallet control register 80c are given to the image composition circuit 84h, and the frame memory 86 set in the frame memory register 80a. The X address for frame, the Y address for frame memory 86, binary image data for one dot, the X address for frame memory 88, the Y address for frame memory 88, and the color image data for one dot are supplied to the frame memory transfer controller 84a.
[0056]
As described above, in the telephone mode, binary image data, its address data, color image data, and its address data are set in the frame memory register 80a. At this time, the frame memory transfer controller 84a gives the binary image data and its address data to the write controller 84e, and gives the color image data and its address data to the selector 84b. The selector 84b selects the output of the frame memory transfer controller 84a when LCNT0 is "0", that is, indicates the telephone mode. The color image data and address data output from the frame memory transfer controller 84a are provided to the write controller 84d via the selector 84b.
[0057]
On the other hand, in the game mode, only binary image data and its address data are set in the frame memory register 80a, and the frame memory transfer controller 84a gives the binary image data and address data to the write controller 84e. The color image data and the address data are given from the PPU 78 to the selector 84d. LCNT0 of the LCD control data indicates “1” in the game mode. At this time, the selector 84d selects the output from the PPU 78. Therefore, in the game mode, the output from the PPU 78 is given to the write controller 84d via the selector 84b.
[0058]
As will be described in detail later, for both binary image data and color image data, the address data indicates only the write start address. For this reason, both the write controllers 84e and 84d update the write address one dot at a time using the given address data as a reference, and sequentially add binary image data and color image data for one dot to the updated addresses. Write. As a result, binary image data and color image data corresponding to a predetermined number of dots are stored in the frame memories 86 and 88, respectively.
[0059]
Each of the frame memories 86 and 88 has a capacity capable of storing image data of 160 × 160 dots, but 1 bit is assigned to each dot of the frame memory 86, and 8 bits are assigned to each dot of the frame memory 88. Assigned. Therefore, binary image data for one dot is written to each address of the frame memory 86, and color image data for one dot is written to each address of the frame memory 88.
[0060]
When the LCD control data LCNT1 indicates “1”, the read controller 84f reads binary image data from the frame memory 86 and supplies the read binary image data to the image composition circuit 84h. On the other hand, when LCNT1 indicates “0”, reading of binary image data from the frame memory 86 is stopped. The read controller 84c specifies the read start line of the frame memory 88 based on the image start line data, and starts reading color image data from the specified read start line. The read color image data is given to the image composition circuit 84h through the tone control circuit 84g.
[0061]
The tone control circuit 84g performs the following tone control or output control in response to the numerical values indicated by the LCNTs 4 and 3. That is, if LCNT4 and 3 indicate “01”, the RGB level of the color image data is lowered (tone down), and the color image data with the tone down is supplied to the image composition circuit 84h. If the LCNTs 4 and 3 indicate “11”, the RGB level of the color image data is raised (tone up), and the color image data with the tone raised is supplied to the image composition circuit 84h. Further, if LCNT4 and 3 indicate “10”, the color image data is directly supplied to the image composition circuit 84h, and if LCNT4 and 3 indicate “00”, the output of the color image data to the image composition circuit 84h is stopped. .
[0062]
The image composition circuit 84h is configured as shown in FIG. The line counter 8402h counts the number of lines forming one frame and supplies the count value to the comparator 8403h. The comparator 8403h is also supplied with the synthesis start line data and synthesis end line data set in the output control register 80b. The comparator 8403h changes the output to a high level when the count value of the line counter 8402h matches the data value of the synthesis start line data, and when the count value of the line counter 8402h matches the data value +1 of the synthesis end line data Return the output from high level to low level. For this reason, the output of the comparator 8403h becomes a low level from the start position to the end position of the area 1 shown in FIG. 16, and becomes a high level from the start position to the end position of the area 2 shown in FIG.
[0063]
The selector 8401h selects the palette data 0 for area 1 set in the palette control register 80c when the output of the comparator 8403h is low level, and is output from the tone control circuit 84g when the output of the comparator 8403h is high level. Select color image data. The output of the selector 8401h is given to the selector 8407h.
[0064]
The blending circuit 8404h performs blending processing on the palette data 1 for area 2 set in the palette control register 80c and the color image data output from the tone control circuit 84g. The selector 8405h selects the area 2 palette data 1 when LCNT2 of the LCD control data indicates “0”, and selects the output of the blending circuit 8404h when LCNT2 indicates “1”. The output of the selector 8405h is given to the selector 8406h. The output of the comparator 8403h is also supplied to the selector 8406h. The selector 8406h selects the area 1 palette data 1 set in the palette control register 80c when the output of the comparator 8403h is at a low level, and selects the output of the selector 8405h when the output of the comparator 8403h is at a high level.
[0065]
The selector 8407h receives the binary image data read by the read controller 84h, and selects either one of the selectors 8401h and 8406h according to the data value (bit value) of each dot forming the binary image data. To do. Specifically, when the bit value indicates “0”, the output of the selector 8401h is selected, and when the bit value indicates “1”, the output of the selector 8406h is selected.
[0066]
The switch 8408h is turned off when LCNT5 of the LCD control data indicates “0”, and turned on when LCNT5 indicates “1”. Therefore, the output of the selector 8407h is output to the LCD 18 via the switch 8408h only when the LCNT5 indicates “1”.
[0067]
In area 1, selector 8401h selects area 1 pallet data 0, and selector 8406h selects area 1 pallet data 1. The selector 8407h selects the area 1 palette data 0 when each bit value of the binary image data is “0”, and selects the area 1 palette data 1 when each bit value indicates “1”. As a result, a character indicating the reception state and the remaining battery level is displayed in area 1 as shown in FIG.
[0068]
In area 2, the selector 8401h selects color image data, and the selector 8406h selects the output of the selector 8405h. When blending processing is not performed, palette data 1 for area 2 is given from selector 8405h to selector 8406h. The selector 8407h selects color image data when each bit value of the binary image data is “0”, and selects the area 2 palette data 1 when each bit value indicates “1”. As a result, for example, a character and a color image indicating the date and the current time are displayed in the area 2 as shown in FIG.
[0069]
The incoming call waiting screen shown in FIG. 2 includes binary image data indicating the reception state, remaining battery level, date and current time as shown in FIG. 18, and color image data indicating a game character as shown in FIG. . The telephone CPU 28 shown in FIG. 7 first sets address data corresponding to the head of area 1 in the frame memory register 80a and frames binary image data (displayed in area 1) indicating the reception state and the remaining battery level one dot at a time. Set in memory register 80a. Subsequently, the telephone CPU 28 sets address data corresponding to the head of area 2 in the frame memory register 80a, and sets binary image data (displayed in area 2) indicating the date and current time in the frame memory register 80a one dot at a time. To do. The LCD controller 84 repeatedly reads binary image data updated for each dot from the frame memory register 80a, and writes the read binary image data of each dot to the frame memory 86 based on the address data. As a result, the binary image data shown in FIG. 18 is obtained in the frame memory 86.
[0070]
Following the setting of the binary image data, the telephone CPU 28 sets the address data corresponding to the head of area 2 and the color image data of each dot indicating the game character in the frame memory register 80a. The LCD controller 84 repeatedly reads color image data updated for each dot from the frame memory register 80a, and writes the read color image data to the frame memory 88 based on the address data. As a result, the color image data shown in FIG. 19 is obtained in the frame memory 88.
[0071]
LCD controller 84 reads binary image data and color image data from frame memories 86 and 88, controls tone of color image data, coloration based on binary image data, synthesis of binary image data and color image data, and The composite image data is output according to the set values of the output control register 80b and the palette control register 80c. As a result, the standby screen shown in FIG.
[0072]
When the operator performs a dial operation, the telephone CPU 28 sets address data corresponding to the head of area 2 and binary image data indicating the other party's telephone number in the frame memory register 80a. The LCD controller 84 writes the binary image data in the frame memory 86 in the same manner as described above. For this reason, the binary image data indicating the date and the current time is updated with the binary image data indicating the telephone number of the other party. As a result, the date and current time displayed on the LCD 18 are also switched to the telephone number of the other party.
[0073]
The telephone CPU 28 also establishes a connection with the other party through the transmission / reception circuit 32 and the antenna 14. When the connection is established, the other party's voice data is received, and the received voice data is output from the speaker 16 via the voice codec 30.
The operator's voice data captured by the microphone 26 is output from the antenna 12 via the voice codec 30 and the transmission / reception circuit 32.
[0074]
On the other hand, when there is an incoming call through the antenna 14 and the transmission / reception circuit 32, the telephone CPU 28 sets address data corresponding to the head of area 2 and binary image data indicating the incoming message and the telephone number of the caller in the frame memory register 80a. To do. The LCD controller 84 writes the binary image data into the frame memory 86, and the binary image data indicating the date and the current time is updated by the binary image data indicating the incoming message and the telephone number of the caller. As a result, the date and current time displayed on the LCD 18 are also updated to the incoming message and the telephone number of the caller. The telephone CPU 28 also provides the ring tone data to the speaker 48 via the adder 46. A ring tone is output from the speaker 48.
[0075]
Here, when the operator performs an incoming call operation, the telephone CPU 28 stops outputting the ringtone data and establishes a connection with the caller. After the connection is established, the voice data of the other party is output from the speaker 16 via the voice codec 30 and the operator's voice data captured by the microphone 26 is transmitted via the voice codec 30 and the transmission / reception circuit 32 as described above. 12 is output.
[0076]
When the operator operates the game activation key 20 while waiting for an incoming call, the telephone CPU 28 sets a game activation flag. The telephone CPU 28 also sets the address data corresponding to the head of area 2 and the binary image data in which all the dots are “0” in the frame memory register 80a, and sets “1” in LCNT0 of the LCD control data. The LCD controller 84 writes binary image data in which all dots are “0” to the frame memory 86 based on the address data, and selects the PPU 78 as the input destination of the color image data.
[0077]
On the other hand, the game CPU core 50 draws background image data and object image data forming a game screen (color image) in the VRAMs 72 and 74, and sets the palette data of the stationary character and the moving character in the color palette RAM 68. Further, the attribute of the motion character is set in the OAM 76, and the setting values related to the background and the output of the object are set in the register 70. As a result, for example, the color image data shown in FIG. 21 is created by the PPU 78 and output to the LCD controller 84. The LCD controller 84 writes the color image data output from the PPU 78 in the frame memory 88. In each of the frame memories 86 and 88, binary image data shown in FIG. 20 and color image data shown in FIG. 21 are obtained.
[0078]
The LCD controller 84 reads binary image data and color image data from the frame memories 86 and 88 in the same manner as described above, performs tone control on the color image data according to the values of LCNT4 and LCNT of the LCD control data, and outputs a binary image. The palette data and the color image data are synthesized based on the data, the synthesis start line data, and the synthesis end line data. As a result, the game screen shown in FIG. 4 is displayed on the LCD 18.
[0079]
The game CPU core 50 also provides the telephone CPU 28 with a key code indicating the * key 24d and #key 24e and function information assigned to the * key 24d and #key 24e through the FIFO register 1 shown in FIG. Here, the function information assigned to the * key 24d indicates “start”, and the function information assigned to the # key 24e indicates “select”. Therefore, the telephone CPU 28 sets “1” to the start key bit KO6 of the game key register 3 when the * key 24d is operated, and sets the select key bit KO7 of the game key register 3 when the # key 24e is operated. Set “1”. Since each bit of the game key register 1 is set with a logical sum of a numerical value corresponding to the operation of the game key 22 and a numerical value output from the game key register 3, the game CPU core 50 sets the set value of the game key register 1. The game process corresponding to is performed.
[0080]
After the game is started, in response to the operation of the game key 22, the background image data, the object image data, and the object attributes are updated, and the setting values of the color palette register 68 and the register 70 are updated. As a result, the color image data output from the image processing unit 78 also changes, causing a movement on the game screen. On the other hand, sound effect data is output from the SPU 64 as necessary, and sound effects are generated from the speaker 48.
[0081]
When the * key 24d is operated while the game is in progress, the game CPU 50 causes the SPU 64 and the PPU 78 to stop outputting BGM data and color image data in order to shift to the pause state. As a result, the output of the BGM and the movement of the game screen are stopped. When the key 24d is operated again, the game CPU 50 activates the SPU 64 and the PPU 78 to cancel the pause state, and resumes the output of BGM data and color image data. BGM is output again from the speaker 48, and the game screen on the LCD 18 also starts to move again.
[0082]
When the menu screen is displayed while the game is in progress, the game CPU core 50 changes the set value of the register 70 in response to the operation of the # key 24e. The setting value to be changed is a setting value related to the cursor displayed on the menu screen, and the display position of the cursor is changed by this change.
[0083]
When there is an incoming call while the game is in progress, the telephone CPU 28 sets the start key bit KO6 of the game key register 3 to "1" and sets "11" to the LCD control data LCNT4, 3 in addition to the above processing. . The telephone CPU 28 also sets the binary image data indicating the incoming message and the telephone number of the caller and the address data corresponding to the head of the area 2 in the frame memory register 80a, and the ring tone data is added via the adder 46 to the speaker. 48. On the other hand, the game CPU core 50 causes the SPU 64 to stop outputting BGM data and stop its own processing in order to pause the game.
[0084]
The LCD controller 84 stores the binary image data set in the frame memory register 80a in the frame memory 86. The LCD controller 84 also reads binary image data and color image data from the frame memories 86 and 88, performs tone-up on the color image data, and palettes based on the binary image data, composition start line data, and composition end line data. Combining data and color image data. As a result, the incoming call guidance screen shown in FIG. 5 is displayed on the LCD 18, and the output of the speaker 48 is switched from BGM to the ring tone.
[0085]
When the operator performs an incoming call operation, the telephone CPU 28 stops the output of the ring tone data and establishes a connection with the caller as described above. After the connection is established, the voice data of the other party is output from the speaker 16 via the voice codec 30, and the voice data of the operator captured by the microphone 26 is output from the antenna 14 via the voice codec 30 and the transmission / reception circuit 32. .
[0086]
When the call is finished, the telephone CPU 28 resets the LCD control data LCNT4, 3 to "10" and also outputs the address data corresponding to the head of the area 2 and the binary image data in which all dots are "0" to the frame memory register 80a. Set to. As a result, the display on the LCD 18 returns to the game screen shown in FIG. However, the movement of the game screen remains stopped, and the output of BGM is also stopped. That is, the game maintains a paused state. This pause state is canceled in response to the operation of the * key 24d by the operator.
[0087]
Specifically, the telephone CPU core 28a processes the flowcharts shown in FIGS. 22 to 31 and FIG. First, in step S1, the LCD control data set in the LCD controller control register 80c is set to an initial value “110010”. That is, the LCD display on / off flag shown in FIG. 14 is set to “1”, the color image tone control flag is set to “10”, the binary image tone control flag is set to “0”, and the binary image is output. The control flag is set to “1”, and the mode selection flag is set to “0”.
[0088]
In the subsequent step S3, the subroutine shown in FIGS. 25 and 26 is processed to display the incoming call waiting screen shown in FIG. First, LCNT5 of the LCD control data is updated to “0” in step S81 shown in FIG. Thereby, the display of the LCD 18 is turned off. Next, in step S83, the count value N is set to "1", and in each of steps S85, S87, and S89, the frame memory register 80a stores the X address for the frame memory 86, the Y address for the frame memory 86, and one dot worth. Binary image data is set. Specifically, the head address of area N (corresponding to area N of the display screen) formed in the frame memory 86 and binary image data for one dot to be written to this head address are set in the frame memory register 80a. In a succeeding step S91, it is determined whether or not the writing of the binary image data to the area N is completed. If NO, the process of step S89 is repeated. If YES, the process proceeds to step S93.
[0089]
The LCD controller 84 first reads the head address data and binary image data set in the frame memory register 80a, and writes the binary image data to the address on the frame memory 86 indicated by the head address data. When the writing of binary image data for one dot is completed, the LCD controller 84 updates the address of the writing destination itself. Therefore, it is not necessary to update the write address on the telephone CPU 28 side, and the binary image data is written to a desired address in the frame memory 86 only by repeating the binary image data setting process in step S89.
[0090]
In step S93, it is determined whether the count value N has reached “2”. If NO, the count value N is incremented in step S95 and the process returns to step S85. If YES, the process proceeds to step S97. As a result, the binary image data indicating the reception state and the remaining battery capacity character is drawn in the area 1 of the frame memory 86, and the binary image data indicating the date and time and the current time are drawn in the area 2 of the frame memory 86. In this embodiment, the processing is such that the image data of the entire screen is rewritten, but the image data may be rewritten only in an area that needs to be changed (the same applies to steps S97 to S103 related to area 2 described later). .
[0091]
In subsequent steps S97 to S101, the X address for the frame memory 88, the Y address for the frame memory 88, and the color image data for one dot are set in the frame memory register 80a. The X address and Y address set in steps S97 and S99 indicate the head address in the frame memory 88, and the color image data for one dot set in step S101 is image data to be written to this head address. In step S103, it is determined whether or not the writing of the color image data to the area 2 is completed. If the writing is not completed, the process returns to step S101. If the writing is completed, the process proceeds to step S105. As a result, the color image data of the game character shown in FIG.
[0092]
In each of steps S105 to S109, area 1 pallet data 0, area 1 pallet data 1 and area 2 pallet data 1 are set in the pallet control register 80c. As a result, the background color and character color (character color) of the binary image displayed in area 1 of the LCD 18 and the character color of the binary image displayed in area 2 are determined. Note that the background color of the binary image in area 2 is transparent as described above.
[0093]
In each of steps S111 to S115, the composition start line data, composition end line data, and image start line data are set in the output control register 80c. The composition start line data indicates from which line of the binary image the composition of the color image starts, the composition end line data indicates which line of the binary image the composition of the color image ends, and the image start line data Indicates from which line of the frame memory 88 the reading is to be started.
[0094]
When the process of step S115 is completed, the process proceeds to step S117, and LCNT5 of the LCD control data is set to “1” in order to turn on the display of the LCD 18. As a result, the incoming call waiting screen shown in FIG.
[0095]
Returning to FIG. 22, in each of steps S5, S13, S21 and S35, it is determined whether or not the game activation key 20 is operated, whether or not the hold key 24b is operated, whether or not the dial operation is performed, and whether or not there is an incoming call. If it is determined in step S5 that the game activation key 20 is operated, the game CPU activation flag shown in FIG. 13 is set in step S7, and “1” is set in LCNT0 of the LCD control data in step S9. Thereby, the game mode is started. When the process of step S9 is completed, the subroutine shown in FIG. 27 is processed in step S11.
[0096]
First, in step S121, LCNT5 of the LCD control data is updated to “0”, and the display on the LCD 18 is turned off. Next, in each of steps S122 and S123, the X address for frame memory 86 and the Y address for frame memory 86 are set in frame memory register 80a. The address set here indicates the head address of the formed area 2. In step S124, binary image data for one dot is set in the same frame memory register 80a, and in the subsequent step S125, it is determined whether or not the writing of binary image data to area 2 has been completed. If NO, the processing in step S124 is repeated. If YES, the area 2 palette data 1 is set in the palette control register 80c in step S126, and the LCD control data LCNT5 is returned to "1" in step S127. The display of the LCD 18 is turned on. By this subroutine processing in step S <b> 11, binary image data in which all dots are “0” is drawn in area 2 of the frame memory 86. As a result, the date and the current time displayed on the incoming call waiting screen are deleted.
[0097]
If it is determined in step S13 that the hold key 24b is operated, the game CPU activation flag is reset in step S15, and “0” is set to LCNT0 of the LCD control data in step S17. Thereby, the telephone mode is started. When the process of step S17 is completed, the subroutine shown in FIGS. 28 and 29 is processed in step S19 to display an incoming call waiting screen on the LCD 18.
[0098]
First, in step S131 shown in FIG. 28, LCNT5 of the LCD control data is updated to “0”, and the display of the LCD 18 is turned off. Next, in each of steps S133, S135, and S137, the X address for the frame memory 86, the Y address for the frame memory 86, and binary image data for one dot are set in the frame memory register 80a. The address data set in steps S133 and S135 indicates the head address of area 2 formed in the frame memory 86, and the binary image data set in step S137 is data to be written to this head address. In step S139, it is determined whether or not the writing of binary image data to area 2 has been completed, and the process of step S137 is repeated until a determination result of YES is obtained. As a result, the date and current time binary image data forming the incoming call waiting screen are written in the area 2 of the frame memory 86.
[0099]
In subsequent steps S141 to S147, the X address for the frame memory 88, the Y address for the frame memory 88, and the color image data for one dot are set in the frame memory register 80a. The X address and Y address set in steps S141 and S143 indicate the head address of area 2 formed in the frame memory 88, and the color image data for one dot set in step S145 is the image data to be written to this head address. It is. In step S147, it is determined whether or not the writing of color image data to area 2 is completed. If the writing is not completed, the process returns to step S145. If the writing is completed, the process proceeds to step S149. As a result, the color image data of the game character forming the incoming call waiting screen is drawn in the frame memory 88.
[0100]
Subsequently, in step S149, the palette data 1 for area 2 is set in the palette control register 80c, and in each of steps S151 to S155, the synthesis start line data, the synthesis end line data, and the image start line data are set in the output control register 80b. Thereafter, in step S157, the LCD control data LCNT5 is returned to "1". As a result, the incoming call waiting screen shown in FIG.
[0101]
If it is determined in step S21 that there is a dial operation, the subroutine shown in FIG. 27 is first processed in step S23. However, the binary image data drawn in the frame memory 86 at this time is image data indicating the other party's telephone number. Therefore, the telephone number of the other party is displayed on the LCD 18 instead of the date and the current time. When the process in step S23 is completed, a call process is performed in step S25, and whether or not the hold key 24b is operated is determined in step S27. Then, unless the hold key 24b is operated, the process of step S25 is repeated. When the hold key 24b is operated, the subroutine shown in FIG. 27 is processed again in step S29. At this time, binary image data indicating the date and the current time is drawn in the frame memory 86. As a result, the display on the LCD 18 is updated to the date and the current time from the telephone number of the other party.
[0102]
If it is determined in step S35 that there is an incoming call, the state of the game CPU activation flag is determined in step S37. Here, if the game CPU activation flag is in the reset state, the process directly proceeds to step S43. On the other hand, if the game CPU activation flag is in the set state, the start key bit KO6 of the game key register 3 shown in FIG. 15 is set to “1” in step S39, and the LCD control data LCNT4 shown in FIG. And 3 are set to “11”, and then the process proceeds to step S43. By the process of step S39, the start key bit KO6 is set regardless of the operation of the * key 24d (functioning as a start key), and the game shifts to the pause state. Further, the tone of the game screen is increased by the process of step S41.
[0103]
In step S43, the subroutine shown in FIG. 27 is processed. At this time, in the frame memory 86, an incoming message “incoming” and binary image data indicating the telephone number of the caller are drawn. Subsequently, a ringing tone is generated from the speaker 48 at step S45, and whether or not the hook key 24a is operated is determined at step S47. If the hook key 24a is operated, the output of the ringtone is stopped in step S49, and the call process is performed in step S51. In step S53, it is determined whether or not the hold key 24b is operated, and the call process in step S51 is repeated unless the hold key 24b is operated.
[0104]
When the hold key 24b is operated, the process proceeds from step S53 to step S55, and the state of the game CPU activation flag is determined. If the game activation flag is in the reset state, the process proceeds to step S59. If the game activation flag is in the set state, the LCD control data LCNT4 and 3 are set to “10” in step S57, that is, the game. After restoring the tone of the screen, the process proceeds to step S59. In step S59, the subroutine shown in FIG. 27 is processed, whereby binary image data in which all dots are “0” is written into the frame memory 86. The incoming message displayed on the LCD 18 and the telephone number of the caller are deleted by the process of step S59. When the process of step S59 is completed, the process proceeds to step S31.
[0105]
If NO is determined in any of steps S5, S13, S21 and S35, first, the remaining battery level and the reception state are detected in steps S61 and S63, and today's date and current time are detected in step S65. Subsequently, the subroutine shown in FIG. 30 is processed in step S67, and when the process of step S67 is completed, the process proceeds to step S31.
[0106]
Referring to FIG. 30, first, count value N is set to "1" in step S161, and then in steps S163 and S165, the X address for frame memory 86 and the Y address for frame memory 86 are stored in frame memory register 80a. set. In step S167, binary image data for one dot is set in the same frame memory register 80a. The address data set in steps S163 and S165 is the head address of the area N formed in the frame memory 86, and the binary image data set in step S167 is data to be written to this head address. In step S169, it is determined whether or not the binary image data has been written to the area N. If NO, the process in step S167 is repeated. If YES is determined in the step S169, it is determined whether or not the count value N is “2” in a step S171. If NO, the count value N is incremented in a step S173, and then the process returns to the step S163.
[0107]
As a result, the processing of steps S163 to S171 is repeated twice, and binary image data is written in each of areas 1 and 2 formed in the frame memory 86. In area 1, binary image data indicating the character of the reception state and the remaining battery level is stored, and in area 2, binary image data indicating the character of today's date and the current time is stored. Each character reflects the reception state, remaining battery level, date, and remaining battery level detected in steps S61 to S67.
[0108]
If YES is determined in the step S171, the area 1 pallet data 0, the area 1 pallet data 1 and the area 2 pallet data are set in the pallet control register 80c in steps S175, S177 and S179. The binary image data stored in the frame memory 86 is output to the LCD 18 through a coloring process using the set area 1 pallet data 0, area 1 pallet data, and area 2 pallet data 1. Area 1 of LCD 18 displays the current reception state and current battery remaining amount, and area 2 displays a character indicating today's date and current time.
[0109]
Returning to FIG. 22, in step S31, the state of the game CPU activation flag is determined. On the other hand, if the game CPU activation flag is set, it is determined in step S33 whether an interrupt request is set in the interrupt register 1. If no interrupt request is set, the process directly returns to step S5 as in the reset state described above. Therefore, when the telephone mode is set, and when the game mode is set but no interrupt request is given, the processes in steps S5 to S67 are performed without performing the processes in and after step S69 shown in FIG. repeat.
[0110]
If an interrupt request is set in the interrupt register 1, the setting value of the FIFO register 1 is detected in step S69, and the content of the detected setting value is determined in each of steps S71 and S75. If the detected setting value is a key transfer request, key transfer processing is performed in step S73. If the detected setting value is an FEP (Front End Processing) transfer request, FEP transfer processing is performed in step S77. If the detected setting value is another request, the corresponding processing is performed in step S79. When the process of step S73, S77 or S79 is completed, the process returns to step S3. The key transfer process is a process performed on the side of the telephone CPU core 28a in order to assign the start function and the select function to the * key 24d and the # key 24e, and the FEP transfer process is for inputting the player name. This is processing performed on the telephone CPU core 28a side.
[0111]
The key transfer process in step S73 follows a subroutine shown in FIG.
First, in step S181, a setting value is detected from the FIFO register 1, and it is determined in step S183 whether the detected setting value is an end code. Referring to FIG. 32, when a key transfer request is set in FIFO register 1, a key code indicating one of telephone keys 24 is set next to this key transfer request and it is desired to assign this key code. Function information indicating the function is set next to the key code. The end code is set after such repetition of the key code and function information.
[0112]
Therefore, the key code is detected in step S181, and NO is determined in the first step S183. In step S185, the key item that matches the detected setting value, that is, the key code is specified from the function assignment table 34a (formed in the SRAM 34) shown in FIG. For example, if the lower 4 digits of the key code are “1010”, “# key” is specified, and if the lower 4 digits of the key code is “1011”, “* key” is specified. In step S187, the set value of the FIFO register 1 is detected again. As described above, the setting value following the key code is function information, and the function information is detected in step S187. In step S189, the detected function information is assigned to the key item specified in step S185. When the process of step S189 is completed, “0” is set in the corresponding bit of the game key register 3 in step S191, and the process returns to step S181.
[0113]
For example, when function information indicating “select” (lower 8 bits is “10000000”) is detected following the key code indicating “# key”, the function of selecting “# key” in the function assignment table 34a is selected. Is assigned, and “0” is set in KO7 of the game key register 3 shown in FIG. When function information indicating “start” (lower 8 bits are “01000000”) is detected following the key code indicating “* key”, the start function is added to the item “* key” in the function assignment table 34a. Is assigned, and “0” is set in KO6 of the game key register 3.
[0114]
When the set value detected in step S181 indicates an end code, the process proceeds to step S193 through step S183, and it is determined which of the telephone keys 24 has been operated with reference to the telephone key register 28b shown in FIG. In step S195, the function information assigned to the determined operation key is searched from the function assignment table 34a, and in step S197, it is determined whether the function information has been found from the function assignment table 34a.
[0115]
According to FIG. 33, in addition to the “# key” and “* key”, a key item indicating the numeric key 24c is also provided in the function assignment table 34a, and no item of function information is assigned to the key item. Can also exist. Therefore, it is determined in step S197 whether function information has been found. If the function information cannot be found, the routine returns to the routine shown in FIG. 24 as it is. However, if the function information is found, the corresponding bit of the game key register 3 is set to “1” in step S199 and FIG. Return to the routine shown in.
[0116]
For example, when the numeric key indicating “1” is pressed by the operator, no bit of the game key register 3 is set to “1”, but when the * key 24d is pressed by the operator, the game key register KO6 of 3 is set to “1”.
[0117]
The FEP transfer process in step S77 in FIG. 24 follows a subroutine shown in FIG. First, the cursor display position data is detected from the FIFO register 1 in step S201, and then the subroutine shown in FIG. 27 is processed in step S203.
At this time, the binary image data drawn in the area 2 in the frame memory 86 is image data indicating a cursor. The drawing position of the cursor is determined based on the cursor display position data, and the binary image data is stored in the frame memory 86 as shown in FIG.
[0118]
On the other hand, the “Please input name” guidance message and the color image data indicating the name input frame shown in FIG. 35B are drawn in the frame memory 88 by the game CPU 40. As a result, the player name input screen shown in FIG.
[0119]
When the processing in step S203 is completed, the set values of the telephone key register 28b and the game key register 2 are detected in step S205, and in the subsequent step S207, it is determined whether or not the A button 22b is operated. If “NO” here, it is considered that the telephone key 24 has been operated, and the process proceeds to a step S209 to perform the FEP processing. When the FEP process ends, the process returns to step S203. A character string corresponding to the operation of the telephone key 24 is generated by the FEP process, and the generated character string is displayed on the LCD 18 by the process of the subsequent step S203.
[0120]
For example, when the telephone key 24 is operated to input “Yamada” to perform kana-kanji conversion and further input “Taro”, binary image data is drawn in the frame memory 86 as shown in FIG. In the name input frame on the LCD 18, the characters “Taro Yamada” are displayed as shown in FIG. The cursor points to "Taro".
[0121]
When the A button 22b is operated by the operator after the name input is completed, “YES” is determined in step S207, and “FEP result sending” and the JIS code corresponding to the created character string in each of steps S211 and S213 are FIFO. Set to register 2. In step S215, an interrupt request is set in the interrupt register 2, and in step S217, the subroutine shown in FIG. 27 is processed. When the process of step S217 is completed, the routine returns to the routine shown in FIG.
[0122]
In step S217, binary image data in which all bits are “0” is drawn in area 2 of the frame memory 86, and only the binary image data of the character indicating the reception state and the remaining battery level remains in the frame memory 86. However, color image data indicating “Taro Yamada” is drawn in the frame memory 88 in the manner shown in FIG. 37B by the processing of the game CPU 40 described later, and the player name input screen shown in FIG. Will be displayed.
[0123]
The game CPU core 50 processes the flowcharts shown in FIGS. First, in step S221, the state of the game CPU activation flag is determined. When the set state is reached, game CPU display processing is performed in step S223. This game CPU display process follows a subroutine shown in FIG.
[0124]
Referring to FIG. 40, first, in step S271, still character data for forming background image data is set in VRAM 72, and in step S273, still character palette data is set in color palette RAM 68. Subsequently, in step S275, it is determined whether or not the screen to be displayed this time is a screen on which object image data is to be output. If NO, the process directly proceeds to step S283. If YES, the processes in steps S277 to S281 are performed. Then, the process proceeds to step S283. For example, on the game screen shown in FIG. 4, it is necessary to display an object image (motion character). In this case, the process proceeds to step S277. On the other hand, on the menu screen shown in FIG. 3 and the player name input screen shown in FIGS. 6A and 6B, only the background image needs to be displayed. In this case, the process proceeds to step S283.
[0125]
When displaying an object image, first, the moving character data is set in the VRAM 74 in step S277, and the moving character palette data is set in the color palette RAM 68 in step S279. In step S281, the motion character attribute is set in the OAM 76. When the processing in step S281 is completed, the process proceeds to step S283.
[0126]
In step S283, setting values relating to the output of the background image and the object image are set in the register 70, and in the subsequent step S285, it is determined whether or not the processing for one frame has been completed. If “NO” here, the process returns to the step S271 to repeat the above-described processing, but if “YES”, the process returns to the upper hierarchy routine.
[0127]
The PPU 78 colors the still character data according to the palette data in the color palette RAM 68 according to the set value of the register 70, and also colors the motion character data according to the palette data in the color palette RAM 68 as necessary. The colored color image data is written into the frame memory 88 by the LCD controller 84 and then output to the LCD 18 by the same LCD controller 84. As a result, a color image is displayed on the LCD 18.
[0128]
In the game CPU display process in step S223 shown in FIG. 38, a menu screen as shown in FIG. This menu screen is formed by stationary characters. When a desired game is selected from the menu screen displayed on the LCD 18, the process proceeds from step S225 to step S227. In each of steps S227 to S237, the key transfer request, the key code indicating “# key”, the function information indicating “select”, the key code indicating “* key”, the function information indicating “start”, and the end code are FIFOs. Set to register 1. When the end code setting is completed, an interrupt request is set in the interrupt register 1 shown in FIG. 13 in step S239. As a result, the above-described key transfer processing is executed by the telephone CPU core 28a, the select function is assigned to the # key 24e, and the start function is assigned to the * key 24d.
[0129]
In step S241, the SPU 64 is instructed to output BGM data related to the selected game. BGM based on the BGM data is output from the speaker 48. In the subsequent step S243, the set value of the game key register 1 is detected. Then, it is determined in each of steps S245, S251 and S261 which bit of K0 to K7 shown in FIG. 15 is set to “1”.
[0130]
When K7 corresponding to the select key is set to “1”, YES is determined in a step S245, and it is determined whether or not the display of the LCD 18 is a menu screen in a step S247. If the display on the LCD 18 is not a menu screen, the process directly returns to step S243, and as a result, the operation of the # key 24d is invalidated. On the other hand, if the display on the LCD 18 is a menu screen, the process returns to step S243 through the selection process in step S249.
[0131]
When K6 corresponding to the start key is set to “1”, “YES” is determined in the step S251, and the game is paused in a step S253. Specifically, the K6 bit is returned to “0”, the sound output to the SPU 64 is stopped, and the current game data is stored in the flash memory 54. In step S255, the set value of the game key register 1 is detected. In step S257, it is determined whether or not K6 corresponding to the start key indicates “1”. Here, unless it is determined YES, the processes of steps S255 and S257 are repeated, and the game screen is stopped during this time. If YES is determined in the step S257, the pause state is canceled in a step S259, and the process returns to the step S243. As a result, the movement of the game screen and the output of BGM are resumed.
[0132]
By storing the game data in step S253, the game can be resumed from the point of interruption by another operation (for example, restart) even if the pause state cannot be recovered for some reason (for example, battery exhaustion) after the call ends. Can do.
[0133]
When bits other than K6 and K7 shown in FIG. 15 are set to “1”, YES is determined in step S261, and game processing, game CPU display processing, and sound effect output processing are performed in steps S263, S265, and S267, respectively. To do.
In the game process in step S263, the settings of the color palette RAM 68, the register 70, the VRAMs 72 and 74, and the OAM 76 are updated as necessary. In the game CPU display process in step S265, a game screen including a screen, a stationary object, and a moving character as shown in FIG. In the sound effect output process of step S267, sound effect data is output from the SPU 64.
[0134]
If any of K0 to K7 shown in FIG. 15 is “0”, NO is determined in step S261, and the process directly returns to step S243.
[0135]
If a scene occurs in which the player's name is input during the game process in step S263, the game CPU core 50 processes the subroutine shown in FIG. First, in step S291, a game CPU display process shown in FIG. 40 is performed. As a result, the message “Please input name” as shown in FIG. 35B and the color image data of the name input frame are written in the frame memory 88, and the name input shown in FIG. A screen is displayed. However, the cursor is not yet displayed when step S291 is completed.
[0136]
In step S293, the FEP transfer request is set in the FIFO register 1, in step S295, the cursor display position data is set in the FIFO register 1, and when the processing in step S295 is completed, an interrupt request is set in the interrupt register 1 in step S297. As a result, the FEP transfer process is performed on the telephone CPU core 28a side, and the cursor is displayed in the name input frame as shown in FIG.
[0137]
In step S299, it is determined whether or not an interrupt request is set in the interrupt register 2. If YES is determined in this step, the set value (FEP result transmission) of the FIFO register 2 is detected in step S301, and the set value (JIS code) of the FIFO register 2 is detected in step S303. Further, a game CPU display process is performed in step S305 to display the name in the name display frame based on the detected JIS code. As a result, the message, name display frame and name color image data as shown in FIG. 37B are drawn in the frame memory 88, and the name input screen as shown in FIG. . The drawing position of the color image data indicating the name is determined based on the cursor display position data described above. When the process of step S305 is completed, the process returns to the upper layer routine.
[0138]
As can be seen from the above description, the game CPU core 50 executes game processing as necessary, and the telephone CPU core 28a always executes telephone processing. The telephone CPU core 28a is assigned * key 24d and # key 24e, and the game key register 1 is provided with a K6 bit assigned a start function (pause function) and a K7 bit assigned a select function. .
[0139]
Here, the game CPU core 50 transfers the key information indicating the * key 24d to the telephone CPU core 28a together with the bit information indicating the K6 bit, and the key information indicating the # key 24e together with the bit information indicating the K7 bit. To 28a. The telephone CPU core 28a takes these key information and bit information and registers them in the function assignment table 34a. When the * key 24d is operated, the K6 bit of the game key register 1 is set to "1", and when the # key 24e is operated, the K7 bit of the game key register 1 is set to "1". The game CPU core 50 executes the start function when the K6 bit indicates “1”, and executes the select function when the K7 bit indicates “1”.
[0140]
Thus, when a specific key connected to the telephone CPU core 28a is operated, processing related to the specific function is executed in the game CPU core 50. That is, the process related to the specific function of the game CPU core 50 is executed in accordance with the operation of the specific key connected to the telephone CPU core 28a, thereby realizing a variety of key inputs.
[0141]
The game CPU core 50 is also assigned a frame memory 88 for storing color image data. A color image based on the color image data stored in the frame memory 88 is displayed on the LCD 18. The telephone key 24 assigned to the telephone CPU core 28a has a character input function.
[0142]
When a character is input by operating the telephone key 24, the telephone CPU core 28a transfers a character code indicating the input character to the game CPU core 50. The game CPU core 50 takes in the character code from the telephone CPU core 28 a and writes color image data indicating characters based on the taken-in character code into the frame memory 88. That is, when the telephone key 24 connected to the telephone CPU core 28a is operated, color image data indicating the input character by the key operation is written into the frame memory 88 by the game CPU core 50.
[0143]
The telephone CPU 28a is further assigned a frame memory 86 for storing binary image data, and the display displays an image based on the binary image data stored in the frame memory 86 in addition to the color image.
[0144]
At this time, the telephone CPU core 28a writes binary image data indicating the input character to the frame memory 86, and when a confirmation instruction is given (when the A button 22b is operated), the key code corresponding to the input character is displayed. The binary image data is erased from the frame memory 86 while being transferred to the game CPU core 50. Thereby, instead of erasing the image (input characters) based on the binary image data, a color image (same input characters) based on the color image data is displayed on the LCD 18.
[0145]
Note that the game CPU core 50 transfers position information (cursor display position data) indicating the writing position of the binary image data to the telephone CPU core 28a prior to taking in the character code. For this reason, the telephone CPU core 28a writes binary image data in the frame memory 86 based on the transferred cursor display position data. The game CPU core 50 also writes the color image data indicating the character based on the character code in the frame memory 88 in association with the writing position of the binary image data.
[0146]
As described above, the game CPU core 50 displays arbitrary characters on the LCD 18 in response to the operation of the telephone key 24 assigned to the telephone CPU core 28a. For this reason, the key input can be diversified.
[0147]
In this embodiment, areas 1 and 2 are formed as shown in FIG. 16, and characters indicating the reception state and the remaining battery level are displayed in area 1 as shown in FIG. However, the areas 1 and 2 may be formed as shown in FIG.
[0148]
In this embodiment, when an incoming call is received during the game, the tone of the game screen is raised. However, the tone of the game screen may be lowered.
[0149]
In this embodiment, the game start key function and select key function are assigned to the telephone keys (# and *), but other functions of the game may be assigned to the telephone keys.
[Brief description of the drawings]
FIG. 1 is an external view showing an embodiment of the present invention.
FIG. 2 is an illustrative view showing one example of an incoming call waiting screen.
FIG. 3 is an illustrative view showing one example of a menu screen.
FIG. 4 is an illustrative view showing one example of a game screen.
FIG. 5 is an illustrative view showing one example of an incoming call guidance screen;
6A is an illustrative view showing an example of a player name input screen in the middle of inputting a player name, and FIG. 6B is an example of a player name input screen after the player name input is completed. It is an illustration figure shown.
7 is a block diagram showing a configuration of the embodiment in FIG. 1; FIG.
FIG. 8 is a block diagram showing a configuration of a game CPU.
FIG. 9 is a block diagram showing a configuration of a key controller and its periphery.
FIG. 10 is a block diagram showing a configuration of an LCD controller and its periphery.
FIG. 11 is a block diagram illustrating a configuration of an image synthesis circuit.
FIG. 12 is an illustrative view showing a mapping state of a memory that can be accessed by a game CPU core;
13 is an illustrative view showing a configuration of a register 80. FIG.
FIG. 14 is an illustrative view showing a configuration of LCD control data.
FIG. 15 is an illustrative view showing a configuration of game key registers 1 to 3;
FIG. 16 is an illustrative view illustrating an area formed on an LCD display screen.
FIG. 17 is an illustrative view illustrating colors displayed on the LCD display screen.
18 is an illustrative view showing one example of binary image data drawn in a frame memory 86. FIG.
FIG. 19 is an illustrative view showing one example of color image data drawn in a frame memory 88;
20 is an illustrative view showing another example of binary image data drawn in the frame memory 86. FIG.
FIG. 21 is an illustrative view showing another example of color image data drawn in the frame memory 88;
FIG. 22 is a flowchart showing a part of the operation of the telephone CPU core.
FIG. 23 is a flowchart showing another portion of the operation of the telephone CPU core.
FIG. 24 is a flowchart showing still another part of the operation of the telephone CPU core.
FIG. 25 is a flowchart showing still another portion of the operation of the telephone CPU core.
FIG. 26 is a flowchart showing another part of the operation of the telephone CPU core.
FIG. 27 is a flowchart showing still another part of the operation of the telephone CPU core.
FIG. 28 is a flowchart showing still another portion of the operation of the telephone CPU core.
FIG. 29 is a flowchart showing another portion of the operation of the telephone CPU core.
FIG. 30 is a flowchart showing still another portion of the operation of the telephone CPU core.
FIG. 31 is a flowchart showing still another portion of the operation of the telephone CPU core.
FIG. 32 is an illustrative view showing data set in the FIFO register 1 during key transfer processing;
FIG. 33 is an illustrative view showing a function assignment table;
FIG. 34 is a flowchart showing another portion of the operation of the telephone CPU core.
35A is an illustrative view showing binary image data drawn in the frame memory 86 during the player name input process, and FIG. 35B is color image data drawn in the frame memory 88 during the player name input process. (C) is an illustrative view showing a player name input screen displayed on the LCD.
36A is an illustrative view showing binary image data drawn in the frame memory 86 during the player name input process, and FIG. 36B is color image data drawn in the frame memory 88 during the player name input process. (C) is an illustrative view showing a player name input screen displayed on the LCD.
37A is an illustrative view showing binary image data drawn in the frame memory 86 during the player name input process, and FIG. 37B is color image data drawn in the frame memory 88 during the player name input process. (C) is an illustrative view showing a player name input screen displayed on the LCD.
FIG. 38 is a flowchart showing a part of the operation of the game CPU core.
FIG. 39 is a flowchart showing another portion of the operation of the game CPU core.
FIG. 40 is a flowchart showing still another portion of the operation of the game CPU core.
FIG. 41 is a flowchart showing yet another portion of the operation of the game CPU core.
FIG. 42 is an illustrative view showing one portion of operations relating to another embodiment of the present invention;
FIG. 43 is an illustrative view showing another portion of operations relating to another embodiment of the present invention;
[Explanation of symbols]
10 ... Mobile communication terminal with game function
18 ... LCD
20 ... Game start key
22 ... Game key
24 ... Telephone key
28 ... Telephone CPU
40 ... Game CPU
50 ... Game CPU core
64 ... Audio processing unit
68 ... Color palette RAM
70, 80 ... registers
72, 74 ... VRAM
76 ... OAM
78. Image processing unit
82 ... Key controller
84 ... LCD controller
86, 88 ... frame memory

Claims (5)

A first processor for executing a first process;
A second processor for executing a second process ;
Comprising a plurality of first keys that are connected to the first processor, the plurality of second keys <br/> connected to the second processor you and,
The first process includes a request process for requesting the second processor to set at least one of the plurality of second keys as a specific key,
The second process includes a key operation determination process for determining whether or not the specific key is operated, and a first specific signal generation process for generating a specific signal to be given to the first processor when the specific key is operated. Including
The first processor executes the first process in response to the operation of the first key, and executes the specific function process in the first process when the specific signal is input during the execution of the first process. you, the electronic device. Further comprising a register having a specific bit of the specific function is assigned,
It said first specific signal generation processing is processing for setting a predetermined value in the specific bit,
The specific function execution processing, the specific bit is a process for executing the specific function when indicating the predetermined value, according to claim 1 Symbol mounting electronic devices. The request processing, look including the notification process for notifying the bit information indicating the specific bit key information indicating the specific key in the second processor,
In the key operation determination process, it is determined whether the operation of the specific key based on the key information,
Wherein the first specific signal generation processing, sets the predetermined value to the specific bits based on the bit information, the electronic apparatus according to claim 2, wherein. The first process is a game process executed when necessary,
The second process is a telephone processing executed at all times,
The specific function is related to the game processing,
The second key, the associated with the telephone processing when the game processing is not being executed, the electronic device according to any one of claims 1 to 3. The specific function is a pause function that pauses a running game,
The electronic device according to claim 4 , wherein the second process further includes a detection process for detecting an incoming call and a second specific signal generation process for generating the specific signal in response to the detection of the incoming call.

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