JP4547864B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor and a manufacturing method thereof.
[0002]
[Prior art]
Field effect transistors (FETs) including thin film transistors (TFTs) currently used in many electronic devices are, for example, channel formation regions and source / drains formed in a silicon semiconductor substrate or silicon semiconductor layer. Region, SiO formed on silicon semiconductor substrate surface or silicon semiconductor layer surface ₂ And a gate electrode provided to face the channel formation region with the gate insulating film interposed therebetween. Alternatively, it includes a gate electrode formed on the substrate, a gate insulating film formed on the substrate including the gate electrode, and a channel formation region and a source / drain region formed on the gate insulating film. . For manufacturing field effect transistors having these structures, very expensive semiconductor manufacturing apparatuses are used, and reduction of manufacturing costs is strongly demanded.
[0003]
Therefore, in recent years, attention has been focused on research and development of FETs using organic semiconductor materials that can be manufactured based on methods exemplified by spin coating, printing, and spraying without using vacuum technology.
[0004]
An example of a method of manufacturing an FET (organic FET) using such an organic semiconductor material (see IEDM Tech. Digest (1999), DJGundlach, et al., "High mobility, low voltage organic thin film transistors") is shown below. This will be described with reference to FIGS. 14A to 14D and FIGS. 15A to 15C.
[0005]
[Step-10]
First, a gate electrode 112 made of a Ti / Au laminated film is formed on a substrate 110 made of plastic such as PET or polyimide based on, for example, a lift-off method (see FIG. 14A). In the Ti / Au laminated film, the Ti film is the lower layer and the Au film is the upper layer, and the Ti film functions as a kind of adhesion layer. The same applies to the following description. In all the drawings, the Ti / Au laminated film is represented by one layer.
[0006]
[Step-20]
Next, on the entire surface of the substrate 110 including the gate electrode 112, for example, based on the sputtering method, SiO 2 ₂ An insulating film 113 made of is formed. Thereafter, the source / drain electrode 114 is formed on the insulating film 113 based on the lift-off method in the same manner as the gate electrode 112. The source / drain electrode 114 is also made of, for example, a Ti / Au laminated film. Specifically, based on the photolithography technique, after forming a resist layer 120 having an opening where a source / drain electrode 114 is to be formed (see FIG. 14B), a Ti / Au laminated film is formed on the entire surface. Film. Then, the structure shown in FIG. 14C can be obtained by removing the resist layer 120.
[0007]
[Step-30]
Next, a channel structure layer 117 is formed over the entire surface of the substrate 110 including the source / drain electrodes 114 and the insulating film 113 (see FIG. 14D). The channel constituent layer 117 is made of, for example, a pentacene molecular thin film formed based on a resistance heating vapor deposition method or an organic semiconductor thin film mainly composed of polythiophene. A portion of the channel constituent layer 117 formed on the insulating film 113 between the source / drain electrode 114 and the source / drain electrode 114 corresponds to the channel formation region 118.
[0008]
[Step-40]
Thereafter, a resist layer 121 made of, for example, polyvinyl alcohol (PVA) is formed on a part of the channel constituent layer 117 including the channel formation region 118 based on the photolithography technique and the etching technique (see FIG. 15A). .
[0009]
[Step-50]
Next, using the resist layer 121 as a mask, for example, O ₂ The channel constituent layer 117 is etched by a plasma etching method to perform element isolation (see FIG. 15B). Thereafter, by removing the resist layer 121, the FET shown in FIG. 15C can be obtained.
[0010]
[Non-Patent Document 1]
IEDM Tech. Digest (1999), DJGundlach, et al., "High mobility, low voltage organic thin film transistors"
[Non-Patent Document 2]
MD Musick et al., Chem. Mater. (1997), 9, 1499; Chem. Mater. (2000), 12, 2869
[0011]
[Problems to be solved by the invention]
By the way, in general, transfer characteristic and maximum drain current can be cited as characteristic indicators of FETs, and these characteristics generally become better as the gate length is shorter. Therefore, it is preferable that the gate length shown in FIG.
[0012]
Here, the gate length depends on the resolution in the lithography technique in the lift-off method executed in [Step-20]. That is, it depends on the resolution at the time of forming the resist layer 120 shown in FIG. Therefore, when high performance is required for the FET, an expensive exposure apparatus with high resolution is required. That is, the performance of the FET and the manufacturing cost of the FET have a trade-off relationship.
[0013]
Further, in the lithography technique in the lift-off method executed in [Step-20], alignment of the source / drain electrode 114 with respect to the gate electrode 112 is necessary. That is, it is necessary to align the mask when forming the resist layer 120 shown in FIG. Since a certain amount of misalignment must be assumed due to the accuracy of the exposure apparatus and the warpage / extension / contraction of the substrate, the source / drain electrode 114 must be designed to partially overlap the gate electrode 112. However, these overlaps cause an increase in parasitic capacitance between the source / drain electrode 114 and the gate electrode 112. The parasitic capacitance causes an increase in switching time when the organic FET is used as a switching element, and reduces a transmission gain for an AC signal when the organic FET is used as an amplifier. Therefore, it is preferable to minimize the overlap between the source / drain electrode 114 and the gate electrode 112 as much as possible. However, like the gate length, the reduction in overlap between the source / drain electrode 114 and the gate electrode 112 is in a trade-off relationship with the manufacturing cost.
[0014]
Therefore, an object of the present invention is to obtain a short gate length with high accuracy and easily, and to form the gate electrode and the source / drain electrodes in a self-aligned manner. It is an object of the present invention to provide a field effect transistor and a method for manufacturing the same that can reduce the photolithography process.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, a field effect transistor according to the first aspect of the present invention provides:
(A) a gate electrode formed on a substrate, having a top surface, a first side surface, and a second side surface, and having a substantially square cross-sectional shape;
(B) an insulating film formed on the top surface, the first side surface, and the second side surface of the gate electrode;
(C) a first source / drain electrode formed on a portion of the insulating film located on the top surface of the gate electrode;
(D) a second source / drain electrode formed on the portion of the substrate facing the first side of the gate electrode;
(E) a third source / drain electrode formed on the portion of the substrate facing the second side of the gate electrode; and
(F) a semiconductor material layer formed from the second source / drain electrode through the first source / drain electrode to the third source / drain electrode;
Comprising
A first channel forming region comprising a gate electrode, a first source / drain electrode, a semiconductor material layer portion formed on a portion of the insulating film located on the first side surface of the gate electrode; A first field-effect transistor is composed of the two source / drain electrodes,
A second channel forming region comprising a gate electrode, a first source / drain electrode, a semiconductor material layer portion formed on a portion of the insulating film located on the second side surface of the gate electrode, A third field effect transistor is constituted by the three source / drain electrodes.
[0016]
In order to achieve the above object, a field effect transistor according to the second aspect of the present invention provides:
(A) a gate electrode formed on a substrate, having a top surface, a first side surface, and a second side surface, and having a substantially square cross-sectional shape;
(B) an insulating film formed on the top surface of the gate electrode and at least the first side surface;
(C) a first source / drain electrode formed on a portion of the insulating film located on the top surface of the gate electrode;
(D) a second source / drain electrode formed on the portion of the substrate facing the first side of the gate electrode; and
(E) a semiconductor material layer formed from the first source / drain electrode to the second source / drain electrode;
Comprising
A portion of the semiconductor material layer formed on the portion of the insulating film located on the first side surface of the gate electrode corresponds to a channel formation region.
[0017]
In order to achieve the above object, a field effect transistor according to the third aspect of the present invention provides:
(A) a gate electrode formed on a substrate, having a first side surface and a second side surface, and having a triangular cross-sectional shape;
(B) an insulating film formed on the first side surface and the second side surface of the gate electrode;
(C) a first source / drain electrode formed on a portion of the insulating film located on the second side surface of the gate electrode;
(D) a second source / drain electrode formed on the portion of the substrate facing the first side of the gate electrode; and
(E) a semiconductor material layer formed from the first source / drain electrode to the second source / drain electrode;
Comprising
A portion of the semiconductor material layer formed on the portion of the insulating film located on the first side surface of the gate electrode corresponds to a channel formation region.
[0018]
In order to achieve the above object, a method for manufacturing a field effect transistor according to the first aspect of the present invention is a method for manufacturing a so-called bottom contact type field effect transistor according to the first aspect of the present invention. Yes,
The gate electrode, the first source / drain electrode, the first channel formation region, and the second source / drain electrode constitute a first field effect transistor,
A method of manufacturing a field effect transistor in which a second field effect transistor is configured by a gate electrode, a first source / drain electrode, a second channel formation region, and a third source / drain electrode. And
(A) forming a gate electrode having a top surface, a first side surface, and a second side surface and having a substantially square cross-sectional shape on a substrate;
(B) forming an insulating film on the top surface, the first side surface, and the second side surface of the gate electrode;
(C) forming a first source / drain electrode on the portion of the insulating film located on the top surface of the gate electrode, and forming a second source on the portion of the substrate facing the first side surface of the gate electrode; Forming a third source / drain electrode on the portion of the substrate facing the second side surface of the gate electrode;
(D) A semiconductor material layer is formed from the second source / drain electrode through the first source / drain electrode to the third source / drain electrode, and thus located on the first side surface of the gate electrode. A first channel forming region comprising a semiconductor material layer portion formed on an insulating film portion, and a semiconductor formed on the insulating film portion located on the second side surface of the gate electrode Obtaining a second channel forming region comprising a portion of the material layer;
It is characterized by comprising.
[0019]
The method for manufacturing a field effect transistor according to the second aspect of the present invention for achieving the above object is a method for manufacturing a field effect transistor according to the first aspect of the present invention of the so-called top contact type. Yes,
The gate electrode, the first source / drain electrode, the first channel formation region, and the second source / drain electrode constitute a first field effect transistor,
A method of manufacturing a field effect transistor in which a second field effect transistor is configured by a gate electrode, a first source / drain electrode, a second channel formation region, and a third source / drain electrode. And
(A) forming a gate electrode having a top surface, a first side surface, and a second side surface and having a substantially square cross-sectional shape on a substrate;
(B) forming an insulating film on the top surface, the first side surface, and the second side surface of the gate electrode;
(C) Forming a semiconductor material layer on at least the insulating film located on the top surface, the first side surface, and the second side surface of the gate electrode, so that the insulation located on the first side surface of the gate electrode. A first channel formation region comprising a semiconductor material layer portion formed on the film portion is obtained, and a semiconductor material layer formed on the insulating film portion located on the second side surface of the gate electrode is obtained. Obtaining a second channel forming region comprising a portion;
(D) forming a first source / drain electrode over the portion of the semiconductor material layer located on the top surface of the gate electrode, and forming a second over the portion of the substrate facing the first side of the gate electrode; Forming a source / drain electrode together with forming a third source / drain electrode on the portion of the substrate facing the second side of the gate electrode;
It is characterized by comprising.
[0020]
The method for manufacturing a field effect transistor according to the third aspect of the present invention for achieving the above object is a method for manufacturing a field effect transistor according to the second aspect of the present invention of the so-called bottom contact type. Yes,
(A) forming a gate electrode having a top surface, a first side surface, and a second side surface and having a substantially square cross-sectional shape on a substrate;
(B) forming an insulating film on the top surface of the gate electrode and at least the first side surface;
(C) forming a first source / drain electrode on the portion of the insulating film located on the top surface of the gate electrode, and forming a second source on the portion of the substrate facing the first side surface of the gate electrode; Forming a drain electrode;
(D) A semiconductor material layer is formed from the first source / drain electrode to the second source / drain electrode, and thus formed on the portion of the insulating film located on the first side surface of the gate electrode. Obtaining a channel forming region comprising a portion of the semiconductor material layer,
It is characterized by comprising.
[0021]
In order to achieve the above object, a method for manufacturing a field effect transistor according to the fourth aspect of the present invention is a method for manufacturing a field effect transistor according to the second aspect of the present invention of the so-called top contact type. Yes,
(A) forming a gate electrode having a top surface, a first side surface, and a second side surface and having a substantially square cross-sectional shape on a substrate;
(B) forming an insulating film on the top surface of the gate electrode and at least the first side surface;
(C) forming a semiconductor material layer on at least the top surface of the gate electrode and the insulating film located on the first side surface, and thus on the insulating film portion positioned on the first side surface of the gate electrode; Obtaining a channel formation region comprising a portion of the semiconductor material layer formed in
(D) forming a first source / drain electrode over the portion of the semiconductor material layer located on the top surface of the gate electrode, and forming a second over the portion of the substrate facing the first side of the gate electrode; Forming a source / drain electrode;
It is characterized by comprising.
[0022]
The method for manufacturing a field effect transistor according to the fifth aspect of the present invention for achieving the above object is a method of manufacturing a field effect transistor according to the third aspect of the present invention of the so-called bottom contact type. Yes,
(A) forming a gate electrode having a first side surface and a second side surface and having a triangular cross-sectional shape on a substrate;
(B) forming an insulating film on the first side surface and the second side surface of the gate electrode;
(C) forming a first source / drain electrode on the portion of the insulating film located on the second side surface of the gate electrode, and forming a second source on the portion of the substrate facing the first side surface of the gate electrode; Forming a source / drain electrode of
(D) A semiconductor material layer is formed from the first source / drain electrode to the second source / drain electrode, and thus formed on the portion of the insulating film located on the first side surface of the gate electrode. Obtaining a channel forming region comprising a portion of the semiconductor material layer,
It is characterized by comprising.
[0023]
In order to achieve the above object, a method for manufacturing a field effect transistor according to the sixth aspect of the present invention is a method for manufacturing a field effect transistor according to the third aspect of the present invention of the so-called top contact type. Yes,
(A) forming a gate electrode having a first side surface and a second side surface and having a triangular cross-sectional shape on a substrate;
(B) forming an insulating film on the first side surface and the second side surface of the gate electrode;
(C) forming a semiconductor material layer on at least the top surface of the gate electrode and the insulating film located on the first side surface, and thus on the insulating film portion positioned on the first side surface of the gate electrode; Obtaining a channel formation region comprising a portion of the semiconductor material layer formed in
(D) forming a first source / drain electrode on the portion of the insulating film located on the second side surface of the gate electrode, and forming a second source on the portion of the substrate facing the first side surface of the gate electrode; Forming a source / drain electrode of
It is characterized by comprising.
[0024]
The field effect transistor according to the first to third aspects of the present invention, or the method for producing the field effect transistor according to the first to sixth aspects of the present invention (hereinafter collectively referred to as "the field effect transistor"). The semiconductor material layer may be composed of an organic material, or may be composed of an organic material and an inorganic material, or Moreover, it can be set as the structure which consists of inorganic materials (specifically Si, Ge, Se, for example).
[0025]
More specifically, as an organic material constituting the semiconductor material layer, 2,3,6,7-dibenzoanthracene (also referred to as pentacene), C ₉ S ₉ (Benzo [1,2-c; 3,4-c ′; 5,6-c ″] tris [1,2] dithiol-1,4,7-trithione), C _{twenty four} H ₁₄ S ₆ (Alpha-sexithiophene), phthalocyanine represented by copper phthalocyanine, fullerene (C ₆₀ ), Tetrathiotetracene (C ₁₈ H ₈ S _Four ), Tetraselenotetracene (C ₁₈ H ₈ Se _Four ), Tetratellurtetracene (C ₁₈ H ₈ Te _Four ), Poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid (PEDOT / PSS). The structural formula (1) of poly (3,4-ethylenedioxythiophene) and the structural formula (2) of polystyrene sulfonic acid are shown in FIG.
[0026]
Alternatively, as the organic material constituting the semiconductor material layer, for example, a heterocyclic conjugated conductive polymer and a heteroatom-conjugated conductive polymer exemplified below can be used. In the structural formula, “R” and “R ′” are alkyl groups (C _n H _{2n + 1} ).
[0027]
[Heterocyclic conjugated conductive polymer]
Polypyrrole [see structural formula (3) in FIG. 11]
Polyfuran [see structural formula (4) in FIG. 11]
Polythiophene [see structural formula (5) in FIG. 11]
Polyselenophene [see structural formula (6) in FIG. 11]
Polytellophene [see structural formula (7) in FIG. 11]
Poly (3-alkylthiophene) [see structural formula (8) in FIG. 11]
Poly (3-thiophene-β-ethanesulfonic acid) [see structural formula (9) in FIG. 11]
Poly (N-alkylpyrrole) [see structural formula (10) in FIG. 12]
Poly (3-alkylpyrrole) [see structural formula (11) in FIG. 12]
Poly (3,4-dialkylpyrrole) [see structural formula (12) in FIG. 12]
Poly (2,2′-thienylpyrrole) [see structural formula (13) in FIG. 12]
[0028]
[Containing heteroatom-containing conductive polymer]
Polyaniline [see structural formula (14) in FIG. 12]
Poly (dibenzothiophene sulfide) [see structural formula (15) in FIG. 12]
[0029]
When the semiconductor material layer is composed of an organic material and an inorganic material, it is preferable that the inorganic material is composed of fine particles composed of a conductor or a semiconductor, and the organic material is composed of organic semiconductor molecules. In this case, a conductive path is formed by the fine particles and organic semiconductor molecules bonded to the fine particles, and conductivity (carrier movement) of the conductive path is controlled based on an electric field formed by a voltage applied to the gate electrode. It is preferable to configure so that.
[0030]
In this way, fine particles are connected by organic semiconductor molecules to form a conductive path, thereby forming a network-type conductive path in which the conductive paths in the fine particles and the conductive paths along the molecular skeleton in the organic semiconductor molecules are connected. In this structure, the charge transfer in the conductive path is dominant in the axial direction of the molecule along the main chain of the organic semiconductor molecule. Since the conduction path does not include intermolecular electron transfer, the mobility is not limited by intermolecular electron transfer, which is the cause of the low mobility of conventional organic semiconductors. Therefore, the mobility in the axial direction in the organic semiconductor molecule can be utilized to the maximum. For example, when a molecule having a conjugated system formed along the main chain is used as an organic semiconductor molecule, high intramolecular mobility due to delocalized p electrons can be used.
[0031]
It is desirable that the functional group at the terminal of the organic semiconductor molecule is chemically bonded to the fine particles. Furthermore, it is desirable that the organic semiconductor molecules and the fine particles are alternately bonded to each other by the functional groups that the organic semiconductor molecules have at both ends to form a network-type conductive path. Alternatively, the organic semiconductor molecules are formed by the functional groups. It is desirable that the particles and the fine particles are connected two-dimensionally or three-dimensionally. This results in a structure in which charge transfer in the conductive path occurs predominantly in the axial direction of the molecule along the main chain of the organic semiconductor molecule, and the mobility in the axial direction of the molecule, for example, due to delocalized p-electrons is high. Intramolecular mobility can be maximized.
[0032]
Moreover, it is preferable that the conjugate | bonded_body of microparticles | fine-particles and an organic-semiconductor molecule forms the conductive path by comprising single layer or multiple layers. Specifically, a single layer of the conjugate can be formed by performing the step of contacting the organic semiconductor molecules once after forming the fine particle layer, and by repeating this step twice or more, Multiple layers can be formed. In this case, it is desirable to form the first fine particle layer on a base layer having good adhesion to the fine particles.
[0033]
Gold (Au), silver (Ag), and platinum (Pt) can be exemplified as the fine particles composed of a conductor, and cadmium sulfide (CdS), cadmium selenide (CdSe), and silicon (Si) as fine particles composed of a semiconductor. Can be mentioned. The particle diameter of the fine particles is preferably 10 nm or less.
[0034]
As a molecule that plays a role of fixing fine particles (a role as a kind of solder) in an underlayer (a molecular solder layer that works as a kind of adhesive for fixing only one fine particle), a silane compound, It is preferable to use a molecule having a functional group that can be chemically bonded to the fine particles, for example, to the substrate or various electrodes formed on the substrate. Specific examples include amino groups having affinity for gold (Au), (3-aminopropyl) trimethoxysilane (APTMS) having a thiol group, and mercaptosilane.
[0035]
An organic semiconductor molecule is an organic semiconductor molecule having a conjugated bond, and has a thiol group (SH) and an amino group (—NH) at both ends of the molecule. ₂ ), An isocyano group (—NC), Thioacetyl group Group (-SCOCH _Three Or Carboxy group It is desirable to have (—COOH), and more specifically, the following materials can be exemplified as the organic semiconductor molecule. In addition, thiol group (-SH), amino group (-NH ₂ ), An isocyano group (—NC) and Thioacetyl group (-SCOCH _Three ) Is a functional group that binds to conductive fine particles such as gold (Au), Carboxy group (—COOH) is a functional group bonded to the semiconductor fine particles.
[0036]
4,4′-biphenyldithiol [see structural formula (16) in FIG. 13]
4,4′-Diisocyanobiphenyl [see the structural formula (17) in FIG. 13]
4,4′-Diisocyano-p-terphenyl [see structural formula (18) in FIG. 13]
2,5-bis (5'- Thioacetyl group -2'-thiophenyl) thiophene [see structural formula (19) in FIG. 13]
[0037]
As a method for forming the semiconductor material layer, although it depends on the material constituting the semiconductor material layer, a physical vapor deposition method (PVD method) exemplified by a vacuum deposition method or a sputtering method; various chemical vapor deposition methods ( CVD method); spin coating method; printing method such as screen printing method and inkjet printing method; air doctor coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, Any of the gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar coater method, dipping method, and spray method can be mentioned.
[0038]
In the present invention, as a substrate, various glass substrates, various glass substrates having an insulating layer formed on the surface, a quartz substrate, a quartz substrate having an insulating layer formed on the surface, and silicon having an insulating layer formed on the surface A substrate can be mentioned. Furthermore, examples of the substrate include a plastic film, a plastic sheet, and a plastic substrate made of a polymer material exemplified by polyethersulfone (PES), polyimide, polycarbonate, and polyethylene terephthalate (PET). If a substrate made of such a flexible polymer material is used, for example, a field effect transistor can be incorporated or integrated into a display device or electronic device having a curved shape.
[0039]
In the present invention, as a material constituting the gate electrode, gold (Au), platinum (Pt), aluminum (Al), copper (Cu), palladium (Pd), nickel (Ni), chromium (Cr), Name metals such as titanium (Ti), tantalum (Ta), tungsten (W), alloys containing these metal elements, conductive particles made of these metals, or conductive particles of alloys containing these metals. Can do. Furthermore, the various conductive polymers mentioned above can also be mentioned. The gate electrode depends on the material constituting the gate electrode, but a combination of PVD method and etching technique exemplified by vacuum deposition method and sputtering method; a combination of various CVD methods and etching technology; spin coating method And etching techniques; printing methods such as screen printing and ink jet printing using conductive paste and various conductive polymer solutions described above; lift-off method; shadow mask method; various coating methods and etching techniques described above And a combination of spraying and etching techniques.
[0040]
In the present invention, the cross-sectional shape of the gate electrode is specified, but this cross-sectional shape is a shape when the gate electrode is cut in a virtual plane perpendicular to the direction in which the top surface or side surface of the gate electrode extends. It is. In the field effect transistor according to the first aspect to the second aspect of the present invention or the field effect transistor according to the first aspect to the fourth aspect of the present invention, the cross-sectional shape of the gate electrode Can be a substantially quadrilateral having an arbitrary shape including a square, a rectangle, a trapezoid, and an isosceles trapezoid. In addition, when the cross-sectional shape of the gate electrode is a substantially quadrangle, a shape whose top surface is convex upward is also included in the shape of a substantially quadrangle. In the field effect transistor according to the third aspect of the present invention or the field effect transistor according to the fifth to sixth aspects of the present invention, the cross-sectional shape of the gate electrode is an equilateral triangle, It can be a triangle having an arbitrary shape including an isosceles triangle. The portion of the ridgeline of the gate electrode may be rounded.
[0041]
The insulating film can be formed by oxidizing or nitriding the surface of the gate electrode, or can be obtained by forming an oxide film or a nitride film on the surface of the gate electrode. As a method for oxidizing the surface of the gate electrode, although depending on the material constituting the gate electrode, O ₂ Examples thereof include an oxidation method using plasma and an anodic oxidation method. In addition, as a method of nitriding the surface of the gate electrode, depending on the material constituting the gate electrode, N ₂ A nitriding method using plasma can be exemplified. Furthermore, as an oxide film or a nitride film to be deposited on the surface of the gate electrode, SiO ₂ As well as inorganic insulating materials exemplified by SiN, SiON, spin-on-glass (SOG), metal oxide high dielectric insulating film, polymethyl methacrylate (PMMA), polyvinylphenol (PVP), polyvinyl alcohol ( Organic insulating materials exemplified in PVA) can be mentioned, and combinations thereof can also be used. As a method for forming an insulating film, PVD methods exemplified by vacuum deposition methods and sputtering methods; various CVD methods; spin coating methods; printing methods such as screen printing methods and ink jet printing methods; various coating methods described above; immersion methods; Any of a casting method and a spray method can be mentioned. Alternatively, for example, for an Au electrode, it is immersed by an insulating molecule having a functional group that can form a chemical bond with the gate electrode, such as a linear hydrocarbon modified at one end with a mercapto group. An insulating film can be formed on the surface of the gate electrode by coating the surface of the gate electrode in a self-organized manner by a method such as a method.
[0042]
In the present invention, as a material constituting the first source / drain electrode, the second source / drain electrode, and the third source / drain electrode, gold (Au), silver (Ag), platinum (Pt), aluminum ( Metals such as Al), copper (Cu), palladium (Pd), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), indium (In), tin (Sn) An alloy containing these metal elements, conductive particles made of these metals, or conductive particles of alloys containing these metals can be given. Furthermore, the various conductive polymers mentioned above can also be mentioned. The first source / drain electrode, the second source / drain electrode, and the third source / drain electrode depend on the formation form of these electrodes, but the PVD method exemplified by the vacuum evaporation method and the sputtering method. And etching technique; lift-off method; shadow mask method and the like.
[0043]
In the field effect transistor according to the first or second aspect of the present invention, the first source / drain electrode is formed on a portion of the insulating film located on the top surface of the gate electrode. In the field effect transistor according to the third aspect of the present invention, the first source / drain electrode is formed on a portion of the insulating film located on the second side surface of the gate electrode. More specifically, the first source / drain electrode is formed directly on the insulating film portion (so-called bottom contact type), or alternatively, the insulating film is interposed through the semiconductor material layer. (So-called top contact type).
[0044]
In the field effect transistor according to the first to third aspects of the present invention, the second source / drain electrode is formed on the portion of the substrate facing the first side surface of the gate electrode. More specifically, the second source / drain electrode is formed directly on the base (so-called bottom contact type), or is formed on the base via a semiconductor material layer. (So-called top contact type). In the field effect transistor according to the first aspect of the present invention, the third source / drain electrode is formed on the portion of the base that faces the second side surface of the gate electrode. Specifically, the third source / drain electrode is formed directly on the base (so-called bottom contact type), or is formed on the base via a semiconductor material layer (so-called “so-called bottom contact type”). Top contact type).
[0045]
In the field effect transistor according to the first to third aspects of the present invention, the first channel formation region or the extending portion of the channel formation region is on the first source / drain electrode, and It is formed on the second source / drain electrode, or is formed below the first source / drain electrode and below the second source / drain electrode. Further, in the field effect transistor according to the first aspect of the present invention, the extension portion of the second channel formation region is on the first source / drain electrode and the third source / drain electrode. Or formed under the first source / drain electrode and under the third source / drain electrode.
[0046]
In the field effect transistor according to the first aspect of the present invention, or alternatively, in the field effect transistor obtained by the method for manufacturing the field effect transistor according to the first aspect and the second aspect of the present invention. In this case, the first field effect transistor and the second field effect transistor can be operated (driven) by simultaneous control, or can be operated (driven) by different controls. You can also
[0047]
In the present invention, the gate length is substantially determined by the film thickness of the gate electrode, and the source / drain electrode and the gate electrode can be formed in a self-aligned manner. A short gate length can be obtained, the parasitic capacitance between the gate electrode and the source / drain electrode is not increased, and the photolithography process can be reduced.
[0048]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on embodiments of the invention (hereinafter abbreviated as embodiments) with reference to the drawings.
[0049]
(Embodiment 1)
The first embodiment relates to a field effect transistor according to the first aspect of the present invention and a method for manufacturing the field effect transistor according to the first aspect of the present invention. A schematic partial cross-sectional view of the field-effect transistor of the first embodiment is shown in FIG. 3, and a schematic plan view is shown in FIG. In FIG. 4, the first source / drain electrode, the second source / drain electrode, the third source / drain electrode, and the gate electrode are shown by hatching in order to clearly show the extended portions. Further, in the schematic partial sectional view of the field effect transistor, only one set of field effect transistors is shown for convenience, and there is a difference from the schematic plan view shown in FIG. is there.
[0050]
The field effect transistor of the first embodiment is
(A) It is formed on a substrate, has a top surface, a first side surface, and a second side surface, and has a substantially square cross-sectional shape (more specifically, a rectangle or a trapezoid whose upper side is longer than the bottom side). Gate electrode 12,
(B) an insulating film 13 formed on the top surface, the first side surface, and the second side surface of the gate electrode 12;
(C) a first source / drain electrode 14 formed on a portion of the insulating film 13 located on the top surface of the gate electrode 12;
(D) a second source / drain electrode 15 formed on the portion of the substrate facing the first side surface of the gate electrode 12;
(E) a third source / drain electrode 16 formed on the portion of the substrate facing the second side of the gate electrode 12, and
(F) a semiconductor material layer 17 formed from the second source / drain electrode 15 through the first source / drain electrode 14 to the third source / drain electrode 16;
It has.
[0051]
The first electrode comprises a gate electrode 12, a first source / drain electrode 14, and a semiconductor material layer 17 formed on the insulating film 13 located on the first side surface of the gate electrode 12. The channel formation region 18 and the second source / drain electrode 15 of the first field effect transistor FET ₁ A portion of the semiconductor material layer 17 formed on the gate electrode 12, the first source / drain electrode 14, and the portion of the insulating film 13 located on the second side surface of the gate electrode 12. The second field effect transistor FET is formed by the second channel forming region 19 and the third source / drain electrode 16. ₂ Is configured.
[0052]
The gate length in the field effect transistor of the first embodiment is generally defined by the thicknesses of the gate electrode 12 and the insulating film 13.
[0053]
In the field effect transistor according to the first embodiment, the base is a substrate 10 made of glass, and SiO formed on the surface of the substrate 10. ₂ It is comprised from the insulating layer 11 which consists of. The gate electrode 12 is made of aluminum (Al), and the insulating film 13 is made of aluminum oxide (Al ₂ O _Three ). Further, the first source / drain electrode 14, the second source / drain electrode 15, and the third source / drain electrode 16 are made of a Ti / Au laminated film. The semiconductor material layer 17 (the first channel formation region 18 and the second channel formation region 19) introduces polythiophene [see structural formula (5) in FIG. 11] or a side chain such as trimethylsilylethynyl. It consists of pentacene solubilized.
[0054]
As shown in FIG. 4, the field effect transistor according to the first embodiment includes eight gate electrodes, eight first source / drain electrodes 14, eight second source / drain electrodes 15, and eight gate electrodes. The source / drain electrode 16 is composed of a source / drain electrode 16, and is located between the first source / drain electrode 14 and the first source / drain electrode 14. 3 source / drain electrodes 16. In other words, except for the field effect transistors located at both ends, the third source / drain electrode 16 constituting the first field effect transistor and the second source / drain constituting the second field effect transistor. The electrode 16 is the same source / drain electrode. Then, by applying appropriate voltages to the first source / drain electrode connection portion 14A, the second source / drain electrode connection portion 15A, and the gate electrode extension portion 12B, the eight first field effect transistors FWT are applied. ₁ And eight second field effect transistor FETs ₂ Can be operated (driven) by simultaneous control. With the structure shown in FIG. 4, a very long gate width can be obtained with a small area, and a high transfer gain can be obtained in combination with a short gate length. One first field effect transistor FWT shown in FIG. ₁ And one second field effect transistor FET ₂ Can be configured to operate (drive) under different control.
[0055]
In the field effect transistor of the first embodiment, the first source / drain electrode 14 is formed directly on the portion of the insulating film 13 located on the top surface of the gate electrode 12. Further, the second source / drain electrode 15 and the third source / drain electrode 16 are directly formed on the base (more specifically, on the insulating layer 11). That is, each electrode 14, 15, 16 is a so-called bottom contact type.
[0056]
Hereinafter, with reference to FIGS. 1A to 1C, FIGS. 2A to 2C, and FIG. 3 which are schematic partial cross-sectional views of a substrate and the like, the field effect of the first embodiment will be described. A method for manufacturing a type transistor will be described.
[0057]
[Step-100]
For example, a 100 nm thick SiO film formed by sputtering ₂ A substrate 10 made of glass, for example, having an insulating layer 11 made of glass formed on the surface is prepared. Then, a gate electrode 12 having a top surface, a first side surface, and a second side surface and having a substantially square cross-sectional shape is formed on the substrate (more specifically, on the insulating layer 11).
[0058]
Specifically, a gate electrode forming layer 12A made of aluminum (Al) and having a thickness of 0.7 μm is formed on the insulating layer 11 by vacuum deposition, and then a gate electrode forming layer 12A on which a gate electrode is to be formed. A resist layer 20 is formed on this portion based on the photolithography technique (see FIG. 1A). Thereafter, the portion of the gate electrode forming layer 12A not covered with the resist layer 20 is etched based on a reactive ion etching method using a chlorine-based gas, and further, the portion of the gate electrode forming layer 12A is over-etched. Thus, the gate electrode 12 can be obtained (see FIG. 1B). Note that the etching profile of the gate electrode 12 is vertical or slightly reversely tapered [that is, the cross-sectional shape of the gate electrode 12 is substantially square (more specifically, a rectangle or a trapezoid whose upper side is longer than the bottom). It is preferable to select the formation conditions of the resist layer 20 and the etching conditions of the gate electrode formation layer 12A.
[0059]
[Step-110]
After that, the insulating film 13 is formed on the top surface, the first side surface, and the second side surface of the gate electrode 12 (see FIG. 1C). Specifically, by anodizing the gate electrode 12 made of aluminum or by exposing the gate electrode 12 made of aluminum to oxygen plasma, Al ₂ O _Three An insulating film 13 made of can be obtained.
[0060]
[Step-120]
Next, a first source / drain electrode 14 is formed on the portion of the insulating film 13 located on the top surface of the gate electrode 12 by a lift-off method, and the base body facing the first side surface of the gate electrode 12 is formed. A second source / drain electrode 15 is formed on this portion, and a third source / drain electrode 16 is formed on the portion of the substrate facing the second side surface of the gate electrode 12 together.
[0061]
Specifically, after the resist layer 21 is formed on the entire surface, an opening 22 is provided in the resist layer 21 based on a photolithography technique. In addition, it is preferable to select the formation conditions of the resist layer 21 so that the side wall of the opening 22 has a reverse taper. Further, the alignment of the opening 22 in the resist layer 21 may not be as precise as the left.
Next, a Ti / Au laminated film is formed on the entire surface including the inside of the opening 22 based on, for example, resistance heating vapor deposition (see FIG. 2A). Note that the thickness of the Ti film was 10 nm, and the thickness of the Au film was 100 nm. Here, the film forming conditions of the Ti / Au laminated film are that the Ti / Au laminated film is cut off at the side surface of the gate electrode 12, and the first source / drain electrode 14 and the second source / drain electrode 15 are completely formed. The first source / drain electrode 14 and the third source / drain electrode 16 are selected to be completely insulated.
[0062]
Then, the Ti / Au laminated film on the resist layer 21 is removed by removing the resist layer 21 using an organic solvent such as acetone. Thus, the first source / drain electrode 14 is formed directly on the portion of the insulating film 13 located on the top surface of the gate electrode 12, and the base body (more specifically, the first side surface of the gate electrode 12 is faced). The second source / drain electrode 15 is formed on the insulating layer 11), and at the same time, the portion of the base (more specifically, the insulating layer 11) facing the second side surface of the gate electrode. A third source / drain electrode 16 can be formed thereon (see FIG. 2B).
[0063]
[Step-130]
Next, a semiconductor material layer 17 is formed from the second source / drain electrode 15 through the first source / drain electrode 14 to the third source / drain electrode 16. Specifically, an organic semiconductor material dissolved in a solvent is applied to the entire surface based on, for example, a spin coating method, and then dried / heat treated to form the semiconductor material layer 17 on the entire surface ((C) in FIG. 2). reference). In this way, a first channel formation region 18 composed of a portion of the semiconductor material layer 17 formed on the portion of the insulating film 13 located on the first side surface of the gate electrode 12 can be obtained, and the gate electrode Thus, the second channel forming region 19 composed of the portion of the semiconductor material layer 17 formed on the portion of the insulating film 13 located on the second side surface of the twelve can be obtained.
[0064]
Thereafter, although not essential, a resist layer is formed on the semiconductor material layer 17 based on a photolithography technique, and a portion of the semiconductor material layer 17 not covered with the resist layer is formed, for example, by O ₂ It is preferable to perform a kind of element isolation by etching by exposure to plasma. Thus, a field effect transistor having the structure shown in FIG. 3 can be obtained.
[0065]
(Embodiment 2)
The second embodiment relates to a modification of the method for manufacturing the field effect transistor of the first embodiment. 5A to 5C are schematic partial cross-sectional views in which the vicinity of the top surface and the first side surface of the gate electrode 12 is enlarged for the method of manufacturing the field effect transistor of the second embodiment. Will be described with reference to FIG.
[0066]
[Step-200]
First, in the same manner as in [Step-100] to [Step-120] of the first embodiment, a gate electrode 12 having a top surface, a first side surface, and a second side surface and having a substantially square cross-sectional shape is a base. After forming the insulating film 13 on the top surface, the first side surface, and the second side surface of the gate electrode 12, the top surface of the gate electrode 12 is formed. A first source / drain electrode 14 is formed on the portion of the insulating film 13 located on the surface, and a second source / drain electrode 15 is formed on the portion of the substrate facing the first side surface of the gate electrode 12. In addition, a third source / drain electrode 16 is formed on the portion of the substrate facing the second side surface of the gate electrode 12.
[0067]
[Step-210]
Next, a semiconductor material layer made of an organic material and an inorganic material is formed from the second source / drain electrode 15 through the first source / drain electrode 14 to the third source / drain electrode 16. That is, a semiconductor material layer composed of fine particles (made of Au) and an organic semiconductor connected to each other in a three-dimensional network structure is formed.
[0068]
[Step-210A]
Specifically, first, the whole is immersed in a solution having a concentration of several percent in which (3-aminopropyl) trimethoxysilane (APTMS) is dissolved in methanol, and then the solution is washed with methanol to replace the solvent. Is evaporated to form a molecular solder layer (underlayer) 26 for fixing the Au fine particles 28 for one layer (see FIG. 5A). Mercaptosilane may be used instead of APTMS.
[0069]
[Step-210B]
Next, the substrate 10 on which the molecular solder layer 26 is formed is immersed for several minutes to several tens of minutes in a dispersion liquid (concentration of several millimoles) in which Au fine particles 28 corresponding to an inorganic material are dispersed in a solvent such as toluene or chloroform. Thereafter, the solvent is evaporated. As a result, the Au fine particles 28 are fixed to the surface of the molecular solder layer 26, and the first Au fine particle layer 28A made of the Au fine particles 28 is formed on the molecular solder layer 26 (see FIG. 5B). ). The molecular solder layer 26 has a functional group such as an amino group that can be chemically bonded to the Au fine particles 28, and only one Au fine particle 28 that is bonded to the functional group is present on the molecular solder layer 26. Fixed. Excess Au fine particles 28 not fixed to the molecular solder layer 26 are washed away.
[0070]
[Step-210C]
Subsequently, after immersing the substrate 10 in a solution having a concentration of several millimoles or less in which 4,4′-biphenyldithiol molecules corresponding to organic materials are dissolved in ethanol, the substrate is washed with ethanol to replace the solution, and then the solvent is evaporated. Let At this time, the 4,4′-biphenyldithiol molecule 29 is bonded to the surface of the Au fine particle 28 via the —SH group at the end of the molecule. A large number of 4,4′-biphenyldithiol molecules 29 are bonded to the surface of one Au fine particle 28 so as to wrap the Au fine particle 28. Since some of them also bind to other Au fine particles 28 using the -SH group at the other molecular end, the Au fine particles 28 are formed into a two-dimensional network by 4,4'-biphenyldithiol molecules 29. The first combined layer 27A is formed (see FIG. 5C). Since many unreacted —SH groups of the 4,4′-biphenyldithiol molecule 29 remain on the surface of the conjugate layer 27A, the surface of the conjugate layer 27A has a strong binding force to the Au fine particles 28. Have.
[0071]
[Step-210D]
Next, in the same manner as in [Step-210B], the substrate 10 is immersed for several minutes to several tens of minutes in a dispersion liquid in which the Au fine particles 28 are dispersed in a solvent such as toluene or chloroform, and then the solvent is evaporated. As a result, the Au fine particles are bonded and fixed to the surface of the first combined body layer 27A to form the second Au fine particle layer. Here, the Au fine particles of the second layer are connected to the Au fine particle layer 28A of the first layer by 4,4′-biphenyldithiol molecules, and are also connected to the Au fine particles of the same second layer. The connection of the fine particles is three-dimensional.
[0072]
[Step-210E]
Subsequently, in the same manner as in [Step-210C], after immersing the substrate 10 in a solution having a concentration of several millimoles or less in which 4,4′-biphenyldithiol molecules are dissolved in ethanol, the solution is replaced by washing with ethanol. Thereafter, the solvent is evaporated. As a result, a large number of 4,4′-biphenyldithiol molecules are bonded so as to enclose the Au fine particles, and a second conjugate layer in which the Au fine particles are connected by the 4,4′-biphenyldithiol molecules is formed. .
[0073]
Thereafter, by repeating [Step-210D] and [Step-210E], the semiconductor material layer 27 in which a three-dimensional network type conductive path is formed can be obtained. A semiconductor material layer 27 having a desired thickness can be formed by appropriately selecting the number of repetitions (MD Musick et al., Chem. Mater. (1997), 9, 1499; Chem. Mater. ( 2000), 12, 2869).
[0074]
Thereafter, although not essential, a resist layer is formed on the semiconductor material layer 27 based on the photolithography technique, and a portion of the semiconductor material layer 27 not covered with the resist layer is formed, for example, by O ₂ It is preferable to perform a kind of element isolation by etching by exposure to plasma.
[0075]
In addition, although each conjugate layer is formed of the same material, the material constituting the fine particles, the particle size of the fine particles, and the organic semiconductor molecules are changed for each conjugate layer or for each of the plurality of conjugate layers. The characteristics of the layer 27 may be controlled. Although the semiconductor material layer 27 is also formed on the source / drain electrodes, the first source / drain electrodes 14 and the first source / drain electrodes 15 sandwiched between the first source / drain electrodes 14 and 15 are formed. Insulating film 13 only on the portion of insulating film 13 on the side surface and on the second side surface of gate electrode 12 sandwiched between first source / drain electrode 14 and third source / drain electrode 16 The semiconductor material layer 27 may be formed only on this part.
[0076]
(Embodiment 3)
The third embodiment relates to a field effect transistor according to the first aspect of the present invention and a method for manufacturing the field effect transistor according to the second aspect of the present invention. FIG. 6C shows a schematic partial cross-sectional view of the field-effect transistor of the third embodiment.
[0077]
In the field effect transistor according to the third embodiment, the first source / drain electrode 14 is formed on the portion of the insulating film 13 located on the top surface of the gate electrode 12 via the semiconductor material layer 37. Has been. The second source / drain electrode 15 is formed on the substrate (more specifically, on the insulating layer 11) via the semiconductor material layer 37, and the third source / drain electrode 16 is The semiconductor material layer 37 is formed on the substrate (more specifically, on the insulating layer 11). That is, each electrode 14, 15, 16 is a so-called top contact type.
[0078]
Except for these points, the structure of the field effect transistor of the third embodiment can be substantially the same as the structure of the field effect transistor of the first embodiment, and thus detailed description thereof is omitted.
[0079]
Hereinafter, a method for manufacturing the field effect transistor according to the third embodiment will be described with reference to FIGS. 6A to 6C which are schematic partial cross-sectional views of a substrate and the like.
[0080]
[Step-300]
First, in the same manner as in [Step-100] in the first embodiment, a gate electrode 12 having a top surface, a first side surface, and a second side surface and having a substantially square cross section is formed on a substrate (more specifically, Is formed on the insulating layer 11). Next, the insulating film 13 is formed on the top surface, the first side surface, and the second side surface of the gate electrode 12 in the same manner as in [Step-110] in the first embodiment.
[0081]
[Step-310]
Next, a semiconductor material layer 37 is formed on the insulating film 13 located on at least the top surface, the first side surface, and the second side surface of the gate electrode 12. Specifically, the insulating layer 11 on which the semiconductor material layer 37 is to be formed and a resist layer (not shown) from which the insulating film 13 is exposed are formed based on a photolithography technique, and the substrate 10 is rotated by an oblique evaporation method. After vapor deposition of pentacene, the resist layer is removed. Thus, as shown in FIG. 6A, the first channel formation region comprising the portion of the semiconductor material layer 37 formed on the portion of the insulating film 13 located on the first side surface of the gate electrode 12. 18, and a second channel formation region 19 composed of a portion of the semiconductor material layer 37 formed on the portion of the insulating film 13 located on the second side surface of the gate electrode 12 is obtained. Can do. The formation conditions of the pentacene thin film are illustrated in Table 1 below. The semiconductor material layer 37 extends from the first channel formation region 18 on the insulating layer 11, and extends from the second channel formation region 19 onto the insulating layer 11.
[0082]
[Table 1]
[Conditions for film formation]
Substrate temperature: 0-200 ° C
Deposition rate: 0.01 nm / second to 1 nm / second
Pressure: 10 ^-Five Pa-10 ^-3 Pa
[Typical film formation conditions]
Substrate temperature: 60 ° C
Deposition rate: 0.05 nm / second
Pressure: 1 × 10 ^-Four Pa
[0083]
[Step-320]
Thereafter, the first source / drain electrode 14 is formed on the portion of the semiconductor material layer 17 located on the top surface of the gate electrode 12 by a lift-off method, and the substrate facing the first side surface of the gate electrode 12 is formed. (More specifically, the second source / drain electrode 15 is formed on the portion of the insulating layer 11, and at the same time, the substrate facing the second side surface of the gate electrode 12 (more specifically, A third source / drain electrode 16 is formed on the insulating layer 11).
[0084]
Specifically, after the resist layer 31 is formed on the entire surface, an opening 32 is provided in the resist layer 31 based on a photolithography technique. In addition, it is preferable to select the formation conditions of the resist layer 31 so that the side wall of the opening part 32 becomes reverse taper. Further, the alignment of the opening 32 in the resist layer 31 may not be as precise as the left. Next, a Ti / Au laminated film is formed on the entire surface including the inside of the opening 32 in the same manner as in [Step-120] of the first embodiment, for example, based on the resistance heating vapor deposition method (see FIG. 6B). ). Here, the Ti / Au laminated film is formed under the condition that the Ti / Au laminated film is cut off on both side surfaces of the gate electrode 12 so that the first source / drain electrode 14 and the second source / drain electrode 15 are separated. The first source / drain electrode 14 and the third source / drain electrode 16 are selected so as to be completely insulated.
[0085]
Thereafter, the Ti / Au laminated film on the resist layer 31 is removed by removing the resist layer 31 in the same manner as in [Step-120] of the first embodiment. Thus, the first source / drain electrode 14 is formed on the portion of the insulating film 13 located on the top surface of the gate electrode 12 via the semiconductor material layer 37 and faces the first side surface of the gate electrode 12. A second source / drain electrode 15 is formed on a portion of the base (more specifically, the insulating layer 11) via a semiconductor material layer 37, and the base (facing the second side surface of the gate electrode) More specifically, the third source / drain electrode 16 can be formed on the insulating layer 11) via the semiconductor material layer 37 (see FIG. 6C).
[0086]
In the third embodiment, the semiconductor material layer 37 can be formed by the same method as the semiconductor material layer 27 described in the second embodiment.
[0087]
(Embodiment 4)
The fourth embodiment relates to a field effect transistor according to the second aspect of the present invention and a method for manufacturing the field effect transistor according to the third aspect of the present invention. FIG. 7B shows a schematic partial cross-sectional view of the field-effect transistor of the fourth embodiment.
[0088]
The field effect transistor of Embodiment 4 is
(A) a gate electrode 12 formed on a substrate, having a top surface, a first side surface, and a second side surface, and having a substantially quadrangular (more specifically, for example, rectangular) cross-sectional shape;
(B) the insulating film 13 formed on the top surface of the gate electrode 12 and at least the first side surface (also on the second side surface in the fourth embodiment);
(C) a first source / drain electrode 14 formed on a portion of the insulating film 13 located on the top surface of the gate electrode 12;
(D) a second source / drain electrode 15 formed on the portion of the substrate facing the first side surface of the gate electrode 12, and
(E) a semiconductor material layer 47 formed from the first source / drain electrode 14 to the second source / drain electrode 15;
It has.
[0089]
A portion of the semiconductor material layer 47 formed on the portion of the insulating film 13 located on the first side surface of the gate electrode 12 corresponds to the channel formation region 48. That is, a channel formation comprising the gate electrode 12, the first source / drain electrode 14, and the semiconductor material layer 47 formed on the portion of the insulating film 13 located on the first side surface of the gate electrode 12. The region 48 and the second source / drain electrode 15 constitute a field effect transistor.
[0090]
The gate length in the field effect transistor of the fourth embodiment is generally defined by the thicknesses of the gate electrode 12 and the insulating film 13.
[0091]
In the field effect transistor according to the fourth embodiment, the base is a substrate 10 made of glass, and SiO formed on the surface of the substrate 10. ₂ It is comprised from the insulating layer 11 which consists of. The gate electrode 12 is made of aluminum (Al), and the insulating film 13 is made of aluminum oxide (Al ₂ O _Three ). Furthermore, the first source / drain electrode 14 and the second source / drain electrode 15 are made of a Ti / Au laminated film. Further, the semiconductor material layer 47 (channel forming region 48) is made of pentacene.
[0092]
In the field effect transistor according to the fourth embodiment, the first source / drain electrode 14 is formed directly on the insulating film 13 located on the top surface of the gate electrode 12. The second source / drain electrode 15 is directly formed on the base (more specifically, on the insulating layer 11). That is, each of the electrodes 14 and 15 is a so-called bottom contact type. Reference numeral 215 is an electrode formed at the same time as the electrodes 14 and 15 are formed, but has no function.
[0093]
Hereinafter, with reference to FIGS. 7A and 7B which are schematic partial cross-sectional views of a substrate and the like, a method for manufacturing the field effect transistor according to Embodiment 4 will be described.
[0094]
[Step-400]
First, in the same manner as in [Step-100] and [Step-110] of the first embodiment, a gate electrode 12 having a top surface, a first side surface, and a second side surface and having a substantially square cross-sectional shape is a base. (More specifically, after forming on the insulating layer 11), the insulating film 13 is formed on the top surface of the gate electrode 12 and on at least the first side surface (also on the second side surface in the fourth embodiment). Form.
[0095]
[Step-410]
Next, in the same manner as in [Step-120] of the first embodiment, the first source / drain electrode 14 is formed on the portion of the insulating film 13 located on the top surface of the gate electrode 12, and the gate electrode A second source / drain electrode 15 is formed on the portion of the substrate facing the first side surface of 12. At this time, the electrode 215 is also formed on the portion of the base that faces the second side surface of the gate electrode 12. In this way, the structure shown in FIG. 7A can be obtained. Here, the Ti / Au laminated film is formed under the condition that the Ti / Au laminated film is cut off on both side surfaces of the gate electrode 12 so that the first source / drain electrode 14 and the second source / drain electrode 15 are separated. Choose to be completely insulated.
[0096]
[Step-420]
Thereafter, a semiconductor material layer 47 is formed from the first source / drain electrode 14 to the second source / drain electrode 15. Specifically, in the same manner as in [Step-310] of the third embodiment, the insulating layer 11, the gate electrode 12, the first source / drain electrode 14, the second source / A resist layer (not shown) from which the drain electrode 15 and the like are exposed is formed based on a photolithography technique. Then, pentacene is deposited by an oblique deposition method from one direction, and then the resist layer is removed. The formation conditions of the pentacene thin film may be the same as illustrated in Table 1. In this way, as shown in FIG. 7B, a channel formation region 48 composed of a portion of the semiconductor material layer 47 formed on the portion of the insulating film 13 located on the first side surface of the gate electrode 12 is obtained. be able to. The semiconductor material layer 47 is not formed on the portion of the insulating film 13 located on the second side surface of the gate electrode 12.
[0097]
Thereafter, although not essential, a resist layer is formed on the semiconductor material layer 47 based on the photolithography technique, and a portion of the semiconductor material layer 47 not covered with the resist layer is formed, for example, by O ₂ It is preferable to perform a kind of element isolation by etching by exposure to plasma.
[0098]
In the fourth embodiment, it is not necessary to select the resist layer formation condition and the gate electrode formation layer etching condition so that the etching profile of the gate electrode 12 is vertical or slightly reversely tapered, and the cross-sectional shape of the gate electrode 12 is not necessary. It is sufficient that a certain aspect ratio is given to.
[0099]
In the fourth embodiment, the semiconductor material layer 47 can also be formed by the same method as the semiconductor material layer 27 described in the second embodiment.
[0100]
(Embodiment 5)
The fifth embodiment relates to a field effect transistor according to the second aspect of the present invention and a method for manufacturing the field effect transistor according to the fourth aspect of the present invention. FIG. 8B shows a schematic partial cross-sectional view of the field-effect transistor of the fifth embodiment.
[0101]
In the field effect transistor according to the fifth embodiment, the first source / drain electrode 14 is formed on the portion of the insulating film 13 located on the top surface of the gate electrode 12 through the semiconductor material layer 57. Has been. The second source / drain electrode 15 is formed on the base (more specifically, on the insulating layer 11) via the semiconductor material layer 57. That is, each of the electrodes 14 and 15 is a so-called top contact type.
[0102]
Except for these points, the structure of the field effect transistor of the fifth embodiment can be substantially the same as the structure of the field effect transistor of the fourth embodiment, and thus detailed description thereof is omitted.
[0103]
Hereinafter, a method for manufacturing the field effect transistor according to the fifth embodiment will be described with reference to FIGS. 8A and 8B which are schematic partial sectional views of a substrate and the like.
[0104]
[Step-500]
First, in the same manner as [Step-100] and [Step-110] of the first embodiment, a gate electrode 12 having a top surface, a first side surface, and a second side surface and having a substantially square cross-sectional shape is a base. (More specifically, after forming on the insulating layer 11), the insulating film 13 is formed on the top surface of the gate electrode 12 and at least the first side surface (also on the second side surface in the fifth embodiment). Form.
[0105]
[Step-510]
Thereafter, a semiconductor material layer 57 is formed on the insulating film 13 located on at least the top surface and the first side surface of the gate electrode 12. Specifically, in the same manner as in [Step-310] of Embodiment 3, the insulating layer 11 on which the semiconductor material layer 57 is to be formed and the resist layer (not shown) from which the insulating film 13 is exposed are applied to the photolithography technique. Form based on. Then, pentacene is deposited by an oblique deposition method from one direction, and then the resist layer is removed. The formation conditions of the pentacene thin film may be the same as illustrated in Table 1. In this way, as shown in FIG. 8A, a channel formation region 58 is obtained which is composed of a portion of the semiconductor material layer 57 formed on the portion of the insulating film 13 located on the first side surface of the gate electrode 12. be able to. Note that the semiconductor material layer 57 is not formed on the portion of the insulating film 13 located on the second side surface of the gate electrode 12. The semiconductor material layer 57 extends from the channel formation region 58 on the insulating layer 11.
[0106]
[Step-520]
Next, the first source / drain electrode 14 is formed on the portion of the semiconductor material layer 57 located on the top surface of the gate electrode 12, and the substrate (specifically, the first side surface of the gate electrode 12 is faced). The second source / drain electrode 15 is formed on the insulating layer 11) (see FIG. 8B). Specifically, the same step as [Step-320] in the third embodiment is performed.
[0107]
In the fifth embodiment, the semiconductor material layer 57 can also be formed by the same method as the semiconductor material layer 27 described in the second embodiment.
[0108]
(Embodiment 6)
The sixth embodiment relates to a field effect transistor according to the third aspect of the present invention and a method for manufacturing the field effect transistor according to the fifth aspect of the present invention. A schematic partial cross-sectional view of the field-effect transistor of the sixth embodiment is shown in FIG.
[0109]
The field effect transistor of the sixth embodiment is
(A) a gate electrode 62 formed on a substrate, having a first side surface and a second side surface, and having a triangular cross-sectional shape;
(B) an insulating film 63 formed on the first side surface and the second side surface of the gate electrode 62;
(C) a first source / drain electrode 64 formed on a portion of the insulating film 63 located on the second side surface of the gate electrode 62;
(D) a second source / drain electrode 65 formed on the portion of the substrate facing the first side surface of the gate electrode 62, and
(E) a semiconductor material layer 67 formed from the first source / drain electrode 64 to the second source / drain electrode 65;
It has.
[0110]
A portion of the semiconductor material layer 67 formed on the portion of the insulating film 63 located on the first side surface of the gate electrode 62 corresponds to the channel formation region 68. That is, a channel is formed of the gate electrode 62, the first source / drain electrode 64, and the semiconductor material layer 67 portion formed on the insulating film 63 portion located on the first side surface of the gate electrode 62. The region 68 and the second source / drain electrode 65 constitute a field effect transistor.
[0111]
The gate length in the field effect transistor of the sixth embodiment is generally defined by the length of the slope of the first side surface of the gate electrode.
[0112]
In the field effect transistor of the sixth embodiment, the substrate is made of glass substrate 10 and SiO formed on the surface of substrate 10. ₂ It is comprised from the insulating layer 11 which consists of. The gate electrode 62 is made of aluminum (Al), and the insulating film 63 is made of aluminum oxide (Al ₂ O _Three ). Furthermore, the first source / drain electrode 64 and the second source / drain electrode 65 are made of a Ti / Au laminated film. Furthermore, the semiconductor material layer 67 (channel formation region 68) is made of polythiophene [see structural formula (5) in FIG. 11] or pentacene solubilized by introducing a side chain, as in the first embodiment. Become.
[0113]
In the field effect transistor of the sixth embodiment, the first source / drain electrode 64 is formed directly on the insulating film 63 located on the top surface of the gate electrode 62. The second source / drain electrode 65 is formed directly on the base (more specifically, on the insulating layer 11). That is, each of the electrodes 64 and 65 is a so-called bottom contact type.
[0114]
Hereinafter, a method for manufacturing the field effect transistor according to the sixth embodiment will be described with reference to FIGS. 9A to 9D which are schematic partial sectional views of a substrate and the like.
[0115]
[Step-600]
For example, a 100 nm thick SiO film formed by sputtering ₂ A substrate 10 made of glass, for example, having an insulating layer 11 made of glass formed on the surface is prepared. Then, a gate electrode 62 having a first side surface and a second side surface and having a triangular sectional shape is formed on the substrate (more specifically, on the insulating layer 11).
[0116]
Specifically, after forming a 0.7 μm-thick gate electrode formation layer on the insulating layer 11 by vacuum evaporation, the gate electrode formation layer portion on which the gate electrode is to be formed is made of aluminum (Al). A resist layer is formed on the substrate based on a photolithography technique. Although the cross-sectional shape of the resist layer is triangular, the resist layer having such a cross-sectional shape can be formed by a known method. Thereafter, the resist layer and the gate electrode formation layer are etched back, and the gate electrode formation layer is overetched, whereby the gate electrode 12 can be obtained (see FIG. 9A).
[0117]
[Step-610]
After that, an insulating film 63 is formed on the first side surface and the second side surface of the gate electrode 62 (see FIG. 9C). Specifically, by anodizing the gate electrode 62 made of aluminum, or by exposing the gate electrode 62 made of aluminum to oxygen plasma, Al ₂ O _Three An insulating film 63 made of can be obtained.
[0118]
[Step-620]
Next, a first source / drain electrode 64 is formed on the portion of the insulating film 63 located on the second side surface of the gate electrode 62 by a lift-off method, and the surface is formed on the first side surface of the gate electrode 62. A second source / drain electrode 65 is formed on the portion of the substrate (specifically, the insulating layer 11) to be formed.
[0119]
Specifically, after a resist layer is formed on the entire surface in the same manner as [Step-320] in Embodiment 3, an opening is provided in the resist layer based on a photolithography technique. Next, a Ti / Au laminated film is formed on the entire surface including the inside of the opening based on, for example, resistance heating oblique vapor deposition from one direction. Here, the Ti / Au laminated film is formed under the condition that the Ti / Au laminated film is cut off at the first side surface of the gate electrode 62, and the first source / drain electrode 64 and the second source / drain electrode 65 are formed. Choose to be completely insulated. Thereafter, the Ti / Au laminated film on the resist layer is removed by removing the resist layer in the same manner as in [Step-120] of the first embodiment. In this way, the first source / drain electrode 64 is formed directly on the portion of the insulating film 63 located on the second side surface of the gate electrode 62, and the base (specifically, the first side surface of the gate electrode 62 is specified). Specifically, the second source / drain electrode 65 can be formed directly on the insulating layer 11) (see FIG. 9C).
[0120]
[Step-630]
Thereafter, a semiconductor material layer 67 is formed from the first source / drain electrode 64 to the second source / drain electrode 65. Specifically, an organic semiconductor material dissolved in a solvent is applied over the entire surface based on, for example, a spin coating method, and then dried / heat treated to form the semiconductor material layer 67 over the entire surface. In this manner, a channel formation region 68 composed of a portion of the semiconductor material layer 67 formed on the portion of the insulating film 63 located on the first side surface of the gate electrode 62 can be obtained.
[0121]
Thereafter, although not essential, a resist layer is formed on the semiconductor material layer 67 based on a photolithography technique, and a portion of the semiconductor material layer 67 that is not covered with the resist layer is, for example, O ₂ It is preferable to perform a kind of element isolation by etching by exposure to plasma. Thus, a field effect transistor having the structure shown in FIG. 9D can be obtained.
[0122]
In the sixth embodiment, the semiconductor material layer 67 can also be formed by the same method as the semiconductor material layer 27 described in the second embodiment.
[0123]
(Embodiment 7)
The seventh embodiment relates to a field effect transistor according to the third aspect of the present invention and a method for manufacturing the field effect transistor according to the sixth aspect of the present invention. FIG. 10B shows a schematic partial cross-sectional view of the field effect transistor according to the seventh embodiment.
[0124]
In the field effect transistor according to the seventh embodiment, the first source / drain electrode 64 is formed on the insulating film 63 located on the top surface of the gate electrode 62 with the semiconductor material layer 77 interposed therebetween. Has been. The second source / drain electrode 65 is formed on the base (more specifically, on the insulating layer 11) via the semiconductor material layer 77. That is, each of the electrodes 64 and 65 is a so-called top contact type.
[0125]
Except for these points, the structure of the field effect transistor of the seventh embodiment can be substantially the same as the structure of the field effect transistor of the sixth embodiment, and thus detailed description thereof is omitted.
[0126]
Hereinafter, a method for manufacturing the field effect transistor according to the seventh embodiment will be described with reference to FIGS. 10A and 10B which are schematic partial cross-sectional views of a substrate and the like.
[0127]
[Step-700]
First, in the same manner as in [Step-600] and [Step-610] of the sixth embodiment, the gate electrode 62 having the first side surface and the second side surface and having a triangular cross section is formed on the substrate (specifically, Is formed on the insulating layer 11), and then an insulating film 63 is formed on the first side surface and the second side surface of the gate electrode 62.
[0128]
[Step-710]
Next, a semiconductor material layer is formed on the insulating film 63 located on at least the top surface and the first side surface of the gate electrode 62. Specifically, a resist layer (not shown) from which the insulating layer 11 to be formed with the semiconductor material layer 77 is exposed is formed based on a photolithography technique, and pentacene is deposited by oblique deposition from one direction. The resist layer is removed. The formation conditions of the pentacene thin film may be the same as illustrated in Table 1. Thus, as shown in FIG. 10A, a channel formation region 78 composed of a portion of the semiconductor material layer 77 formed on the portion of the insulating film 63 located on the first side surface of the gate electrode 62 is obtained. be able to. The semiconductor material layer 77 extends from the channel formation region 78 over the insulating layer 11. Further, the semiconductor material layer 77 is formed not only on the portion of the substrate facing the first side surface of the gate electrode 62 but also on the portion of the substrate facing the second side surface of the gate electrode 62. This semiconductor material layer portion is indicated by reference numeral 77A in FIG.
[0129]
[Step-720]
Thereafter, a first source / drain electrode 74 is formed on the portion of the insulating film 63 located on the second side surface of the gate electrode 62, and on the portion of the substrate facing the first side surface of the gate electrode 62. Then, a second source / drain electrode 75 is formed (see FIG. 10B). Specifically, a step similar to [Step-620] in Embodiment 6 may be performed.
[0130]
In the seventh embodiment, the semiconductor material layer 77 can also be formed by the same method as the semiconductor material layer 27 described in the second embodiment.
[0131]
As mentioned above, although this invention was demonstrated based on embodiment of this invention, this invention is not limited to these. The structure and manufacturing conditions of the field effect transistor are illustrative and can be changed as appropriate.
[0132]
When the field effect transistor of the present invention is applied to and used in a display device or various electronic devices, it may be a monolithic integrated circuit in which a large number of field effect transistors are integrated on a substrate, or each field effect transistor may be cut. May be used individually as discrete parts.
[0133]
【The invention's effect】
In the present invention, the gate length is determined by the film thickness of the gate electrode, and the source / drain electrode and the gate electrode can be formed in a self-aligned manner. In addition, it is not necessary to perform highly accurate alignment (mask alignment), and the parasitic capacitance between the gate electrode and the source / drain electrode is not increased. Further, the number of photolithography processes can be reduced, and an increase in manufacturing cost of the field effect transistor due to the introduction of an expensive manufacturing apparatus can be avoided. In the present invention, a conductive layer made of electrons or holes is induced in the semiconductor material layer (channel formation region) near the interface between the insulating film on the side surface of the gate electrode and the semiconductor material layer by the voltage applied to the gate electrode. A channel region is formed. Since the length of the channel region is mainly determined by the thickness of the gate electrode, a gate length of 1 μm or less can be easily achieved.
[Brief description of the drawings]
FIGS. 1A to 1C are schematic partial cross-sectional views of a substrate and the like for explaining a method of manufacturing a field effect transistor according to a first embodiment of the invention.
FIGS. 2A to 2C are schematic views of a substrate and the like for explaining the method of manufacturing the field effect transistor according to the first embodiment of the invention, following FIG. FIG.
3 is a schematic partial cross-sectional view of a substrate and the like for explaining the method for manufacturing the field effect transistor according to the first embodiment of the invention, following FIG. 2C. FIG.
FIG. 4 is a schematic plan view of the field-effect transistor according to the first embodiment of the invention.
5A to 5C are schematic partial cross-sectional views of a substrate and the like for explaining the method for manufacturing a field effect transistor according to the second embodiment of the invention.
6A to 6C are schematic partial cross-sectional views of a substrate and the like for explaining a method for manufacturing a field effect transistor according to Embodiment 3 of the invention.
7A to 7B are schematic partial cross-sectional views of a substrate and the like for explaining a method for manufacturing a field effect transistor according to Embodiment 4 of the present invention.
8A to 8B are schematic partial cross-sectional views of a substrate and the like for explaining the method for manufacturing a field effect transistor according to the fifth embodiment of the invention.
9A to 9D are schematic partial cross-sectional views of a substrate and the like for explaining the method for manufacturing a field effect transistor according to the sixth embodiment of the invention.
FIGS. 10A to 10B are schematic partial cross-sectional views of a substrate and the like for describing a method for manufacturing a field effect transistor according to a seventh embodiment of the present invention.
FIG. 11 illustrates a structural formula of a polymeric material suitable for use in the present invention.
FIG. 12 illustrates a structural formula of a polymeric material suitable for use in the present invention.
FIG. 13 illustrates a structural formula of a polymeric material suitable for use in the present invention.
14A to 14C are schematic partial cross-sectional views of a substrate and the like for explaining a conventional method of manufacturing a field effect transistor using an organic semiconductor material.
15A to 15C are schematic views of a substrate and the like for explaining a method of manufacturing a field effect transistor using a conventional organic semiconductor material, following FIG. 14C. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Substrate, 11 ... Insulating layer, 12, 62 ... Gate electrode, 12A ... Gate electrode forming layer, 12B ... Gate electrode extension part, 13, 63 ... Insulating film, 14, 64, 74 ... 1st source / drain electrode, 14A ... 1st source / drain electrode connection part, 15, 65, 75 ... 2nd source / drain electrode, 15A ... 2nd source / drain electrode connection part, 16 ... 3rd source / drain electrode, 17, 27, 37, 47, 57, 67, 77 ... Semiconductor material layer, 18 ... 1st channel Formation region, 19 ... second channel formation region, 48, 58, 68, 78 ... channel formation region, 20, 20, 31 ... resist layer, 21 ... resist layer, 22, 32 ..Openings, 26 ... molecular solder layer (underlayer), 2 ... Au fine particles, 27A ... first layer binding layer, 28A ... Au fine particle layer, 29 ... 4,4'-biphenyl dithiol molecules, FET ₁ ... First field effect transistor, FET ₂ ... Second field effect transistor

Claims (7)

(A) a gate electrode formed on a substrate, having a first side surface and a second side surface, and having a triangular cross-sectional shape;
(B) an insulating film formed on the first side surface and the second side surface of the gate electrode;
(C) a first source / drain electrode formed on a portion of the insulating film located on the second side surface of the gate electrode;
(D) a second source / drain electrode formed on the portion of the substrate facing the first side of the gate electrode; and
(E) a semiconductor material layer formed from the first source / drain electrode to the second source / drain electrode;
Comprising
A field effect transistor, wherein a portion of a semiconductor material layer formed on a portion of an insulating film located on a first side surface of a gate electrode corresponds to a channel formation region. The field effect transistor according to claim 1 , wherein the semiconductor material layer is made of an organic material. The field effect transistor according to claim 1 , wherein the semiconductor material layer is made of an organic material and an inorganic material. (A) forming a gate electrode having a first side surface and a second side surface and having a triangular cross-sectional shape on a substrate;
(B) forming an insulating film on the first side surface and the second side surface of the gate electrode;
(C) forming a first source / drain electrode on the portion of the insulating film located on the second side surface of the gate electrode, and forming a second source on the portion of the substrate facing the first side surface of the gate electrode; Forming a source / drain electrode of
(D) A semiconductor material layer is formed from the first source / drain electrode to the second source / drain electrode, and thus formed on the portion of the insulating film located on the first side surface of the gate electrode. Obtaining a channel forming region comprising a portion of the semiconductor material layer,
A method of manufacturing a field effect transistor. (A) forming a gate electrode having a first side surface and a second side surface and having a triangular cross-sectional shape on a substrate;
(B) forming an insulating film on the first side surface and the second side surface of the gate electrode;
(C) forming a semiconductor material layer on at least the top surface of the gate electrode and the insulating film located on the first side surface, and thus on the insulating film portion positioned on the first side surface of the gate electrode; Obtaining a channel formation region comprising a portion of the semiconductor material layer formed in
(D) forming a first source / drain electrode on the portion of the insulating film located on the second side surface of the gate electrode, and forming a second source on the portion of the substrate facing the first side surface of the gate electrode; Forming a source / drain electrode of
A method of manufacturing a field effect transistor. 6. The method of manufacturing a field effect transistor according to claim 4, wherein the semiconductor material layer is made of an organic material. 6. The method of manufacturing a field effect transistor according to claim 4 , wherein the semiconductor material layer is made of an organic material and an inorganic material.

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