JP2002198539A - Thin-film field-effect transistor structure using organic/ inorganic hybrid semiconductor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor(TFT) device structure that shows high field effect mobility and high current modulation at a lower operating voltage than an organic/inorganic hybrid TFT device with the newest technique, and is based on an organic/inorganic hybrid semiconductor material. SOLUTION: This structure includes a set of conductive gate electrodes covered with a high-permittivity insulator, the layer of the organic/inorganic hybrid semiconductor, a set of electric conductive source electrode corresponding to each gate line and electric conductive drain electrode, and a passivation layer that is optionally selected and covers the device structure for protection. By high-permittivity gate insulator, gate voltage dependency in the organic/ inorganic hybrid semiconductor is utilized, thus achieving the field-effect mobility at a high level in the extremely low operation voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to the field of organic-inorganic hybrid materials as semiconducting channels in thin film field effect transistors (TFTs), and more particularly to the field of flat-type hybrid materials.
It relates to the low voltage operation of such transistors using high dielectric gate insulators in applications such as panel displays.

[0002]

[Related Application] This application is based on "Thin-Film Field-Effect
Transistor With Organic Semiconductor Requir
ing Low Operating Voltages (a thin film field effect transistor using an organic semiconductor having a low required operating voltage), which is a continuation of a part of pending US application Ser. No. 09 / 323,804, filed on Jun. 2, 1999. Application.
This U.S. application Ser. No. 09 / 323,804 is disclosed in U.S. application Ser. No. 08 / 827,01, filed Mar. 25, 1997.
No. 8, No. 5,981,970, issued Nov. 9, 1999, the teachings of which are incorporated herein by reference. In addition, this application filed a `` Product And Process For Forming A Semic
Partial continuation of pending US application Ser. No. 09 / 259,128 filed Feb. 26, 1999 entitled "Onductor Structure On A Host Substrate". No. 6,210,47 filed on Apr. 3, 2001.
No. 9 and corresponding Japanese patent application 2000
No. 47152, the teachings of which are incorporated herein by reference.

[0003]

BACKGROUND OF THE INVENTION Liquid crystal displays (LCDs) and other flat displays
・ Thin film field effect transistors used for panel applications
(TFT) is generally an amorphous silicon semiconductor.
Using silicon (aSi: H) or polycrystalline silicon,
Silicon dioxide and / or nitride as gate insulator
Use silicon. Recent development of materials is based on thin film field effect
Amorphous silicon as transistor semiconductor
Low cost and / or low temperature alternatives
As a substitute, such as hexathiophene and its derivatives
Organic oligomers and organic molecules such as pentacene
Exploration (G. Horowitz, D. Fichou, X. Penn)
g, Z. Xu, F. Garnier, Solid State Commun. Volu
me72, pg. 381, 1989; US Patent No. 5,347, 1
No. 44). SiO_TwoTo pentacene with gate insulator
1cm with TFT based^TwoV^-1sec ^-1Electric field in the range
Effective mobility is realized (Y.Y.Lin, D.J.Gundlach, S.
F. Nelson, T.N. Jackson, IEEE Electron Device Let
t. Vol.18 pp. 606-608 1997).
It is a potential candidate. Based on this pentacene
The major drawback of the organic TFTs that have been
Sometimes high operating voltages are needed to produce high current modulation
(0.4 μm thick SiO_TwoGate insulator
When used, generally about 100 V). Gate insulator
When the thickness of is reduced, the above characteristics are improved.
Insulation thickness reduction is associated with manufacturing difficulties and reliability issues
There are limits imposed by For example, the current generation TFTLC
In device D, the thickness of the TFT gate insulator is generally
0.3 to 0.4 μm. Recently, high dielectric constant (ε)
Pentacene device with heat insulator, equivalent thickness
Sano SiO_TwoLower than pentacene TFTs using
Pressure has been shown to achieve high mobility (US Patent
Nos. 5,981,970 and 5,946,551,
C.D.Dimitrakopoulos, S.Purushothaman, J.Kymissi
s, A. Callegari, J.M.Shaw, Science, 283, 822-8
24 (1999); C.D.Dimitrakopoulos, J.Kymissis, S.Pur
ushothaman, D.A.Neumayer, P.R.Duncombe, R.B.Lai
bowitz Advanced Materials, Vol. 11, 1372-137
5, (1999)).

Recently, a new type of TFT has been identified. That is, an organic-inorganic hybrid material such as organic-inorganic perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI ₄ is provided as a semiconductor. This type of organic-inorganic hybrid material is called “molecular-scale composite material (molecular s).
cale composites) "(K. Chon
drousdis, CDDimitrakopoulos, CRKagan, I.Kym
issis, DBMitiz, `` Thin Film Field Effect Tra
nsistors With Organic-Inorganic HybridMaterials
As Semiconducting Channels, US Patent Application No. 0
U.S. Pat. No. 6,180,956, based on Ser. No. 9 / 261,515 (filed Mar. 3, 1999) and corresponding Japanese Patent Application No. 200050047; "Organic-Inorganic Hy
bridMaterials as Semiconducting Channels in T
hin-Film Field-EffectTransistors '', CRKagan,
DBMitiz, CDDimitrakopoulos, Science Vol. 2
86, 945-947, (1999)). These transistors have problems similar to those described above for pentacene.
That is, in order to realize high mobility and simultaneously generate high current modulation, a high operating voltage is required (0.5 μm
Typically, when a SiO ₂ insulating film having a thickness of about 60 V is used, about 60 V). As the thickness of the gate insulator is reduced, the operating voltage required to achieve the above characteristics is reduced. Again, especially in large area applications such as flat panel displays where the gate insulator is deposited on the surface of the gate electrode rather than being thermally grown on a Si single crystal, the insulating The reduction in body thickness has limitations imposed by manufacturing constraints and reliability issues. The use of high-k gate insulators to achieve high mobility at low voltages, as shown for organic TFTs, is not an obvious solution. The reason is that such an insulator is not considered to affect the mobility measured from a crystalline inorganic semiconductor whose mobility is considered to be a constant parameter.
Organic-inorganic perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI
_{In 4} , conduction occurs in the inorganic component and the organic component is insulating (DBMitzi, CAFeild, WTA Harrison,
AMGuloy, Nature, Vol. 369, 467-469 (1994);
U.S. Patent No. 6,180,956, supra. This means (C
Is true with respect _{6 H 5 C 2 H 4 NH} 3) 2 SnI 4. However, the organic part consists of conjugated organic molecules, for example oligothiophene containing molecules, the inorganic part is insulating,
Other hybrid materials can be designed to be used to template the composition of the conjugated organic molecule to increase the conductivity and / or mobility of the hybrid material.

[0005] Organic / inorganic hybrid perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI ₄ is used as a semiconductor, a heavily doped Si wafer is used as a gate electrode, and 500 nm thermally grown SiO ₂ is used as a gate insulator. And the electrical properties of a TFT having Pd source and drain electrodes as previously shown (US Pat. No. 6,18,18).
No. 0,956; “Organic-Inorganic Hybrid Materia
ls as SemiconductingChannels in Thin-Film Fie
ld-Effect Transistors '', CRKagan, DBMitzi,
CDDimitrakopoulos, Science Vol. 286, 945-9
47, (1999)), which can be properly modeled using the standard field-effect transistor equation (SMSze "Physic
s of Semiconductor Devices '', Wiley, New yor
k, 1981, pg. 442). Organic-inorganic hybrid perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ used in these devices
SnI ₄ behaves as a p-type semiconductor. "Organic-Ino
rganicHybrid Materials as Semiconducting Chann
els in Thin-Film Field-Effect Transistors,
CRKagan, DBMitzi, CDDimitrakopoulos, Scie
nce Vol. 286, 945-947, of Figure 1, which is taken from (1999) is a discrete voltage applied to the gate (V _G), the current flowing between the source electrode and the drain electrode (I _D) The dependence on the voltage (V _D ) applied to the drain electrode is shown. When the gate electrode is negatively biased with respect to the grounded source electrode, (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI ₄
Operate in the accumulation mode, and the accumulation carriers are holes. At low V _D , I _D increases linearly with V _D (linear region) and is approximately given by:

(Equation 1) Here, L is the channel length, W is the channel width, the C _i the capacitance per unit area of the insulating layer, V _T is the threshold voltage, furthermore, mu is a field-effect mobility. By plotting the I _D vs. V _G at constant small V _D, the value of the slope of this plot by equal to g _m, the μ from transconductance of the formula can be calculated in the linear region.

(Equation 2)

When the source electrode is grounded (ie, V _S =
0), the drain electrode when the negative bias than the gate electrode (i.e., -V _D ≧ -V _G), a current flowing between the source electrode and the drain electrode (I _D) is a pinch-off in the accumulation layer (Saturated no more)
(Saturation region) can be modeled by the following equation.

(Equation 3) Figure 2 (left vertical axis) shows the saturation, the V _G dependence of I _D with a semi-logarithmic scale (CRKagan, DBMitzi, CDDi
mitrakopoulos, Science Vol. 286, 945-947, (1
999)). The field effect mobility is

(Equation 4) It can be calculated from the slope of the pair V _G plot. FIG.
(Right vertical axis) shows a plot of the square root versus V _G of I _D.
From this plot, a mobility of 0.55 cm ² V ⁻¹ sec ⁻¹ is calculated.

[0007]

SUMMARY OF THE INVENTION The present invention overcomes the need to use high operating voltages without having to reduce the thickness of the insulator and provides a desirable combination of high field effect mobility and high current modulation. Clarify the TFT structure that realizes the above. Such a structure is based on an organic-inorganic hybrid material (eg, organic-inorganic perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ ) as a semiconductor.
An inorganic high dielectric constant gate insulator layer (eg, barium zirconate titanate) in combination with SnI ₄ ).

The present invention provides a method for fabricating an organic-inorganic hybrid TFT structure. In this method, a glass substrate (40
0 ° C or lower), plastic substrates in general (400 ° C or lower),
A high dielectric constant gate insulator is deposited and processed at a temperature compatible with transparent plastic substrates (150 ° C. or less). This temperature is substantially lower than the processing temperatures (up to 650 ° C.) when these materials are used in memory applications.
An advantage of the present invention is a method of fabricating an organic-inorganic hybrid TFT structure in which a high-k gate insulator and all other materials are deposited and processed at a temperature below 100 ° C.

[0009]

SUMMARY OF THE INVENTION A broad aspect of the claimed invention is directed to a substrate having an electrically conductive gate electrode disposed thereon, a gate insulator layer disposed on the gate electrode, and a gate insulator high layer. A transistor comprising an electrically conductive source electrode and an electrically conductive drain electrode disposed thereon, and a layer of an organic-inorganic hybrid semiconductor disposed on the gate insulator and the source electrode and the drain electrode. Device structure.

Another aspect of the present invention is a source electrode, a drain electrode, a gate electrode, a gate insulator, and disposed between and in electrical contact with the source electrode and the gate electrode. Comprising a semiconductor material,
A transistor device structure wherein the gate insulator is disposed between the gate electrode and the active region, and the semiconductor material is an organic-inorganic hybrid material.

[0011]

DETAILED DESCRIPTION OF THE INVENTION The proposed TFT structure comprises a high dielectric constant thin film gate insulator and an organic-inorganic perovskite (C ₆
And organic-inorganic hybrid semiconductor such as _{H 5 C 2 H 4 NH 3} ) 2 SnI 4, gates, metal as an electrode of a source, and a drain, a conductive polymer, and the high concentration-doped high conductivity material, or a combination thereof Use

The above structure is used as a gate insulator layer.
There are many candidate materials with high dielectric constants that can be
You. The candidate materials include Ta_TwoO_Five, Y_TwoO_Three, TiO_Two,
Al_TwoO _Three, Si_ThreeN_Four, And PbZr_XTi_1-XO
_Three(PZT), Bi_FourTi_ThreeO₁₂, BaMgF_Four, Zircon
Barium titanate (BZT) and Ba_XSr_1-XTi
O_Three(BST), including but not limited to
Family of analogs, including but not limited to
No. In the past, these materials were mainly used for memory devices
Researched and used in combination with inorganic semiconductors
(P.Balk, Advanced Materials, Volume 7, pg.
703, 1995 and references therein) and organic
Researched and used in combination with semiconductors (US
Nos. 5,981,970 and 5,946,551
No.), with organic-inorganic hybrid semiconductors for electronic device applications
It has never been studied and used in combination. Generally this
These insulators have a dielectric constant exceeding 150 for inorganic semiconductors.
Annealed above 600 ° C to achieve the rate (ε)
It is. In the case of an organic semiconductor, the processing temperature is generally 400 ° C.
Kept below. High dielectric constant (ε) gate insulator
Very high dielectric constant embedded in polymer matrix
May be a composite material composed of inorganic particles
(S.Liang, S.R.Chong. E.P.Giannelis, "Electron
ic Components and Technology Conference '', IEE
E, 1998, pp. 171-175). This type of dielectric is
In the fine text, it is called a composite dielectric.

In general, the proposed structure is a TFT structure, an inorganic high dielectric constant gate in combination with a semiconductor organic-inorganic hybrid material (eg, organic-inorganic perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI ₄ ). Use insulator. High ε insulator
Deposited in vacuum, by sputtering, or by any other method, including but not limited to electron beam evaporation, laser ablation, molecular beam evaporation, chemical vapor deposition, or about 4
A 00 ° C. anneal step is applied in a subsequent solution process or by anodization. In all of these ways,
The processing temperature must be kept below 400 ° C. in order to be able to use glass substrates or high temperature resistant plastics such as, for example, polyimide. Some of these methods can be used at processing temperatures below 100 ° C. that are compatible with transparent plastic substrates such as polycarbonate.

The term for high ε with a dielectric constant ε> 3.9 is S
It means the dielectric constant of iO ₂ . Therefore, in this application, a high dielectric constant gate insulator is defined as an insulator having a dielectric constant ε> 3.9. BZ treated and sputtered at room temperature
T is usually a dielectric constant ε ≒ 17. The high dielectric constant ε> 3.9 organic insulator, which also satisfies other requirements such as environmental stability, high breakdown voltage, excellent film-forming ability, and no mobile charge, is the same as the inorganic insulator described above. Instead, it could be used for the proposed structure. Barium titanate / epoxy composite dielectric material (S. Liang, SRChong. EPGianneli
s, `` ElectronicComponents and Technology Confe
rence ", IEEE, 1998, pp. 171-175) may also be used as the gate insulator in the proposed structure.

The general sequence used to fabricate the proposed TFT structure includes the following steps. That is, either the substrate itself, in which case heavily doped Si, or a patterned metal (or conductive polymer, or other conductive material) gate electrode deposited and patterned on the substrate. And one of a variety of methods including, but not limited to, spin coating from solution, sputtering, chemical vapor deposition (CVD), laser ablation deposition, physical vapor deposition, and anodization. A step of depositing a high dielectric constant gate insulator on the gate electrode surface and optionally annealing the film at an appropriate temperature limited by the upper limit of 400 ° C. to improve the film quality and increase the dielectric constant. Forming the electrically conductive source and drain electrodes on the surface of the gate insulator; vapor deposition, sublimation, spin from solution Cloth, dip coating from a solution, or comprise a self-assembly of the layer from a solution by one of a variety of processes including, but not limited to, organic-inorganic hybrid semiconductor on the surface of the gate insulator (e.g., organic-inorganic hybrid perovskite (C ₆ H ₅ C ₂ H ₄
Depositing NH ₃ ) ₂ SnI ₄ ); and
Providing an optional passivation coating of an insulator by chemical vapor deposition (CVD), physical vapor deposition, or spin coating and curing, or other means.

The sequence of steps including the deposition of the organic-inorganic hybrid semiconductor and the fabrication of the source and drain electrodes comprises:
It can be reversed to allow for process compatibility and ease of manufacture.

FIG. 1 shows an organic-inorganic hybrid perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ S as a spin-coated semiconductor layer.
nI ₄ is added to the gate electrode corresponding to a device using a heavily doped Si wafer as a gate electrode, a thermally grown SiO ₂ film having a thickness of 500 nm as a gate insulator, and further using Pd source and drain electrodes. shown in obtained discrete voltage (V _G), the current flowing between the source electrode and the drain electrode of the (I _D), the dependence of the voltage applied to the drain electrode (V _D). The linear region of the plot (ie, at small V _D ) can be modeled with Equation 1 as described above. L = 28 μm and W = 1000 μm.

[0018] Figure 2 (left vertical axis) corresponds to the same device as above, showing the V _G dependence of I _D in the saturation region. While maintaining the drain voltage at −100 volts, the gate voltage −
The current modulation for a change from 50 to +50 volts is about 10 ⁴ . By patterning the hybrid semiconductor, the current modulation was increased to about 10 ⁶ . Field effect mobility μ
Is

(Equation 5) Is calculated from the slope of the pair V _G plot (FIG. 2 (right vertical axis)), was 0.55cm ² V ^-1 sec ^-1. These data are comparable to those of a similar TFT structure described earlier as part of the prior art overview. As mentioned earlier, the mobility is acceptable for the actual TFT application, but the operating voltage is too high compared to the drive circuit used for aSi: H TFT, especially in AMLCD . The field-effect mobility measured from a TFT device as corresponding to FIGS. 1 and 2 shows a gate voltage dependence. In particular, high mobility can be obtained with a relatively high gate voltage. This in turn requires these devices to use unrealistically high operating voltages in order to obtain acceptable mobility. To solve this problem, we examined the dependence of the applied gate voltage V _G of the field-effect mobility μ measured from TFT device to correspond to FIGS. 1 and 2 in detail.

FIG. 3 shows that V _D is kept constant at −100 V and V _S
Always when set to 0 volts, shows the dependence of μ on the maximum V _G used in a variety of gate voltage sweep experiments. The observed behavior may be due to the dependence of the mobility on the gate electric field E. here,

(Equation 6) Where y is the insulator thickness or the accumulated carrier concentration at the semiconductor / insulator interface. Both the gate field and the accumulated carrier concentration at the semiconductor / insulator interface increase linearly with increasing gate voltage or with decreasing insulator thickness. By using a relatively thin layer of thermally grown SiO ₂ as a gate insulator (thickness 150 nm), when keeping the drain voltage to -20 volts, the gate voltage -10
0.5 cm ² V ^-1 s for the change from
A mobility of ec ^{-1 and} an on / off ratio greater than 10 ⁴ could be achieved. Figures 4 and 5 show the operating characteristics of such a device. In single-crystalline inorganic semiconductors, such as silicon, whose mobility is not increased by increasing the gate voltage, and thus at high gate electric fields, the relative voltage required to achieve a specific on-current and a specific current is relatively small. Thin gate dielectric layers are commonly used. Thus, by using a thinner dielectric layer, the operating voltage of a silicon TFT device can be reduced. However, this approach suffers from the limitations of thinner dielectrics being more susceptible to pin-hole defect than thicker gate dielectrics, and having a lower dielectric breakdown voltage and higher leakage current. There is. For large area applications of substrates such as glass or plastic, these limitations are even more pronounced and can be serious. Therefore, reducing the thickness of the gate dielectric is not the best way to take advantage of the gate voltage dependent mobility of TFTs based on organic-inorganic hybrids.

Another cause of gate voltage dependence shown in FIG.
Is the semiconductor / insulator interface due to the change in applied gate voltage
It may be a change in the accumulated carrier concentration on the surface. Organic
Inorganic hybrid semiconductor TFTs accumulate extra charge carriers
Makes it easier to fill the capture condition,
Easy carrier without disturbing the capture process
You will be able to move. Shown in the prior art
As in the case of the organic semiconductor TFT (see Patent No.
5,981,970 and 5,946,551,
And Science Vol. 283, pp. 822-824, (199
9)). We use SiO _TwoTo a larger thickness with similar thickness
Organic-inorganic hybrid by replacing with electrical insulator
We propose to facilitate charge storage at the semiconductor / insulator interface.
You. In this case, SiO_TwoAccumulation carrier concentration similar to
Degree, but with all other parameters the same,
Lower gate field and therefore lower gate voltage
Is obtained.

If this hypothesis is correct, the device should achieve high mobility at lower voltages than TFTs using equivalent thicknesses of SiO ₂ . Conversely, in other words, if the mobility depends on the electric field but is independent of the carrier concentration, a relatively small mobility should be observed at a lower gate voltage used in the latter sample. It is. As shown below, the field-effect mobilities measured from two different insulator-based devices of equal thickness but different dielectric constants support our hypothesis. The following example shows an organic-inorganic hybrid perovskite (C ₆ H ₅ C ₂₎ using a high dielectric constant inorganic film as a gate insulator.
The fabrication of TFTs based on H ₄ NH ₃ ) ₂ SnI ₄ and the resulting high field-effect mobility at low operating voltages are described in detail.

Example 1 We use organic-inorganic perovskite (C₆H_Five
C_TwoH_FourNH_Three)_TwoSnI _FourAnd as gate insulator
TFTs with barium ruconate titanate (BZT)
Manufactured. Ultrasonic wave of silicon oxide substrate or quartz substrate
Wash in isopropanol bath using agitation and dry with nitrogen
did. Then, insert this with the opening corresponding to the gate line
Assemble with metal mask and install in electron beam evaporation equipment
Pumped down to high vacuum. 3 following 15nm titanium
Two-layer gate metallization of 0 nm Pt, e-beam evaporation
To adhere to the substrate. Take the sample from the assembly
Removed and covered with a layer of BZT. The BZT layer is made of BZT powder
RF magnetron sputtering of baking target
Using Ar / O_TwoIt was deposited in a mixed gas. Base
The plate is kept at room temperature during sputtering and the chamber pressure
Is about 2.5 × 10^-3Torr. The power density is 0.
8Wcm^-2Met. The dielectric constant ε of this BZT film is usually
It is about 17. Pt source and drain electrodes
Through the shadow mask, the surface of the BZT gate insulator layer
To a gas phase. With a channel length (L) of about 10 μm
Fabricate and use silicon thin film masks to make devices
Used. Organic-inorganic hybrid perovskite (C₆H_FiveC_TwoH_FourN
H_Three)_TwoSnI_FourLayer is 20 millimeters per milliliter
Gram of anhydrous methanol solution by spin coating
I wore it. This solution is 0.2 μm polytetrafluoro
Filtration through ethylene Whatman washer filter
And on the substrate for 2 minutes at 2500 rpm in an inert atmosphere
Rotated. The resulting 30 nm thick film was
Dried at 80 ° C. for 10 minutes (US Pat. No. 6,180,
No. 956).

As can be readily appreciated, the relatively small increase in dielectric constant obtained using this amorphous BZT gate insulator instead of SiO ₂ is suitable for the purpose of organic-inorganic hybrid perovskite semiconductor TFT applications. I have.
However, the scope of the present invention is not limited to only such deposition processes. Most films of the BZT film and the previously mentioned high-k gate insulator can be alternately deposited using other methods. Depending on the particular high-k gate insulator, one or more of the following methods can be applied. Deposition of the organometallic precursor of the oxide component from a solution (US Pat. No. 5,946,551), laser ablation, anodization, CVD deposition;
These methods can be used without departing from the spirit of the invention.

On the other hand, organic-inorganic hybrid perovskite semiconductor layers can be deposited using sublimation in vacuum (Mitzi, Prikas and Chondroudis Chem. Mater.
Vol. 11, 542, (1999)) or dip coating (Lia
ng, Mitzi, and Prikas Chem. Mater. Vol. 10,
304, (1998)), stamping, screening,
Spraying, inkjet printing, and other solution processing methods can be used to apply.

High work function metals such as gold, platinum, and palladium are preferred for making the source and drain electrodes, but include chromium, titanium, copper, aluminum, molybdenum, tungsten, nickel, conductive polymers, conductive polymers. Other source and drain contact materials, such as conductive oligomers and conductive organic molecules, can be used without departing from the spirit of the invention.

Next, a sample of the completed TFT is
Using an ett Packard Model 4145A semiconductor parameter analyzer, it was electrically tested in an inert atmosphere to determine operating characteristics.

FIG. 8 (left vertical axis) shows an organic-inorganic hybrid perovskite (C ₆ H ₅ C ₂ H ₄ N) schematically shown in FIGS.
Representative device characteristics of a TFT based on H ₃ ) ₂ SnI ₄ are shown. Here, the thickness of the BZT gate insulator is about 17
7.5 nm, the dielectric constant of which is ε ≒ 17.
The BZT gate insulator was sputter deposited as previously described. The source-drain interval (channel length, L) is 15.8 μm, and the channel width W is 100
0 μm. FIG. 8 (left vertical axis) shows _{ID at} saturation.
Shows the V _G-dependent in the semi-log plot. Figure 8 (right vertical axis) shows a plot of the square root versus V _G of I _D. The field effect mobility μ is

(Equation 7) Calculated from the slope of the pair V _G plot, 0.3cm ² V ^-1 s
ec ^-1 . The current modulation is about 10 ⁵ for a 4 volt gate voltage change.

FIG. 9 shows an organic-inorganic hybrid perov as a semiconductor.
Skye (C₆H_FiveC_TwoH_FourNH_Three)_TwoSnI_FourUse
Zircon with a layer thickness of about 177.5 nm
Barium titanate film (while keeping the substrate at room temperature,
TFT device using (deposited by
It is a measured operating characteristic. Source current of drain current
Dependence on rain voltage is shown at various gate voltage levels
You. FIG. 9 shows the device described in the previous paragraph.
And the discontinuous voltage (V _G)so,
The current flowing between the source and drain electrodes (I_D)of
The voltage applied to the drain electrode (V_D)
You.

The devices of FIGS. 8 and 9 use a much smaller maximum operating voltage (up to 4 volts) to reduce the mobility and on / off ratio measured from devices of similar thickness of SiO ₂ gate insulator. Comparable mobility and on-
An off ratio has been achieved. However, here, devices of this similar thickness of SiO ₂ gate insulator required higher operating voltages to produce such mobilities and on / off ratios. B of the device corresponding to FIGS. 8 and 9
It should be noted that the thickness of the ZT gate insulator is 15% thicker than the SiO ₂ gate insulator of the device corresponding to FIGS. This means that the operating voltage of the device corresponding to FIGS. 8 and 9 can be 15% lower than 4V.

Therefore, when a film having a high dielectric constant is used as a gate insulator, it is clear that a TFT device based on an organic-inorganic hybrid can realize high mobility at a low voltage. This implies that the gate voltage dependence in this device is due to the relatively high concentration of charge carriers realized in these insulators, since the applied gate field is kept very small. Demonstrate the hypothesis.

Illustrative examples useful for practicing the present invention are provided.
Inorganic hybrid semiconductor material is butyl ammonium iodide
Methyl ammonium tin [(C_FourH₉NH_Three)_TwoCH_ThreeN
H_ThreeSn_TwoI₇], Phenethyl ammonium iodide meth
Luammonium tin [(C₆H_FiveC_TwoH_FourNH_Three)_TwoCH_Three
NH_ThreeSn_TwoI₇], Butane diammonium tin iodide
[(H_ThreeNC_FourH₈NH_Three) SnI_Four], Butyl iodide
Monium tin, hexyl ammonium tin iodide,
Nonylammonium tin iodide and dodeci iodide
Perovs of luammonium tin and their derivatives
Kite (C₆H_FiveC _TwoH_FourNH_Three)_TwoSnI_FourOne or more of
Is a number.

Despite the specific mechanism of how to achieve the properties, we have fabricated a structure that achieves high field-effect mobility and high current modulation in a TFT based on an organic-inorganic hybrid perovskite, and fabricated this structure. We argue that it has revealed the process of doing so. The present invention
Although described with reference to the preferred embodiment, numerous modifications, changes, and improvements will occur to those skilled in the art without departing from the spirit and scope of the invention. All references cited herein are hereby incorporated by reference, and all references cited in the references cited herein are hereby incorporated by reference.

In summary, the following items are disclosed regarding the configuration of the present invention.

(1) A substrate on which an electrically conductive gate electrode is disposed, a layer of a gate insulator disposed on the gate electrode, and a source electrode and a drain disposed on the layer of the gate insulator A transistor device structure comprising: an electrode; and a layer of an organic-inorganic hybrid semiconductor disposed on the gate insulator, the source electrode, and the drain electrode. (2) The transistor device structure according to (1), wherein the gate insulator has a high dielectric constant. (3) The structure according to (1), wherein said substrate is selected from the group consisting of glass, plastic, quartz, undoped silicon, and heavily doped silicon. (4) The structure according to (3), wherein the plastic substrate is selected from the group consisting of polycarbonate, mylar, polyimide, and polyethylene terephthalate. (5) The gate electrode material is chromium, titanium, copper, aluminum, molybdenum, tungsten, nickel,
The structure according to (1), wherein the structure is selected from the group consisting of gold, platinum, palladium, conductive polyaniline, conductive polypyrrole, or a combination thereof. (6) the gate electrode has a thickness of 30 nm to 500 nm and is formed by a process selected from the group consisting of vapor deposition, sputtering, chemical vapor deposition, electrodeposition, spin coating, and electroless plating; The structure according to the above (1). (7) The gate insulator is made of barium strontium titanate, barium zirconate titanate, lead zirconate titanate, lanthanum lead titanate, strontium titanate, bismuth titanate, barium magnesium fluoride, tantalum pentoxide, The structure according to (1), wherein the structure is selected from the group consisting of titanium dioxide and yttrium trioxide, aluminum trioxide, and silicon nitride. (8) The structure according to (7), wherein the gate insulator has a thickness in the range of 80 nm to 1000 nm. (9) wherein said gate insulator is produced by a process selected from the group consisting of sputtering, chemical vapor deposition, sol-gel coating, dip coating, vapor deposition, laser ablative deposition and anodizing. Structure described in. (10) The above (7), wherein the gate insulator is an organic material.
Structure described in. (11) The structure according to (1), wherein the organic-inorganic hybrid semiconductor is any organic-inorganic hybrid semiconductor that exhibits an increase in field-effect mobility with an increase in gate voltage. (12) The transistor device according to (1), wherein the organic-inorganic hybrid semiconductor is a perovskite material. (13) The structure according to the above (12), wherein the organic-inorganic hybrid semiconductor is perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI ₄ . (14) The organic-inorganic hybrid semiconductor includes butylammonium / methylammonium / tin, phenethylammonium / methylammonium / tin, butanediammonium / tin, butylammonium / tin, hexylammonium iodide, The structure according to (12), selected from the group consisting of tin, nonylammonium tin iodide, and one or more of tin dodecylammonium tin iodide and derivatives thereof. (15) The structure according to the above (11), wherein the organic-inorganic hybrid semiconductor layer has a thickness ranging from two monomolecular layers to 400 nm. (16) The structure according to (1), further comprising an insulating passivation layer that protects the structure from exposure to other processes and an external environment. (17) The structure according to (16), wherein the passivation layer includes a polymer passivation film selected from the group consisting of polyimide, parylene, and undoped polyaniline. (18) The structure according to the above (1), wherein the gate insulator is a composite material layer composed of high dielectric constant particles contained in a matrix material exhibiting a low dielectric constant. (19) providing a substrate on which a gate electrode is disposed, arranging a layer of a gate insulator on the gate electrode, and arranging a source electrode and a drain electrode on the layer of the gate insulator; A method for fabricating a transistor device structure comprising the steps of: placing an organic-inorganic hybrid semiconductor layer over the gate insulator and the source and drain electrodes. (20) The method according to (19), wherein the organic-inorganic hybrid semiconductor layer is deposited by a process selected from the group consisting of sublimation, vapor deposition, molecular beam deposition, or a combination thereof. (21) said organic-inorganic hybrid semiconductor layer is deposited by a solution-based process selected from the group consisting of spin coating, dip coating, self-assembly from solution, stamping, screening, thermal spraying, inkjet printing, or a combination thereof. The method according to (19) above. (22) The organic-inorganic hybrid semiconductor layer consists of deposition through a mask, screen printing, stamping, and lithographic patterning of a blanket film to minimize leakage and stray currents in the TFT device. The method of (19) above, which is optionally divided in a process selected from the group. (23) the source electrode and the drain electrode are chromium, titanium, copper, aluminum, molybdenum, tungsten, nickel, gold, palladium, platinum, a conductive polymer, a conductive oligomer, and a conductive small organic molecule;
And a method selected from the group consisting of and combinations thereof. (24) an optional ohmic contact layer made of a material selected from the group consisting of platinum, palladium, conductive polymers, conductive oligomers, semiconductive polymers, semiconductive oligomers, and combinations thereof; The above (2) disposed between the source / drain electrode and the semiconductor layer
The method according to 3). (25) The above (23), wherein the thickness of the source electrode and the drain electrode is in the range of 30 nm to 500 nm.
The method described in. (26) The method according to (19), wherein the source electrode and the drain electrode are patterned by a method selected from the group consisting of a deposition method via a shadow mask and a lithography patterning method. (27) The method according to the above (19), wherein the organic-inorganic hybrid semiconductor is any organic-inorganic hybrid semiconductor exhibiting an increase in field-effect mobility with an increase in gate voltage. (28) The method according to the above (19), wherein the organic-inorganic hybrid semiconductor is perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI ₄ . (29) The organic-inorganic hybrid semiconductor includes butylammonium / methylammonium / tin, phenethylammonium / methylammonium / tin, butanediammonium / tin, butylammonium / tin, butylammonium / tin, and hexylammonium / iodide. (19) The method according to (19) above, wherein the method is selected from the group consisting of tin, nonylammonium tin iodide, and one or more of tin dodecylammonium tin iodide and derivatives thereof. (30) The method according to the above (19), wherein the gate insulator is a composite material layer composed of high dielectric constant particles contained in a matrix material exhibiting a low dielectric constant. (31) a substrate on which a plurality of gate electrodes are arranged, a layer of a gate insulator arranged on the gate electrode, and substantially each of the gate electrodes arranged on the gate insulator. A partially overlapping organic-inorganic hybrid semiconductor layer and a plurality of sets of source and drain electrodes positioned on the organic-inorganic hybrid semiconductor and the high dielectric constant gate insulator in alignment with each of the gate electrodes; A thin film transistor device structure comprising: (32) A transistor device structure including a source electrode, a drain electrode, a gate electrode, a gate insulator, and a semiconductor material disposed between the source electrode and the gate electrode and in electrical contact with the source and drain electrodes. Wherein the gate insulator is disposed between the gate electrode and the active region, and the semiconductor material is an organic-inorganic hybrid material.

[Brief description of the drawings]

FIG. 1 shows an organic / inorganic hybrid perovskite (C ₆ H ₅₎ as a semiconductor together with a 500 nm thick SiO ₂ gate insulator.
FIG. 4 shows measured operating characteristics of a TFT device using C ₂ H ₄ NH ₃ ) ₂ SnI ₄ . It shows the dependence of drain current as a function of source-drain voltage for different discontinuous values of gate voltage (Kagan, Mitzi, an
d Dimitrakopoulos, Science Vol. 286, pp. 945
-947, (1999)). In this device, L
= 28 μm and W = 1000 μm.

FIG. 2 is a graph showing the dependence of the drain current on the gate voltage at a fixed source-drain voltage on a semi-log scale on the left vertical axis, and the square root of the drain current in the saturation region for the TFT device corresponding to FIG. FIG. 4 is a graph showing a linear scale plot on the right vertical axis as a function of gate voltage.

FIG. 3 shows different gate voltages and the same source-drain voltage (−1) for the device characterized in FIG.
FIG. 4 is a plot of the field-effect mobility calculated at (00V), and shows a strong gate voltage dependence of the mobility.

FIG. 4 shows an organic-inorganic hybrid perovskite (C ₆ H ₅₎ as a semiconductor together with a 150 nm thick SiO ₂ gate insulator.
FIG. 4 shows measured operating characteristics of a TFT device using C ₂ H ₄ NH ₃ ) ₂ SnI ₄ . It shows the dependence of drain current as a function of source-drain voltage for different discontinuous values of gate voltage. In this device, L
= 28 μm and W = 1000 μm.

FIG. 5 is a graph showing the gate voltage dependence of the drain current at a fixed source-drain voltage on a semi-log scale on the left vertical axis, and the square root of the drain current in the saturation region for the TFT device corresponding to FIG. FIG. 4 is a graph showing a linear scale plot on the right vertical axis as a function of gate voltage.

FIG. 6 has a high dielectric constant gate insulator according to the present invention;
1 is a schematic diagram of a TFT device based on an organic-inorganic hybrid.

FIG. 7 has a high dielectric constant gate insulator according to the present invention;
1 is a schematic diagram of a TFT device based on an organic-inorganic hybrid.

FIG. 8 shows an organic-inorganic hybrid perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI ₄ used as a semiconductor, and a barium zirconate titanate film having a thickness of about 177.5 nm as a gate insulator. Figure 3 shows the measured operating characteristics of a TFT device using (sputter deposited while keeping the substrate at room temperature). The gate voltage dependence of the drain current at a fixed source-drain voltage is shown on a semi-log scale on the left vertical axis, and is used to calculate the electric field mobility.
The square root of the drain current in the saturation region is on the right vertical axis,
5 is a graph showing a plot as a function of gate voltage.

FIG. 9: A barium zirconate titanate film having a layer thickness of about 177.5 nm is used as a semiconductor, using an organic-inorganic hybrid perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI ₄ as a semiconductor and a gate insulator. Figure 3 shows the measured operating characteristics of a TFT device using (sputter deposited while keeping the substrate at room temperature). At different gate voltage levels,
FIG. 6 is a diagram illustrating the source / drain voltage dependence of the drain current.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI theme coat テ ー マ (Reference) H01L 29/78 617J 617V 619A 618A 616V 616K 29/28 (72) Inventor Christos Dimitris Dimitraco Poros United States 10604 West Harrison, New York 791 Lake Street 791 (72) Inventor Cherry Linney Kagan United States 10562 Ossining Waterview Drive, New York 43 (72) Inventor David Brian Michi United States 10541 Ma Hopac Friendly Road, New York 33 F term (reference) 4M104 AA10 BB02 BB04 BB05 BB06 BB07 BB09 BB13 BB14 BB16 BB18 BB36 CC01 CC05 DD34 DD37 DD43 DD51 DD53 GG09 5F110 AA01 AA17 BB01 CC03 CC07 DD01 DD02 DD03 DD05 EE01 EE02 EE03 EE04 EE08 EE14 EE41 EE42 EE43 EE44 EE45 FF01 FF02 FF03 FF09 FF21 FF23 NN24 FF27 FF28 FF29 FF36 GG02 GG05 GG02 GG05 GG02

Claims (32)

[Claims] A substrate on which an electrically conductive gate electrode is disposed; a layer of a gate insulator disposed on the gate electrode; a source electrode and a drain electrode disposed on the layer of the gate insulator. And a layer of an organic-inorganic hybrid semiconductor disposed on the gate insulator and the source electrode and the drain electrode. 2. The transistor device structure according to claim 1, wherein said gate insulator has a high dielectric constant. 3. The structure of claim 1, wherein said substrate is selected from the group consisting of glass, plastic, quartz, undoped silicon, and heavily doped silicon. 4. The structure of claim 3, wherein said plastic substrate is selected from the group consisting of polycarbonate, mylar, polyimide, and polyethylene terephthalate. 5. The method according to claim 1, wherein the gate electrode material is chromium, titanium,
The structure of claim 1, wherein the structure is selected from the group consisting of copper, aluminum, molybdenum, tungsten, nickel, gold, platinum, palladium, conductive polyaniline, conductive polypyrrole, or a combination thereof. 6. The semiconductor device according to claim 1, wherein said gate electrode has a thickness of 30 nm to 500 n.
2. The structure of claim 1, wherein the structure is m in thickness and further produced by a process selected from the group consisting of vapor deposition, sputtering, chemical vapor deposition, electrodeposition, spin coating, and electroless plating. 7. The method according to claim 7, wherein the gate insulator is made of barium titanate.
Strontium, barium zirconate titanate, lead zirconate titanate, lanthanum lead titanate, strontium titanate, bismuth titanate, barium / magnesium fluoride, tantalum pentoxide, titanium dioxide and yttrium trioxide, aluminum trioxide, and chamber The structure of claim 1, wherein the structure is selected from the group consisting of silicon halides. 8. The method according to claim 1, wherein said gate insulator has a thickness of
The structure of claim 7, wherein the thickness is in the range of nm. 9. The gate insulator is formed by a process selected from the group consisting of sputtering, chemical vapor deposition, sol-gel coating, dip coating, vapor deposition, laser ablative deposition, and anodizing. 7. The structure according to 7. 10. The structure according to claim 7, wherein said gate insulator is an organic material. 11. The structure according to claim 1, wherein said organic-inorganic hybrid semiconductor is any organic-inorganic hybrid semiconductor exhibiting an increase in field-effect mobility with an increase in gate voltage. 12. The transistor device according to claim 1, wherein the organic-inorganic hybrid semiconductor is a perovskite material. 13. The organic-inorganic hybrid semiconductor is perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI _4.
Structure described in. 14. An organic-inorganic hybrid semiconductor comprising: butylammonium / methylammonium / tin, phenethylammonium / methylammonium / tin, butanediammonium / tin, butylammonium / tin / iodide, hexyl iodide 13. The structure of claim 12, wherein the structure is selected from the group consisting of one or more of ammonium tin, nonylammonium tin iodide, and dodecylammonium tin iodide and derivatives thereof. 15. The structure according to claim 11, wherein said organic-inorganic hybrid semiconductor layer has a thickness in a range from two monolayers to 400 nm. 16. The structure of claim 1, further comprising an insulating passivation layer that protects the structure from being exposed to other processing and from an external environment. 17. The structure of claim 16, wherein said passivation layer comprises a polymer passivation film selected from the group consisting of polyimide, parylene, and undoped polyaniline. 18. The structure of claim 1, wherein said gate insulator is a composite layer of high dielectric constant particles contained in a low dielectric constant matrix material. 19. A method comprising: providing a substrate on which a gate electrode is disposed; arranging a layer of a gate insulator on the gate electrode; and forming a source electrode and a drain electrode on the layer of the gate insulator. A method of fabricating a transistor device structure comprising: arranging; and arranging a layer of an organic-inorganic hybrid semiconductor over the gate insulator and the source and drain electrodes. 20. The method of claim 19, wherein the organic-inorganic hybrid semiconductor layer is deposited by a process selected from the group consisting of sublimation, evaporation, molecular beam evaporation, or a combination thereof. 21. The organic-inorganic hybrid semiconductor layer is formed by a solution-based process selected from the group consisting of spin coating, dip coating, self-assembly from solution, stamping, screening, thermal spraying, inkjet printing, or a combination thereof. 20. The method of claim 19, wherein said method is applied. 22. The organic-inorganic hybrid semiconductor layer is deposited via a mask, screen printed, stamped, and lithographically patterned over the surface to minimize leakage and stray currents in the TFT device. 20. The method of claim 19, wherein the method is optionally divided in a process selected from the group consisting of: 23. The method according to claim 23, wherein the source electrode and the drain electrode are formed of chromium, titanium, copper, aluminum, molybdenum,
20. The method of claim 19, wherein the method is made from a material selected from the group consisting of tungsten, nickel, gold, palladium, platinum, conductive polymers, conductive oligomers, and conductive small organic molecules, and combinations thereof. 24. Gold, platinum, palladium, conductive polymer,
An optional ohmic contact layer made of a material selected from the group consisting of conductive oligomers, semiconducting polymers, semiconducting oligomers, and combinations thereof is disposed between the source / drain electrodes and the semiconductor layer 24. The method of claim 23, wherein the method is performed. 25. The method according to claim 23, wherein the thickness of the source electrode and the drain electrode ranges from 30 nm to 500 nm. 26. The method of claim 19, wherein said source electrode and said drain electrode are patterned by a method selected from the group consisting of deposition via a shadow mask and lithographic patterning. 27. The method of claim 19, wherein said organic-inorganic hybrid semiconductor is any organic-inorganic hybrid semiconductor that exhibits an increase in field effect mobility with increasing gate voltage. 28. The organic-inorganic hybrid semiconductor is perovskite (C ₆ H ₅ C ₂ H ₄ NH ₃ ) ₂ SnI _4.
The method described in. 29. The organic-inorganic hybrid semiconductor comprises butylammonium / methylammonium / tin, phenethylammonium / methylammonium / tin, butanediammonium / tin, butylammonium / tin, hexyl iodide, and hexyl iodide. 20. The method of claim 19, wherein the method is selected from the group consisting of one or more of ammonium tin, nonylammonium tin iodide, and dodecylammonium tin iodide and derivatives thereof. 30. The method of claim 19, wherein said gate insulator is a composite layer of high dielectric constant particles contained in a matrix material exhibiting a low dielectric constant. 31. A substrate on which a plurality of gate electrodes are disposed, a layer of a gate insulator disposed on the gate electrode, and substantially each of the gate electrodes disposed on the gate insulator. A layer of an organic-inorganic hybrid semiconductor that partially overlaps, and a plurality of source and drain electrodes positioned on the organic-inorganic hybrid semiconductor and the high dielectric constant gate insulator in alignment with each of the gate electrodes And a thin film transistor device structure comprising: 32. A transistor device structure comprising a source electrode, a drain electrode, a gate electrode, a gate insulator, and a semiconductor material disposed between said source electrode and said gate electrode and in electrical contact therewith. Wherein the gate insulator is disposed between the gate electrode and the active region, and the semiconductor material is an organic-inorganic hybrid material.