JP4545439B2 - Digital controller for high frequency power supply - Google Patents

Description

  The present invention relates generally to voltage control, and more particularly to digital voltage control for high frequency voltage regulators.

  This application is a US Provisional Patent Application No. 60/338 entitled “Digital Controller for High Frequency Switching Power Supplies”, filed December 12, 2001, the disclosure of which is incorporated herein by reference. , Claim the profit of 712. This application is also filed on Nov. 8, 2002, the disclosure of which is incorporated herein by reference, US patent application Ser. No. 10/291, filed “Adaptive Voltage Regulator for Powered Digital Devices”. Claims priority to 098.

  Analog voltage controllers are widely used with power converters for DC-DC (DC-DC) converters. Analog controllers are fast and can generally be made using widely available components. However, the operation of the analog controller depends on the accuracy of the individual components included in the controller. Therefore, considerable effort must be expended to ensure that analog components that comply with very strict quality control standards are selected. In addition, even after careful selection in this way, the tone of analog components is subject to manufacturing process variations, operating temperatures, and aging over time. Furthermore, analog design is not easily implemented using existing automated design methods. Therefore, the design of analog controllers tends to be time consuming and laborious.

  Some existing voltage controllers include one or more digitally mounted components. However, digital components mounted on existing voltage controllers are not operating as desired. For example, digital signal processors (DSPs) have been implemented in voltage regulators to perform arithmetic operations such as multiplication as part of compensator operation. However, these DSP implementations do not go well, take up a lot of space, and are overly complex for the task being performed. In addition, since DSPs require that digital data be manipulated, the DSP implementation requires a large and energy consuming analog / digital converter (ADC). The ADCs in these controllers are precision analog components that take up a large amount of valuable space on the chip, consume a large amount of power, and are similar to the analog components of existing legacy controllers. Subject to performance variations induced by temperature and induced by processing.

  Thus, the voltage control technique would benefit from providing a voltage controller that is small, energy and space efficient and whose performance does not depend on temperature and process variations of individual controller components. .

  The present invention provides a small, fast, accurate and energy efficient voltage controller whose performance is independent of temperature variations and other variations of component part characteristics. Advocate techniques and help to overcome problems. In a preferred embodiment, all functions of the controller of the present invention are implemented using digital logic gates, thereby avoiding the need for precision analog components and performance variations of precision analog components. In a preferred embodiment, the digital logic gates that form the controller of the present invention can be efficiently modeled using existing electronic design automation such as hardware description language (HDL), thereby Design is simplified and design time is reduced.

  Preferably, the delay line ADC composed exclusively of digital logic gates supplies a digitally encoded error signal indicating the difference between the output voltage and the reference voltage. The delay line ADC disclosed herein preferably performs functions associated with analog voltage comparison devices within existing analog controllers. Alternatively, the delay line ADC preferably performs the combined function of the ADC and digital voltage comparison device in an existing voltage controller that is partially digitally implemented.

  In a preferred embodiment, hybrid / digital pulse width modulation and compensators are also implemented digitally. In a preferred embodiment, the compensator includes a look-up table that rapidly converts the digital error signal from the delay line ADC into a digital control signal, which is supplied digitally as an output from the compensator. The expressed duty ratio. In a preferred embodiment, the digital pulse width modulator receives as input a digital control signal supplied by a compensator and converts this digital signal as an output from the controller into a time variable control signal controlled by a duty ratio. . Preferably, the controller output is supplied to the power converter to increase or decrease the regulator output voltage in response to a comparison between the output voltage and the reference voltage.

  The advantages of implementing the digital controller technology disclosed herein include: All-digital controllers are inherently insensitive to processing and parameter variations, rapid programmability for various controller performance characteristics, reduction or elimination of tuning passive components, and other digital systems Because of its ease of integration, it is very attractive in high frequency, low to medium power DC-DC converters. The benefits of compensator programmability and the need to tune passive components may be used for power converter configurations and power stage parameter value ranges. Furthermore, when implementing a digital controller, it is possible to implement an impractical control scheme for analog controller design.

  For example, it may be desirable to use a dedicated digital controller IC (integrated circuit) to have the ability to precisely match the phase shifted duty ratio to a simple and robust control for a voltage regulator module (VRM). In transformer isolated DC-DC converters, digital signal transmission through the isolation can be used to address bandwidth limitations and / or large gain variations associated with standard analog techniques. In general, more sophisticated control methods may be used to achieve improved dynamic response.

  Another advantage of digital techniques is that they are well established and automated digital design techniques can be applied. Controller designs can be described at a functional level using a hardware description language (HDL). Preferably, synthesis, simulation and verification tools are available to design from an HDL description for implementation on a standard cell ASIC (application specific integrated circuit) or FPGA (field programmable gate array). The design can then be implemented using various manufacturing processes that are integrated with other digital systems or modified to meet updated specifications. In contrast to the realization of an analog IC controller, the design of the digital controller is preferably well-standardized and therefore advances in fabrication technology can be exploited.

  The foregoing and other advantages of the present invention will be better understood upon reading the following description of a preferred exemplary embodiment of the invention used in conjunction with the drawings.

  In this disclosure, the transistor terminal is either the source or drain of a field effect transistor (FET) or the emitter or collector of a bipolar junction transistor (BJT). As used herein, a comparator is any device that receives two voltage values and provides as an output a signal indicating the difference between the two received voltage values. In this specification, the terms “comparator” and “voltage comparator” are used interchangeably. In this disclosure, energy storage components include both analog and digital devices, including, for example, capacitors, inductors, and powered digital logic gates. The term “energy storage component” is simply intended to exclude wiring and other conductive instruments that operate to connect one electronic component to another. As used herein, a resistor is a device having a resistance value aggregated into a solid form. As used herein, a resistor actually includes wiring or other conductive links between electronic components. As used herein, an electronic memory is a digital electronic storage device that can provide a stored value in response to identifying the address of the stored value's electronic memory. As used herein, a digital electronic calculator may include a digital electronic storage device and / or a digital device that performs an arithmetic operation that includes any one or more of addition, subtraction, multiplication, and / or division. .

  As used herein, a signal tap array may include any number of signal taps. The signal tap array preferably includes a plurality of signal taps, each tap being connected to one delay cell in the array of delay cells. However, the signal tap array may include signal taps that are connected to only a subset of the delay cells in the delay cell array. As used herein, a binary digital code is a conventional digital code, where an array of bits identifies a coefficient value equal to various powers of the number “2”. For example, the digital code “101” corresponds to 1 · 1 + 0 · 2 + 1 · 4 = 5. A binary digital code is identified from a “thermometer code” in which each bit in an array is the same numerical weight.

  FIG. 1 is a block diagram of a voltage regulator 100 including a digital voltage controller 150 according to a preferred embodiment of the present invention. The regulator 100 preferably includes a power converter 200 and a controller 150. The power converter (“converter”) 100 is preferably a synchronous step-down converter. The power converter preferably includes a gate driver 204 connected to the gate of the transistor switch 202, the first terminal of the transistor being connected to the positive node 114 of the power supply 102, and the second terminal of the transistor being the node 116. Connected to. The gate driver 206 provides an output connected to the gate of the transistor switch 208, one terminal of which is connected to the negative node 112 of the power supply, and the other terminal of the transistor is connected to the node 116. Inductor 210 is preferably between node 116 and node 118. Capacitor 212 is preferably between node 118 and node 112.

In the embodiment of FIG. 1, the power converter 200 is connected to the power supply V _g 102 and generates the output voltage V _O 104. The output voltage V _O is connected across the load 110 between the node 118 and the node 112 of the converter 200, and the load is connected in parallel with the capacitor 212. The operation of the converter 200 is well known in the art and therefore will not be discussed in detail in this disclosure. It will be appreciated that the present invention is not limited to the design of the transducer 200. A wide range of design and operating principles can be incorporated into the converter 200 and will not affect the operation of the preferred embodiment of the controller 150. It will be appreciated that the converter 200 of FIG. 1 is only one of many converter designs that may be used with the controller 150.

In a preferred embodiment, the controller 150 includes a delay line ADC 700, a compensator 300, and a pulse width modulator (PWM) 400 (preferably a hybrid digital pulse width modulator). Preferably, the voltages V _sense 108 and V _ref 106 are inputs to the controller 150, particularly the delay line ADC 700. The equipment (not shown) that supplies V _ref 106 is preferably not part of controller 150. Preferably, an external memory 160 can be used to supply information to the compensator 300 when needed. Delay line ADC 700 preferably serves as a voltage comparator in the embodiment of FIG. Although the delay line ADC 700 is a preferred voltage comparator for this application, the present invention is not limited to using the delay line ADC 700 to generate a signal indicative of the voltage difference between the voltages V _sense 108 and V _ref 106. In an alternative embodiment, a range of devices, either analog or digital, that provide a signal indicative of the voltage difference between the two voltage sources can be used with the controller 150, and all such variations Forms are intended to be included within the scope of the present invention.

In this embodiment, the converter 200 and controller 150 form a closed loop feedback system 100 that is preferably stable over a range of values of input voltage 102 and load current, and over a range of processing and temperature variations. The output voltage V _O 104 is adjusted to meet the voltage reference V _ref 106 (or a scaled reference). In this embodiment, the output voltage 104 is sensed and compared to V _ref 106. Digital error signal 152 is preferably transmitted to compensator 300. The output (digital control signal) 154 of the compensator 300 is an input to the pulse width modulator 400, which in turn has a constant frequency variable duty ratio for controlling the switching power transistors 202, 208. A signal (power control signal) 156 is preferably generated. A preferred embodiment of a digital controller architecture for implementing this control scheme is shown in FIG.

Preferably, V _sense 108 is a scaled version of V _O 104. This can be expressed mathematically as V _sense = HV _O. However, this disclosure considers H to have a value of 1 for the sake of brevity. Thus, to discuss the rest, V _sense 108 and V _O 104 have the same value. Preferably, V _O 104 produces a digital error signal e (n) 152 sampled by an A / D (analog / digital) converter. Preferably, sampling of V _O 104 occurs once per switching period T _S. Here, the index value “n” indicates the current switching period.

Generally speaking, effective voltage regulation is usually such that V _O (t) 104 is within the specified range of V _ref 106, ie, V _ref − (ΔV _O ) _max / 2 to V _ref + (ΔV _O ). Require that it is in the range of _max / 2. In other words, the steady state output voltage 104 has an acceptable range of V _O = V _ref ± ΔV _O / 2. In order to keep V _O 104 within an acceptable range, the analog equivalent of the least significant bit (LSB) of the A / D characteristic must not exceed the desired magnitude of ΔV _O. Preferably, the specifications for ΔV _O and (ΔV _O ) _max are such that only a few digital values are needed to represent an analog voltage error magnitude equal to V _ref 106 -V _sense 108. It is.

FIG. 3 is a block diagram of the operation of the digital voltage controller 150 of FIG. In the embodiment of FIG. 3, the digital representation of the error signal 152 takes nine values, one from -4 to +4 (decimal). The ADC 158 preferably has a sufficiently high resolution to accurately adjust the V _O 104, but only a few bits are required to represent the digital error signal e (n) 152. In the preferred embodiment, the value of the digital error signal 152 is used as a lookup table address. Thereafter, an arbitrary relationship is established between the magnitude of the digital error signal 152 and the magnitude of the numeric entry at the look-up table address pointed to by the value of the digital error signal 152. In Table 1 later in this document, the correlation of the preferred embodiment between the digital error value and the desired control signal magnitude is confirmed. In the present specification, the “digital error magnitude” is a value corresponding to the magnitude of the difference between the measured voltages. Preferably, the digital error value corresponds to a lookup table address where the magnitude of the digital error is there.

  A novel delay line ADC configuration 700 that takes advantage of the required static A / D characteristics and provides a simple digital implementation by itself is described in connection with FIG. It will be appreciated that delay line ADC 700 is the preferred embodiment of ADC 158, although it is not the only available.

  In addition to mitigating the requirements of ADC 158, the ability to represent error signal 152 using a limited number of bits allows the implementation of the next controller component, compensator 300, to be simplified. Preferably, compensator 300 optionally calculates digital control signal 154 using digital error signal 152 along with the value of the stored signal from the previous cycle. The digital control signal is a digitally represented duty ratio of a constant frequency signal in the preferred embodiment.

  Calculations in the compensator 300 can be established according to proven digital control theory. However, a standard implementation of a linear control law in compensator 300 will generally involve the use of digital adder (s) and / or digital multiplier (s). Such devices tend to increase the size of the controller 150 and tighten the clock frequency requirements for the controller 150. In order to effectively take advantage of the fact that only a few bits are needed to represent the digital error signal 152, the preferred embodiment of the compensator 300 instead has lookup tables 302, 304, and 306, and The duty ratio 154 is calculated using the adder 318. Preferably, the current and previous values of digital error signal 152 serve as look-up tables 302, 304, and 306 as address (s) from which values can be obtained. Since the digital error signal 152 preferably takes only a small number of values, the number of entries in the lookup tables 302, 304, and 306 is correspondingly small. As a result, the implementation of tables 302, 304, and 306 requires only minimal physical property on the chip. Further, the calculation of duty ratio 154 is preferably performed in a small number of cycles of system clock 120. The discussion in FIG. 3 is directed to an embodiment that includes three look-up tables and one adder, but that more than one adder may be used, and less than three, or It will be appreciated that more than four lookup tables may be used.

  Preferably, the compensator 300 can be programmed to execute different control algorithms by adjusting the values of the entries in the look-up tables 302, 304, and 306. One control algorithm supported in the embodiment of FIG. 3 is described as follows.

(1) d (n + 1) = d (n) + α (e (n)) + β (e (n−1)) + γ (e (n−2))
Here, α (•), β (•), and γ (•) may be either linear or non-linear functions of the digital error signal 152. However, various control algorithms can be implemented. One additional example is
(2) d (n + 1) = d (n) + ae (n) + be (n−1) + ce (n−2)
It is described by. Here, a, b, and c are constants and correspond to basic PID (proportional, integral, and differential) control algorithms. In the controller 150 design, once a, b, and c are selected (eg, to achieve the desired closed-loop bandwidth and appropriate phase margin), the products a · e, b · e, and c · e is preferably pre-calculated for all possible values of error “e” and is preferably programmed into lookup tables 302, 304, and 306 from external memory 160. As an alternative to using external memory 160, look-up tables 302, 304, and 306 may be pre-programmed and real-wired on the chip at design time, or other at run time through an appropriate interface. May be programmed from system components. Thus, external memory 160 is one useful technique for supplying data to lookup tables 302, 304, and 306, although the alternative techniques described above can be utilized.

  Due to the programmability of the compensator 300, the same controller 150 hardware may change the different power stages by modifying the data entries in the look-up tables 302, 304, and 306 rather than by changing the hardware. Preferably, it can be used for configuration and different power stage parameters. Furthermore, the compensator 300 preferably allows experimentation with various non-linear control algorithms without requiring time-consuming, time-consuming and inconvenient replacement of precision analog components.

  FIG. 4 is a block diagram of a pulse width modulator 400 included in the digital voltage controller of FIG. FIG. 5 is a plot of various signal waveform values of the pulse width modulator of FIG. A pulse width modulator (PWM) 400 (preferably a hybrid digital PWM) preferably completes the controller architecture. The PWM 400 preferably generates a periodic waveform c (t) 156 from the duty ratio 154, and preferably controls the transistor switches 202 and 208 of the power converter 200 by the periodic waveform. Preferably, PWM 400 can be effectively used to achieve high switching frequency operation and control of Vo 104 within a narrow defined range.

The PWM 400 preferably operates as a D / A converter (DAC) of the voltage regulator 100. In general, the resolution of PWM 400 determines the set of available output voltage values 104. If the resolution of the PWM 400 is not sufficiently high, an undesirable limit cycle oscillation of the value of Vo 104 may occur. If none of the achievable output voltage 104 falls within the range of ΔV _O centered on V _ref 106, duty ratio 154 generally oscillates between two or more values. Avoiding this limit cycle operation can be achieved by ensuring that the output voltage increment corresponding to the least significant bit of the duty ratio 154 is less than [Delta] V _O. This condition has been evaluated as a function of steady state input / output voltage for different converter configurations.

A high resolution, high frequency digital pulse width modulator (DPWM) can be constructed using a high speed clock counter and a digital comparator. In order to achieve n-bit resolution at the switching frequency f _s , the desired clock frequency is 2 ⁿ f _s . This desired clock frequency generally leads to tighter timing constraints and increased power consumption. For example, an 8-bit resolution with a switching frequency of f _s = 1 MHz would require a clock frequency of 256 MHz. High time resolution and low power consumption can be achieved using a tapped delay line scheme similar to a ring oscillator operating at the switching frequency. However, this implementation requires a large area digital multiplexer. The PWM architecture chosen for use in the preferred embodiment is by a hybrid delay line / counter approach. In this approach, n bit resolution, _{(here, n c <n) n} c-bit counter is accomplished using. Here, the remaining n _d = n−n _c bits of resolution are obtained from the tapped delay line.

The embodiment of FIG. 4 includes a 2-bit counter (n _c = 2) 406 and a 4-cell ring oscillator (n _d = 2, 2 ⁿ _d) including flip-flops 416, 418, 420, and 422 operating as delay cells. = 4) is used to obtain a 4-bit (n = 4) resolution PWM400. Preferably, at the beginning of the switching cycle, output SR flip-flop 410 is set (set) and output pulse c (t) 156 of PWM 400 goes high. Preferably, ^pulse, a 2 _nc f s = the oscillator 402 at a frequency of 4f _s propagates, the pulse is the role of clock pulses for the counter 406. The switching period is preferably divided into 2 ⁿ _d 2 ⁿ _c = 16 slots. Preferably, when the output of counter 406 matches the most significant bit of n _c 452 of digital input 154 and the pulse reaches the tap selected by the least significant bit of n _d 450 of digital input 154, an output flip-flop 410 is reset and the output pulse goes low.

It will be appreciated that a resolution using any number of bits n450 may be used, including a wide range of n _c 452 and n _d 454 bits. Preferably, the “pulse on” period during which output pulse 156 (power command signal) is on corresponds to the value of digital input 154. This “pulse on” period is preferably the product of the duty ratio represented by the digital input 154 and the switching period (the reciprocal of f _s , the switching period). In order to avoid a very high clock frequency required to accurately establish a pulse-on period with high resolution using only a counter and a comparator, the pulse-on period is obtained by separating two separate pulse-on components separately. It preferably occurs by establishing. By determining the first and second components of the pulse on period for the output signal 156 for a given switching period, the first and second components of the duty ratio for the output signal 156 are efficiently determined.

In the preferred embodiment, the first component of the pulse-on period, i.e., the first portion, is preferably established using a high order ordered bit selection n _c 452 of the digital input 154. Counter 406 preferably counts at a clock frequency of 120 to a value equal to “2” raised to a power of n _c 452. The second component of the pulse-on period, i.e., the second portion, is preferably established using a low-ordered bit selection n _d 454 of the digital input 154. The second component of the pulse on period is preferably established using a delay line 402 having a specified number of flip-flops. The number of flip-flops used is preferably equal to 2 raised to n _d 454. Preferably, the magnitude of the digital value of the n _d 454-bit array determines the number of flip-flop delays that form the second component of the pulse-on period. This hybrid (counter and delay line combination) approach requires a significantly higher frequency for the counter 406 while still maintaining high accuracy for the resulting pulse-on period during which the output signal c (t) 156 is high. Is preferably avoided.

In the exemplary waveform of FIG. 5, the duty ratio of the output pulse is 11/16. The basic delay cell of the ring oscillator 402 of FIG. 4 consists of a single resettable flip-flop. Preferably, the respective delays of cells 416, 418, 420, and 422 and the number of cells in ring 402 determine the switching frequency f _s . Modify any of cells 416, 418, 420, and 422 by inserting an additional delay element between the output of the cell and the input to the subsequent cell to adjust the switching frequency. Can do. The additional delay element can be a standard logic gate or a gate with adjustable delay if switching frequency adjustment, ie synchronization with an external clock, is desired.

The self-oscillating DPWM (Digital Pulse Width Modulator) embodiment shown in FIG. 4 has a simple HDL description, an even number of time slots in a period, and can be stopped and restarted by command (propagation of signals through the ring). And have several desirable properties including a relatively small size. An experimental prototype chip was designed, in which DPWM has 8-bit resolution (n = 8) using a 3-bit counter (n _c = 3) and a long ring of 32 cells (n _d = 5). Was. The PWM 400 preferably operates at a switching frequency of f _s = 1 MHz. The ring preferably oscillates at 2 ^nc f _s = 8 MHz. This 8 MHz signal is preferably used as a system clock for all chips. The experimental results for PWM 400 shown in FIG. 6 show the measured duty ratio of the output pulse as a function of 8-bit digital input 154. The minimum (3.1%) duty ratio and the maximum (97.3%) duty ratio are preferably established at the design stage.

  Generally, the static and dynamic output voltage adjustment capability depends on the characteristics of the A / D converter used. Conventional high speed, high resolution A / D converters consume power and chip area and require precision analog components. In the switching power supply, the detected analog voltage signal is supplied by the switching power converter. This signal generally has a lot of switching noise, which can be a problem for many conventional A / D converters such as the basic flash configuration. Accordingly, the inventors sought an alternative ADC embodiment described below in connection with FIG.

FIG. 7 is a block diagram of a delay line ADC 700 that preferably forms part of the voltage controller 150 of FIG. FIG. 8 is a schematic diagram of delay cell ADC 800 corresponding to delay cells 710, 712, 714, 716, and 718 included in delay line ADC 700 of FIG. An embodiment of the timing waveform of the embodiment of FIG. 7 of delay line ADC 700 is shown in FIG. In this disclosure, the name “delay cell 800” will generally be used when referring to a delay cell. Where a particular delay cell is indicated, a reference numeral specifying that delay cell will be used. Preferably, each delay cell 800 has an input 804, an output 810, and a reset input R812. Preferably, cell output 810 is reset to zero when reset input 812 is active high. In a preferred embodiment, an array 740 of delay cells 800 (preferably comprising logic gates) receives the sensed analog voltage 108. Thus, for each cell in array 740, V _sense 108 = V _DD .

The preferred embodiment of the delay line ADC700 converter is based on the principle that the propagation delay of a CMOS (complementary metal oxide semiconductor) logic gate increases when the gate supply voltage decreases. For the first array (to the first order), as a function of the power supply V _DD , the propagation delay t _{d of the} signal through the CMOS logic gate is

によって与えられる。ここで、Ｖ_ｔｈはＣＭＯＳデバイスのしきい値電圧であり、Ｋは、デバイス／処理パラメータおよびゲートの容量性負荷によって決まる定数である。明確に、Ｖ_ＤＤが増加すると伝播遅延が短くなる。しきい値Ｖ_ｔｈより大きい電源の場合、遅延はほぼＶ_ＤＤに逆比例する。

Given by. Where V _th is the threshold voltage of the CMOS device and K is a constant determined by the device / processing parameters and the capacitive load of the gate. Clearly, the propagation delay decreases as V _DD increases. For power supplies greater than the threshold _Vth , the delay is approximately inversely proportional to V _DD .

To perform the conversion, a test signal 704 is propagated through the cell array 740 at the beginning of the switching cycle. After a fixed conversion time interval (preferably equal to (6/8) T _s in the example waveform of FIG. 9), taps t ₁ 728 to t ₈ 736 are sampled by the “sample” signal 738. Preferably, the “sample” signal is a clock pulse for a series 750 of D-type flip-flops 720, 722, 724, and 726. The results of flip-flop outputs q ₁ 752 to q ₈ 758 are preferably communicated to digital encoder 730 to generate digital error signal 152. Preferably, all cells in delay line 700 are reset using the last part of the switching cycle to prepare for the next conversion cycle.

As V _sense 108 increases, cell delay t _d decreases and test pulse 704 propagates further through cell array 740. Conversely, as V _sense 108 decreases, cell delay t _d increases and test pulse 704 propagates only to a small number of cells 800 in cell array 740. The sampled tap outputs (q ₁ -q ₈ ) give the A / D conversion result in the “thermometer” digital code. For example, for the case shown by waveform 900 in FIG. 9, the test pulse propagates from taps t ₁ to t ₆ but not to taps t ₇ and t ₈ , so the flip-flop digital outputs (q ₁ , q ₂ , Q ₈ ) is equal to 11111100.

Ideally, V _sense 108 is equal to V _ref 106 and the test pulse 704 propagates to the first half 760 of the tapped delay cell. In the embodiment of FIG. 7, this zero error case corresponds to a flip-flop output equal to (q ₁ , q ₂ , q ₃ , q ₄ , q ₅ , q ₆ , q ₇ , q ₈ ) = 11110000. Preferably, encoder 152 converts the array of flip-flop outputs 770 into digital information encoded in a more useful form. In the preferred embodiment, this more useful form is the digital error signal 152.

In the preferred embodiment, the digital error signal 152 provides a difference between V _sense 108 and V _ref 106, i. The desired steady state operation of the power supply corresponds to a zero value of the digital error signal 152. Preferably, encoder 730 provides a digital error signal 152 having a digital value whose magnitude is proportional to the difference between the analog voltages of V _sense 108 and V _ref 106. Table 1 and the following discussion describe the encoder 730 in more detail. “Digital error magnitude” was discussed earlier in this disclosure. For consistency of terminology, the term “magnitude of digital error” is included in Table 1. However, the entries in the table are represented in decimal form for convenience.

図１４は、図７の遅延線ＡＤＣ７００に含まれる変換器７３０の機能のブロック図である。好ましい実施形態において、符号化器７３０は、入力として、遅延線ＡＤＣ７００の温度計符号７７２を受け取り、符号化されたデジタル出力１５２を出力する。温度計符号７７２は、フリップフロップ出力の配列７７０に含まれるデジタル値の配列である。温度計符号は、識別ベクトル７７６およびオーバフロー指示器７７８を符号化器７８４に供給する識別器ブロック７７４に送られるのが好ましい。その後、符号化器ブロックはデジタル出力１５２を供給する。

FIG. 14 is a block diagram of functions of converter 730 included in delay line ADC 700 of FIG. In the preferred embodiment, encoder 730 receives as input a thermometer code 772 of delay line ADC 700 and outputs an encoded digital output 152. The thermometer code 772 is an array of digital values included in the array 770 of flip-flop outputs. The thermometer code is preferably sent to an identifier block 774 that provides an identification vector 776 and an overflow indicator 778 to an encoder 784. The encoder block then provides a digital output 152.

  The second and third columns of Table 1 specify input and output for encoder 730. Since this is a simple binary transformation from one encoding scheme to another, the encoder can be implemented using behavioral HDL and synthesis techniques. . However, other conversion mechanisms can be used. It will be appreciated that the data in Table 1 is exemplary. Different voltage ranges of Vsense may be associated with the digital values in columns 2 and 3 for one or more entries in Table 1.

In the preferred embodiment of the delay line ADC 700, the length of the delay line array 740 is advantageous for the analog / digital conversion characteristics to determine a reference voltage value centered there. The number of cells 800 and the delay of each cell 800 preferably determine the range (ΔV _O ) _{max of} the delay line ADC 700 and the effective LSB voltage resolution. In the experimental prototype chip, the delay line length and cell delay were designed (by simulation) to have the values V _ref ≈2.5 V, ΔV _O ≈40 mV. Eight cells 800, each with an associated tap, provide an A / D voltage conversion range (ΔV _O ) _max = (8 + 1) ΔV _O ≈360 mV.

Some advantages of the preferred delay line ADC 700 are that its basic configuration does not require any precision analog components and can be implemented using standard digital logic gates. Therefore, the delay line ADC 700 is sufficiently standardized and can be based on the HDL description. With delay line ADC 700, sampling at high switching frequencies (within a range of hundreds of KHz to several MHz) can be easily achieved using integrated circuits made using state-of-the-art sub-micron CMOS processing. it can. Further, the preferred embodiment of the delay line ADC 700 has a built-in noise immunity that allows the sampling to be efficiently averaged between the input analog signal V _sense 108. Arises from the possibility of extending over the majority of the switching period. Accordingly, the digital output 152 is preferably unaffected by sharp noise spikes in the output voltage 104 of the power converter 200.

A conversion characteristic 1000 measured for the prototype delay line ADC 700 is shown in FIG. The shaded portion of the characteristic (plot) 1000 indicates the voltage at which the digital output code 152 takes one of two consecutive values. The characteristic 1000 shows a certain degree of non-linearity, but is monotonous. Also, the width of the code “bin” is approximately equal to the desired ΔV _O value. In voltage regulator applications, A / D defects (sign flipping and non-linearity) have little impact on closed loop operation. During steady state operation, the output voltage 104 preferably converges to a voltage corresponding to the zero value of the digital error signal 152. For a set of 10 prototype chips, we found that the average zero-error bin width is equal to 53 mV with a standard deviation of 3.6 mV. The measured reference voltage was V _ref = 2.7 V, but the measured current consumption of the delay line ADC 700 was about 10 μA.

The basic delay line ADC 700 results in a reference voltage V _ref 106 that is indirectly determined by the length of the delay line 700 and indirectly by the delay versus voltage characteristics of each delay cell 800. In fact, due to processing and temperature variations, the reference value obtained with the basic delay line A / D configuration is difficult to control precisely. Variations in the effective V _ref 106 cause variations in the regulated output voltage 104 that may be performed suboptimally by the regulator 100. Therefore, the delay line ADC 700 is preferably calibrated before being implemented in the operating voltage regulator 100. In other words, the degree of delay of the delay line ADC 700 is preferably correlated with a known voltage value. This established correlation is preferably used during subsequent operation of controller 150 to ensure that the degree of signal propagation delay of test pulse 704 along delay cell array 740 is associated with a particular voltage.

11 is a block diagram of a preferred digital calibration scheme 1100 for the delay line ADC 700 of FIG. 7, and FIG. 12 is a plot of timing waveforms for the calibration scheme 1100 of FIG. A preferred calibration technique is to apply a stable and precise calibration reference voltage 1102, preferably generated using standard bandgap techniques, to the input 782 of the delay line ADC 700 and the actual analog input voltage V _sense 106. Digitally subtracting the conversion result from the value of the digital output 152 obtained when. The calibration reference voltage 1102 need not be so, but may be the same as the reference voltage 106 discussed in connection with FIGS. 1, 3, and 7.

In the preferred embodiment, two conversions are performed within each switching period. In one half of the switching period, the calibration reference voltage V _ref 1102 is preferably applied to the delay line ADC700. The reference conversion result e _ref 1108 is ideally zero, but the actual value may have a finite magnitude due to processing and temperature variations. The reference conversion error value e _ref 1108 is preferably stored in the register 1106. In the second part of the period, V _sense 108 is preferably applied to delay line ADC 700. Preferably, delay line ADC 200 provides an uncalibrated digital output 152 corresponding to the analog voltage value of V _sense 108 as described in connection with FIG. The uncalibrated output 152 is then preferably subtracted from e _ref 1108 to obtain a calibrated digital output 1152. In the preferred embodiment where calibration is used, the calibrated digital output 1152 is used in place of the uncalibrated digital output 152, thereby providing greater accuracy for the correction of the output voltage V _O 104. Herein, the terms “calibrated digital output”, “corrected digital output”, “calibrated digital error signal”, and “corrected digital error signal” are used interchangeably.

  The generation of the reference conversion error value 1108 is not necessary, but can be performed in each switching period. An appropriate frequency for the reference conversion can be selected based on the characteristics of the particular voltage controller 150. Alternatively, other calibration schemes can be implemented with the present invention, including but not limited to schemes based on the delay locked loop (DLL) principle.

The controller 150 described herein was designed and implemented in a standard 0.5 micron CMOS process. The chip design was described using HDL. The design was reduced to a standard cell gate using synthesis and timing verification tools. A preferred embodiment of delay line ADC 700 occupies less than 0.2 mm ² (square millimeters). The total effective chip area for controller 150 is preferably less than 1 mm ² .

  In a preferred embodiment, compensator 300 includes three tables (for e (n), e (n-1), and e (n-2)). Preferably, the digital error signal 152 generated by the delay line ADC 700 may have nine possible values. In the preferred embodiment, the outputs from lookup tables 302, 304, and 306 have 8 bits, 9 bits, and 8 bits, respectively. Therefore, the total storage capacity of the on-chip memory is preferably 234 bits. However, in an alternative embodiment, the number of compensator 300 tables, the number of bits in the lookup table, the number of possible values of the digital error signal 152, and the total number of bits in the storage capacity of the on-chip memory are preferred as described above It will be appreciated that there may be fewer or more of these items disclosed in the embodiments.

  In the preferred embodiment, the bit length of the table entry is determined by the range of values of error signal 152 (± 4) and by the arrangement of pole zeros with the desired accuracy. Adder 318 preferably generates a 10-bit signed value, which is added to 8-bit duty cycle signal 154 by eliminating the sign bit and by truncating the least significant bit. It is preferably reduced.

To illustrate the closed loop operation of the preferred embodiment, a controller chip was used with the synchronous buck converter shown in FIG. The input voltage V _g 102 was set between 4V and 6V, the output voltage 104 was adjusted to V _O = 2.7V, the load current was set between 0A and 2A, and the switching frequency was set to 1 MHz. The filter parts used had values of L210 = 1 μH (microhenry) and C212 = 100 μF (microfarad). Based on the standard averaging model of the converter 200, the compensator 300 was designed using a pole zero matching method to achieve a loop crossover frequency of about 50 KHz and a phase margin of about 50 °. When the converter 200 is powered up, the converter loads the table entry from the external memory 160 into the compensator 300, then samples the output voltage 104 and generates a pulsed waveform c (t) 156. Begin.

FIG. 2 is a plot of output voltage 104 and output current transient response obtained for regulator 100 of FIG. The transient waveform of 50% to 100% load in the experiment is shown in FIG. In a preferred embodiment, V _O 104 remains within the range 202 of (ΔV _O ) _max . FIG. 13A is a plot of measured load voltage 104 against load current for voltage controller 100 of FIG. FIG. 13B is a plot of measured load voltage 104 versus power supply 102 for voltage controller 100 of FIG.

  A novel digital voltage controller has been described. It is understood that the specific embodiments shown in the drawings and described in this specification are for purposes of example and should not be construed as limiting the invention as set forth in the appended claims. Should be. Further, it will be apparent to those skilled in the art that many of the specific embodiments described can be used and numerous modifications can be made without departing from the inventive concepts. It will also be apparent that the methods detailed can in many instances be performed in a different order, or that equivalent structures and processes can be substituted for the various structures and processes described. . Accordingly, the present invention is to be construed as including each and every feature and novel combination of features that is present in and / or possessed by the invention described herein. It is.

1 is a block diagram of a voltage regulator including a digital voltage controller according to a preferred embodiment of the present invention. 2 is a plot of output voltage and output current transient response obtained using the regulator of FIG. It is a block diagram of operation | movement of the digital voltage controller of FIG. FIG. 2 is a block diagram of a pulse width modulator included in the digital voltage controller of FIG. 1. 5 is a plot of signal waveform values for the pulse width modulator of FIG. 5 is a plot of duty cycle output as a function of digital input for the pulse width modulator of FIG. FIG. 2 is a block diagram of a delay line ADC included in the voltage controller of FIG. 1. 8 is a schematic diagram of a delay cell ADC corresponding to a delay cell included in the delay line of FIG. 8 is a timing waveform plot for a tap signal of the delay line ADC of FIG. 8 is a plot of conversion characteristics of the delay line ADC of FIG. FIG. 8 is a block diagram of a preferred digital calibration scheme for the delay line ADC of FIG. 12 is a plot of timing waveforms for the calibration scheme of FIG. FIG. 13A is a plot of measured load voltage adjustment versus load current for the voltage regulator of FIG.

FIG. 13B is a plot of measured load voltage adjustment versus power for the voltage regulator of FIG.
FIG. 8 is a block diagram of functions of an encoder 730 included in the delay line ADC 700 of FIG. 7.

Claims (16)

An analog / digital converter (ADC) that converts analog input to digital input;
A compensator (300) including a look-up table (302) and determining a digital control signal (154) based on the digital error signal;
A voltage for controlling an output voltage of a switching power converter having a switching period, comprising a modulator (400) operative to provide a power control signal (156) in response to the established digital control signal A controller (150),
The analog / digital converter (ADC) includes a delay line analog / digital converter (700) including a delay cell array (740), and the delay cell array (740) includes a plurality of delay line cells;
In order to sample the detection voltage once every switching period of the switching power converter, a detection voltage source ( 108 ) connected to the delay line analog / digital converter is provided ,
A reference voltage source ( 106 ) connected to the delay line analog / digital converter is provided ;
A test voltage source (704) connected to the delay line analog / digital converter is provided ;
Wherein the detection voltage and the reference voltage, the synchronization with the switching period of the switching power converter, selectively said switch supplies the delay line analog / digital converter is provided,
A plurality of taps (752, 754) for measuring the degree of propagation of the test signal through the delay line are provided,
The degree of propagation of the test signal through the delay line when the reference voltage is supplied to the delay line analog / digital converter, and the detection voltage when the reference voltage is supplied to the delay line analog / digital converter. the difference between the degree of propagation of the test signal through the delay line, the switching fixed at the power converter within a switching period, the calibrator supplies the digital error signal representing a difference between the sensing voltage and the reference voltage provided, in order to determine the digital control signal, said digital error signal is provided to the compensator,
Each of the delay cells of the delay line analog / digital converter is reset within the switching period of the switching power converter ;
Voltage controller, characterized in that.   The controller according to claim 1, wherein the controller does not include passive electronic components.   The controller of claim 1, wherein the controller is implemented entirely using digital logic gates.   The controller of claim 1, wherein all energy storage components in the controller are digital logic gates. The controller of claim 1, wherein the delay line analog / digital converter is operative to provide a thermometer code output (772) representative of the degree of propagation. The controller of claim 1, wherein the reference voltage source comprises a bandgap voltage generator. The delay line analog to digital converter comprises an encoder (730) that operates to convert the thermometer code into an encoded digital output that is used to determine the digital error signal. The controller according to claim 5 .   The controller of claim 1, wherein the modulator is a digital pulse width modulator.   The controller of claim 1, wherein the modulator comprises a counter (406) that operates to determine a first component of a pulse-on period for the power control signal.   The controller of claim 1, wherein the modulator comprises a delay line (402) that operates to determine a second component of a pulse-on period for the power control signal. The modulator is
A counter that operates to determine a first component of a pulse-on period for the power control signal;
The controller according to claim 1, further comprising a delay line that operates to determine a second component of a pulse-on period for the power control signal. A method for controlling an output voltage of a switching power converter having a switching period, the method comprising:
Comparing a first voltage associated with the converter output voltage with a second voltage associated with a reference voltage (700);
Generating a digital error signal representative of the result of the comparison;
Providing a power control signal (156) representative of the generated error signal;
The comparing step includes:
Receiving the output voltage of the switching power converter once every switching period of the switching power converter;
In synchronism with the switching period of the switching power converter, and supplying the output voltage to the power input of the delay cell array of the delay line analog / digital converter, a pulse of the delay line analog / digital converter in the first pulse signal Driving to determine an uncalibrated error value based on measuring a degree of propagation of the first pulse signal through the delay cell array of the delay line analog / digital converter ;
In synchronization with the switching period of the switching power converter, the reference voltage is supplied to power inputs of a plurality of delay cells of the delay line analog / digital converter, and the delay line analog / digital converter is supplied with a second pulse. Determining a reference error value based on pulse driving with a signal and measuring a degree of propagation of the second pulse signal through the delay cell array of the delay line analog / digital converter ;
Determining a difference between the uncalibrated error value and the reference error value and providing the digital error signal, wherein the digital error signal is provided to a compensator to determine the power control signal. ,
The comparing, generating, and supplying steps are performed entirely using digital logic gates ;
Each delay cell of the delay cell array of the delay line analog / digital converter is reset within the switching period of the switching power converter.
A method characterized by that. The method of claim 12 , wherein the comparing step includes powering an array (740) of a plurality of delay cells using the converter output voltage. The method of claim 12 , wherein the step of providing includes determining a digital control signal from the generated error signal according to a control algorithm. The method of claim 14 , wherein the determining step includes selecting a lookup table entry based on the value of the generated error signal. The method of claim 12 , wherein the providing step includes determining a duty ratio from the generated error signal according to a control algorithm.

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