JP4544242B2 - Display device - Google Patents

Description

  The present invention relates to a display device and a manufacturing method thereof, and more specifically, to a liquid crystal display device and a manufacturing method thereof.

Liquid crystal display devices are widely used in notebook personal computers, display devices for car navigation, personal digital assistants (PDAs), mobile phones, etc., taking advantage of their thinness and low power consumption. . This liquid crystal display device can be broadly divided into a transmissive type that performs display by controlling light from a backlight, a reflective type that reflects external light such as sunlight, and recently both of them. There is a display device called a combination type having the above characteristics.
These display devices are required to have low power consumption due to their use, and therefore, a high aperture ratio is required so as to maximize the utilization efficiency of the backlight. In the combined type, since a transmissive part and a reflective part are formed in the same pixel and a multi-function is provided in the pixel, it is necessary to use a space as effectively as possible.

When an image is displayed on the liquid crystal display device, a scanning pulse is applied from a scanning line to a switching element provided in each pixel, for example, a TFT (Thin Film Transistor), and turned on / off to select a display pixel. Then, a signal corresponding to the image signal is applied to the data line, applied to the electrodes sandwiching the liquid crystal via the TFT source and drain, and the light incident on the liquid crystal is modulated to display an image.
After the voltage corresponding to the image signal is written to each pixel, the charge due to the voltage applied to the liquid crystal electrode leaks and changes through the liquid crystal and the switching element within the period until the next writing operation. In order to guarantee the display image quality, it is necessary to maintain the applied voltage. Therefore, in a liquid crystal display device, a sufficient auxiliary capacity (CS) is usually configured as compared with the amount of leakage.

FIG. 1 shows an example of an equivalent circuit diagram of a conventional liquid crystal display device, and FIG. 2 shows a plan view of the configuration of the liquid crystal display device shown in FIG.
FIG. 1 shows an equivalent circuit of 2 × 3 pixels. In the equivalent circuit, one pixel includes a liquid crystal element and electrodes sandwiching the liquid crystal element, a transistor Tr that is a switching element, and an auxiliary capacitor CS. Ccl1... Ccl6 indicate the capacitance of a liquid crystal capacitor including a liquid crystal element, a display electrode sandwiching the liquid crystal element, and a common electrode, and CS1... CS6 indicate a capacitance value of an auxiliary capacitor (also referred to as a storage capacitor) of each pixel.

The plurality of scanning lines WLn−1, WLn, WLn + 1 are arranged in parallel, and are connected to the gate electrodes of the transistors Tr1, Tr4, Tr2, Tr5, Tr3, Tr6 made of, for example, TFTs, respectively. / OFF is controlled to select a pixel.
From the data signal lines BLn-1, BLn, BLn + 1 arranged in parallel, a voltage corresponding to the image signal is applied to each pixel. The data signal lines BLn-1, BLn, BLn + 1 are connected to, for example, the source region of the transistors Tr1, Tr2, Tr3, or Tr4, Tr5, Tr6, and are selected by the scanning lines WLn-1, WLn, or WLn + 1. While charging the auxiliary capacitor CS to the pixel, a voltage is applied to the electrodes on both sides of the liquid crystal element to modulate the light incident on the liquid crystal element and display an image.

  FIG. 2 shows a configuration diagram of a scanning line, a data signal line, and one pixel formed on a transparent substrate. As shown in FIG. 2, the auxiliary capacitance line CSLn-1 is used as one electrode, and the auxiliary capacitance CS1 is formed thereon. One impurity region, for example, the source region of the transistor Tr1 is connected to the data signal line BLn-1 through a conductive material deposited in the contact hole H1. Further, through the conductive material deposited in the contact holes H2 and H3, the other impurity region of the transistor Tr1, for example, the drain region is the other electrode of the auxiliary capacitor CS1, for example, a semiconductor electrode, and an upper ITO electrode (not shown) Connected to.

Usually, the transistors Tr1,..., Tr6 use N-channel thin film transistors TFT. That is, N-type source and drain impurity regions implanted with phosphorus (P) or the like are formed in the semiconductor thin film on both sides of the gate electrode, and when a positive voltage higher than a threshold value is applied to the gate electrode (scanning line), An N channel composed of an N-type inversion layer is formed between the drains, and the source and the drain are made conductive. That is, the transistor is turned on. On the other hand, when a voltage lower than the threshold value is applied to the gate electrode (scanning line), a channel that conducts the source and the drain is not formed, and the transistor is turned off.
In addition, the auxiliary capacitor CS1 can normally form the largest capacitor. It is formed of a semiconductor film (layer) / insulating film / metal MOS structure. In FIG. 2, for example, the auxiliary capacitance CS1 is formed by the auxiliary capacitance line CSLn-1 (metal), the gate insulating film constituting the transistor Tr1, and the N-type semiconductor film into which the phosphorus or the like is implanted. Hereinafter, such a MOS capacitor is expressed as an N-type MOS structure.

When the auxiliary capacitance electrode is kept at a constant potential, the auxiliary capacitance portion generally has an N-type MOS structure.
In addition, in the case of common inversion driving in which the auxiliary capacitor electrode is swung in the same phase as the counter electrode, the semiconductor film forming the auxiliary capacitor CS is not formed in an intrinsic state, so that a sufficient capacitance is not formed. That is, it is common to contain phosphorus (N +) or boron (P +) at a high concentration.

In the conventional method described above, phosphorus (N +) or boron (P +) is injected only once at a high concentration, and the manufacturing cost can be reduced.
However, since the above structure requires an independent auxiliary capacitance line, there is a problem that the aperture ratio is lowered.
In view of this, a CS-on-gate structure has been proposed in which the storage capacitor line is also used as a scanning line (gate line) in the previous stage or the subsequent stage.

3 shows another example of a conventional liquid crystal display device, FIG. 3A is an equivalent circuit diagram of the liquid crystal display device, and FIG. 3B is a plan view of the configuration of the liquid crystal display device. . 3A and 3B, the same components as those in FIG. 1 are denoted by the same reference numerals. In addition, overlapping description will be omitted as appropriate.
FIG. 3A shows an equivalent circuit of 2 × 2 pixels. In FIG. 3A, in place of the auxiliary capacitance lines CSLn−1, CSn, CSn + 1 shown in FIG. 1, auxiliary capacitances CS1, CS4, CS2, CS5 are directly connected to the scanning lines WLn−1, WLn, WLn + 1, respectively. Connected.
FIG. 3B shows a configuration of a scanning line, a data signal line, and one pixel formed on a transparent substrate. Instead of the auxiliary capacitance line CSLn-1 shown in FIG. 2, an auxiliary capacitance CS1 is formed so as to overlap the scanning line WLn.

Also in this case, normally, the transistors Tr1,..., Tr5 use N-channel thin film transistors TFT. The auxiliary capacitor CS1 is also an N-type MOS capacitor. That is, the transistors Tr1,..., Tr5 turn on the transistor when a positive voltage higher than the threshold value is applied to the gate electrode (scanning line), and turn on the transistor when the voltage lower than the threshold value is applied to the gate electrode. Set to the OFF state.
Further, as shown in FIG. 3B, the auxiliary capacitor CS1 is formed of an N-type semiconductor film into which a scan line WLn (metal), a gate insulating film constituting the transistor Tr1, and phosphorus are implanted.
Such a CS-on-gate structure has the advantage of improving the aperture ratio because it is not necessary to form an independent auxiliary capacitance line.

In order to keep the NMOS transistor Tr1 in the off state, the potentials of the scanning lines WLn−1, WLn,... Are normally set to about 0V to −6V. Moreover, in the liquid crystal display device, the transistor Tr1 is held almost OFF during the period for displaying one screen, that is, the scanning line potential is held at 0 V or less.
However, in the CS on-gate structure as shown in FIG. 3, for example, when forming the scanning line (gate line) WLn and the auxiliary capacitor CS1 in the subsequent stage, the scanning line / gate insulation is applied in the state where the above potential is applied. In the N-type MOS structure formed of a film / N-type semiconductor film, a sufficient capacity cannot be obtained.
FIG. 4 is a graph showing the capacitance-voltage characteristics of the N-type MOS structure.
When, for example, −2 V is applied to the scanning lines WLn−1 and WLn shown in FIG. 3B and Tr1 is turned off, CS1 is charged while Tr1 is on. Therefore, the semiconductor electrode of CS1 is The gate voltage that is higher than the scanning lines WLn−1 and WLn and applied to CS1 is a negative voltage. As a result, majority carrier electrons are eliminated from the surface of the semiconductor film, and a depletion layer (and / or an inversion layer) is formed on the surface of the semiconductor film. Is small.
This trend is shown in FIG. When the scanning potential is used at about 1.5 V or less, the N-type MOS capacitor can always ensure only a small capacity.
In order to increase the capacitance value of the auxiliary capacitor CS1, it is necessary to implant phosphorus (N +) or boron (P +) at a high concentration into the semiconductor film electrode of the auxiliary capacitor CS1. By doing so, problems such as a decrease in yield due to an increase in processes and occurrence of defects occur.

5 to 7 show an example of a manufacturing process of a conventional liquid crystal display device.
In FIG. 5A, gate electrodes (scanning lines) 102 a and 102 b to be scanning lines are formed over the glass substrate 101. The material is a metal such as Ta, Cr, Mo, Ti, and Al, and a pattern is formed by wet etching or dry etching through a photoresist process.
In FIG. 5B, a gate insulating film 103 and a semiconductor film (however, referred to as a semiconductor layer in FIG. 5) 104a are formed over the gate electrodes 102a and 102b. Examples of the gate insulating film 103 include a silicon nitride film and a silicon oxide film, and an anodic oxide film obtained by anodizing a gate electrode. As the semiconductor film, an amorphous silicon film, a polysilicon film obtained by crystallizing an amorphous silicon film, a polysilicon film formed directly, or the like is used.

In FIG. 5C, a protective insulating film 105 is formed over the semiconductor film 104a. For the protective insulating film 105, a silicon nitride film, a silicon oxide film, or the like is used.
In FIG. 5D, resists 107a and 107b are formed in a self-aligning manner using the gate electrodes 102a and 102b as light shielding masks. Thereafter, the protective insulating film 105 is removed by wet etching or dry etching. Thereafter, phosphorus (P) or the like is doped at a low concentration using the remaining protective insulating films 105a and 105b as a mask. A portion (region) into which an impurity of the semiconductor film is implanted is denoted as 104b. Here, the semiconductor film 104b is an n ⁻ type semiconductor.

In FIG. 6A, a resist 108 having a shape covering a portion where an LDD region is formed by a pixel transistor is formed. Here, the resist is generally referred to as a protective mask. Thereafter, wet etching or dry etching is performed to remove the remaining protective insulating film 105b in the auxiliary capacitance forming portion.
Thereafter, phosphorus or the like is implanted at a high concentration to metalize the semiconductor film 104b. The metallized portion of the semiconductor film 104b is denoted as 104c.
Here, although not shown, a photoresist process and an implantation process are performed on a portion into which the second doping species (boron or the like) are implanted. Thereafter, heat treatment for activating the doped element is performed as necessary.

  Normally, this wet etching or dry etching is performed by a process having etching selectivity with respect to the semiconductor film 104b. However, when the semiconductor film 104b has a pinhole or the like, the underlying gate insulating film 103 is etched, This portion has a very low breakdown voltage and becomes a current leakage path, which causes a defect such as a point defect. Further, the number of steps for removing the protective insulating film 105b increases, which causes a cost increase.

In FIG. 6B, in order to perform element isolation, the semiconductor film 104b outside the gate electrodes 102a and 102b is removed using means such as photolithography and dry etching.
In FIG. 6C, an interlayer insulating film 109 is formed using a silicon nitride film, a silicon oxide film, or the like. Thereafter, contact holes 110a and 110b are formed using means such as photolithography and wet etching.

In FIG. 7A, a metal film such as Al, Ta, or W is deposited as the connection metal 112 between the data signal lines 111a and 111b and the pixel electrode, and then removed using means such as photolithography and dry etching. Then, a pattern is formed.
In FIG. 7B, the second interlayer insulating film 113 is formed of a silicon nitride film, a silicon oxide film, or the like. Further, a photosensitive organic film, a photosensitive SOG (spin on glass) film, or the like may be used in order to give this layer a planarization effect. Again, a contact hole with the pixel electrode 114 is formed. Thereafter, the pixel electrode 114 is formed using a transparent conductive film such as ITO or IXO.

Thereafter, although not shown, a corresponding color filter substrate prepared separately and this TFT substrate are overlapped, an assembly process is performed with a liquid crystal layer interposed therebetween, and a polarizing plate is attached to complete a liquid crystal display device.
As described above, in the conventional manufacturing method, a special process is required to complete the auxiliary capacitance structure, which causes an increase in cost and increases a leakage current that causes defects. Conventionally, there is a problem that a yield drop occurs due to such an increase in processes and occurrence of defects.

The above is a conventional example of a bottom gate type transistor in which a scanning line (gate electrode) is formed below a semiconductor film (layer), and a top gate type transistor in which a scanning line (gate electrode) is formed above the semiconductor film. However, a problem occurs in the manufacturing method.
8 and 9 show a conventional example of a method for manufacturing a liquid crystal display device having a top-gate transistor structure.
As shown in FIG. 8A, a base layer 122 and a semiconductor film 123a are formed over a glass substrate 121. For the base layer 122, for example, a silicon nitride film or a silicon oxide film is used. As the semiconductor film 123a, an amorphous silicon film, a polysilicon film obtained by crystallizing an amorphous silicon film, a polysilicon film formed directly, or the like is used.

As shown in FIG. 8B, part of the semiconductor film 123a is removed using means such as photolithography or dry etching in order to secure a region for element isolation.
Then, a gate insulating film 124 is formed over the semiconductor film 123a. Examples of the gate insulating film 124 include a silicon nitride film and a silicon oxide film.
Subsequently, gate electrodes 125a and 125b are formed in a region for forming the transistor TFT and a region for forming the auxiliary capacitor.
Next, phosphorus or the like is doped at a low concentration in a self-aligning manner using the gate electrodes 125a and 125b as an implantation mask. The implanted portion of the semiconductor film is an n ⁻ type semiconductor and is denoted as 123b.

As shown in FIG. 8C, a resist 126 is formed so as to cover the region where the LDD region is formed by the pixel transistor TFT. The semiconductor film 123b is metallized by implanting phosphorus or the like at a high concentration in another region. The metallized portion of the semiconductor film 123b is denoted as 123c.
Although not shown here, a photoresist process and an implantation process are performed in accordance with the portion into which the second dope species (boron or the like) are implanted. Thereafter, heat treatment for activating the doped element is performed as necessary.

In FIG. 9A, an interlayer insulating film 127 is formed using a silicon nitride film, a silicon oxide film, or the like. Thereafter, contact holes 128a and 128b are formed using means such as photolithography and wet etching.
In FIG. 9B, a metal film such as Al, Ta, or W is deposited as the connection metal 130 between the data signal lines 129a and 129b and the pixel electrode 132, and thereafter, using means such as photolithography and dry etching. Remove to form a pattern.
Subsequently, a second interlayer insulating film 131 is formed using a silicon nitride film, a silicon oxide film, or the like. Further, a photosensitive organic film, a photosensitive SOG (spin on glass) film, or the like may be used in order to give this layer a planarization effect. Again, a contact hole with the pixel electrode 132 is formed. Thereafter, the pixel electrode 132 is formed using a transparent conductive film such as ITO or IXO.
Thereafter, although not shown, a corresponding color filter substrate prepared separately and this TFT substrate are overlapped, an assembly process is performed with a liquid crystal layer interposed therebetween, and a polarizing plate or the like is further attached to complete a liquid crystal display device.

  In the structure shown in FIGS. 8B and 8C, the gate electrode 125b is formed in the region where the auxiliary capacitance is formed. Therefore, impurities cannot be injected into the semiconductor film 123a below the gate electrode 125b and metallization can be performed. There is no problem. In the range of conventional methods, this problem can be solved by increasing the number of steps of removing the mask after the mask is formed and implanted in the initial stage, or as an independent auxiliary as shown in FIG. It is necessary to form a capacitance line.

  The present invention has been made in view of the above problems, and an object thereof is to provide a display device including a high aperture ratio and a large capacity auxiliary capacity, and a method for manufacturing the display device without increasing the number of manufacturing steps. is there.

A display device according to the present invention includes a plurality of scanning lines and signal lines intersecting each other, and pixels arranged at each intersection of both wirings on an insulating substrate, each pixel including at least a pixel electrode, a thin film transistor for driving this through the wirings drawn out from the source or drain of the thin film transistor of the semiconductor film, holds the written signal charges to the pixel electrode from the signal line, different said thin film transistor and the conductivity type and a storage capacitance of the MOS structure, in the above display device in which the auxiliary capacitance line of the auxiliary capacitance consists of structure which also serves as the front or rear stage of the scanning lines, a pair of electrodes configured to sandwich the insulating film of the storage capacitor wiring of the storage capacitor one electrode extends out of the different drawn out wiring and conductive from the source or drain of the thin film transistor Made from the conductive layer, wherein is directly connected to the junction between the auxiliary capacity wiring and the led out from the source or drain of the thin film transistor wiring, the connection electrode for connecting the wiring of the wiring and the auxiliary capacitance of the thin film transistor is provided It has been.

Further, the wiring of the one electrode of the auxiliary capacitor and the wiring drawn from the source or drain of the thin film transistor are made of a semiconductor film formed in the same layer.
The connection electrode is formed of a conductive material filled in a contact hole formed in an upper layer of the wiring of the one electrode of the auxiliary capacitor and the wiring extracted from the source or drain of the thin film transistor. The wiring of the thin film transistor is connected.
The contact hole is one contact hole formed on the junction, and is drawn from the wiring of the one electrode of the auxiliary capacitor and the source or drain of the thin film transistor by a conductive material filled in the contact hole. Connect to the specified wiring.
The conductive material is formed of the same conductive material as the signal line.
The auxiliary capacitor is an auxiliary capacitor having a MOS structure having a conductivity type different from that of the thin film transistor, and the auxiliary capacitor includes the other electrode configured by sandwiching the insulating film with respect to the one electrode, the electrodes that share the scan lines.
The connection electrode is provided in the pixel.
The conductivity type of the semiconductor film constituting the thin film transistor is N type, the conductivity type of the semiconductor film forming the wiring of the one electrode of the auxiliary capacitor is P type, and the junction portion forms a PN junction.
The thin film transistor includes first and second thin film transistors connected in series with the scanning line as the same gate.

According to the present invention described above, in the semiconductor film, the conductivity type of the source / drain region of the transistor (in other words, the conductivity type of the channel between the source and drain is reversed to the conductivity type of the semiconductor film region forming the auxiliary capacitance). When the source / drain region of the transistor and the conductivity type of the channel are N-type, the semiconductor film region that forms the auxiliary capacitance is set to P-type, whereby the scan line voltage (OFF) that turns off the N-channel transistor ( A large capacitance can be obtained by applying a zero or negative voltage to the auxiliary capacitor of the P-type MOS structure, and the semiconductor forming the auxiliary capacitor when the source / drain regions of the transistor and the channel conductivity type are P-type. The same effect can be achieved if the membrane region is made N-type.
Further, in order to form the above structure, it is sufficient to inject impurities of different types when the impurities are implanted, so that the manufacturing process is not increased.
Furthermore, since a sufficient capacitance can be obtained with the above structure, the mask for protecting the channel formation region of the semiconductor film facing the scanning line must be removed by etching when impurities are implanted into the auxiliary capacitance formation region of the semiconductor film. Since there is no, there are fewer factors causing defects.

According to the present invention, a structure of a switching transistor and an auxiliary capacitor, which has not been possible in the past, becomes possible, the auxiliary capacitance increases, and the aperture ratio improves.
In manufacturing the display device according to the present invention, it is possible to form an effective auxiliary capacitor without increasing the number of processes or with a small number of processes.
In addition, since the number of times that the surface of the semiconductor film is exposed to wet etching or dry etching is reduced, it is possible to suppress the occurrence rate of defects such as a leakage current between the semiconductor film and the auxiliary capacitance gate electrode, and the yield is improved.
According to the present invention, the non-transmissive region is reduced, and the aperture ratio can be greatly improved. Accordingly, the backlight luminance can be reduced, and the power consumption can be reduced.

Hereinafter, embodiments of a display device and a method for manufacturing the same according to the present invention will be described with reference to the accompanying drawings, taking a liquid crystal display device as an example.
First Embodiment FIGS. 10A and 10B are diagrams showing an equivalent circuit and a configuration of a liquid crystal display device according to the present embodiment. The circuit layout of FIG. 10A is the same as the conventional example shown in FIG. 3A, except that in FIG. 10A, auxiliary capacitors (also referred to as holding capacitors) PCS1, PCS2, PCS4, PCS5. The semiconductor film has a conductivity type different from that of the transistors NTr1, NTr2, NTr4, and NTr5. In this example, the transistors NTr1, NTr2, NTr4, and NTr5 are formed of N-channel TFTs, and the auxiliary MOS capacitors are formed of a P-type MOS structure. That is, the auxiliary MOS capacitor is formed by the scanning line (metal), the gate insulating film, and the P-type semiconductor film.
Further, this conductivity type may be changed to form a transistor with a P-channel TFT and an auxiliary capacitor with an N-type MOS structure.

FIG. 10A shows an equivalent circuit of 2 × 2 pixels. In FIG. 10A, a plurality of scanning lines WLn−1, WLn, WLn + 1 are arranged in parallel and connected to the gate electrodes of transistors NTr1 and NTr4 or NTr2 and NTr5 made of, for example, N-channel TFTs. Then, ON / OFF of each transistor is controlled to select a pixel to operate.
The auxiliary capacitors PCS1, PCS2, PCS4, and PCS5 of the P-type MOS structure formed of the scanning line / gate insulating film / P-type semiconductor film are directly connected to the scanning lines WLn-1, WLn, WLn + 1, respectively.
Further, data signal lines BLn−1, BLn, and BLn + 1 that are arranged in parallel and apply a voltage according to an image signal to each pixel are one impurity region of the transistors NTr1, NTr2, or NTr4, NTr5, for example, A voltage is applied to the electrode of the liquid crystal element while charging the auxiliary capacitor PCS having a P-type MOS structure for the pixel selected by the scan line WLn−1, WLn, or WLn + 1, connected to the source region, The light incident on the liquid crystal is modulated to display an image.

FIG. 10B is a plan view of the configuration of the scanning lines, data signal lines, and one pixel formed on the transparent substrate. 10B, the P-type MOS auxiliary capacitor PCS1 shown in FIG. 10A is formed on the scanning line WLn via a gate insulating film (not shown).
One impurity region, for example, the source region (a wiring film or a wiring layer drawn from the source region) of the N-channel transistor NTr1 is connected to the data signal line BLn-1 through the conductive material deposited in the contact hole H1. Yes. Further, the other impurity region, for example, the drain region of the N-channel transistor NTr1 is connected to the semiconductor film of the auxiliary capacitor PCS1 and an upper ITO electrode (not shown) through a conductive material filled in the contact holes H2 and H3. ing.

FIG. 11 is a schematic cross-sectional view of the pixel structure shown in FIG. 10B. FIG. 10B is a cross-sectional view along the semiconductor film pattern from the data signal line to the auxiliary capacitor. Yes. However, the TFT transistor portion is not shown in a double gate structure in which transistors are arranged in series due to space limitations, and has a single gate structure.
In FIG. 11, scanning lines 1 a and 1 b (WLn−1 and WLn) are formed on a transparent substrate (not shown), and a gate insulating film 2 is formed so as to cover the scanning lines 1 a and 1 b (WLn−1 and WLn). Films 3, 4, 5, and 6 are formed to form TFT transistors and auxiliary capacitors.
In the semiconductor film 3, for example, a wiring film is formed of an N ⁺ type semiconductor film (region) into which high concentration phosphorus (P) is implanted, and a wiring film drawn from the source / drain is formed. For example, a wiring film 4 is formed of a P ⁺ type semiconductor film (region) into which boron (B) at a high concentration is implanted, and constitutes a wiring film drawn from the i-type semiconductor film 6 of the auxiliary capacitance electrode. The center of the semiconductor film 5 is a so-called i-type (intrinsic semiconductor) semiconductor film in which no impurity is implanted, and both sides thereof are LDD regions into which, for example, phosphorus (P) is implanted at a low concentration. The semiconductor film 5 constitutes a channel region of the TFT transistor, and FIG. 11 shows an example formed with an N channel. 6 is a so-called i-type semiconductor film in which no impurity is implanted.
7a and 7b are stopper films formed so that the i-type semiconductor films 5 and 6 thereunder are not implanted with impurities, and 8 is an interlayer insulating layer.

In the interlayer insulating layer 8, a contact hole is formed above the wiring film of the N ⁺ type semiconductor film (region) 3 and the wiring film of the P ⁺ type semiconductor film (region) 4, and a conductive material in the contact hole However, the connection electrode 10 connecting the wiring film of the N ⁺ type semiconductor film 3 and the wiring film of the P ⁺ type semiconductor film 4 is formed, and the data signal line 9 is formed.
The gate electrode 1a, the gate insulating film 2, and the semiconductor films 4 and 5 constitute an N-channel TFT transistor. On the other hand, the gate electrode 1b, the gate insulating film 2, and the semiconductor films 4 and 6 constitute a P-channel transistor. The capacity of the P-channel transistor is used as an auxiliary capacity.

When the wiring film of the N ⁺ type semiconductor film (region) 3 and the wiring film of the P ⁺ type semiconductor film (region) 4 are directly connected, the N ⁺ type semiconductor film 3 and the P ⁺ type semiconductor film are connected. 4, a PN junction is generated, and a potential loss occurs. Therefore, it is desirable to connect the N ⁺ type semiconductor film 3 to the P ⁺ type semiconductor film 4 through a metal. In this embodiment, the contact hole connected to the N ⁺ type semiconductor film 3 and the contact hole connected to the P ⁺ type semiconductor film 4 are filled with metal to form the connection electrode 10, and the two are connected.
The material of the connection electrode 10 is preferably a material used for the data signal line 9. If the same metal as that of the data signal line 9 is used, a special process for connection is not required, and therefore it can be manufactured at low cost.
In addition to the metal for connection, the same material as the pixel electrode (FIGS. 7 and 9) can be used.
However, the contact hole is not always necessary, and a metal layer may be formed immediately above the N ⁺ type semiconductor film 3 and the P ⁺ type semiconductor film 4.

FIGS. 12A, 12B, and 12C show the scanning line voltages applied to the scanning lines WLn−1, WLn, and WLn + 1 in the liquid crystal display device of this embodiment shown in FIG. A timing chart is shown. In FIG. 12A, Vdd and Vssg are voltages for turning on and off the TFT transistors of the respective pixels. Here, as an example, Vdd = 13V, Vssg = -2V.
In FIG. 12B, the broken line represents the potential of the common electrode, and the broken line represents the change timing of the pixel potential.
As shown in FIGS. 12A, 12B, and 12C, when an image is displayed, each scanning line WLn-1, WLn, WLn + 1,... Sequentially outputs a high level voltage signal (Vdd) to each pixel. The transistors NTr1, NTr4, NTr2, and NTr5 are output and turned on to operate each pixel.
In order to display one screen, each pixel operates only once. Therefore, the period in which the scanning line voltage is Vdd is much shorter than the period in which Vssg is set, and each transistor displays one screen. It is almost kept in the OFF state. That is, a voltage of −2 V is applied to WLn−1, WLn, and WLn + 1 for most of the display period.
Accordingly, for example, the P-type MOS auxiliary capacitor PCS1 shown in FIGS. 10 and 11 applies a voltage of −2 V to the metal electrode (scanning line) for most of the time.

On the other hand, for the electrode including the other P-type semiconductor film of the auxiliary capacitor PCS1, when the transistor NTr1 is in the ON state, a high level signal from the data signal line BLn-1 is assisted through the source / drain of the transistor NTr1. While charging the capacitor PCS1, a voltage is applied to both electrodes of the liquid crystal. When the auxiliary capacitor PCS1 is charged, the potential of the semiconductor film electrode becomes higher than Vssg. When the transistor NTr1 is in the OFF state, the source and drain of the transistor NTr1 are cut off, the signal from the data signal line BLn-1 does not supply voltage to the liquid crystal and the auxiliary capacitor PCS1, and the auxiliary capacitor PCS1 is on both sides of the liquid crystal. A voltage is supplied to the electrodes.
As shown in FIG. 12B, the potential of the semiconductor film of the auxiliary capacitor PCS1 (which is the same as the pixel potential) gradually decreases or increases, but is always higher than Vssg. Then, the voltage Vg from the metal side (scanning line side) of the auxiliary capacitor PCS1 to the semiconductor film is always a negative voltage.

As already described with reference to the graph of FIG. 4, when such a voltage Vg is applied to an N-type MOS capacitor composed of a scanning line (metal) / gate insulating film / N-type semiconductor film, majority carriers of the N-type semiconductor are converted into electrons. Therefore, with a negative scanning line voltage (or voltage Vg), majority carriers are eliminated from the surface of the semiconductor film, and a depletion layer (and / or inversion layer) is formed. Therefore, the auxiliary capacitor insulating layer is thick. As shown in FIG. 4, the obtained capacitance value is small.
FIG. 13 is a graph showing the capacitance-voltage characteristics of the P-type MOS structure.
In a P-type MOS capacitor composed of a scanning line (metal) / gate insulating film / P-type semiconductor film, the majority carrier of the P-type semiconductor is a hole, so that the negative scanning line voltage (or voltage Vg) is P-type. A depletion layer is not formed on the surface of the semiconductor film, and majority carriers gather on the contrary. As a result, a large capacitance value is obtained as shown in FIG.
Therefore, according to the present embodiment, a sufficient capacitance is formed in the use range of normal driving conditions (period in which the scanning line voltage is Vssg).

Thus, when the normal pixel transistor is formed of an N-channel type, the auxiliary capacitor must be formed of a P-type MOS capacitor, and when the pixel transistor is formed of a P-channel type, the auxiliary capacitor is formed. The capacitor is preferably formed of an N-type MOS capacitor.
In this embodiment, the auxiliary capacitor is formed by the next scanning line (gate line) WLn, but it may be the previous scanning line (gate line) WLn-2.
When the scanning line WLn forming the auxiliary capacitor becomes high level, the pixel potential has been greatly shifted in the past. However, by using the P-type MOS capacitor as in the present embodiment, the scanning line WLn When becomes high level, as shown in FIG. 12B, the P-type MOS capacitance is effectively reduced, and the shift amount is reduced. This improves the display quality.

14A and 14B show a method for manufacturing a liquid crystal display device according to this embodiment. The manufacturing method of the present embodiment is obtained by changing the steps of the conventional manufacturing method shown in FIG. 6A in the conventional method shown in FIGS. 5, 6, and 7.
Following the step of FIG. 5D, in FIG. 14A, high concentration implantation of phosphorus is performed in the vicinity of the TFT transistor to form the N ⁺ type semiconductor film 3, and the semiconductor film is metallized. At that time, the resist 11b is formed in the vicinity of the auxiliary capacitor so as not to perform high concentration implantation of phosphorus. In general, a resist is also called a protective mask. Therefore, after the high concentration implantation of phosphorus, the vicinity of the auxiliary capacitance is the N ⁻ type semiconductor film 4a as in the step of FIG.
Further, the conventional process for removing the protective insulating film on the auxiliary capacitor is not necessary.
In FIG. 14B, the resist pattern 11b in the vicinity of the auxiliary capacitance is removed, and high-concentration boron is implanted in the vicinity of the auxiliary capacitance to form the P ⁺ type semiconductor film 4b. At that time, a resist 11c is formed in the vicinity of the TFT transistor so as not to perform high concentration boron implantation.
Thereafter, heat treatment for activating the doped element is performed as necessary.

As described above, the liquid crystal display device according to the present embodiment includes the first conductivity type element and the second conductivity type MOS structure. If such two types of conductive elements are used, it is possible to form a CMOS-type drive circuit or logic circuit in the display pixel region, the outer region thereof, or both.
FIG. 15 shows an example of the configuration of a display device in which each pixel is driven by such a CMOS. In FIG. 15, a plurality of scanning lines and a plurality of data signal lines arranged in parallel are driven by a scanning line driving circuit and a data signal line driving circuit, respectively, and each pixel arranged in a matrix is, for example, an N-channel TFT. And driven by a drive circuit constituted by a P-type MOS capacitor.
In addition, in a liquid crystal display device having such a circuit, the method as in this embodiment can be configured without an increase in special steps, and is the most suitable configuration example. For example, it is preferably used in a polysilicon transistor liquid crystal display device using a polysilicon film having high mobility as a semiconductor.

According to the present embodiment, a sufficient capacity for the auxiliary capacity can be obtained in the use range of the normal driving condition (period in which the scanning line voltage is Vssg). Further, since the auxiliary capacitor can be formed with a CS on-gate structure, a high aperture ratio can be obtained.
In addition, according to the liquid crystal device manufacturing method of the present embodiment, the number of steps in which the semiconductor film is exposed to etching is reduced, so that defects and the like are reduced.

Second Embodiment This embodiment shows another configuration example of the liquid crystal display device of the present invention.
16 and 17 are a plan view and a schematic cross-sectional view of the configuration of the liquid crystal display device according to the present embodiment.
The liquid crystal display device shown in FIGS. 16 and 17 is basically the same as that shown in FIGS. 10B and 11. Therefore, the description which overlaps about this embodiment is abbreviate | omitted suitably, and the same code | symbol is used for the same component as FIG. 10 (B) and FIG.
The difference between FIG. 16 and FIG. 10B and FIG. 17 and FIG. 11 is that contact holes H2 and H3 connecting the N ⁺ type semiconductor film 3 and the P ⁺ type semiconductor film 4 shown in FIG. FIG. 16 shows one contact hole H4. The connection electrode 10 formed by filling the two contact holes shown in FIG. 11 with the conductive material is the connection electrode 30 formed of the conductive material filled in the same contact hole in FIG. .

The contact connecting the N ⁺ type semiconductor film 3 and the P ⁺ type semiconductor film 4 is preferably the same contact hole extending over both conductivity types. By using one contact hole, the area in the pixel can be used effectively, and the aperture ratio is improved.

Third Embodiment This embodiment shows another configuration example of the liquid crystal display device of the present invention.
FIG. 18 is a plan view of the configuration of the liquid crystal display device according to the present embodiment.
18, the same reference numerals are used for the same components as those in FIGS. 16 and 11.
The difference between FIG. 18, FIG. 11, and FIG. 16 is that in FIG. 18, a part of the auxiliary capacitor PCS1 is disposed below the data signal line BLn-1.
In this case, since the region necessary for forming the necessary auxiliary capacitance is originally formed in a region that does not transmit light, for example, a metal region (in this case, a data signal line), loss of transmittance is small. Thus, a large aperture ratio can be ensured.
In this case, the transistor structure can be formed by a bottom gate type or a top gate type.

In the bottom gate structure shown in FIG. 18, when the auxiliary capacitor PCS1 is formed below the data signal line BLn-1, since the protective insulating film remains on the semiconductor film, the coupling capacitance between the signal line and the semiconductor film is reduced. To do. This improves display quality such as crosstalk.
In addition, since the coupling capacitance with the electrode under the signal line is reduced, the total signal line capacitance is reduced, and the rise and fall times of the signal line potential are reduced, thereby improving the display quality.

Fourth Embodiment Although the bottom gate type transistor structure has been described above as an example, the present invention can also be applied to a top gate type transistor structure.
FIG. 19 is a cross-sectional view of an example of the configuration of the liquid crystal display device having a top gate structure according to this embodiment.
In the liquid crystal display device of FIG. 19, semiconductor films 43, 44, 45, and 46 are formed on a base layer (not shown) formed on a transparent substrate (not shown), and a gate insulating film 42 is formed on the semiconductor film. Further, the scanning lines 41a and 41b (WLn-1 and WLn) and the interlayer insulating film 48 are formed thereon. Thereby, a TFT transistor and an auxiliary capacitor are formed.
43 is an N ⁺ type semiconductor film, and 44 is a P ⁺ type semiconductor film. The center of the semiconductor film 45 is an i-type semiconductor film, and both ends thereof are LDD regions. The semiconductor film 45 constitutes a channel region of the TFT transistor, and FIG. 19 shows an N channel. The semiconductor film 46 is also an i-type semiconductor film.

The semiconductor film 46 is also a so-called i-type semiconductor film in which no impurity is implanted. In the interlayer insulating film 48, the wiring film of the N ⁺ type semiconductor film 43, the wiring film of the P ⁺ type semiconductor film 44, and the contact hole are formed, and the conductive material in the contact hole is the wiring of the N ⁺ type semiconductor film 43. A connection electrode 50 for connecting the film and the wiring film of the P ⁺ type semiconductor film 44 is formed, and a data signal line 49 is formed.
The gate electrode (which constitutes part of the scanning line) 41a, the gate insulating film 42, and the semiconductor films 43 and 45 constitute an N-channel TFT transistor. On the other hand, the gate electrode 41b, the gate insulating film 42, and the semiconductor films 44 and 46 constitute a P-channel transistor, and the capacitance of the P-channel transistor is used as an auxiliary capacitor.
The structure shown above is a schematic cross-sectional view of the structure shown in FIG. Moreover, the structure corresponding to FIG. 16 may be sufficient.
Further, the pixel transistor may be an N channel or a P channel.

20A and 20B show a method of manufacturing a liquid crystal display device having a top gate structure according to this embodiment. The manufacturing method of the present embodiment is obtained by changing the steps of the conventional manufacturing method shown in FIG. 8C in the conventional manufacturing method shown in FIGS.
Following the step of FIG. 8B, a resist 47a having a shape covering the LDD regions on both sides of the channel region 45 is formed in the TFT transistor region in FIG. 20A. Then, high concentration implantation of phosphorus is performed in the vicinity of the TFT transistor, an N ⁺ type semiconductor film 43 is formed, and the semiconductor film is metalized.

At this time, a resist 47b is formed in the vicinity of the auxiliary capacitance so as not to perform high concentration implantation of phosphorus. Therefore, after the high concentration implantation of phosphorus, the vicinity of the auxiliary capacitance is the N ⁻ type semiconductor film 44a as in FIG. 8B.
In FIG. 20B, the resist 47b in the vicinity of the auxiliary capacitance is removed, and high-concentration boron is implanted in the vicinity of the auxiliary capacitance to form a P ⁺ type semiconductor film 44b. At that time, a resist 47c is formed in the vicinity of the TFT transistor so as not to perform high concentration boron implantation.
Thereafter, heat treatment for activating the doped element is performed as necessary.

  This embodiment has the same effect as the first and second embodiments.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the gist of the present invention.
In the above embodiments, the liquid crystal display device has been described as an example, but the present invention can also be applied to display devices with other driving methods.

6 shows an equivalent circuit of an example of a conventional display device. The top view of the structure of the conventional display apparatus shown in FIG. 1 is shown. (A) shows an equivalent circuit of another example of a display device having a conventional bottom gate structure, and (B) shows a plan view of the configuration of the display device. 4 is a graph showing measurement results of voltage-capacitance characteristics of auxiliary capacitors in the conventional display device shown in FIG. 3. (A)-(D) are sectional drawings explaining the manufacturing method of the conventional display apparatus shown by FIG. 5A to 5C are cross-sectional views illustrating a method for manufacturing the conventional display device shown in FIG. 6A and 6B are cross-sectional views illustrating a method for manufacturing the conventional display device shown in FIG. (A)-(C) are sectional drawings explaining the manufacturing method of the display device which has the conventional top gate structure. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device having a conventional top gate structure. (A) shows the equivalent circuit of the display apparatus concerning the 1st Embodiment of this invention, (B) shows the top view of a structure of this display apparatus. It is sectional drawing which shows the structure of the display apparatus concerning the 1st Embodiment of this invention. (A)-(C) are timing charts of scanning line signals and pixel potentials in the display device according to the first embodiment of the present invention. 4 is a graph showing measurement results of voltage-capacitance characteristics of an auxiliary capacitor in the display device according to the first embodiment of the present invention. (A) And (B) is sectional drawing explaining the manufacturing method of the display apparatus concerning the 1st Embodiment of this invention. It is a figure which shows the drive circuit in the display apparatus concerning the 1st Embodiment of this invention. The top view of the structure of the display apparatus concerning the 2nd Embodiment of this invention is shown. It is sectional drawing of a structure of the display apparatus concerning the 2nd Embodiment of this invention. The top view of the structure of the display apparatus concerning the 3rd Embodiment of this invention is shown. It is sectional drawing of the structure of the display apparatus concerning the 4th Embodiment of this invention. (A) And (B) is sectional drawing explaining the manufacturing method of the display apparatus concerning the 4th Embodiment of this invention.

Explanation of symbols

1a, 1b ... scan lines, 2 ... gate insulating film, 3 ... ^{N +} -type semiconductor layer, 4, 4b ... ^{P +} -type semiconductor layer, 4a ... N ^- -type semiconductor layer, 5 ... channel region (semiconductor film), 6 ... i-type semiconductor film, 7a, 7b ... stopper insulating film, 8 ... interlayer insulating film, 9 ... data signal line, 10 ... connection electrode, 11a, 11b, 11c ... resist, 30 ... connection electrode, 40 ... underlayer, 41a, 41b ... scanning line, 42 ... gate insulating film, 43 ... N ⁺ type semiconductor film, 44, 44b ... P ⁺ type semiconductor film, 44a ... N ^- type semiconductor film, 45 ... channel region, 46 ... i type semiconductor film, 48 ... Interlayer insulating film, 49 ... Data signal line, 50 ... Connection electrode, 47a, 47b, 47c ... Resist, 101 ... Glass substrate, 102a, 102b ... Gate electrode, 103 ... Gate insulating film, 104a, 104b, 104c ... Semiconductor film 10 105a, 105b ... protective insulating film, 107a, 107b ... resist, 108 ... resist, 109 ... interlayer insulating film, 110a, 110b ... contact hole, 111a, 111b ... data signal line, 112 ... connecting metal, 113 ... second Interlayer insulating film, 114 ... pixel electrode, 121 ... glass substrate, 122 ... underlayer, 123a, 123b, 123c ... semiconductor film, 124 ... gate insulating film, 125a, 125b ... gate electrode (scanning line), 126 ... resist, 127 ... Interlayer insulating film, 128a, 128b ... Contact hole, 129a, 129b ... Data signal line, 130 ... Connection metal, 131 ... Second interlayer insulating film, 132 ... Pixel electrode, WL ... Scan line, BL ... Data signal line, CSL: auxiliary capacitance line, CS, PCS: auxiliary capacitance, Tr, NTr: transistor, Ccl: liquid Element capacity, H1, H2, H3, H4 ... contact hole.

Claims (9)

A plurality of scanning lines and signal lines intersecting each other, and pixels arranged at each intersection of both wirings are provided on an insulating substrate,
Each pixel holds at least the pixel electrode, a thin film transistor for driving this through the wirings drawn out from the source or drain of the thin film transistor comprising a semiconductor film, the written signal charges to the pixel electrode from the signal Line An auxiliary capacitor having a MOS structure having a different conductivity type from the thin film transistor ,
In the display device having a structure in which the auxiliary capacitance line of the auxiliary capacitance also serves as the scanning line in the previous stage or the subsequent stage,
The wiring of the auxiliary capacitor in which one electrode of a set of electrodes configured with the insulating film of the auxiliary capacitor sandwiched therebetween is a semiconductor film having a conductivity type different from that of the wiring drawn from the source or drain of the thin film transistor Consists of
Connection electrodes for connecting the junction of the wiring drawn out from the source or drain of the wiring of the auxiliary capacitance thin film transistor is directly connected, the wiring and the auxiliary capacitance drawn from the source or drain of the thin film transistor wiring A display device is provided. The display device according to claim 1, wherein the wiring of the one electrode of the auxiliary capacitor and the wiring drawn out from the source or drain of the thin film transistor are made of a semiconductor film formed in the same layer. The connection electrode is formed of a conductive material filled in a contact hole formed in an upper layer of the wiring of the one electrode of the auxiliary capacitor and the wiring extracted from the source or drain of the thin film transistor. The display device according to claim 2, wherein a wiring drawn from a source or a drain of the thin film transistor is connected. The contact hole is one of a contact hole formed on the joint, from the source or drain of the said conductive material filled in the contact hole and the wiring of the one electrode of the storage capacitor the thin film transistor The display device according to claim 3, wherein the display device is connected to the drawn wiring. The display device according to claim 3, wherein the conductive material is formed of the same conductive material as the signal line. The auxiliary capacitor is an auxiliary capacitor having a MOS structure having a conductivity type different from that of the thin film transistor, and the auxiliary capacitor includes the other electrode configured by sandwiching the insulating film with respect to the one electrode, display device of the electrode according to claim 1, wherein that share the scan lines. The display device according to claim 1, wherein the connection electrode is provided in the pixel. The conductivity type of the semiconductor film constituting the thin film transistor is N type,
The conductivity type of the semiconductor film forming the wiring of the one electrode of the auxiliary capacitor is P type,
The display device according to claim 1, wherein the joint portion forms a PN junction. The display device according to claim 1, wherein the thin film transistor includes first and second thin film transistors connected in series with the scanning line serving as the same gate.

Images