JP4517579B2 - Current control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a current control circuit for controlling a current flowing through a load when a capacitive load is started.
[0002]
[Prior art]
Conventionally, various measures for monitoring a transient state at the time of starting a load and avoiding an influence on the entire circuit have been proposed. For example, when a capacitive load is started up or when a decoupling capacitor is connected in parallel to the load, a large current instantaneously flows through the capacitive load or the decoupling capacitor when the power is turned on.
[0003]
In order to suppress this large current, that is, an inrush current, a method has been proposed in which a variable impedance element is arranged in series with a DC power supply and a load, and the impedance of the variable impedance element is gradually reduced (see, for example, Patent Document 1). . Specifically, a MOSFET is used as the variable impedance element, and the output current is gradually increased by gradually increasing the gate voltage. Such a method can suppress the occurrence of an inrush current to the decoupling capacitor.
[0004]
[Patent Document 1]
JP 2002-290223 A
[0005]
[Problems to be solved by the invention]
However, in the circuit configuration of the above prior art, a parallel circuit of a plurality of MOSFETs is used instead of a single MOSFET for the purpose of reducing power loss in the MOSFET and securing an output current path corresponding to the load current. However, there is a possibility that an excessive current flows in one MOSFET due to variations in gate threshold voltages of a plurality of MOSFETs. If an excessive current flows in one MOSFET as described above, an inrush current flows in the decoupling capacitor or the capacitive load, and the original purpose of suppressing the inrush current cannot be achieved.
[0006]
SUMMARY OF THE INVENTION An object of the present invention is to provide a current control circuit that can reliably prevent an excessive current from flowing when a load is started.
[0007]
[Means for Solving the Problems]
  In order to achieve the above object, the invention according to claim 1Connected to DC power supplyControl the current through the capacitive loadElectricFlow control circuitBecauseOf the capacitive loadDetection circuit that outputs detection voltage according to the voltage between both terminalsWhen,The DC power supply andCapacitive loadConsisting of a variable impedance element connected between, a signal source and a differential amplifier circuit,Of the variable impedanceControl circuit that supplies control voltage to the control terminalAndThe signal source outputs a reference voltage whose voltage value increases at a predetermined rate until the signal voltage reaches a predetermined voltage value, and the differential amplifier circuit receives the detection voltage and the reference voltage at a pair of input terminals, respectively. The control voltage is output from the output terminal, and the voltage value of the reference voltage increases at the same rate as the increase rate of the detection voltage in the increase period of the detection voltage, and the reference voltage is larger than the detection voltage. Is set toIt is characterized by that.
[0008]
  In the current control circuit configured in this way,Detection circuitOf capacitive loadDetection voltage according to the voltage between both terminalsTheoutputAnd thisInput to differential amplifier circuitTo do.The signal source outputs a reference voltage whose voltage value increases at a predetermined rate until it reaches a predetermined voltage value. In the differential amplifier circuit, a detection voltage and a reference voltage are input to a pair of input terminals, respectively, and a control voltage is output toward the variable impedance element. The differential amplifier circuit is set so that the reference voltage increases at the same rate as the increase rate of the detection voltage and the reference voltage is larger than the detection voltage during the increase period of the detection voltage.. Thus, at the start of the capacitive loadVoltage between both terminals of capacitive loadWhile monitoring the capacitive loadchargingIs controlled while monitoring the current to the capacitive load that flows at the time of startup, and it is possible to reliably prevent a situation in which an excessive current flows at the time of load startup.
[0009]
  The invention according to claim 2A current control circuit for controlling a current flowing in a capacitive load connected to a DC power supply, wherein the detection circuit outputs a detection voltage corresponding to a voltage between both terminals of the capacitive load; the DC power supply and the capacitor A variable impedance element connected between the capacitive loads, a signal source and a differential amplifier circuit, and a control circuit for supplying a control voltage to the variable impedance control terminal, the signal source having a predetermined voltage A reference voltage whose voltage value increases at a predetermined rate until reaching the value, and the differential amplifier circuit has the detection voltage and the reference voltage input to a pair of input terminals, respectively, and the control voltage is output from an output terminal. The reference voltage is set to be larger than the detection voltage by a certain value during the increase period of the detection voltage.
[0011]
  Claim3The invention described is a current control circuit for controlling a current flowing in a capacitive load connected to a DC power supply, the variable impedance element being connected between the DC power supply and the capacitive load, and the variable impedance element A detection circuit that outputs a detection voltage corresponding to the voltage between the two terminals, a signal source and a differential amplifier circuit, and a control circuit that supplies a control voltage to the control terminal of the variable impedance, the signal source Outputs a reference voltage whose voltage value decreases at a predetermined rate until it reaches a predetermined voltage value, and the differential amplifier circuit has the detection voltage and the reference voltage input to a pair of input terminals, respectively, and an output terminal The control voltage is output from the reference voltage, and during the decrease period of the detection voltage, the reference voltage decreases at the same rate as the decrease rate of the detection voltage, and the reference voltage is equal to the detection voltage. Characterized in that it is set to be larger.
[0012]
  Claim4The invention described is a current control circuit for controlling a current flowing in a capacitive load connected to a DC power supply, the variable impedance element being connected between the DC power supply and the capacitive load, and the variable impedance element A detection circuit that outputs a detection voltage corresponding to the voltage between the two terminals, a signal source and a differential amplifier circuit, and a control circuit that supplies a control voltage to the control terminal of the variable impedance, the signal source Outputs a reference voltage whose voltage value decreases at a predetermined rate until it reaches a predetermined voltage value, and the differential amplifier circuit has the detection voltage and the reference voltage input to a pair of input terminals, respectively, and an output terminal The control voltage is output from the control voltage, and the reference voltage is set to be larger than the detection voltage by a certain value during the decrease period of the detection voltage.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below. First, an embodiment when the present invention is realized by a voltage control method will be described with reference to FIG. FIG. 1A is a circuit diagram of the current control circuit 10 according to the embodiment of the present invention, and FIG. 1B is a timing chart for explaining the operation of the circuit diagram shown in FIG. is there.
[0021]
As shown in FIG. 1A, a current control circuit 10 includes a capacitive load 1 (hereinafter simply referred to as “load 1”), a DC power supply 2 with a power supply voltage Vin, and a MOSFET 3 (hereinafter referred to as a variable impedance element). In this configuration, a feedback loop including a voltage detector 4, a control circuit 5, and a control signal source 6 is added to a circuit in which “FET3” is simply connected in series.
[0022]
The voltage detector 4 having the attenuation α has a non-inverting input terminal connected to the high potential side of the load 1 and an inverting input terminal connected to the low potential side of the load 1, and detects the voltage across the load 1. The output terminal of the voltage detector 4 is connected to the inverting input terminal of the control circuit 5, and the output terminal of the control signal source 6 is connected to the non-inverting input terminal of the control circuit 5. The control circuit 5 is composed of an operational amplifier with an amplification degree Av, and the difference between the output voltage Vi1 of the control signal source 6 and the output voltage Vi2 of the voltage detector 4 is output. The output terminal of the control circuit 5 is connected to the gate of the FET 3.
[0023]
FIG. 5 is a circuit example of the control signal source 6. As shown in the figure, the control signal source 6 is connected between a series circuit of a DC power source 51, a constant current source 52 and an NPN transistor 54 (hereinafter simply referred to as “transistor 54”) and the collector and emitter of the transistor 54. And a capacitor 53. An ON / OFF signal as an input signal of the control signal source 6 is applied to the base of the transistor 54. Further, the voltage of the capacitor 53 is taken out as the signal source output of the control signal source 6.
[0024]
When the ON / OFF signal applied to the base of the transistor 54 is OFF, the transistor 54 is non-conductive and there is no output from the control signal source 6. When the ON / OFF signal is turned ON, the transistor 54 becomes conductive and current flows to the constant current source 52. Along with this, the capacitor 53 is gradually charged, and the voltage of the capacitor 53 increases linearly until it reaches a predetermined level as time passes. The voltage of the capacitor 53 is taken out as a signal source output.
[0025]
Next, the operation of the current control circuit 10 shown in FIG. 1A will be described with reference to the timing chart shown in FIG. The horizontal axis of the timing chart is a time axis, and will be described by dividing into timings T0 to T3 for convenience.
[0026]
During the period from T0 to T1, the current control circuit 10 is in a non-operating state. The ON / OFF signal applied to the control signal source 6 is OFF, and the output voltage Vi1 from the control signal source 6 is at a zero level. At this time, no voltage is applied to the load 1, and the source-drain voltage Vds (hereinafter simply referred to as “drain voltage Vds”) of the FET 3 is equal to the power supply voltage Vin of the DC power supply 2.
[0027]
When the ON / OFF signal of the control signal source 6 is switched to ON at the timing T1, the output voltage Vi1 of the control signal source 6 increases linearly. Along with this, the output voltage from the control circuit 5 increases. However, until the output voltage reaches the gate threshold voltage of the FET 3, the FET 3 does not conduct and no current flows through the load 1, so that the voltage detector 4 Output voltage Vi2 remains at the zero level.
[0028]
When the source-gate voltage Vgs (hereinafter simply referred to as “gate voltage Vgs”) of the FET 3 reaches the gate threshold voltage at the timing of T2, the FET 3 becomes conductive and the output current Ids begins to flow. Then, the capacitive load 1 starts charging, and the voltage across the load 1 begins to gradually increase. The voltage detector 4 outputs a voltage that is α times the voltage across the load 1. As shown in FIG. 1B, the output voltage Vi2 from the voltage detector 4 increases linearly during the period T2-T3. As described above, this corresponds to the progress of charging of the capacitive load 1.
[0029]
The rate of increase dV / dt of the output voltage Vi1 from the control signal source 6 is substantially the same as the rate of increase of the output voltage Vi2 of the voltage detector 4, and the output voltage Vi1 of the control signal source 6 is a voltage. It is set in advance so as to be slightly larger than the output voltage Vi2 of the detector 4, that is, Vi1-Vi2 = ΔV. Accordingly, the output voltage of the control circuit 5, that is, the gate voltage Vgs of the FET 3 is equal to ΔV multiplied by the amplification degree Av of the control circuit 5 (Vgs = ΔV × Av).
[0030]
When the voltage across the load 1 increases during the period of T2-T3, the drain voltage Vds gradually decreases accordingly. That is, a relationship of −Vds / dt = (dV / dt) × (1 / α) is established. When the load 1 is fully charged at the timing T3, the voltage across the load 1 becomes equal to the power supply voltage Vin of the DC power supply 2. Therefore, current no longer flows through the load 1.
[0031]
Since the output voltage Vi1 from the control signal source 6 continues to increase after the timing T3, the gate voltage Vgs also starts to increase, and the gate voltage Vgs also increases when the output voltage Vi1 of the control signal source 6 reaches a constant value of the maximum level. Stop and become a constant value. The maximum value of the gate voltage Vgs at this time is a value depending on the power supply voltage of the control circuit 5.
[0032]
As described above, the output voltage characteristic of the control signal source 6 is set in accordance with the charging characteristic of the load 1 so that the drain voltage Vds decreases linearly during the period T2-T3 when the load 2 is started. It is.
[0033]
The current Ids flowing through the load 1 can be expressed by Ids = C × dVds / dt (C: capacitance of the load 1). As described above, since the drain voltage is set to linearly decrease, dVds / dt is constant, and thus the current Ids flowing through the load 1 is constant. In other words, by controlling the current Ids flowing through the load 1 to be constant, an inrush current that may flow when the capacitive load 1 starts is prevented. The above description is based on the premise that there is no load at the time of startup.
[0034]
The case where the current control circuit of the present invention is realized by the voltage control method has been described above, but the present invention can also be realized by the current control method. In this case, the current detector 7 may directly detect the current Ids flowing through the load 1 and input the output voltage corresponding to the detected current Ids from the current detector 7 to the control circuit 5. As the current detector 7, a resistor or a Hall element can be used. However, the connecting portion does not need to be between the load 1 and the drain of the FET 3, and may be connected to the source side of the FET 3.
[0035]
Next, examples of the present invention will be described. FIG. 2A is a circuit diagram showing the current control circuit according to the first embodiment, and FIG. 2B is a timing chart for explaining the operation of the current control circuit shown in FIG. is there. 2A, the same reference numerals are given to the same or corresponding elements as the circuit components shown in FIG. 1A, and the description thereof is omitted.
[0036]
The current control circuit 20 shown in FIG. 2A is basically the same as the circuit configuration shown in FIG. 1A, and a load 1, a DC power source 2, and an FET 3 are connected in series. A feedback loop including a voltage detector 4, a control signal source 6 and a control circuit 5 is formed between the load 1 and the FET 3. The non-inverting input terminal of the voltage detector 4 is connected to the high potential side of the load 1 and the inverting input terminal is connected to the low potential side of the load 1 to detect the voltage across the load 1. Further, the control signal source 6 having the configuration shown in FIG. 5 can be applied.
[0037]
The output terminal of the voltage detector 4 is connected to one input terminal of the control circuit 5, and the output of the control signal source 6 is connected to the other input terminal of the control circuit 5. The output terminal of the control circuit 5 is connected to the gate of the FET 3.
[0038]
The control circuit 5 is composed of a differential amplifier circuit. The differential amplifier circuit includes an operational amplifier 51, a resistor 52 is provided between the inverting input terminal of the operational amplifier 51 and the voltage detector 4, a resistor 53 is provided between the non-inverting terminal and the control signal source 6, and a non-inverting terminal. A resistor 54 is connected between the ground and the ground. A parallel circuit of a capacitor 55 and a resistor 56 is connected to the feedback path between the output terminal and the inverting input terminal of the operational amplifier 51.
[0039]
Next, the operation of the current control circuit 20 shown in FIG. 2A will be described with reference to the timing chart shown in FIG.
[0040]
Prior to T1, the current control circuit 20 is in a non-operating state. The ON / OFF signal applied to the control signal source 6 is OFF, and the output voltage A from the control signal source 6 is at a zero level. At this time, no voltage is applied to the load 1, and the drain voltage D of the FET 3 is equal to the power supply voltage of the DC power supply 2.
[0041]
When the ON / OFF signal of the control signal source 6 is switched to ON at the timing T1, the output voltage A of the control signal source 6 gradually increases. Along with this, the output voltage C from the control circuit 5 applied to the gate of the FET 3 starts to increase. Until the gate voltage C reaches the gate threshold voltage, no voltage is applied to the load 1, so that the output voltage B from the voltage detector 4 is also maintained at the zero level.
[0042]
When the gate voltage C reaches the gate threshold voltage at the timing T2, the FET 3 becomes conductive and the output current E starts to flow. Then, the capacitive load 1 starts charging, and the voltage across the load 1 starts to increase linearly. As the charging of the load 1 proceeds, the output voltage B from the voltage detector 4 also increases linearly.
[0043]
The rate of increase of the output voltage A from the control signal source 6 is substantially the same as the rate of increase of the output voltage B of the voltage detector 4, and the output voltage A of the control signal source 6 is higher in the voltage detector 4. Is set in advance so as to be slightly higher than the output voltage B.
[0044]
When the voltage across the load 1 increases during the period T2-T3, the drain voltage D gradually decreases accordingly. When the load 1 is fully charged at the timing T3, the current E no longer flows through the load 1.
[0045]
Since the output voltage A from the control signal source 6 continues to increase after the timing T3, the gate voltage C starts to increase from the level of the gate threshold voltage, and the output voltage A of the control signal source 6 becomes a constant value at the maximum level. At that point, the gate voltage C also stops increasing and maintains a constant value. However, the gate voltage C does not exceed the power supply voltage of the operational amplifier 51.
[0046]
As described above, the characteristics of the output voltage A of the control signal source 6 are matched with the charging characteristics of the load 1 so that the current flowing through the load 1 becomes substantially constant during the period T2-T3 when the load 2 is started. It is set in the form. For this reason, the inrush current which may flow at the time of starting of the capacitive load 1 can be prevented.
[0047]
Next, a second embodiment of the present invention will be described. FIG. 3A is a circuit diagram showing a current control circuit according to the second embodiment, and FIG. 3B is a timing chart for explaining the operation of the current control circuit shown in FIG. is there. In FIG. 3 (a), elements that are the same as or correspond to the circuit components shown in FIG. 1 (a) or 2 (a) are given the same reference numerals, and descriptions thereof are omitted.
[0048]
The current control circuit 30 shown in FIG. 3A has a circuit configuration approximate to the current control circuit 20 according to the first embodiment shown in FIG. In the current control circuit 20 shown in FIG. 2A, the voltage detection circuit 4 directly detects the voltage across the load 1, whereas in the current control device 30 shown in FIG. The detection circuit 4 detects the voltage between the source and drain of the FET 3. Although the voltage detection location is different, the voltage between the source and the drain of the FET 3 changes corresponding to the voltage across the load 1, so that the detection of the voltage between the source and the drain of the FET 3 is substantially equal to the load 1. This is equivalent to detecting the voltage at both ends.
[0049]
The control signal source 6 ′ incorporated in the current control device 30 is different in specific circuit configuration from the control signal source 6 incorporated in the current control device 20 shown in FIG. FIG. 6 shows a circuit example of the control signal source 6 ′. A series circuit of a DC power source 51, a PNP transistor 54 ′ (hereinafter simply referred to as “transistor 54 ′”) and a constant current source 52, and a constant current source are shown. 52 and a capacitor 53 connected in parallel to 52. An ON / OFF signal as an input signal of the control signal source 6 ′ is applied to the base of the transistor 54 ′. Further, the voltage of the capacitor 53 is taken out as a signal source output of the control signal source 6 '.
[0050]
When the ON / OFF signal applied to the base of the transistor 54 'is OFF, the transistor 54' is in a conducting state. At this time, since the power supply voltage of the DC power supply 51 is applied to the capacitor 53, the capacitor 53 is fully charged. Therefore, when the ON / OFF signal is OFF, the signal source output from the control signal source 6 'is at the maximum level.
[0051]
When the ON / OFF signal is switched ON, the transistor 54 'is turned off. As a result, the capacitor 53 and the constant current source 52 constitute a closed circuit, and the discharge current of the capacitor 53 flows to the constant current source 52. Accordingly, the voltage of the capacitor 53 decreases almost linearly with the passage of time, and reaches a zero level when a predetermined time has passed. The linearly decreasing voltage of the capacitor 53 is output as the signal source output.
[0052]
Next, the operation of the current control circuit shown in FIG. 3A will be described with reference to the timing chart shown in FIG.
[0053]
Prior to T1, the current control circuit 30 is in a non-operating state. The ON / OFF signal applied to the control signal source 6 'is OFF, and the output voltage A from the control signal source 6' is at the maximum level. At this time, no voltage is applied to the load 1, and the drain voltage D of the FET 3 is equal to the power supply voltage of the DC power supply 2. Therefore, the output voltage B of the voltage detector 4 that detects the source-drain voltage of the FET 3 is also at the maximum level, and the gate voltage C output from the control circuit 5 is at the zero level.
[0054]
When the ON / OFF signal of the control signal source 6 'is switched ON at the timing T1, the output voltage A of the control signal source 6' decreases linearly. At this time, since the output voltage B of the voltage detector 4 is in a state where the maximum level is maintained, the difference between the output voltages A and B increases linearly and the output voltage C from the control circuit 5 applied to the gate of the FET 3. Begins to increase.
[0055]
When the gate voltage C reaches the gate threshold voltage at the timing T2, the FET 3 becomes conductive and the output current E starts to flow. That is, the capacitive load 1 starts charging, and the voltage across the load 1 begins to increase linearly. As the charge of the load 1 proceeds, the voltage between the source and drain of the FET 3 decreases, so that the output voltage B from the voltage detector 4 that detects the voltage between the source and drain of the FET 3 decreases linearly. .
[0056]
The rate of decrease of the output voltage A from the control signal source 6 ′ is substantially the same as the rate of decrease of the output voltage B from the voltage detector 4, and the output voltage A of the control signal source 6 ′ is more. It is set in advance so as to be slightly larger than the output voltage B of the voltage detector 4.
[0057]
When the voltage across the load 1 increases during the period of T2-T3, the drain voltage D decreases linearly. When the load 1 becomes fully charged at the timing T3, the voltage across the load 1 becomes equal to the voltage of the DC power supply 2, and the drain voltage D of the FET 3 becomes zero. Therefore, current no longer flows through the load 1.
[0058]
Since the output voltage A from the control signal source 6 ′ continues to decrease after the timing T3, the gate voltage C continues to increase beyond the gate threshold voltage, and the output voltage A of the control signal source 6 ′ becomes zero level. At that point, the gate voltage C also stops increasing and becomes a constant value.
[0059]
As described above, the characteristic of the output voltage A of the control signal source 6 ′ is changed to the charging characteristic of the load 1 so that the current flowing through the load 1 becomes substantially constant during the period of T 2 to T 3 corresponding to the start of the load 2. They are set together. For this reason, the inrush current which may flow at the time of starting of the capacitive load 1 can be prevented.
[0060]
Next, a third embodiment of the present invention will be described. 4A is a circuit diagram showing a current control circuit according to the third embodiment, and FIG. 4B is a timing chart for explaining the operation of the current control circuit shown in FIG. 4A. is there. In FIG. 4 (a), the same or corresponding elements as those shown in FIG. 1 (a), FIG. 2 (a), or FIG. To do.
[0061]
The current control circuit 40 shown in FIG. 4 (a) includes a control circuit 5 and a control signal source 6 in a circuit in which a DC power source 2, a load 1, a current detector 7, and an FET 3 are connected in series. The feedback loop is added. The current detector 7 detects a current flowing through the load 1 and outputs a voltage corresponding to the detected current. As described above, a resistor or a Hall element is used. An output terminal of the current detector 7 is connected to an inverting input terminal of an operational amplifier 51 constituting the control circuit 5 via a resistor 52. On the other hand, the output terminal of the control signal source 6 is connected to the non-inverting input terminal of the operational amplifier 51 through the resistor 53. The configuration of the control circuit 5 is the same as the configuration of the control circuit shown in FIGS. 2A and 3A, and the output terminal of the control circuit 5 is connected to the gate of the FET 3. is there. As the control signal source 6, one having the configuration shown in FIG. 5 can be applied.
[0062]
Next, the operation of the current control circuit 40 shown in FIG. 4A will be described with reference to the timing chart shown in FIG.
[0063]
Prior to T1, the current control circuit 40 is in a non-operating state. The ON / OFF signal applied to the control signal source 6 is OFF, and the output voltage A from the control signal source 6 is at a zero level. At this time, the current E does not flow through the load 1, and the output voltage B from the current detector 7 is at a zero level.
[0064]
When the ON / OFF signal of the control signal source 6 is switched to ON at the timing T1, the output voltage A of the control signal source 6 gradually increases. Along with this, the output voltage C from the control circuit 5 applied to the gate of the FET 3 starts to increase. Until the gate voltage C reaches the gate threshold voltage, the current E does not flow through the load 1, so that the output voltage B from the current detector 7 also remains at the zero level.
[0065]
When the output voltage A of the control signal source 6 reaches a predetermined level at the timing T2, the gate voltage C becomes the gate threshold voltage, and the FET 3 becomes conductive. Then, the output current E begins to flow. The current detector 7 detects the output current E and applies an output voltage B proportional to the detected output current E to the control circuit 5. The control circuit 5 operates to control the impedance of the FET 3 so that the output voltage B approaches the output voltage A from the control signal source 6 having a target value.
[0066]
In this embodiment, since the output voltage A from the control signal source 6 is set to increase at a constant rate during the period T2-T3, the current E flowing through the load 1 also starts from zero level and is constant. It is controlled to increase at a rate. In this way, since the current flowing through the load 1 is directly detected and fed back, and the load current is controlled so as to approach the target value, the output voltage of the control signal source 6 is flat at a predetermined level between T2 and T3. If the characteristic is such that the load 1 can be controlled at a constant current during startup.
[0067]
When the load 1 becomes fully charged at the timing T3, the voltage across the load 1 becomes equal to the voltage of the DC power supply 2, no current flows through the load 1, and the output voltage B of the current detector 7 becomes zero level. .
[0068]
Since the output voltage A from the control signal source 6 continues to increase after the timing T3, the gate voltage C continues to increase beyond the gate threshold voltage, and the output voltage A of the control signal source 6 is a constant value at a high level. At that point, the gate voltage C also stops increasing and becomes a constant value. Note that the gate voltage C increases slightly over time during the period T2-T3.
[0069]
As described above, in this embodiment, the current flowing through the load 1 is controlled to gradually increase during the period T2-T3 when the load 2 is activated. For this reason, the capacitive load 1 can be started with a slow start.
[0070]
The present invention is not limited to the above-described embodiments or examples, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment and various examples, the control at the time of starting the capacitive load has been described. However, the present invention can be applied even to a configuration in which a decoupling capacitor is connected in parallel to the load. . In this case, an inrush current flowing in the decoupling capacitor when energizing the load can be prevented. In particular, when starting the load with a voltage higher than the normal driving voltage, an excessive current flows through the decoupling capacitor at the time of starting, which is particularly effective in such a case.
[0071]
For example, by inserting an impedance element between the battery and the robot internal circuit and controlling this impedance element, the voltage applied to the robot internal circuit can be gradually increased without causing an inrush current to flow in the robot internal circuit. Can do. Since the load on the robot's internal circuit is a motor and its drive circuit for moving the robot's lower limbs, upper limbs, etc., an excessive voltage is applied to the drive circuit by preventing inrush current from flowing in the decoupling capacitor connected in parallel to this motor. Is not applied or the battery does not supply an excessive current, so that the reliability can be improved.
[0072]
In the above-described embodiment, a configuration in which only one FET as a variable impedance element is connected in series with the load is shown. However, a variable impedance element parallel circuit formed by connecting a plurality of variable impedance elements in parallel is connected in series with the load. You may make it connect. By adopting such a configuration, it is possible to reduce power loss in the variable impedance element, and it is possible to flow a load current that exceeds the allowable current that can be passed through the single variable impedance element.
[0073]
In addition to the battery, the output of the DC-DC converter may be used as the DC power source, and an example using a MOSFET as the variable impedance element has been shown, but a bipolar transistor may be used instead of the MOSFET. Good.
[0074]
【The invention's effect】
  BookAccording to the invention, the loadDetection voltage according to the voltage between both terminalsMonitorThe signal source outputs a reference voltage whose voltage value increases at a predetermined rate until reaching a predetermined voltage value, and the differential amplifier circuit has a detection voltage and a reference voltage inputted to a pair of input terminals, respectively, and an output terminal The control voltage is output from the control voltage, and during the detection voltage increase period, the reference voltage is set so that the voltage value increases at the same rate as the increase rate of the detection voltage and the reference voltage is greater than the detection voltageBecause of the loadDetection voltage according to the voltage between both terminalsIn this way, it is possible to reliably prevent a situation in which an excessive current flows when the load is started.
[Brief description of the drawings]
1A is a circuit diagram when the present invention is realized by a voltage control method, and FIG. 1B is a timing chart for explaining the operation of the circuit diagram shown in FIG. is there.
2A is a circuit diagram of a current control circuit according to a first embodiment of the present invention, and FIG. 2B is a timing for explaining the operation of the circuit diagram shown in FIG. It is a chart.
3A is a circuit diagram of a current control circuit according to a second embodiment of the present invention, and FIG. 3B is a timing for explaining the operation of the circuit diagram shown in FIG. 3A. It is a chart.
4A is a circuit diagram of a current control circuit according to a third embodiment of the present invention, and FIG. 4B is a timing for explaining the operation of the circuit diagram shown in FIG. 4A. It is a chart.
FIG. 5 shows a specific circuit configuration of a control signal source used in a current control circuit according to the first and third embodiments.
FIG. 6 shows a specific circuit configuration of a control signal source used in a current control circuit according to the second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Capacitive load, 2 ... DC power supply, 3 ... MOSFET, 4 ... Voltage detector,
5 ... Control circuit (differential amplifier), 6, 6 '... Control signal source, 7 ... Current detector,
10, 20, 30, 40 ... current control circuit

Claims (4)

A current control circuit for controlling a current flowing through a capacitive load connected to a DC power supply;
A detection circuit that outputs a detection voltage according to a voltage between both terminals of the capacitive load;
A variable impedance element connected between the DC power source and the capacitive load;
Comprising a signal source and a differential amplifier circuit, and a control circuit for supplying a control voltage to the variable impedance control terminal,
The signal source outputs a reference voltage whose voltage value increases at a predetermined rate until a predetermined voltage value is reached,
In the differential amplifier circuit, the detection voltage and the reference voltage are respectively input to a pair of input terminals, and the control voltage is output from an output terminal,
At increasing the period before Symbol detection voltage, the reference voltage and characterized in that the increased voltage value at the same rate as the increase ratio of the detection voltage and the reference voltage is set to be larger than the detection voltage Current control circuit. A current control circuit for controlling a current flowing through a capacitive load connected to a DC power supply;
A detection circuit that outputs a detection voltage according to a voltage between both terminals of the capacitive load;
A variable impedance element connected between the DC power source and the capacitive load;
Comprising a signal source and a differential amplifier circuit, and a control circuit for supplying a control voltage to the variable impedance control terminal,
The signal source outputs a reference voltage whose voltage value increases at a predetermined rate until a predetermined voltage value is reached,
In the differential amplifier circuit, the detection voltage and the reference voltage are respectively input to a pair of input terminals, and the control voltage is output from an output terminal,
The current control circuit, wherein the reference voltage is set to be larger than the detection voltage by a certain value during the increase period of the detection voltage. A current control circuit for controlling a current flowing through a capacitive load connected to a DC power supply;
  A variable impedance element connected between the DC power source and the capacitive load;
  A detection circuit that outputs a detection voltage according to a voltage between both terminals of the variable impedance element;
  Comprising a signal source and a differential amplifier circuit, and a control circuit for supplying a control voltage to the variable impedance control terminal,
  The signal source outputs a reference voltage whose voltage value decreases at a predetermined rate until a predetermined voltage value is reached,
  In the differential amplifier circuit, the detection voltage and the reference voltage are respectively input to a pair of input terminals, and the control voltage is output from an output terminal,
  In the decrease period of the detection voltage, the reference voltage is set so that the voltage value decreases at the same rate as the decrease rate of the detection voltage, and the reference voltage is larger than the detection voltage. Current control circuit. A current control circuit for controlling a current flowing through a capacitive load connected to a DC power supply;
  A variable impedance element connected between the DC power source and the capacitive load;
  A detection circuit that outputs a detection voltage according to a voltage between both terminals of the variable impedance element;
  Comprising a signal source and a differential amplifier circuit, and a control circuit for supplying a control voltage to the variable impedance control terminal,
  The signal source outputs a reference voltage whose voltage value decreases at a predetermined rate until a predetermined voltage value is reached,
  In the differential amplifier circuit, the detection voltage and the reference voltage are respectively input to a pair of input terminals, and the control voltage is output from an output terminal,
  The current control circuit, wherein the reference voltage is set to be larger than the detection voltage by a certain value during a decrease period of the detection voltage.

Images