JP4503003B2 - Power supply backup system and electronic device having the same - Google Patents

Description

  The present invention relates to a power supply backup system configured to supply power from an auxiliary power supply to a memory even when supply of power from a main power supply is interrupted, and an electronic apparatus including the power supply backup system.

  There is a standard called ACPI (Advanced Configuration and Power Interface) as a power management standard for power saving in electronic devices such as computer devices and peripheral devices. This standard determines power saving interfaces for each of hardware, OS, and peripheral devices, and the OS performs power management. Specifically, the computer main body, peripheral devices, and software cooperate to control ON / OFF of the power supplied to each other. In addition, in such a computer device, when hardware, OS, etc. are suspended in the sleep state for power saving, that is, when work contents are stored in the memory, data is lost due to a power failure or the like. In order to prevent loss and system destruction, a battery backup circuit (for example, Patent Document 1: Japanese Patent Publication No. 2003-180040) is provided.

  With such a battery backup circuit, the work contents are always backed up in preparation for a power failure during operation of the computer device. On the other hand, many small computer devices such as personal computers (PCs) do not have a battery backup circuit.

No. 2003-180040

  By the way, in the computer apparatus having the battery backup circuit as described above, the work content is always backed up regardless of whether it is suspended in the sleep state (power saving state) or not. Battery and a complicated external circuit are required, and it is difficult to reduce the cost and size of the battery backup system. In addition, in a device that does not have a battery backup circuit such as a PC, when the power supply from the outside is interrupted due to an unexpected accident such as a power failure in the power saving state (saving work contents in the memory), The work contents in the memory could not be saved. For this reason, it was not possible to restore the state before the power failure to normal, and there was a possibility that the file that was working in the memory was destroyed.

  In view of the problems as described above, the present invention includes a power backup system capable of backing up the work contents of a memory at low cost even when there is an interruption in the supply of power from the outside due to a power failure or the like. An object is to provide electronic equipment.

  In order to solve the above problems, a power backup system according to the present invention includes a memory for storing work contents (for example, the memory module 130 in the embodiment), a power supply signal indicating that power is supplied to the memory, and a normal A main power supply that outputs a power saving mode signal instructing a transition from the mode to the power saving mode, and a power saving mode control means that outputs a power saving control signal indicating that the transition to the power saving mode has been received in response to the power saving mode signal ( For example, the ACPI controller 150 in the embodiment, and a power switching unit (for example, for switching the power supplied from the main power source to the memory from the high power consumption in the normal mode to the low power consumption in the power saving mode in response to the power saving control signal. Dual circuit 180) in the embodiment, auxiliary power source capable of supplying power toward the memory, and main power source Power supply control means (for example, the battery control unit 160 in the embodiment) capable of controlling the power supply from the auxiliary power supply by monitoring the output status of the power supply signal and the power saving control signal from the power saving mode control means. When the power supply signal from the main power supply to the power supply control means is cut off in the state of shifting to the power saving mode, the power supply control means controls to supply power from the auxiliary power supply to the memory.

  Further, in the power backup system configured as described above, when the power supply signal from the main power supply to the power supply control means is restored in a state where power is supplied from the auxiliary power supply to the memory, the power saving mode control means includes the power switching means and By stopping the output of the power saving control signal to the power control means, the power switching means switches the power supplied from the main power source to the memory to the high power consumption in the normal mode, and then the power control means changes from the auxiliary power source to the memory. The power supply for

  On the other hand, in order to solve the above problems, a power backup system according to the present invention includes a memory for storing work contents (for example, the memory module 130 in the embodiment) and a power supply signal indicating that power is supplied to the memory. And a main power supply that outputs a power saving mode signal instructing the transition from the normal mode to the power saving mode, and a power saving mode control that outputs a power saving control signal indicating that the transition to the power saving mode has been made in response to the power saving mode signal. Means (for example, ACPI controller 150 in the embodiment) and power switching means (in response to a power saving control signal) for switching power supplied from the main power source to the memory from high power consumption in the normal mode to low power consumption in the power saving mode ( For example, the dual circuit 180) in the embodiment, an auxiliary power source capable of supplying power toward the memory, Power supply control means (for example, battery control unit 160 in the embodiment) capable of controlling the power supply from the auxiliary power supply by monitoring the output status of the power supply signal from the power supply and the power saving control signal from the power saving mode control means; It has an interrupt signal transmission means (for example, the SMI handler 190 in the embodiment) for transmitting an interrupt signal to the mode control means, and the power supply signal from the main power source to the power control means is cut off in the normal mode state. When the power supply control means controls the power to be supplied from the auxiliary power supply to the memory, the interrupt signal transmission means that has received the power supply cutoff notification from the power supply control means sends the interrupt signal to the power saving mode. By transmitting to the control means, the power saving mode control means outputs a power saving control signal to the power switching means, and the power switching means switches from the normal mode to the power saving mode. .

  In the power backup system configured as described above, when the power supply signal from the main power source to the power control unit is restored, the power switching unit is preferably switched from the power saving mode to the normal mode.

  Furthermore, in order to solve the said subject, the electronic device which concerns on this invention comprises the power supply backup system in any one of Claim 1 to 5.

  In the electronic device having the above-described configuration, the device is preferably a disk array device.

  According to the power supply backup system of the present invention, even when the power supply to the memory is interrupted due to a power failure or the like in the state of shifting to the power saving mode of low power consumption, power is supplied to the memory from the auxiliary power supply. By performing the supplied control, the work content held in the memory can be backed up by the auxiliary power supply. Therefore, by shifting to the power saving mode, the work contents held in the memory are not lost even when the system is suspended in the sleep state, and the reliability of the backup system can be improved. Here, the auxiliary power source constituting the system may be a small battery having a small capacity and a low cost. This is because the system is in the state of shifting to the power saving mode, and it is sufficient that the auxiliary power supply secures enough power to back up the work content held in the memory. For this reason, a backup system can be realized at low cost without configuring a large-capacity power supply or a complicated external circuit in addition to the backup circuit constituting the system.

  In addition, when the power supply from the main power supply is restored, the power supplied from the main power supply to the memory is switched to the high power consumption in the normal mode, and then the power supply from the auxiliary power supply to the memory is performed. It is configured to stop. As described above, since the mode is switched to the normal mode when the supply of power from the auxiliary power supply is stopped, the operation of the memory can be resumed in the normal mode state when the supply of power from the main power supply is restored.

  Further, according to the power backup system of the present invention, when power supply is interrupted due to a power failure or the like in the normal mode, the power is supplied from the auxiliary power source to the memory, and then the normal mode is switched to the power saving mode. Therefore, the operation of the memory from the time when the power supply is cut off due to a power failure or the like until the mode is switched to the power saving mode is guaranteed. For this reason, it is possible to prevent data loss and system destruction due to a power failure during system operation. Since the power supply signal from the main power supply is restored and the mode is automatically switched to the normal mode again, the operation of the memory can be resumed when the power supply is restored.

  The power backup system of the present invention can be applied to various electronic devices, but is particularly suitable for a disk array device that stores a large amount of input / output data with a host device and requires both performance and reliability. be able to.

  A preferred embodiment of the ACPI system according to the present invention will be described below with reference to FIGS. The ACPI system corresponds to a so-called sleep state S3, which is a power saving state in which the work state is stored in the memory module. This system can be applied to a memory backup circuit of an electronic device such as a disk array device, but can be applied not only to the disk array device but also to various electronic devices such as other storage systems and computers.

  Here, first, a first embodiment of the present invention will be described. As shown in FIG. 1, the ACPI system 100 includes a main power supply 110, a memory VR circuit 120 (stabilized power supply circuit), a memory module 130, an ACPI controller 150, a battery controller 160, an auxiliary power supply 170, a dual circuit 180, A Schottky barrier diode 162 is included. The memory VR circuit 120 includes a coil and a capacitor for current stabilization and rectification. The main power supply 110 and the like are electrically connected via a signal line, and a part of the signal line is grounded.

  When the ACPI controller 150 is in an AC-ON state (a state where electric power is supplied to the ACPI system 100 from the outside), the main power supply 110 supplies a 5V standby signal (power saving mode signal) via the signal line 114 to the ACPI controller 150. And output to the battery control unit 160. Further, when the DC-ON signal is input from the ACPI controller 150 via the signal line 152, the main power supply 110 starts outputting a 5V power signal via the signal line 111 toward the dual circuit 180. Then, after the output of the 5V power supply signal is stabilized, the main power supply 110 validates the power supply determination signal (power supply signal) via the signal line 113 directed to the battery control unit 160. This power supply determination signal indicates that a 5 V power supply signal is output from the main power supply 110 in order to supply power from the main power supply 110 to the memory module 130. In a state where the DC-ON signal is not output from the ACPI controller 150, the main power supply 110 disables the power supply determination signal and then stops outputting the 5V power supply signal to the dual circuit 180. Furthermore, when the ACPI system 100 is suspended in the sleep state S3, the main power supply 110 invalidates the power supply determination signal for the battery control unit 160.

  The dual circuit 180 is controlled by a sleep state control signal (hereinafter referred to as “S3 control signal”) via the signal line 153 output from the ACPI controller 150, and is output from the main power supply 110 to the memory VR circuit 120. The signal to be switched is switched between a 5 V power supply signal via the signal line 111 and a 5 V standby (suspend) signal via the signal line 112. Specifically, when the S3 control signal is invalid, the dual circuit 180 outputs a 5V power signal supplied from the main power supply 110 via the signal line 111 to the memory VR circuit 120. On the other hand, when the S3 control signal is valid, that is, when the system is in the suspended state, the dual circuit 180 outputs a 5V standby signal supplied from the main power supply 110 via the signal line 112 to the memory VR circuit 120. .

  The memory VR circuit 120 is connected to the dual circuit 180 via the power supply line 140, and the memory module 130 is connected to the memory VR circuit 120 via the power supply line 141.

  In the suspended state of ACPI system 100, ACPI controller 150 outputs an S3 control signal for controlling 5V dual circuit 180 and battery controller 160 to signal line 153 and signal line 151, respectively. On the other hand, when the ACPI system 100 returns from the suspended state, the S3 control signal is invalidated. Further, the DC-ON signal of the main power supply 110 is controlled to be turned ON / OFF by supplying and blocking the DC-ON signal via the signal line 152 toward the main power supply 110.

  The battery control unit 160 receives an S3 control signal from the ACPI controller 150 via the signal line 151 and a power supply confirmation signal from the main power supply 110 via the signal line 113 as input signals for battery control. . The battery control unit 160 is connected to the auxiliary power source 170 via the battery input line 163. The battery control unit 160 and the power supply line 141 are connected by the battery output line 161 via the Schottky barrier diode 162. The battery control unit 160 starts supplying power from the auxiliary power supply 170 to the memory module 130 via the battery input line 163 and the battery output line 161 using the invalidity of the power supply determination signal and the validity of the S3 control signal as start conditions. .

  The ACPI controller 150 and the battery control unit 160 use a 5V standby signal via the signal line 114 as their drive power supply. In addition, the ACPI controller 150 and the battery control unit 160 are connected to each other via the signal line 164 and the signal line 163 by the auxiliary power supply 170 even when the standby signal of 5 V toward the ACPI controller 150 is stopped due to a power failure or the like. The operating state is backed up.

  Next, the operation of the ACPI system 100 configured as described above will be described.

  In the state of the sleep state S0, that is, in the full operation state (CPU is also operating), the main power supply 110 validates the power supply determination signal 113, and the ACPI controller 150 invalidates the S3 control signal. In this case, the dual circuit 180 outputs a 5V power supply signal 111 to the memory VR circuit 120 and supplies power to the memory module 130.

  When the suspension to the sleep state S3 is started, the ACPI system 100 causes the memory module 130 to save the context information that is the work content at that time. When the saving of the context information to the memory module 130 is completed, the ACPI controller 150 enables the S3 control signal and disables DC-ON. When the dual circuit 180 recognizes that the S3 control signal is valid, the dual circuit 180 switches the signal from the main power supply 110 to the memory VR circuit 120 to a standby signal of 5V. When the main power supply 110 recognizes the invalidity of the DC-ON signal, the main power supply 110 invalidates the power supply determination signal and turns off the DC-ON signal. At this time, the ACPI controller 150 can validate the S3 control signal by 100 μs earlier than invalidating the DC-ON signal by an internal timer provided therein. For this reason, it is possible to supply power from the auxiliary power supply 170 toward the memory module 130 without giving time to stop the supply of power from the main power supply 110.

  When the supply of power from the auxiliary power supply 170 is started, the battery control unit 160 continues to supply power from the auxiliary power supply 170 to the memory module 130 until the power confirmation signal becomes valid thereafter. In this case, the state of the S3 control signal does not affect the continuation of the output from the auxiliary power supply 170. Since the standby signal 112 of 5V is output unless the AC is turned off due to a power failure or the like, power is supplied from the outside toward the memory module 130, so that the consumption current of the auxiliary power supply 170 becomes 0A.

  When the ACPI system 100 is suspended in the sleep state S3 and becomes AC-OFF due to a power failure or the like, a 5V standby signal from the main power supply 110 is not output. In this case, power supply from the memory VR circuit 120 to the memory module 130 is stopped, but power supply from the auxiliary power supply 170 to the memory module 130 is continued, so that the context information in the memory module 130 is retained. .

  When the DC-ON is executed by the AC-LINK function or the DC switch after the power is restored, the ACPI controller 150 validates the DC-ON signal and invalidates the S3 control signal 151. When the main power supply 110 recognizes the validity of the DC-ON signal, the main power supply 110 starts outputting the 5V power supply signal, and after the output of the 5V power supply signal is stabilized, enables the power supply determination signal directed to the battery control unit 160. When the ACPI system 100 recognizes that the power supply determination signal is valid, the ACPI system 100 starts returning to the sleep state S0 (full operation state). When the battery control unit 160 recognizes the validity of the power supply determination signal, the battery control unit 160 stops the output from the auxiliary power supply 170 to the battery output line 161. At this time, since the output from the memory VR circuit 120 to the memory module 130 is also started, the context information in the memory module 130 is retained, and the ACPI system 100 normally returns to the state before suspension.

  Next, a second embodiment of the system according to the present invention will be described with reference to FIG. 2 with a focus on differences from the first embodiment.

  Similarly to the first embodiment, the system 100 ′ in the present embodiment also includes a main power supply 110, a memory VR circuit 120, a memory module 130, an ACPI controller 150, a battery control unit 160, an auxiliary power supply 170, a dual circuit 180, and the like. However, it is configured to have an SMI (System Management Interrupt) handler 190, and the connection configuration of several signal lines is different from that of the first embodiment.

  As shown in FIG. 2, the battery control unit 160 is connected to a power supply line 140 between the dual circuit 180 and the memory VR circuit 120 via a battery output line 161 ′. A Schottky barrier diode 162 is provided on the battery output line 161 ′. Further, the SMI handler 190 is connected to the ACPI controller 150 via the signal line 191 and is connected to the battery control unit 160 via the signal line 192.

  Under such a configuration of the system 100 ′, the operation of the system 100 ′ when an AC-OFF suddenly occurs due to a power failure or the like while the system 100 ′ is operating in the sleep state S0 (full operation state) will be described. When a power failure occurs, when the battery control unit 160 recognizes that the power determination signal from the main power supply 110 via the signal line 113 is invalid, a signal input from the auxiliary power supply 170 via the battery input line 163 is received. The battery control unit 160 starts outputting a signal to the battery output line 161 ′. The signal output to the battery output line 161 is sent to the memory VR circuit 120 via the power supply line 140 and further supplied to the memory module 130 via the power supply line 141. For this reason, the output of the main power supply 110 is stopped due to a power failure or the like, but the system 100 ′ maintains the state of the sleep state S0.

  When the battery control unit 160 starts outputting a signal to the battery output line 161, the battery control unit 160 notifies the SMI handler 190 via the signal line 192. Receiving this, the SMI handler 190 requests the ACPI controller 150 to suspend to the sleep state S3 via the signal line 191. When the ACPI controller 150 recognizes the suspend request to the sleep state S3, the ACPI controller 150 validates the S3 control signal for the battery control unit 160 and saves the context information in the memory module 130, and then suspends to the sleep state S3. Let it begin. After the suspension to the sleep state S3 is started, the system 100 ′ normally returns to the state before the suspension when the power is restored.

  The system 100 ′ according to the present embodiment requires a power source that can guarantee the operation from the time of AC-OFF due to a power failure or the like until the system 100 ′ is suspended, and thus has a slightly larger capacity than the system 100 according to the first embodiment. Although it requires a power supply, it has the effect of preventing data loss and system destruction due to a power failure during system operation.

  As described in detail above, according to the power backup system of the present invention, even when the power supply to the memory is interrupted due to a power failure or the like in the state of shifting to the power saving mode of low power consumption, By controlling the power supply to the memory from the auxiliary power source, the work content held in the memory can be backed up by the auxiliary power source. Therefore, by shifting to the power saving mode, the work contents held in the memory are not lost even when the system is suspended in the sleep state, and the reliability of the backup system can be improved. Here, the auxiliary power source constituting the system may be a small battery having a small capacity and a low cost. This is because the system is in the state of shifting to the power saving mode, and it is sufficient that the auxiliary power supply secures enough power to back up the work content held in the memory. For this reason, a backup system can be realized at low cost without configuring a large-capacity power supply or a complicated external circuit in addition to the backup circuit constituting the system.

  In addition, when the power supply from the main power supply is restored, the power supplied from the main power supply to the memory is switched to the high power consumption in the normal mode, and then the power supply from the auxiliary power supply to the memory is performed. It is configured to stop. As described above, since the mode is switched to the normal mode when the supply of power from the auxiliary power supply is stopped, the operation of the memory can be resumed in the normal mode state when the supply of power from the main power supply is restored.

  Further, according to the power backup system of the present invention, when power supply is interrupted due to a power failure or the like in the normal mode, the power is supplied from the auxiliary power source to the memory, and then the normal mode is switched to the power saving mode. Therefore, the operation of the memory from the time when the power supply is cut off due to a power failure or the like until the mode is switched to the power saving mode is guaranteed. For this reason, it is possible to prevent data loss and system destruction due to a power failure during system operation. Since the power supply signal from the main power supply is restored and the mode is automatically switched to the normal mode again, the operation of the memory can be resumed when the power supply is restored.

  In addition, the power backup system of the present invention can be applied to various electronic devices, but is particularly suitable for disk array devices that store a large amount of input / output data with a host device and require both performance and reliability. be able to.

  The power backup system according to the present invention and an electronic device including the power backup system can be applied to a mobile phone, a digital home appliance, and the like.

1 is a schematic circuit diagram of a power backup system according to the present invention. It is a schematic circuit diagram in 2nd Example of the power supply backup system which concerns on this invention.

Explanation of symbols

100,100 'ACPI system (power backup system)
110 Main power supply 120 Memory VR circuit 130 Memory module (memory)
150 ACPI controller (power saving mode control means)
160 Battery control unit (power control means)
170 Auxiliary power supply 180 Dual circuit (power switching means)
190 SMI handler (interrupt signal transmission means)

Claims (6)

A memory for storing work contents;
A main power supply that outputs a power supply signal indicating that power is supplied to the memory and a power saving mode signal instructing a transition from the normal mode to the power saving mode;
A power saving mode control means for receiving a power saving mode signal and outputting a power saving control signal indicating that an instruction to shift to the power saving mode has been made;
Power switching means for switching the power supplied from the main power source to the memory in response to the power saving control signal from high power consumption in the normal mode to low power consumption in the power saving mode;
An auxiliary power supply capable of supplying power to the memory;
Power supply control means capable of controlling the power supply signal from the auxiliary power supply by monitoring the output status of the power supply signal from the main power supply and the power saving control signal from the power saving mode control means,
When the power supply signal from the main power supply to the power supply control means is interrupted in the state of shifting to the power saving mode, the power supply control means controls the power supply from the auxiliary power supply to the memory. A power backup system characterized by being made. When a power supply signal from the main power supply to the power supply control unit is restored in a state where power is supplied from the auxiliary power supply to the memory,
When the power saving mode control means stops outputting the power saving control signal to the power switching means and the power supply control means, the power switching means increases the power supplied from the main power source to the memory in the normal mode. 2. The power backup system according to claim 1, wherein after switching to power consumption, the power control unit stops supplying power from the auxiliary power to the memory. 3. A memory for storing work contents;
A main power supply that outputs a power supply signal indicating that power is supplied to the memory and a power saving mode signal instructing a transition from the normal mode to the power saving mode;
A power saving mode control means for receiving a power saving mode signal and outputting a power saving control signal indicating that an instruction to shift to the power saving mode has been made;
Power switching means for switching the power supplied from the main power source to the memory in response to the power saving control signal from high power consumption in the normal mode to low power consumption in the power saving mode;
An auxiliary power supply capable of supplying power to the memory;
Power supply control means capable of monitoring the power supply signal from the main power supply and the power saving control signal output status from the power saving mode control means to control the power supply from the auxiliary power supply;
Having an interrupt signal transmitting means for transmitting an interrupt signal toward the power saving mode control means,
When the power supply signal from the main power supply to the power supply control means is interrupted in the state of the normal mode, the power supply control means controls the power to be supplied from the auxiliary power supply to the memory. The interrupt signal transmitting means that has received a notification of power supply cutoff from the power control means transmits an interrupt signal to the power saving mode control means, so that the power saving mode control means sends the power saving control signal to the power switching means. And the power switching means switches from the normal mode to the power saving mode.   4. The power backup system according to claim 3, wherein when the power supply signal from the main power source to the power control unit is restored, the power switching unit switches the power saving mode to the normal mode. 5.   An electronic apparatus comprising the power supply backup system according to claim 1.   6. The electronic device according to claim 5, wherein the device is a disk array device.

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