JP2002358169A - Semiconductor disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high speed access to start from a higher rank host in the middle of a saving operation by ensuring the temporal continuity of non- volatile memory data. SOLUTION: This semiconductor disk device is provided with semiconductor memories, that is, first and second non-volatile memoirs 101 and 102, a third non-volatile memory 103 whose capacity is the same, a control circuit part 104 for integrally controlling them, a battery 107 for supplying power at power disconnection, a power source control part 106 for controlling power supply from a battery or an external power source device 110, and a control part 105 of interface with a higher rank host 109. In this case, the first memory and the second memory is constituted as a duplexed structure in a conductive state, and at power failure, the duplexed structure is released, and the contents of the second memory are data-saved to the third memory, and when the power source is restored during the saving operation, the data transfer to the higher rank host is operated by the first memory in response to a reading and writing command from the higher rank host, and all the contents of the second memory are saved to the third memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor disk device, and more particularly to a technique for saving data in a semiconductor disk device using a semiconductor memory.

[0002]

2. Description of the Related Art With the increase in the speed of computers, the demand for storage devices that can be accessed at higher speeds than magnetic disk devices that have been widely used in the past has increased the overhead such as rotation waiting time and head movement time as in magnetic disk devices. There has been provided a semiconductor disk device which does not have a high speed and can be accessed at a high speed. However, in order to realize high-speed access, a volatile memory such as a DRAM or an SRAM is often used. When the power is turned off, stored data is lost. A magnetic disk, a flash ROM, and a battery for storing the contents are mounted, and when the power is turned off, the contents of the volatile memory are saved to the magnetic disk or the flash ROM by power supply from the battery. When the power is turned on, the data saved in the flash ROM or the magnetic disk is transferred to the volatile memory, the data is restored, and a read / write command from the host is issued to the volatile memory. In the above-described semiconductor disk device, when the power is restored during the above-described data evacuation operation and a write command is issued from an upper-level host, it is disclosed in Japanese Patent Application Laid-Open No. 5-14324.
According to Japanese Patent Application Publication No. 8 (1999) -1995, in order to shorten the data restoration time, after the power is restored, the data evacuation operation of the volatile memory is stopped.
A process is performed in which the contents of the volatile memory are made valid, and reading and writing are performed only to the volatile memory in accordance with an instruction from an upper host. Further, according to Japanese Patent Application Laid-Open No. 7-36638, a read / write command from a higher-order host is not received until the amount of stored battery power reduced by performing a retreat operation started by power-off is restored. The processing performed only on the magnetic disk is performed.

[0003]

SUMMARY OF THE INVENTION However, Japanese Patent Application Laid-Open No.
In Japanese Patent No. 43248, since the evacuation operation is interrupted immediately after the power recovery during the evacuation operation, the data becomes discontinuous in time when attention is paid to the evacuation data. For this reason, when the save data is restored to the volatile memory, the data can be loaded into the volatile memory as binary data without any problem. There is a problem that the file cannot be recovered (uniqueness is not maintained) and cannot be recovered as a file. Also, JP-A-7-36
In Japanese Patent No. 638, the evacuation operation is performed when the amount of stored power of the battery is insufficient, and the operation is performed by the magnetic disk device in which the data has been saved until the battery is fully charged. Because the nature is not maintained,
There is a similar problem. Further, there is a problem that performance is deteriorated.

SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, it is an object of the present invention to secure temporal continuity of non-volatile memory data and to realize high-speed access with respect to activation from a higher-order host during a save operation.

[0005]

According to another aspect of the present invention, there is provided a semiconductor disk device using a semiconductor memory, comprising: a first volatile memory and a second volatile memory; Three nonvolatile memories, the first volatile memory and the second volatile memory in a duplex configuration when the external power supply is energized, and in the event of a power failure, release the duplex configuration,
When the data in the second volatile memory is saved to the third nonvolatile memory and the external power supply is restored during the saving operation,
The entire contents of the second volatile memory are saved to the third nonvolatile memory while data is transferred to the upper host by the first volatile memory in response to a read / write command from the upper host. Here, in a normal state in which the first volatile memory and the second volatile memory are operating in a redundant configuration, when a forced evacuation command is received from an upper-level host, all contents of the second volatile memory are copied to the second volatile memory. It is saved to the third non-volatile memory.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the semiconductor disk device of the present invention. In FIG. 1, a semiconductor disk 1
00 is connected to the host 109 via the connection bus 111. The semiconductor disk device 100 includes a first volatile memory 101, a second volatile memory 102 having the same capacity as the first volatile memory 101, and a third nonvolatile memory 1 having the same capacity as the first volatile memory 101.
03, the control circuit unit 104, and the interface control unit 1
05, a power control unit 106, and a battery 107. The control circuit unit 104 controls the semiconductor disk device 100 as a whole, and includes a microprocessor 112, a ROM 113 storing firmware, and a work memory 114.
including. The first volatile memory 101, the second volatile memory 102 and the third nonvolatile memory 103 are connected to the internal bus 11
8 connects to the control circuit unit 104 so that the first and second volatile memories 101 and 102 and the third nonvolatile memory 103 can be freely read and written. When the power supply to the semiconductor disk 100 is cut off due to a power cut due to a system stop of the external power supply device 110 or the like, the battery 107 stores the first and second volatile memories 101 and
102, third nonvolatile memory 103, and control circuit unit 10
4 and the power supply control unit 106. The power supply control unit 106 constantly monitors the power supply state of the external power supply 110 and supplies power to the external power supply 110 or the battery 10.
7 to control the power supply from the external power supply 11
When the power supply interruption of 0 is detected, the power supply is immediately switched to the battery 107, the power supply is notified to the control circuit unit 104 by the power failure detection signal 108, and the battery supply stop signal 116 from the control circuit unit 104 is received. Has the function of stopping the power supply from the battery 107. The interface control unit 105 includes a host
It controls the interface, such as controlling the interface protocol with the interface. Here, in the present embodiment, the DRA is stored in the first and second volatile memories 101 and 102 specifically.
M, and a flash ROM is used for the third nonvolatile memory 103.

In the operation of the present embodiment, an instruction from an upper host 109 is transmitted via a connection bus 111 to an interface controller 105 for controlling an interface protocol and the like.
Conveyed to. The interface control unit 105 transmits a command from the host 109 to the control circuit unit 104, and stores a firmware in the control circuit unit 104 in the ROM.
The microprocessor 112 operates by the 113 and the work memory 114 to decode and recognize the instruction from the host 109. According to this command, the data sent from the host 109 is written to the first volatile memory 101 and the second volatile memory 102. Further, data is read from the first volatile memory 101 in accordance with the command, and is transferred to the host 109 via the interface control unit 105. When the power supply from the external power supply 110 is stopped, the power supply control unit 106 detects this and supplies a power failure detection signal 1
08 is made valid, and the control circuit unit 104 that recognizes this saves the contents of the second volatile memory 102 to the third nonvolatile memory 103. When the evacuation is completed normally, the control circuit unit 104 enables the battery power supply stop signal 116, and the power supply control unit 106 that has detected the
Stop the power supply from.

FIG. 2 shows a detailed control procedure of the present embodiment, and the operation will be described below with reference to FIG. First, in the present embodiment, six operation modes of an initial state 211 in which the external power supply device 110 is OFF, a data loading mode 212, a data matching mode 213, an online mode 214, a save mode 215, and an online & save mode 216 are described. Host 109 in each mode
Transfer of data to and from the first volatile memory 101, the second volatile memory 102, and the third volatile memory 103. First, when power supply is started by the external power supply device 110 from the power-off initial state 211, the data loading mode 212 is set, and the power failure detection signal 108 and the battery power supply stop signal 116 are invalidated. Next, the contents of the third nonvolatile memory 103 are loaded into the first volatile memory 101, and the contents of the first volatile memory 101 are validated (step 20).
1). After all the data loading to the first volatile memory 101 is completed for the area, the mode is set to the data matching mode 213, and the contents of the first volatile memory 101 are copied to the second volatile memory 102 in the background. Then, the contents of the first volatile memory 101 and the contents of the second volatile memory 102 are matched (step 202).
After the matching is completed, the microprocessor 112 sets the duplex flag 115 in the work memory 114.
First volatile memory 101 and second volatile memory 102
After the start of the data matching operation, the read command issued from the upper host 109 transfers the data of the first volatile memory 101 to the upper host 109 (step 204). Writing to both the memory 101 and the second volatile memory 102 (step 20)
3). After the matching of the first volatile memory 101 and the second volatile memory 102 has been completed for all areas and the duplex flag 115 has been set, the online mode 214 for normal operation is set. Volatile memory 101
And the second volatile memory 102 are treated as a duplex configuration.
The write command issued from the upper host 109 writes both the first volatile memory 101 and the second volatile memory 102 (step 205), and the read command writes the data in the first volatile memory 101 to the upper host 109. (Step 206). Here, the external power supply 110
When the power supply from the power supply is interrupted, the power supply control unit 106 detects that the power supply of the external power supply device 110 is cut off, and switches the power supply from the battery 107 to the first volatile memory 101 and the second volatile memory. The power is continuously supplied to 102, the third non-volatile memory 103, and the control circuit unit 104, and the power failure detection signal 108 is made valid to inform the control circuit unit 104 and shift to the save mode 215.
In the save mode 215, the microprocessor 112 in the control circuit unit 104 detects that the power failure detection signal 108 has become valid,
15 is cleared, the duplication of the duplicated first volatile memory 101 and the second volatile memory 102 is released (step 207), and the first volatile memory 101 and the second volatile memory 102 are deleted. Operate independently. First, the second volatile memory 102 is replaced with the third nonvolatile memory 103
Used for backup to the first volatile memory 10
1 considers the case where power is restored during the backup operation,
By power supply from the battery 107, data at the time of power interruption is held as it is. Next, the contents of the second volatile memory 102 are saved to the third nonvolatile memory 103 (step 2).
08). When all the contents of the second volatile memory 102 have been saved to the third nonvolatile memory 103, the microprocessor 112 in the control circuit unit 104 enables the battery power supply stop signal 116, and the power supply control that detects this The unit 106 stops supplying power from the battery 107 and enters the initial state 211. If the power of all the contents of the second volatile memory 102 in the save mode 215 is restored before the save to the third nonvolatile memory 103 is completed, the power supply control unit 106 detects this power restoration, Power failure detection signal 108
Is invalidated, the microprocessor 112 in the control circuit unit 104 detects this and recognizes that power has been restored. As a result, it becomes the online & evacuation mode 216,
First volatile memory 101 and second volatile memory 102
While the duplication release state is maintained, the save operation for saving the contents of the second volatile memory 102 to the third nonvolatile memory 103 is continuously performed (step 209). When a read / write command is issued from the upper host 109 in the online & save mode 216, the duplex with the second volatile memory 102 is released, and the first volatile memory 101 from which reading and writing are performed independently is performed. Data is read and written by using only
0). As a result, the contents of the second volatile memory 102 are the contents at the time when the power supply from the external power supply device 110 is stopped, that is, the contents of the third nonvolatile memory 102 while the uniqueness of the data when the system is stopped is secured. The data is saved to the memory 103. In the online & save mode 216, when the data of all the areas of the second volatile memory 102 has been saved to the third nonvolatile memory 103, the mode is shifted to the data matching mode 213, and the first volatile memory 101 is changed. Contents of the second volatile memory 102
In the background, the first volatile memory 101 and the second volatile memory 102 are duplicated (step 202), and the duplicate flag 115 is set to be valid. In the present embodiment, by performing the above control, the third non-volatile memory is maintained in a state where temporally continuous data maintains uniqueness, that is, in a state where consistency as a file system at the time of system termination is maintained. The first volatile memory 101 can be evacuated to the volatile memory 103 even during an evacuation operation.
, The command from the host 109 can be executed without deteriorating the performance.

FIG. 3 shows that in the present embodiment, in a normal state in which the contents of the first volatile memory 101 and the second volatile memory 102 are matched, a command or a switch is used from a system application or a user.
A detailed control procedure when a forced save instruction issued at an arbitrary timing is received will be described. In FIG. 3, the initial state 21
1, data loading mode 212, save mode 21
5 is the same as FIG. 2 and is therefore simplified. In FIG. 3, a first volatile memory 101 and a second volatile memory 1
When the command received from the user is a forced save instruction in the normal state in which the contents of No. 02 are matched, the forced save instruction is determined in the online mode 214, the duplex flag 115 is cleared, and the first volatile memory is cleared. The duplication of 101 and the second volatile memory 102 is released (step 30).
2) Forcibly transit to the online & save mode 216, and forcibly save all the contents of the second volatile memory 102 to the third nonvolatile memory 103. In the present embodiment, the control when the forced evacuation instruction is received makes it possible to avoid the non-evacuation of data in a system in which the frequency of power interruption such as 24-hour operation is extremely low.

[0010]

As described above, according to the present invention,
Even if the power is restored during the evacuation operation, the evacuation operation is continued when the power supply is stopped, that is, with the data at the time of system stop as it is, so the consistency as a file system is ensured and the uniqueness of data is ensured By using the volatile memory for access from the host in power recovery during the evacuation operation, a high-speed response can be achieved. In addition, by providing a function of forcibly saving data, it is possible to avoid a non-evacuation of data in a system in which the frequency of power interruption such as 24-hour operation is extremely low.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a semiconductor disk device according to the present invention.

FIG. 2 is a diagram showing a control procedure of the semiconductor disk device of the present invention.

FIG. 3 is a diagram showing a control procedure by a forced evacuation instruction of the semiconductor disk device of the present invention.

[Explanation of symbols]

101: first volatile memory, 102: second volatile memory, 103: third nonvolatile memory, 104: control circuit unit, 105: interface control unit, 106: power control unit, 107: battery, 108 ... power failure detection signal, 10
9 upper host, 110 external power supply, 111 connection bus, 112 microprocessor, 113 ROM
114: work memory, 115: duplex flag, 116
... Battery power supply stop signal, 118 ... Internal bus, 211 ...
Initial state, 212: Loading mode, 213: Data matching mode, 214: Online mode, 215 ...
Evacuation mode, 216 ... Online & Evacuation mode

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Kunio Suzuki, Inventor 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi Information & Control Systems Co., Ltd. (72) Wataru Kawamata 5-5-2 Omikacho, Hitachi City, Ibaraki Prefecture No. 1 Inside Hitachi Information & Control System Co., Ltd. (72) Inventor Terumitsu Obama 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi Information & Control System Co., Ltd. (72) Inventor Hiroaki Fukumaru Omika, Hitachi City, Ibaraki Prefecture 5-2-1, Machi-cho, Ltd. Information Control Systems Division, Hitachi, Ltd. F-term (reference) 5B018 GA04 HA04 KA03 MA22 NA01 NA06 QA05 5B065 BA05 EA23

Claims (2)

[Claims] 1. A semiconductor disk device using a semiconductor memory, comprising: a first volatile memory and a second volatile memory; a third nonvolatile memory having the same capacity as the first volatile memory and the second volatile memory; A control circuit unit for controlling, a battery for supplying power at the time of power failure of the external power supply, and an interface control unit for controlling an interface with an upper host, wherein the first volatile memory and the The second volatile memory has a dual configuration, and in the event of a power failure, the dual configuration is released, the data in the second volatile memory is saved to the third nonvolatile memory, and the external power supply is restored during the save operation In this case, the second volatile memory performs data transfer to the high-order host by the first volatile memory in response to a read / write command from the high-order host. Wherein the entire contents of the above are saved in the third nonvolatile memory. 2. The system according to claim 1, wherein, when the first volatile memory and the second volatile memory are operating in a duplex configuration in a normal state, when a forced evacuation command is received from the host, A semiconductor disk device wherein all contents of a second volatile memory are saved in the third nonvolatile memory.