JP4500185B2 - Operational amplifier - Google Patents

Description

  The present invention relates to an operational amplifier of a semiconductor integrated circuit, and particularly belongs to an operational amplifier circuit capable of obtaining a high gain.

  In the gain control type amplifier circuit, an operational amplifier is used. However, in recent years, the gain required for the gain control type amplifier is increasing, and errors due to insufficient gain of the operational amplifier are becoming apparent. Therefore, an operational amplifier with a high gain is required. When an operational amplifier having a gain of 60 dB is used to obtain a gain of 1000 times by constructing a gain control type amplifier circuit, an error of 50% occurs and cannot be practically used. However, if an operational amplifier having a gain of 100 dB is used, the error is increased. Within 1%, it can withstand practical use. It is important to improve the gain of the operational amplifier.

  When the gain control type amplifier shown in FIG. 9 is configured, the gain G of the entire circuit is expressed by Expression (1).

G = R2 / {R1 + (R1 + R2) (1 / g)} (1)
Here, g is the gain of the operational amplifier OP1.

The calculation is performed using an example in which R1 = 1 and R2 = 1000.
When OP1 is an ideal operational amplifier, since g = ∞, the gain G of the entire circuit is
G = R2 / R1 (2)
When R1 and R2 are substituted,
G = 1000/1 = 1000 (3)
It becomes. However, the gain g of OP1 is not actually ∞. When a general operational amplifier gain of 60 dB is substituted into equation (1), g = 1000.
G = 1000 / {1+ (1 + 1000) (1/1000)} ≈500 (4)
It becomes. Compared with the expression (3) in which OP1 is an ideal operational amplifier, it is about half, and cannot be put into practical use. This is because the gain of OP1 is small. If the gain of OP1 is set to 100 dB and is substituted into the equation (1), g = 100000.
G = 1000 / {1+ (1 + 1000) (1/100000)} ≈990 (5)
Thus, the difference from Equation (3) is within 1%, which is a practical value. This shows that improvement of the gain of the operational amplifier is important.

  As a means for increasing the gain of the gain control type amplifier, generally, a method is adopted in which the amplifier is configured in a series multi-stage connection. However, as shown below, the circuit scale increases, the current consumption increases, and the response speed decreases. There are many problems.

FIG. 10 is a circuit diagram showing an example of a conventional circuit configuration, in which an output voltage varies depending on an output current difference between a differential pair and a differential pair composed of M1 and M2. The gain is determined by the gain of the differential pair and the impedance of the constant current source composed of M5, M9, and M11, or the gain of the differential pair and the impedance of the constant current source composed of M4, M8, and M10. Generally, these values are not large, and the value obtained as the gain of the entire operational amplifier is about 60 dB. When trying to obtain a high gain using this operational amplifier, if it is configured with only one stage, as shown above, the error is large and it cannot be put into practical use. Is approximately doubled, and the current consumption is also approximately doubled.
Phillip E.M. Allen Douglas R.D. Holberg's "CMOS Analog Circuit Design"

  An object of the present invention is to solve the problem that an error increases when an operational amplifier having a low gain is used in a gain control type amplifier when a high gain is to be obtained. Although methods such as connecting control amplifiers in multiple stages in series have been adopted, there were problems such as being unsuitable for speeding up due to increased circuit scale, increased current consumption, and increased delay time. There is.

  The present invention constitutes an operational amplifier characterized by mounting two differential pairs having sources connected in common as means for obtaining a high gain. The drains of the first differential pair are connected to a constant current source and amplify the input signal. The current flowing in the drain of the second differential pair is controlled by the two transistors whose gate voltages are controlled by the output of the first differential pair, and the input signal is amplified. This signal is amplified by two output transistors whose gate voltages are controlled by the outputs of the second differential pair. Signal amplification is performed through these three stages of signal amplification functions.

  In addition, as a method for controlling the operating point of the output terminal, a method for adjusting the bias of the constant current source connected to the drain of the first differential pair by feeding back the output voltage is used in common with the source. There is a method of adjusting the bias voltage of the constant current source of the two differential pairs to be connected and the constant current source of the output unit.

  Further, depending on the load connected to the output terminal, the system may oscillate when the gain is 0 dB or more and the phase is 180 ° or more. In such a case, a capacitive element is connected for phase compensation. The connection point of the phase compensation capacitor is between the drain of the second-stage differential pair and the output terminal, or between the drain of the first-stage differential pair and the output terminal, or a mixture of both. Alternatively, mixing between the drain of the second-stage differential pair and the output terminal, mixing between the drain of the second-stage differential pair and the drain of the first-stage differential pair, or the difference of the first stage A mixture between the drain of the dynamic pair and the output terminal, and between the drain of the second-stage differential pair and the drain of the first-stage differential pair may be used.

  By using the circuit disclosed in the present invention, the gain of the operational amplifier can be improved. When a general Si-based semiconductor is used, a gain of g1 = 100000 or more can be easily obtained.

  The source has two differential pairs connected in common, and the two differential pairs are connected to the same two input terminals. The output of the first differential pair is configured to flow a current that is opposite to the current flowing through the second differential pair, thereby increasing the gain and controlling the current flowing through the output transistor with this output. To do.

  FIG. 1 shows one configuration example of the circuit of the present invention, in which two differential pairs with their sources connected in common are constituted by NMOS transistors MN11, MN12 and MN13, MN14, and as shown above, The input signal is amplified through the amplification function. As a result, an increase in one differential pair and two PMOSs can provide a very high gain with an equivalent current consumption, and a characteristic that can withstand practical use with a single-stage configuration.

  The gain of the operational amplifier can be improved by using the circuit of the present invention as shown in FIG. The gain g1 of the circuit shown in FIG. 1 is obtained by Expression (6).

g1 = gmn12 · Zp12 · gmp13 · Zn13 · gmp15 · Zn15
+ Gmn11 · Zp11 · gmp14 · Zn14 · gmp16 · Zn16 (6)
Here, gmn12 is the transconductance of MN12, Zp12 is the output impedance of MP12, gmp13 is the transconductance of MP13, Zn13 is the output impedance of MN13, gmp15 is the transconductance of MP15, Zn15 is the output impedance of MN15, and gmn11 is MN11. , Zp11 is the output impedance of MP11, gmp14 is the transconductance of MP14, Zn14 is the output impedance of MN14, gmp16 is the transconductance of MP16, and Zn16 is the output impedance of MN16.

  When a general Si-based semiconductor is used, a gain of g1 = 100000 or more can be easily obtained.

  The circuit shown in FIG. 1 is equipped with a bias adjustment circuit BIAS adjustment circuit 1 for adjusting an output operating point, and adjusts the gate voltages of PMOS transistors MP11 and MP12 constituting a constant current. Further, phase compensation capacitive elements C11, C12, C13, C14, C15, and C16 are connected. The capacitance element for phase compensation may be C11, C12 only, C13, C14 only, C11, C12, C13, C14, C11, C12, C15, C16, C13, C14, C15, C16. .

  FIG. 2 shows one configuration example of the circuit according to the present invention, in which two differential pairs having sources connected in common are constituted by NMOS transistors MN21, MN22 and MN23, MN24, and bias adjustment for adjusting the output operating point is performed. The circuit BIAS adjustment circuit 2 is mounted to adjust the constant current gate voltage composed of the NMOS transistors MN25, MN26, and MN27. Further, phase compensation capacitive elements C21, C22, C23, C24, C25, and C26 are connected. The capacitance element for phase compensation may be C21, C22 only, C23, C24 only, C21, C22, C23, C24, C21, C22, C25, C26, C23, C24, C25, C26. .

  FIG. 3 shows a configuration example of the circuit of the present invention, and is a circuit with a gain higher than that of the first embodiment. Two differential pairs with their sources connected in common are composed of NMOS transistors MN31, MN32 and MN33, MN34, a bias adjustment circuit BIAS adjustment circuit 3 for adjusting the output operating point is mounted, and a PMOS that constitutes a constant current The gate voltages of the transistors MP31 and MP32 are adjusted. In order to increase the output impedance of the PMOS transistors MP31 and MP32, MP37 and MP38 are cascode-connected to the drains of the PMOS transistors MP31 and MP32. Further, in order to prevent a decrease in transconductance due to channel length modulation of the PMOS transistors MP33 and MP34, MP39 and MP310 are cascode-connected to the drains of MP33 and MP34. Capacitance elements C31, C32, C33, C34, C35, and C36 for phase compensation are connected. The capacitance element for phase compensation may be C31, C32 alone, C33, C34 alone, C31, C32, C33, C34, C31, C32, C35, C36, or C33, C34, C35, C36. .

  When the output impedance of MP11 and MP12 is low, the output impedance can be increased by inserting MP37 and MP38 shown in FIG. Further, when gmp13 and gmp14 become low due to the influence of the channel length modulation of MP13 and MP14, gmp13 and gmp14 can be increased by inserting MP39 and MP310 shown in FIG. 3 by cascode connection.

  FIG. 4 shows one configuration example of the circuit of the present invention, which is a circuit with a gain higher than that of the second embodiment. NMOS transistors MN41, MN42 and MN43, MN44, and a bias adjustment circuit BIAS adjustment circuit 4 for adjusting an output operating point are mounted to form a constant current. The gate voltages of the transistors MN45, MN46, and MN47 are adjusted. In order to increase the output impedance of the PMOS transistors MP41 and MP42, MP47 and MP48 are cascode-connected to the drains of the PMOS transistors MP41 and MP42. In order to prevent a decrease in transconductance due to channel length modulation of the PMOS transistors MP43 and MP44, the MP49 and MP410 are cascode-connected to the drains of the MP43 and MP44. Capacitance elements C41, C42, C43, C44, C45, and C46 for phase compensation are connected. The capacitance element for phase compensation may be C41, C42 only, C43, C44 only, C41, C42, C43, C44, C41, C42, C45, C46, C43, C44, C45, C46. .

  FIG. 5 shows one configuration example of the circuit of the present invention, in which two differential pairs having sources connected in common are configured by PMOS transistors MP51, MP52 and MP53, MP54, and bias adjustment for adjusting the output operating point is performed. The circuit BIAS adjustment circuit 5 is mounted to adjust the gate voltages of the NMOS transistors MN51 and MN52 constituting the constant current. Further, phase compensation capacitive elements C51, C52, C53, C54, C55, and C56 are connected. The capacitance element for phase compensation may be C51, C52 only, C53, C54 only, C51, C52, C53, C54, C51, C52, C55, C56, C53, C54, C55, C56. .

  FIG. 6 shows one configuration example of the circuit of the present invention, in which two differential pairs having sources connected in common are configured by PMOS transistors MP61, MP62 and MP63, MP64, and bias adjustment for adjusting the output operating point is performed. The circuit BIAS adjustment circuit 6 is mounted to adjust the gate voltages of the PMOS transistors MP65, MP66, and MP67 constituting the constant current. Further, phase compensation capacitive elements C61, C62, C63, C64, C65, and C66 are connected. The capacitance element for phase compensation may be C61, C62 only, C63, C64 only, C61, C62, C63, C64, C61, C62, C65, C66, C63, C64, C65, C66. .

  FIG. 7 shows an example of the configuration of the circuit of the present invention, which is a circuit with a gain higher than that of the fifth embodiment. Two differential pairs whose sources are connected in common are composed of PMOS transistors MP71, MP72 and MP73, MP74, a bias adjustment circuit BIAS adjustment circuit 7 for adjusting an output operating point is mounted, and an NMOS which constitutes a constant current The gate voltages of the transistors MN71 and MN72 are adjusted. In order to increase the output impedance of the NMOS transistors MN71 and MN72, MN77 and MN78 are cascode-connected to the drains of the NMOS transistors MN71 and MN72. Further, in order to prevent a decrease in transconductance due to channel length modulation of the NMOS transistors MN73 and MN74, the MN79 and MN710 are cascode-connected to the drains of the MN73 and MN74. Capacitance elements C71, C72, C73, C74, C75, and C76 for phase compensation are connected. The capacitance element for phase compensation may be C71, C72 alone, C73, C74 alone, C71, C72, C73, C74, C71, C72, C75, C76, C73, C74, C75, C76. .

  FIG. 8 shows one configuration example of the circuit of the present invention, which is a circuit with a gain higher than that of the sixth embodiment. Two differential pairs whose sources are connected in common are composed of PMOS transistors MP81, MP82 and MP83, MP84, a bias adjustment circuit BIAS adjustment circuit 8 for adjusting an output operating point is mounted, and a PMOS which constitutes a constant current The gate voltages of the transistors MP85, MP86, and MP87 are adjusted. In order to increase the output impedance of the NMOS transistors MN81 and MN82, MN87 and MN88 are cascode-connected to the drains of the NMOS transistors MN81 and MN82. Further, in order to prevent a decrease in transconductance due to channel length modulation of the NMOS transistors MN83 and MN84, the MN89 and MN810 are cascode-connected to the drains of the MN83 and MN84. Capacitance elements C81, C82, C83, C84, C85, and C86 for phase compensation are connected. The capacitance element for phase compensation may be C81, C82 only, C83, C84 only, C81, C82, C83, C84, C81, C82, C85, C86, or C83, C84, C85, C86. .

  This is effective when it is necessary to amplify a minute potential difference of a sensor or the like with an accurate gain. Further, it is suitable as an operational amplifier for use in a circuit that requires high gain in a device that requires miniaturization and low power consumption such as a portable device.

Circuit diagram of the first embodiment according to the present invention Circuit diagram of the second embodiment according to the present invention. Circuit diagram of third embodiment according to the present invention Circuit diagram of the fourth embodiment according to the present invention. Circuit diagram of the fifth embodiment according to the present invention. Circuit diagram of the sixth embodiment according to the present invention. A circuit diagram of a seventh embodiment according to the present invention. Circuit diagram of the eighth embodiment according to the present invention. Circuit diagram showing an example of a general gain control type amplifier Circuit diagram of conventional operational amplifier

Explanation of symbols

VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7, VDD8... Power supply IN11, IN12, IN21, IN22, IN31, IN32, IN41, IN42, IN51, IN52, IN61, IN62, IN71, IN72, IN81, IN82 , Vi1, Vi2... Operational amplifier input terminals OUT11, OUT12, OUT21, OUT22, OUT31, OUT32, OUT41, OUT42, OUT51, OUT52, OUT61, OUT62, OUT71, OUT72, OUT81, OUT82, Vo1, Vo2. Terminals BIAS11, BIAS12, BIAS21, BIAS22, BIAS31, BIAS32, BIAS41, BIAS42, BIAS51, BIAS52, BIAS6 , BIAS 62, BIAS 71, BIAS 72, BIAS 81, BIAS 82... Bias terminal BIAS adjustment circuit 1, BIAS adjustment circuit 2, BIAS adjustment circuit 3, BIAS adjustment circuit 4, BIAS adjustment circuit 5, BIAS adjustment circuit 6, BIAS adjustment circuit 7, BIAS adjustment circuit 8... Output operating point adjustment bias adjustment circuit VCAS3, VCAS4, VCAS7, VCAS8... Cascode connection transistor gate bias MN11, MN12, MN13, MN14, MN21, MN22, MN23, MN24, MN31, MN32 , MN33, MN34, MN41, MN42, MN43, MN44, M1, M2... NMOS transistors MP11, MP12, MP21, MP22, MP31, MP32, MP41, MP constituting a differential pair 2... PMOS transistors MP13, MP14, MP23, MP24, MP33, MP34, MP43, and MP44 constituting a constant current source. A PMOS transistor MP15 that receives the output of the first differential pair and performs signal amplification. MP16, MP25, MP26, MP35, MP36, MP45, MP46, M4, M5... Output PMOS transistors MN15, MN16, MN17, MN25, MN26, MN27, MN35, MN36, MN37,
MN45, MN46, MN47, M3... NMOS transistors MP37, MP38, MP39, MP310, MP47, MP48, MP49, MP410, M6, M7 constituting a constant current source, cascode-connected PMOS transistors MP51, MP52, MP53, MP54, MP61, MP62, MP63, MP64, MP71, MP72, MP73, MP74, MP81, MP82, MP83, MP84... PMOS transistors MN51, MN52, MN61, MN62, MN71, MN72, MN81, constituting a differential pair MN82, M10, M11... NMOS transistors MN53, MN54, MN63, MN64, MN73, MN74, MN83, MN84... Constituting the constant current source and receiving the output of the first differential pair NMOS transistor MN55 to carry out width, MN56, MN65, MN66, MN75, MN76, MN85, MN86 ··· output NMOS transistor MP55, MP56, MP57, MP65, MP66, MP67, MP75, MP76, MP77,
MP85, MP86, MP87... PMOS transistors MN77, MN78, MN79, MN710, MN87, MN88, MN89, MN810, M8, M9... Cascode-connected NMOS transistor IN9. Input terminal OUT9 ... output terminals R1, R2 ... resistor OP1 ... operational amplifier BIAS ... bias voltage VSS ... ground M12, M13, M14, M16, M17 ... bias MOS transistors R1, R2... Cascode voltage generating resistors constituting current mirrors of current

Claims (10)

  The first and second NMOS transistors forming a first differential pair, and the third and fourth NMOS transistors forming a second differential pair, wherein the first, second, third, The sources of the fourth NMOS transistors are connected in common, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor that constitutes a constant current source, and the drain of the second NMOS transistor is connected to the drain of the second NMOS transistor. The drain of the second PMOS transistor constituting the constant current source is connected, and the drain of the third PMOS transistor whose gate is connected to the drain of the second NMOS transistor is connected to the drain of the third NMOS transistor. And the drain of the fourth NMOS transistor is connected to the drain of the first NMOS transistor. The drain of the connected fourth PMOS transistor is connected, and the gate of the first NMOS transistor and the gate of the third NMOS transistor are connected in common to serve as a first input terminal, and the second NMOS transistor And the gate of the fourth NMOS transistor are commonly connected to serve as a second input terminal, and the first, second, third, and fourth sources are commonly connected to a node connected to the second input terminal. An operational amplifier to which a constant current source composed of 5 NMOS transistors is connected.   5. The gate of a fifth PMOS transistor is connected to the drain of the third NMOS transistor in claim 1, and a constant current source composed of a sixth NMOS transistor is connected to the drain of the fifth PMOS transistor. This node is a first output terminal, and the drain of the fourth NMOS transistor is connected to the gate of the sixth PMOS transistor, and the drain of the sixth PMOS transistor is composed of the seventh NMOS transistor. An operational amplifier in which the constant current source is connected and this node becomes the second output terminal.   3. An operational amplifier in which a seventh PMOS transistor and an eighth PMOS transistor are cascode-connected to the drain of the first PMOS transistor and the drain of the second PMOS transistor according to claim 1 or 2.   4. An operational amplifier in which a ninth PMOS transistor and a tenth PMOS transistor are cascode-connected to the drain of the third PMOS transistor and the drain of the fourth PMOS transistor according to claim 1, 2 or 3.   The eleventh and twelfth PMOS transistors forming a third differential pair, and the thirteenth and fourteenth PMOS transistors forming a fourth differential pair, and the eleventh, twelfth, thirteenth, The sources of the fourteenth PMOS transistors are connected in common, the drain of the eleventh PMOS transistor is connected to the drain of an eighth NMOS transistor that constitutes a constant current source, and the drain of the twelfth PMOS transistor is connected. The drain of the ninth NMOS transistor constituting the constant current source is connected, and the drain of the tenth NMOS transistor whose gate is connected to the drain of the twelfth PMOS transistor is connected to the drain of the thirteenth PMOS transistor. A gate connected to the drain of the fourteenth PMOS transistor; The drain of the eleventh NMOS transistor connected to the drain of the MOS transistor is connected, and the gate of the eleventh PMOS transistor and the gate of the thirteenth PMOS transistor are connected in common to serve as a third input terminal. The gate of the twelfth PMOS transistor and the gate of the fourteenth PMOS transistor are commonly connected to form a fourth input terminal, and the eleventh, twelfth, thirteenth, and fourteenth sources are commonly connected. An operational amplifier to which a constant current source composed of a fifteenth PMOS transistor is connected to the node.   6. The gate of a twelfth NMOS transistor is connected to the drain of the thirteenth PMOS transistor according to claim 5, and a constant current source composed of a sixteenth PMOS transistor is connected to the drain of the twelfth NMOS transistor. This node is the third output terminal, and the drain of the 14th PMOS transistor is connected to the gate of the 13th NMOS transistor, and the drain of the 13th NMOS transistor is composed of the 17th PMOS transistor. An operational amplifier in which a constant current source is connected and this node becomes the fourth output terminal.   7. An operational amplifier in which a fourteenth NMOS transistor and a fifteenth NMOS transistor are cascode-connected to the drain of the eighth NMOS transistor and the drain of the ninth NMOS transistor according to claim 5 or 6.   8. An operational amplifier in which a sixteenth NMOS transistor and a seventeenth NMOS transistor cascode-connected to the drain of the tenth NMOS transistor and the drain of the eleventh NMOS transistor according to claim 5 or claim 6 or claim 7 are inserted.   An operational amplifier in which a phase compensation capacitance element is connected to the circuit shown in claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, or claim 8.   A bias adjustment circuit for adjusting an output operating point is added to the circuit shown in claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, or claim 9. Operational amplifier provided.

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