JP2888923B2 - Linearized differential amplifier - Google Patents

Description

Description of the Invention [Object of the Invention] (Industrial application field) The present invention relates to a linearized differential amplifier capable of obtaining a constant transconductance over a wide range.

(Prior Art) A differential amplifier pair, which is a component of a differential amplifier, is widely used as a basic structural unit of an amplifier, for example, as a first-stage amplifier of an operational amplifier.

FIG. 19 is a diagram for explaining a normal emitter-coupled pair, that is, a differential amplification pair. In the drawing, reference numerals 1 and 2 denote input terminals, reference numerals 3 and 4 denote output terminals, and reference numerals 5 and 6 denote first and second bipolar transistors which constitute a differential amplification pair, respectively.
Reference numerals 7 and 8 denote a DC voltage source for providing the first and second offset voltages, 9 a DC current source for determining an operating current of the differential amplifier pair, 10 a positive power supply line, and 11 a negative power supply. Lines, 12 and 13 represent load current sources, and 14 represents load resistance. Assume that the entire differential amplification pair except for the load 15 is 16.

In FIG. 19, the current value of the current source 9 is I _EE , the voltage values of the voltage sources 7 and 8 for giving an offset are zero, the current values of the load current sources 22 and 23 are I _EE / 2, and the input terminal 1 , the input voltage applied between 2 and V _d, the alpha _F transistors 5 and 6
Forward common base current amplification factor of, when the V _T is the thermal voltage,
Current I _d flowing through the load resistor 14 is expressed by the following formula [e.g. literature (Paul R.Gray and Robert G.Meyer: " Analysis an
d Design of Analog Integrated Circuits "second edit
ion, pp. 194-197, John Wiley & Sons, Inc., New York, 1
984)].

Relationship _{I d = α F · tanh (} -V d / 2V T) ...... (1) the input voltage V _d and the output current I _d, as shown in Figure No. 20 (a), the absolute value of V _d is smaller In this case, I _d changes linearly in proportion to V _d , but as the absolute value of V _d increases, I _d deviates from the linear change and approaches ± I _EE .

How to see if there is a linear range, obtained by differentiating the curves in the input voltage V _d, i.e. conveniently examining the curve of the transconductance Gm is better represented by the following formula.

_{G m (V d) = (} α F · I EE) / 2V T · [1-tanh 2 (-V d / 2V T)] ...... (2) curve of G _m twentieth diagram (b) As shown, it has a symmetrical bell shape.

In the following description, for simplicity, the following normalization is performed: x = −V _d / 2V _T y = I _d / α _F I _EE (3) 2) will be normalized as follows to proceed with the description.

y = tanh (x) (4) G _m (x) = dy / dx = 1−tanh ² (x) (5) Generally, an operational amplifier is used with negative feedback.
Since the second and subsequent stages have a large gain, the inverting and non-inverting input terminals of the differential amplifier pair constituting the first stage are imaginary short between the input terminals, and the potential difference between the input terminals is a very small value of, for example, about several millivolts. Becomes Therefore, in this case, the linearity of the differential amplification pair hardly matters.

On the other hand, the differential amplification pair has its transconductance
Utilizing that G _m can be changed in proportion to the operating current, it is used for filters, multipliers, oscillators and the like. In this case, it is common for the voltage applied between the input terminals of the differential amplifier pair to be large in the linear operation range for reasons such as the S / N ratio. Therefore, a larger linear operating range is required to handle larger input signals.

However, as shown in FIG. 20 (b), in the conventional differential amplifier pair, when the transconductance Gm is near V _d = 0, the flat portion is very narrow, and for example, the absolute value of Gm is the maximum value. range of V _d 1% decrease from is about 10mV about at room temperature.

There is an example of a method called emitter degeneration, in which the emitters of a differential amplification pair are not directly connected but connected via a resistor to provide local negative feedback to expand the linear range. This method is simple and effective, but not only increases the noise due to the resistance,
It is difficult to change the transconductance due to the negative feedback, and this is a disadvantage in some applications such as filter applications.

As a method that can change the transconductance using the emitter degeneration, there is a method using a Gilbert gain cell type differential amplifier.

Regarding the gain cell itself, for example, pp. 5
90-600 or by A. Grebene: "Analog Integrated Circuits"
pp. 234-244 (Nakazawa et al., Modern Science Co., 1975), etc., so they will not be described much here, but in short, this method uses the first differential amplifier pair for emitter degeneration. A transistor having a resistor and a short circuit between the base and collector is provided as a load, and the potential difference between both ends is used as an input of a second differential amplifier pair having no emitter degeneration resistor. Thus, the transconductance from the base input terminal of the first differential amplification pair to the collector output terminal of the second differential amplification pair is changed by changing the current of the common emitter of the second differential amplification pair. Can be increased.

Further, the differential amplifier using this gain cell can easily realize a linear input range of about 1 volt.
Japanese Patent Application Laid-Open No. 58-161413 "Multi-purpose filter" is an example of a filter using such a linearized differential amplifier.

However, as a problem of this method, since the signal voltage is compressed and expanded to cancel the exponential function characteristics of the transistor, the linear range is wide, but the S / N ratio is worse than a simple differential amplifier pair There is a disadvantage that.

To solve this problem, a proposal to linearize a differential amplification pair without using emitter degeneration has been proposed in the literature (James C. Schmoock: “An Input Transconductance
Reduntion Technique for High-Slew Rate Operation
al Amplifiers, IEEE Journal of Solid ＝ State Circuit
s, SC-10, no. 6, pp. 407-411, December 1975).

Originally, this proposal mainly used a method of reducing transconductance by using two pairs of differential amplification pairs having asymmetrical emitter areas. However, when the emitter area ratio was about 1: 4, the linear operating range was the most effective. States that it will spread.

However, in this method, although the linear range can be expanded about four times as compared with the case where a conventional simple differential amplifier pair is used, it is still not sufficient. However, since the input terminal is directly at the base of the transistor, the input impedance is large.

Further, in order to obtain a wide linear operation range, a proposal for linearizing a differential amplifier pair without using emitter degeneration has been made in Japanese Patent Application Laid-Open No. 62-200808 "Transconductance amplifier". This method can obtain a very wide linear range comparable to a linearized differential amplifier using a gain cell, and has excellent characteristics with a good S / N ratio.

The principle of this method is, in a nutshell,
Class operation, for which an operating current corresponding to the input voltage is given. In order to realize this, the input voltage is divided by a resistor and applied to the bases of a plurality of transistors, but since these resistors are inserted in series with the base, in terms of noise and frequency characteristics, It is not preferable to make the value too large. Therefore, in order to take advantage of the features of this circuit, the input resistance must be reduced, which is a problem. For example, since a capacitor can be connected to the output terminal of the transconductance amplifier to form an integrator, a filter can be formed by connecting a plurality of the integrators to each other. However, this means that the output terminal of one integrator is connected to the input terminal of another integrator, so that the output terminal of one integrator is loaded with the low input resistance of another integrator and the filter The problem is that the Q value of is significantly reduced.

(Problems to be Solved by the Invention) The above situation is summarized as follows.

A differential amplifier having a wide linear operating range and a variable transconductance is required in filters, multipliers, oscillators, and the like.
The gain cell type differential amplifier circuit using the conventional emitter degeneration has a wide linear operation range but a poor S / N ratio.

A class AB differential amplifier circuit that does not use emitter degeneration has a wide linear range and a good S / N ratio, but has a low input impedance.

In view of these points, an object of the present invention is to provide a linearized differential amplifier having a wide linear operation range and a high input impedance.

[Structure of the Invention] (Means for Solving the Problems) A linearized differential amplifier according to the present invention for achieving the above object has a structure in which input terminals and output terminals of a differential amplifier pair using bipolar transistors are connected. In a differential amplifier connected in parallel, N is an integer of 4 or more, and N
A pair of differential amplification pairs, a means for applying an equivalent offset voltage to each differential amplification pair, a means for weighting these output currents, and a means for adding these output currents. Features.

(Function) When N is an integer of 4 or more, and N is an integer different from each other, an appropriate offset voltage is given to each of the N differential amplification pairs. , Takes a symmetrical value about its input voltage, and monotonically reduces its value for higher and lower voltages.

In the equation (2), V _d is the offset voltage
Numerical calculation can be performed by placing the sum of V _OS and V _d , which is obtained by translating the graph of FIG. 20B shown in equation (2) to the right by V _OS .

As described above, the transconductance of one differential amplification pair has a single-peak characteristic with respect to the input voltage.
By applying the same input voltage and a proper offset voltage to each of the differential amplification pairs, N peaks can be formed.

Therefore, by weighting and adding the output currents of the N differential amplification pairs, one peak having a flat top is synthesized from the N peaks having different heights to expand the linear operation range. Can be. Here, since the number of differential amplification pairs is four or more, the expansion range is 9 compared to a mere differential amplification pair.
This is more than doubled, which is sufficiently practical.

(Example) Hereinafter, an example of the present invention will be described.

First, the basic concept of the linearization in the present invention is that the transconductance Gm shown in FIG. 20 (a) is translated and given a positive / negative offset in the X-axis direction by a circuit as shown in FIG. A plurality is prepared, and they are weighted and added.

That is, in the linearized differential amplifier shown in FIG.
N differential amplification pairs 16 shown in the figure (N is an integer of 4 or more)
Each pair 16 includes an offset voltage applying means 17 (7, 8), an output current weighting means 18,
Adder 19 is provided between the load and the load 15.

The weighting means 18 can be provided on the collector side of each differential amplification pair, but can also be provided on the emitter side.

As the addition means 19, a normal electric addition circuit can be used, but when the output current of each differential amplification pair to be added is supplied with high impedance, it is particularly simple to simply connect each wiring. This is advantageous because it can be realized with a simple wired-OR circuit.

2 (a), 2 (b) and 2 (c) show examples of the load circuit. (A) shows an example of a resistive load 15A, (b) shows an example of a current mirror load 15B, and (C) shows an example of a load 15C provided with a current source having a bias voltage terminal 20.

Here, as can be seen from Figure 20 showing the conventional example (b), from the curve of G _m is a symmetry with respect to y- axis, in order to obtain as wide as possible linear operating range, the positive and negative offset with regard y- axis Should be given symmetrically. Similarly, it should give symmetrically with respect to weight also y- axis with respect to G _m for each of the differential amplifier pair 16. Therefore, when an odd number of differential amplification pairs (for example, 5, 7) are used, no offset is given to one differential amplification pair, and the remaining even-numbered differential amplification pairs are collectively set to an absolute value of two pairs. Are weighted so as to be equally symmetrically offset. If an even number (for example, 4, 6) of differential amplification pairs are used, the same procedure as that for the remaining even number of differential amplification pairs in the case of an odd number may be used.

Let G be the ultimately obtained conductance, α _K , β
The weighting factor for G _m , d _k is the k-th (k is an integer of 1 or more) offset value, N is the number of pairs of differential pairs, and [N / 2] is N / 2
As a symbol representing the integer part of Becomes

In the equation (6), the term with the sum sign indicates that a sum is obtained for k, and indicates a part obtained by combining two even-numbered differential amplification pairs. The term multiplied by β represents a portion where no offset is given when an odd number of differential amplification pairs are used. That is, when linearization is performed using even-numbered differential amplification pairs, β = 0, and when odd-numbered differential amplification pairs are used, β ≠ 0. For example, when linearization is performed using four differential amplification pairs, k = 1,2 because 4 = 2.2, and since 4 is an even number, β = 0 and G (x) = α ₁ {G _m (x−d ₁ ) + G _m (x + d ₁ )} + α ₂ {G _m (x−d ₂ ) + G _m (x + d ₂ )} (7)

In the linearization, it is desirable that the transfer conductance G, which is the first derivative of the current, take a constant value for x as wide as possible.

To do so, the value of the derivative of each order of G should approach zero over as wide a range as possible. A method often used as a function approximation method for approximating a constant value is:
There is a maximum flat approximation and an equiripple approximation.

The maximal flat approximation is an approximation method that makes the derivative of G at x = 0 zero to the highest possible order. The case where the derivatives up to the nth order are zero is called the nth-order maximum average characteristic.

The equiripple approximation seeks to achieve a constant portion of the transconductance with some predetermined tolerance.

For the following description, the result of calculating the derivative of each order of G _m is shown. Here, the n-th derivative of G _m is represented as Gm ⁽ⁿ⁾ .

^{Gm (0) = dy / dx} = 1-tanh 2 (x) = Gm ...... (8) Gm (1) = 2tanh 3 (x) -2tanh (x) ...... (9) Gm (2) = -6tanh ⁴ (x) +8 tanh ² (x) -2 ... (10) Gm ⁽³⁾ = 24 tanh ⁵ (x) -40 tanh ³ (x) + 16 tanh (x) ... (11) Gm ⁽⁴⁾ = -120 tanh ⁶ ( x) +240 tanh ⁴ (x) −136 tanh ² (x) +16 (12) Next, taking the case of using four differential amplification pairs as an example,
A first embodiment of the present invention will be described.

FIG. 3 is a circuit diagram for explaining the configuration of the first embodiment of the present invention. In the figure, 15 is a load, 16A, 16B, 16C, 16D
Are the first to fourth differential amplification pairs, 7A, 7B, 7C, and 7D are DC voltage sources as offset voltage applying means, and 9A, 9B, 9C, and 9D are the first to fourth differential amplification pairs, respectively. Current sources connected to the common emitter, 1, 2 represent input terminals, and 3, 4 represent output terminals.

First, a method of determining specific values of the voltage sources 7A, 7B, 7C, 7D and the current sources 9A, 9B, 9C, 9D will be described. Formula (6), which is a general expression, is specifically written as to the case where four differential amplification pairs are used.

G (x) = α ₁ [Gm (x−d ₁ ) + Gm (x + d ₁ )] + α ₂ [Gm (x−d ₂ ) + Gm (x + d ₂ )] (13) That is, Expression (13) is a circuit. Specifically, it corresponds to the sum of outputs of two pairs of differential pairs having an offset d ₁ and two pairs of differential pairs having an offset d ₂ at a ratio of weights α ₁ and α ₂ . The ratio between the weights α ₁ and α ₂ is important, and the generality is maintained even if α ₂ = 1. Furthermore, from consideration of symmetry, even if 0 <d ₁ <d ₂ (14), generality is not lost. Therefore, equation (13) can be transformed into the following equation.

G (x) = α ₁ [Gm (x−d ₁ ) + Gm (x + d ₁ )] + [Gm (x−d ₂ ) + Gm (x + d ₂ )] (15) The above equation is symmetric with respect to x = 0. Thus, the odd derivative of G (x) is zero at x = 0. Therefore, in order to obtain a flat transconductance characteristic over a wide range, it is an issue to determine a parameter so that even the highest-order even-order derivative becomes zero at x = 0.

Therefore, in the above equation (15), G ″ (0) = G ′
D ₁ , d ₂ , α ₁ that satisfies (0) = 0 are obtained. Here, a dash (') represents a derivative with respect to x. First, the conditions under which the second derivative becomes zero are examined.

G ″ (0) = 2α ₁ [−3X ⁴ + 4X ² −1] +2 [−3Y ⁴ + 4Y ² −1] (16) where X = tanh ² (d ₁ ), Y = tanh ² (d ₂ ) (17) Therefore, it is necessary to satisfy 0 ≦ X <1,0 ≦ Y <1.

Solving equation (16) for Y; In the above equation, if F = −3X ² + 4X−1 (19), the condition that the root satisfies 0 ≦ Y <1 can be calculated from a simple calculation as −1 / 3F ≦ α ₁ <1 / F for F> 0, 1 / F ≦ α ₁ <−1 / 3F for F <0 (20)

Once the value of F is determined, the possible range of F is -1
<F <1/3, but the corresponding α ₁ can vary over the entire range of positive and negative.

The means for obtaining the above condition for G ″ (0) can be summarized as follows.

 One X satisfying 0 ≦ X <1 is determined.

 Calculate the value of F given by equation (19).

(20) determines the possible range of alpha ₁ from the equation, choose alpha ₁ of the range one.

By substituting the F and alpha ₁ value to calculate the value of Y in (18).

X and Y and alpha ₁ set decided by Toto above, G "
This is a parameter for setting (0) = 0.

As is evident from the above procedure, the possible range of X and α ₁ are related, and the range of possible values of Y is determined via α ₁ . Therefore, even if a condition for setting the second derivative to zero is imposed, the degree of freedom for selecting a specific Y from the range of possible Y remains. That is, using this degree of freedom, it is possible that some of the differential coefficients can be reduced to zero. Then, a condition for setting the fourth-order differential coefficient to zero is examined next.

 The fourth derivative is given by the following equation.

G ′ (0) = 16 (−15Y ³ + 30Y ² −17Y + 2) + 16α ₁ · (15X ³ + 30X ² −17X + 2) (21) where X, Y and α ₁ satisfy the above conditions It is assumed that

The value of equation (21) was numerically evaluated using a computer. At this time, not only the expression (21) is evaluated by giving d ₂ , but also the value of Y that makes the fourth-order differential coefficient zero by repetitive calculation, that is, the value of d ₁ and the sixth-order differential at that time Coefficients were also calculated.

According to the calculation results, it was found that a solution satisfying G (0) ≠ and G ′ (0) = 0 exists in the regions of d ₂ ≦ 1.147 and d ₂ ≧ 2.358. In other regions, the derivative of each order becomes zero, but the transfer conductance itself becomes zero, so that the solution is meaningless in terms of a circuit.

Furthermore, since the sixth-order differential coefficient is also zero around d ₂ = 1.2977, a seventh-order maximum flatness characteristic can be obtained under this condition.

Summarizing the above, when the condition of d ₁ = 0.354071095 d ₂ = 1.297724854 α ₁ = 0.5478454142 is satisfied in the equation (15), the seventh-order maximum flatness characteristic is obtained.

Now, an example in which the above result is applied to an actual circuit will be described.

By returning the variable x was subjected to Equation (3) Normalization, the y into the original variables, and _{I d = Yα F / I EE} ...... (22) V d = -X2V T ...... (23). Therefore, Vd offset voltage corresponding to the d _K
When _{K, Vd K = -d K 2V} T, a (k = 1,2) ...... (24 ). Offset voltages V _d1 and V corresponding to these d ₁ and d _2
According to the equation (24), _d2 is given by V _d1 = −0.354071095 · 2V _T = −18.30 mV when the absolute temperature T = 300 K (25) V _d2 = −1.397724854 · 2V _T = −67.07 mV Become.

Therefore, in the circuit configuration in which the input terminals and the output terminals of the four differential amplification pairs shown in FIG. 3 are connected in parallel, for example, means 7B and 7C
DC voltage sources of −18.30 mV and +18.30 mV, respectively, and −67.07 mV and +67.07 as 7A and 7B, respectively.
Using a DC voltage source of mV, as a means for weighting the output current, for example, using current sources 9A, 9B, 9C, 9D connected to the common emitter of each differential amplification pair, each of the current values is about 1 : 0.54781: 0.54781: 1 can realize the 7th-order maximum flatness characteristic.

Here, the current sources 22 and 23 of the load 15 are for determining the DC operating point of the circuit, and are substantially current sources 9A, 9B and 9 respectively.
Set to half of the sum of the current values of C and 9D.

In order to more intuitively explain the operation of the circuit in such a case, the differential amplifier pairs 16A, 16B, 16C, 16 in FIG.
The dependence of the differential output current on the differential input voltage of D
These are shown by graphs 25, 27a, 27b, and 26 in FIG.

Since the output terminals of each differential amplification pair are connected in parallel, the differential output current flowing through the load resistor 24 is the sum of the respective currents, so that 25, 27a, 27b, and 25 shown in FIG. 26
, And the curve indicated by 28 in FIG.

As can be seen from the figure, the curve 28 shows a wider linear range than any of 25 to 27.

In order to make this clearer, the curves obtained by differentiating the curves 25 to 28, that is, the curves of the transconductance are shown in FIG.
From the figure, it can be seen that the transconductance curve 28 'of the linearized differential amplifier of the present example is nine times or more wider than that of the normal differential amplifier pair 26' which is translated in the horizontal axis direction. It can be seen that it provides an operating range.

In the circuit shown in FIG. 3, offset voltage applying means 7A, 7D (7B, 7C) having opposite polarities and the same magnitude are connected to a differential amplification pair.
Transistors 5A and 5D (5B) that constitute 16A and 16D (16B and 16C)
B, 5C), respectively, by utilizing the characteristics of the differential amplification pair, for example, as shown in FIG.
B) is removed by short-circuiting, and instead, a voltage source having a magnitude equal to 7A (7B) is inserted between the base terminal of the transistor 6A (6B) and the input terminal 2 so that the side of the input terminal 2 is positive. Exactly the same effect can be obtained.

Further, an example in which another method is used as the offset voltage applying means will be described with reference to FIG. This method obtains a differential amplifier pair having an offset by intentionally making the emitter areas of two transistors constituting a differential amplifier pair different.

That is, the base-emitter voltage of the transistor
_Assuming that V _be and the collector current are I _C , the following relationship holds: V _be = V _T log _e [I _C / I _S ] (27) Here, V _T , I _S is the aforementioned thermal voltage,
This is the reverse saturation current. Since I _S is proportional to the emitter area, if the emitter area of one transistor of the differential amplifier pair is M times the other, if the collector current is the same, the base-emitter voltage V _be of that transistor becomes V _be = V _T log _e because [I _C / MI _S] a ... (28), when the difference in base-emitter voltages of the transistors and _{ΔV be ΔV be = V T log} e [I C / I S] _{-V T log e [I C /} MI S] = V T log e (M) becomes ... (29).

Therefore, this asymmetric differential amplification pair has apparently V _T
This is equivalent to a symmetric differential amplification pair having an offset voltage of log _e (M). In the case of the present embodiment, M may be determined so that V _T log _e (M) = d _k 2 V _T (k = 1, 2) (30). M1 = ^e2d1 = 13.40261 (31) M2 = ^e2d2 = 2.030215 (32)

That is, the ratio of the emitter area of the transistors forming the differential amplification pair may be set to 1: 13.40261 and 1: 2.030215.

This offset voltage applying means is superior to the embodiment shown in FIGS. 3 and 5 in that it does not require temperature compensation. That is, if the DC voltage source is used as an offset voltage applying means, the value as given by equation (24) should be proportional to V _T. However, the offset voltage means using the difference in emitter area is given by the formula (3)
Since V _T cancel As can be seen from 0), it is possible to automatically generate the appropriate offset voltage corresponding to the temperature.

FIG. 6 is a specific circuit example of the second embodiment. In the figure, the difference from FIGS. 3 and 5 is that the offset voltage applying means is realized not by the voltage source but by the difference in the emitter area of the differential amplifier pair.

In FIG. 6, the offset voltage applying means is such that the emitter area of the transistors 5A and 6D is about 13.40 times the emitter area of the transistors 6A and 5D, and the emitter area of the transistors 5B and 6C is about 2.03 times the emitter area of the transistors 6B and 5C. This is realized by having been set respectively.

Another modification will be described. FIG. 7A shows a circuit for generating offset voltages V _d1 and V _d2 , wherein the offset voltage is a transistor constituting an emitter follower.
Attention is paid to the fact that it can be changed by the difference in the emitter area of 30, 31, 32.

That is, the M value of the expression (30) is calculated using the transistors 30, 31, 32
, A desired offset can be obtained. In this case, a current source including transistors 33, 34, and 35 is provided so that currents equal to the transistors 30, 31, and 32 flow. That is, the transistors 33, 34, and 35 are all transistors having the same emitter area, and their bases are supplied with the same voltage via the terminal 37.
Since this condition is the same as when the above equation (29) is derived, the emitter area ratio M1 of the transistors 30 and 31 is set to about 1: 2.0
3, the emitter area ratio M2 of the transistors 30 and 32 is about 1: 13.40
As a result, the voltage applied to the input terminal 36 has a potential difference between the output terminals 38 and 39 and between the output terminals 38 and 40 by the value of the equation (24).

In this way, when the absolute temperature is 300 K, the output terminals 39 and 40 are about 18.
A potential difference of 30 mV and 67.07 mV can be generated, and the same effect as the circuit of FIG. 3 can be obtained.

Further, since each differential amplification pair of the differential amplifier constituted by using the circuit for generating the offset voltage shown in FIG. 7A can be constituted by using transistors having the same emitter area ratio, the emitter 6 which has higher high frequency characteristics than the circuit of FIG. 6 including a transistor having a large area.
The following maximum flatness characteristics can be obtained.

Next, still another modification will be described. As described above, FIG. 7A shows a circuit for generating an offset.
Can be changed not only by the difference in the emitter area, but also by these operating currents.

That is, the M value of the expression (30) is calculated using the transistors 30, 31, 32
A desired offset can be obtained not only by the emitter area ratio but also by the operating current ratio.

In this case, the transistors 30, 31, and 32 may have the same emitter area, and a current source including the transistors 33, 34, and 35 may be provided to supply a current of M2: M1: 1 to each of the transistors. That is, in this case, the transistors 33, 34, and 35 are transistors having an emitter area ratio of M2: M1: 1, and their bases are supplied with the same voltage via the terminal 37. Since this condition is the same as when the above equation (29) is derived,
The voltage applied to the input terminal 36 has a potential difference between the output terminals 38 and 39 by the value of equation (24).

Therefore, in the circuit configuration shown in FIG. 8 using the circuit shown in FIG. 7A, the emitter areas of the transistors 33, 34, and 35 are set to be equal, and the emitter area ratio of the transistors 30, 31, and 32 is set to 1. : 2.03: 13.04 has the same effect as the circuit of FIG.

Although the offset voltage applying means using the emitter follower has the advantage of improving the frequency characteristic, the transistor constituting the circuit is different from the embodiment shown in FIG. 6 in which the emitter area of the differential amplifier pair itself is changed. However, there remains a problem that the total area occupied by the elements increases.
In order to alleviate this point, a method of reducing the area occupied by the transistor of the offset voltage means using the emitter follower will be described below.

In the circuit of FIG. 7A for generating the offset voltages V _d1 and V _d2 , attention is paid to the fact that the offset voltage can be changed not only by the difference in the emitter area of the transistor but also by these operating currents. . That is, a desired offset can be obtained by realizing the M value of Expression (28) using not only the emitter area ratio of the transistors 30, 31, and 32 but also the operating current ratio. Therefore, not only the area ratio or the current ratio is used, but also the occupied area and the current value can be made appropriate values using both of them.

FIG. 7B shows an example in which the emitter current of the transistor is changed in order to reduce the area occupied by the transistor in this circuit.

In FIG. 7B, the emitter areas of the transistors 41, 42, 43 and 44, 45, 46 are reduced in order to reduce the area occupied by the transistors as compared with FIG. 7A. That is, it is set to about 1: 1.425: 3.661: 3.661: 2569: 1. By doing so, when the absolute temperature is 300K, the output terminals 30 and 40 are about 18.30 m each with respect to the output terminal 38.
V, a potential difference of 67.07 mV can be generated, and better high-frequency characteristics can be obtained than the circuit of FIG. FIG. 9 shows the entire circuit configuration in this case.

Comparing the effect of the area reduction by this method, when the smallest emitter area of the transistor is 1, the sixth transistor
In the circuit shown in the figure, 2 · (13.40 + 1 + 2.03 + 1) = 34.86. When the offset voltage applying means shown in FIG. 7A is applied to the differential amplifier shown in FIG. 9, 2 · (1 + 1 + 2.030 + 1).
+ 13.40 + 4) = 46.86, and when the offset voltage applying means shown in FIG. 7B is applied to FIG. 9, 2 ·
(1 + 3.661 + 1.425 + 2.569 + 3.661 + 4) = 34.63 When the area reduction method shown in FIG. 7 (b) is applied, the number of elements increases but the area is smaller than that of the circuit of FIG. It can be seen that a high-performance circuit can be realized.

Here, in order to more clearly show the effect of the linear range expansion according to the present invention, an amplifier using two conventional differential amplifier pairs and an amplifier using four differential amplifier pairs according to the present invention are normalized. Let's compare with the graph of the input / output characteristics. No.
Figure 10 is a graph of transconductance characteristics.
The horizontal axis is the differential input voltage, and the vertical axis is the normalized transconductance.

In the figure, I represents transconductance in the case of the present invention using four differential amplification pairs, and II represents transconductance characteristics in the case of using two conventional differential amplification pairs. As is apparent from the figure, it can be seen that the linear operation range can be greatly expanded by the present invention.

To compare the size of the quantitative linear range, the width of the V _d up transconductance G normalized by the maximum value (V _d) is 1% decrease from the maximum value - was examined (apex peak) Table 1 shows the results.

From the above table, comparing the width of _Vd until G ( _Vd ) decreases by 1% from the maximum value, the use of four differential pairs is about 9.35 times that of a conventional differential pair, The linear range is extended about 2.32 times as compared with the linearized differential pair using two differential pairs.

As can be seen from the process described above, it is clear that linearization can be performed over a wide range by using a similar procedure using five or more differential pairs. However, in this case, unlike the case of up to four sets, the parameter giving the maximum flatness characteristic cannot be obtained analytically, but must be obtained by numerical calculation.

So far, we have described the conditions to achieve the maximum flatness so that the transconductance approximates the horizontal line as much as possible.However, as another approximation method, there is an equiripple approximation that allows a certain waving, and by allowing the waving A wider linear range is obtained than the maximum flat approximation. Therefore, an embodiment for realizing equiripple approximation in a linearized differential amplifier using four differential pairs will now be described.

Although it is possible to derive analytical conditions related to the parameters required to realize equiripple characteristics, it is a nonlinear system of equations that is difficult to solve, so here we use a computer to approximate the parameters numerically. The value was determined. As an example, if α ₁ = 0.72, α ₂ = 1, d ₁ = 0.55, d ₂ = 1.794, the transconductance is about 0.75% of the maximum value.
Equal ripple characteristics with undulation.

It is natural that all the circuits of the embodiments of the present invention described above can be used to realize the above parameters in a circuit. In order to compare the effect of this embodiment with the other cases, an embodiment of equiripple approximation is shown in FIG. As is clear from FIG. 9A, the flat range is wider than in the case of the maximum flat approximation. However, as can be seen from the partial enlarged view shown in FIG.

For example, if the current mirror shown in FIG. 3B is used as a load circuit, the transconductance times the differential input voltage applied between the input terminals 1 and 2 to another load connected to the output terminal 4. Current can be passed to another load.

According to the present invention, the offset voltage value and the weighting coefficient of the output current are set to a value that gives the maximum flat characteristic, as can be easily conceived from the method of synthesizing the transconductance of each differential amplifier pair shown in FIG. 5 (b). It is clear that by appropriately changing the range, the flatness of the entire transconductance can be reduced to some extent, and the range in which the transconductance can be regarded as constant can be further expanded.

Further, in the embodiments, all the transistors constituting the differential amplifier pair are described as NPN transistors. However, the same effect can be obtained even with PNP transistors. The same effect can be obtained with any of the bipolar transistors used here, such as germanium, silicon, and gallium arsenide. Of course, a hetero bipolar transistor can also be used.

In short, the present invention includes anything intended to extend the flat range of transconductance by connecting four or more differential pairs in parallel.

Further, in the above embodiments, only the application of the amplifier is shown, but the present invention can also be used for a filter, a limiter, a mixer circuit, and the like using the amplifier.

First, an embodiment as a limiter will be described. As is clear from FIG. 4 (a), according to the present invention, for example, N
= 4, it is possible to realize the input / output characteristics as shown by the curve 28 in the same figure, for example, as compared with the input / output characteristics of the conventional mere differential amplifier as shown by the curve 25 in the same figure. The curvature of the shoulder is angular. FIG. 11 shows the normalized input and output for the purpose of comparing these input characteristics. The ideal input / output characteristics of the limiter
Although represented by a polygonal line 47 shown in the figure, according to the present invention, a characteristic 49 closer to an ideal can be realized as compared with a characteristic 48 of a conventional simple differential amplifier. The characteristics when the number N of differential pairs is 4 are shown. Specifically, in the above-described embodiment shown in FIG. 1, FIG. 3, FIG. 5, FIG. 6, FIG.
The load 15 is realized by an appropriate circuit as shown in FIGS. 2 (a) to 2 (c) according to the application, a signal is inputted from the input terminals 1 and 2, and an output whose amplitude is limited is obtained from the output terminals 3 and 4. be able to.

Next, an embodiment in which the amplifier of the present invention is applied to a multiplier will be described.

FIG. 12 is a circuit diagram of an analog multiplier to which the present invention is applied. In the figure, reference numeral 50 (50-1, 50-2, 50-3) denotes a linearized differential amplifier according to the present invention, and the differential amplifier shown in FIG. 6 is used as an example. This part may be the same as that of the embodiment shown in FIG. 8 of the present invention.

FIG. 12 shows three linearized differential amplifiers 50-1, 50-2, 50
-3 is shown, of which 50-
Reference numeral 2 denotes a transistor having characteristics opposite to those of the two transistors below. This is not a necessary condition,
This case will be described because the circuit becomes simple.

In FIG. 12, the differential voltage signal applied to the first input terminals 52 and 53 by the first input signal source 51 changes the differential output current by the transconductance of the second linearized differential amplifier 50-2. The differential output current is generated by diode-connected transistors 54 and 55 so that the operating currents of the first and third linearized differential amplifiers 50-1 and 50-3 are proportional to the differential output current. I have.

On the other hand, the first and third linearized differential amplifiers 50-1, 50-3
Are connected to the second input terminals 57 and 58 by the second input signal source 56.
Are connected so as to be inputted in opposite phases to each other, and the first and third linearized differential amplifiers 50-1, 50-3 are connected to each other.
Are connected so as to add to each other, and the final output is the first and third linearized differential amplifiers 50-1, 50-1,
The output current of 50-3 is converted into a voltage by the load resistors 59 and 60 and output to the output terminals 61 and 62.

First, when the differential input voltage of the first signal source 51 is zero, the operating currents of the first and third linearized differential amplifiers 50-1 and 50-3 are equal. Regardless of the differential input voltage, the changes in the output currents of the first and third linearized differential amplifiers 50-1 and 50-3 cancel each other out, and the output current obtained by adding these changes does not change. That is, the potential difference between the output terminals 61 and 62 also becomes zero. However, when the differential input voltage of the first signal source 51 is not zero, the first and third linearized differential amplifiers 50-
Since the operating currents of 1,50-3 produce opposite polarity changes in proportion to the first input, they have a value proportional to the differential input voltage of the second signal source 56. At this time, the proportional coefficient is the first,
It is determined by the transconductance of the third linearized differential amplifiers 50-1 and 50-3, which is proportional to the operating current, and is therefore proportional to the first input.

Therefore, the differential output obtained at the output terminals 61 and 62 is
The value becomes proportional to the differential input voltage of both the first and second signal sources 51 and 56, and eventually a multiplier can be realized. It is clear from the symmetry of the circuit that if the second differential input signal is zero, the final differential output voltage will also be zero. Thus,
According to the configuration of FIG. 12, a four-quadrant analog multiplier can be realized.

FIG. 13 shows that the value of the current source 63 in the circuit of FIG.
A shows the results of simulating the input / output characteristics when the power supply voltage is ± 0.75 V by applying 1.5 V between the positive power supply terminal 64 and the negative power supply terminal 65.

The horizontal axis in the figure is the differential input voltage of the first signal source 51,
The vertical axis is the difference current value of the current flowing through the load resistors 59 and 60,
The differential input voltage of the second signal source 56 is set to -40 as a parameter.
The range was varied from mV to 40 mV. It can be seen from the figure that the linear operation is performed over the range of ± several + mV for both the first and second inputs.

This circuit is described, for example, in the aforementioned document `` Analog integrated circuit '' 7.
Variable transconductance type multiplier using the conventional differential pair described in Section 3. (pp.234-238) (Id.
Figure 7.3), [or “Bipdar and MOS Analog Integrate
9.4, pp. 456-459 Figure 9.4] of d Circuit Design, but as described in the same section, the linear operating range of the conventional differential pair was less than several mV. By using the linearized differential amplifier according to the present invention, the linear range can be increased by a factor of 10 or more at a low power supply voltage.

By the way, in the above, three linearized differential amplifiers 50-1, 50-2,
The example in which the first and third of the 50-3 are constituted by NPN transistors and the second are constituted by PNP transistors has been described. For example, as shown in FIG.
The same operation as in FIG. 12 can be realized by using three of the same components as 0-1 and returning the output current of the one shown in the center by the current mirror circuits 66 and 67. However, since the central linearized differential amplifier is composed of NPN transistors, it is necessary to change the transistors for setting the bias and the current sources 68 and 63 to 68A and 63A of opposite polarities, respectively.

Next, the linearized differential amplifier of the present invention can be used as a variable transconductor by changing the operating current. Therefore, for example, the document DWHCalder; “Audio F
requency Gyrattor Filters for an Integrated Radio
Paging Receiver ", International Conference on Mobil
e Radio Techniques, IEE Conference, York England, pp.
As described in Figs. 3 and 4 in 21-26, 1984, a gyrator can be constructed using two transconductors, and an inductor can be equivalently realized using the gyrator and a capacitor. Finally, an active filter can be realized by an integrated circuit using the transconductor and the capacitor.

FIG. 15 is a circuit diagram of a fifth-order low-pass filter designed by the method disclosed in the document. The triangular symbols in the figure represent transconductors.
As shown in FIG. 16, a linearized differential amplifier of the present invention (in this case, an example where N = 4 is shown) can be used. In this document, since a conventional linearized differential amplifier with N = 2 is used, this embodiment can secure a linear operation range of twice or more. Actually, since the linearized differential amplifier has an offset voltage of about several mV to 10 mV, the linear operation range is narrowed accordingly. In other words, when the linear operation range is only about 30 mV as in the conventional linearized differential amplifier, the linear operation range is actually significantly narrower in the vertical direction than in the case where the linear operation range is about 100 mV as in the present invention. In fact, the invention results in having a several times linear operating range.

FIG. 17 shows actual measurement results of frequency characteristics of an active filter actually manufactured by applying the linearized differential amplifier according to the present invention shown in FIG. 16 to the low-pass filter shown in FIG. In the figure, the input voltage is 100m with the parameters as the power supply voltage.
It is measured under the condition of Vp-p, and shows good performance up to about 1V. FIG. 18 shows the measurement results of the distortion characteristics at 1 kHz of the prototype active filter.
When viewed from the point that the distortion rate is 1%, it was possible to input about 150 mVp-p for both the power supply voltages of 1.1 V and 1.5 V. As described above, it has been proved that the present invention is suitable for low-voltage operation.

[Effects of the Invention] As described above, since the present invention is a linearized differential amplifier as described in the claims, it has a wide linear operation range,
Also, the input impedance can be increased, and amplifiers, filters, limiters,
It can be widely used for mixer circuits and the like.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an overall outline of the present invention, FIG. 2 is an explanatory diagram showing an example of a load used in the present invention, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. Is an explanatory diagram showing the operation of the above embodiment, FIG. 5 is a circuit diagram showing a modification of the above embodiment, FIG. 6 is a circuit diagram showing another modification of the above embodiment, and FIG. b) is a circuit diagram showing a configuration example of an offset voltage applying means used in another embodiment of the present invention, and FIG.
FIG. 7 is a circuit diagram of a differential amplifier using the circuit shown in FIG. 7 (a), FIG. 9 is a circuit diagram of a differential amplifier using the circuit of FIG. 7 (b), and FIG. FIG. 11 is an explanatory diagram showing the operation in comparison with a conventional example, FIG. 11 is an explanatory diagram showing the characteristics of a normalized output with respect to a normalized input in response to a limiter, and FIG. 12 is a circuit diagram showing an application example to an analog multiplier. FIG. 13 is an explanatory diagram of a simulation result of input / output characteristics of the circuit of FIG. 12, and FIG.
FIG. 12 is an explanatory diagram showing another embodiment of the analog multiplier of FIG. 12, FIG. 15 is a circuit diagram of a fifth-order low-pass filter, and FIG. 16 is an explanatory diagram of a linearized differential amplifier applied to this circuit. ,
Figure 17 is an explanatory diagram of the frequency characteristics of this linearized differential amplifier.
FIG. 18 is a view showing an actual measurement result of the distortion factor characteristic of the active filter, FIG. 19 is an explanatory view of a general differential amplifier pair, and FIG. 20 is an explanatory view showing its operation.

Claims (11)

(57) [Claims] 1. A differential amplifier in which input terminals and output terminals of a differential amplifier pair using bipolar transistors are connected in parallel with each other, wherein N is an integer of 4 or more, and N pairs of differential amplifier pairs are provided. Are arranged in parallel, means for giving an equivalent offset voltage to each differential amplification pair, means for weighting these output currents, and means for adding these output currents are provided. Differential amplifier. 2. The linearized differential amplifier according to claim 1, wherein the means for applying the offset voltage and the means for weighting are characterized in that a change in the differential output current with respect to a change in the differential input voltage has a flat characteristic. A linearized differential amplifier characterized in that the equivalent offset voltage and the output current are weighted as follows. 3. The linearized differential amplifier according to claim 1, wherein said means for applying an offset voltage and said weighting means are configured such that a change in differential output current with respect to a change in differential input voltage has an equal ripple characteristic. A linearized differential amplifier characterized in that the equivalent offset voltage and the output current are weighted as follows. 4. The linearized differential amplifier according to claim 2, wherein the current weighted by said weighting means is a current value of a current source connected to a commonly connected emitter of said differential amplifier pair. A linearized differential amplifier, characterized in that: 5. The linearized differential amplifier according to claim 3, wherein the current weighted by said weighting means is a current value of a current source connected to a commonly connected emitter of said differential amplifier pair. A linearized differential amplifier. 6. The linearized differential amplifier according to claim 4, wherein the number of differential amplification pairs is four, and the equivalent offset voltage applied to each of said four differential amplification pairs is a first differential amplification pair. 1.298 · 2 · V _T for the differential amplifier pair, 0.354 · 2 · V _{T for} the second differential amplifier pair, −0.354 · 2 · V for the third differential amplifier pair _T, relative to the fourth differential amplifier pair -1.298 · 2 · V _T (although V _T is the thermal voltage, V _T = KT /
q, K: Boltzmann's constant, T: absolute temperature, q: charge of electrons), and the weights of the output currents of the four differential amplification pairs are determined by the first and fourth differential amplification pairs. The output current of the other two differential amplification pairs is
A linearized differential amplifier characterized by being configured to be around 5478 times. 7. The linearized differential amplifier according to claim 1, wherein said means for applying said offset voltage is constituted by changing an emitter area of a transistor which is a constituent element of each differential amplification pair. And a linearized differential amplifier. 8. The linearized differential amplifier according to claim 1, wherein said means for adding the output current of said differential amplifier pair comprises a wired amplifier connecting said output terminals of said differential amplifier pair.
A linearized differential amplifier comprising an OR. 9. The linearized differential amplifier according to claim 1, wherein the means for weighting the current varies the transconductance by proportionally changing the operating currents of all the differential amplifier pairs. A linearized differential amplifier, characterized in that: 10. The linearized differential amplifier according to claim 1, wherein the bipolar transistors forming the differential amplification pair are silicon transistors, silicon hetero bipolar transistors, or gallium arsenide hetero bipolar transistors. Linearized differential amplifier. 11. The linearized differential amplifier according to claim 1, wherein said weighting means changes operating currents of all differential amplifier pairs in proportion to absolute temperature. Dynamic amplifier.