JP2002217654A - Differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a normal operation even when an input voltage range fills a power supply voltage, to improve the accuracy of input offset voltage characteristics and to enable a high-speed operation as well. SOLUTION: This differential amplifier circuit is provided with first input differential pair transistors P101 and P102 whose threshold voltage is VTP1, second input differential pair transistors P103 and P104 whose threshold voltage is VTP2 (|VTP2|<|VTP1|), a current source transistor P100 in common to both input differential pairs, first active load transistors N105 and N106 connected to the drain of the first input differential pair transistor and second active load transistors N107 and N108 connected to the source of the first active load transistor and the drain of the second input differential pair transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a differential amplifier circuit using a plurality of parallel-connected input differential pairs and a plurality of stacked active loads.

[0002]

2. Description of the Related Art For example, a threshold voltage of an input differential pair transistor has a general value VTP (approximately -0.55) shown in FIG.
V) In a differential amplifier circuit using an enhancement type p-type MOS transistor, when the input voltage is close to VDD (high potential power supply voltage), the transistor of the differential pair is cut off and does not operate, or There is a problem in that the accuracy of the offset voltage (the value obtained by subtracting the input voltage from the output voltage when the differential amplifier circuit is measured in a voltage follower configuration by shorting the output terminal and the inverting input terminal) is deteriorated. On the other hand, when the threshold voltage is a general value VTN shown in FIG.
In a differential amplifier circuit using an n-type MOS transistor of the enhancement type of 55 V), there is a similar problem when the input voltage is close to VSS (low potential power supply voltage).

[First Prior Art] Therefore, a differential amplifier circuit using a transistor having a small threshold voltage for an input differential pair has been proposed. FIG. 9 shows a p-type MO having a small threshold voltage.
FIG. 14 is a diagram showing a differential amplifier circuit 100C using S transistors P151 and P152 as an input differential pair. This threshold voltage is VTP1 (| VTP1 | <| VTP |
VTP1 is approximately -0.2 V). Note that the transistors P151 and P152 are represented by depletion-type symbols, but this is to indicate an enhancement-type transistor having a threshold voltage smaller than that of a normal threshold voltage. All enhancement type transistors are represented by the same symbols. In the following description, such a transistor may be referred to as a depletion type transistor to distinguish it from a normal enhancement type transistor. P150
Is a p-type MOS transistor as a current source, N153,
N154 is an active load of a current mirror connection.
Type MOS transistors, and their threshold voltages are normal values (VTP, VTN in FIG. 21).

[0004] 200 is a p-type MOS transistor P200
To P202, n-type MOS transistors N203 to N20
6, an output circuit 300 is a resistor R300, a p-type MO
This is a bias circuit including S transistors P300 and P301 and n-type MOS transistors N302 and N303. The bias voltage generated by the bias circuit 300 is applied to the gates of the transistor P150 of the differential amplifier circuit 100C and the transistor P200 of the output circuit 200.

In the differential amplifier circuit 100C shown in FIG. 9, since the threshold voltages of the transistors P151 and P152 of the input differential pair are set to a value VTP1 smaller than usual, the input voltage range on the VDD side is expanded, and the voltage of the node TOP is reduced. The lowering operation is performed, and the voltage of the node TOP is suppressed from approaching VDD. Therefore, the voltage of the node TOP has the characteristic shown in FIG. 19A, and the operation of the current source transistor P150 is maintained. As a result, the input / output voltage can be fully swung to the power supply voltage range, that is, the range of VDD-VSS, and the input offset voltage characteristic becomes the characteristic shown in FIG.

FIG. 11 is a diagram showing a differential amplifier circuit 100C 'in which the polarity of the transistor in the circuit shown in FIG. 9 is inverted. This differential amplifier circuit 100C 'has n
It comprises an N-type MOS transistor N150, n-type MOS transistors N151 and N152 forming a differential pair, and p-type MOS transistors P153 and P154 as active loads connected in a current mirror manner. 200 'is n
MOS transistors N200 to N202, p-type MOS
An output circuit including transistors P203 to P206;
00 ′ is a resistor R300, an n-type MOS transistor N30
0, N301, p-type MOS transistors P302, P3
03 is a bias circuit.

The differential amplifier circuit 100C 'shown in FIG.
The threshold voltages of the transistors N151 and N152 are VTN1 (VTN1 <VTN, VTN1 is approximately 0.2
V), the voltage at the node TOP has the characteristic shown in FIG. 20A, and the operation of the current source transistor N150 is maintained. As a result, the input / output voltage can be fully swung to the range of VDD-VSS, and the input offset voltage characteristic becomes the characteristic shown in FIG.

However, in general, in a differential amplifier circuit, it is necessary to increase the current of a current source transistor in order to improve the operation speed. Differential amplifier circuit 1 shown in FIG.
In the case of 00C, the current Id of the transistor P150 increases. However, the increase in the current causes the voltage of the node TOP to rise to near VDD, resulting in the characteristic shown in FIG. Resulting in. Then, when the voltage of the node TOP becomes close to VDD, the voltage difference between the source and the drain of the current source transistor P150 becomes small, and the current source transistor P150 does not operate. As a result, the input offset voltage characteristic becomes as shown in FIG. 10B, and the accuracy decreases on the VDD side. Further, in the AC operation, as shown in FIG. 23C, distortion occurs on the VDD side as compared with the normal case (b). In the differential amplifier circuit 100C ′ shown in FIG. 11, the same operation is performed on the VSS side.
The voltage of the node TOP has the characteristic shown in FIG. 20B, and the input offset voltage characteristic has the characteristic shown in FIG. Also,
In the AC operation, as shown in FIG. 23D, distortion occurs on the VSS side.

[Second Prior Art] In order to solve the above problems, there is a method of further reducing the threshold voltage of the transistor of the input differential pair. That is, in the differential amplifier circuit 100C of FIG.
The threshold voltage of P152 is changed to VTP2 (| VTP2
| <| VTP1 |). As a result, the input differential pair has a wider input voltage range on the VDD side, and the node T
The operation of lowering the OP voltage is performed, and the operation on the VDD side is further improved.

However, when the operating current Id increases, the voltage characteristic of the node TOP further decreases as shown in FIG. This time, the voltage of the node TOP becomes too low due to the operation on the VSS side. Thereby, the node TOP
The potential difference between the node TOP and the node VO + between the node P1 and the node VO− decreases, and the differential pair of transistors P1
51 and P152 become difficult to operate. This is because, as is apparent from the characteristic C in FIG. 19, the transistor P151 and the transistor P151 should have a linear characteristic on the VSS side.
This is because P152 becomes difficult to operate and the potential of the node TOP is raised by the current source transistor P150 near VSS. From the above, the input offset voltage characteristic becomes the characteristic shown in C of FIG.
The accuracy on the S side is reduced. In the AC operation, FIG.
As shown in FIG. 3D, distortion occurs on the VSS side.

On the other hand, in the differential amplifier circuit 100C 'shown in FIG. 11, the threshold voltage of the transistors N151 and N152 of the input differential pair is set to VTN2 (VTN2 <VTN1) shown in FIG. Improved, but V
The operation on the DD side poses a problem similarly to the above. FIG. 20C shows the voltage characteristics of the node TOP, and FIG. 12C shows the offset voltage characteristics.

[Third Prior Art] FIG. 13 shows an input differential pair of two pairs of depletion type transistors P151 and P152 whose threshold voltage is VTP2 or VTP1 in FIG. 21 and enhancement type transistors P156 and P157 whose threshold voltage is VTP. And a transistor P15 as a current source of the depression type transistors P151 and P152.
0 to the enhancement type transistors P156, P1
57 shows a differential amplifier circuit 100D to which a transistor P155 is connected as a current source 57. This circuit is proposed in Japanese Patent Laid-Open Publication No. Hei. 5-256,026. The VSS side is connected to an enhancement transistor P15.
6, P157, the VDD side is to be complemented by depletion type transistors P151, P152, respectively.

However, transistors P151 and P156
Is connected to the node VO−, and the drains of the transistors P152 and P157 are commonly connected to the node VO +. Therefore, the nodes VO− and VO + are intermediate between the depletion type transistors P151 and P152 and the enhancement type transistors P156 and P157. The operation causes the active loads of the transistors N153 and N154 to operate. Therefore, the enhancement transistor operates well on the VSS side, but has poor characteristics on the VDD side. Even if a depletion transistor having good characteristics on the VSS side and the VDD side is used, there is only an intermediate operation. As shown in FIG. 14, the accuracy of the voltage characteristics decreases on the VDD side.

FIG. 15 shows the differential amplifier circuit 10 shown in FIG.
Differential amplifier circuit 1 with inverted polarity of 0D transistor
It is a figure which shows 00D '. Here, the input differential pair is composed of two pairs of depletion type transistors N151 and N152 whose threshold voltage is VTN2 or VTN1 in FIG. 21 and enhancement type transistors N156 and N157 of VTN, and the depletion type transistors N151 and N1
The current source of N52 is connected to N150, and the current sources of enhancement transistors N156 and N157 are connected to N155. However, this differential amplifier circuit 100
In D ', the same operation is performed on the VSS side, and the accuracy of the input offset voltage characteristic is reduced on the VSS side as shown in FIG.

[Fourth Prior Art] The differential amplifier circuit 100E shown in FIG. 17 includes transistors P150, P156 and P15.
7, N153, N154, and transistors N150, N156, N157, P1
53, P154 and an n-type differential amplifier circuit are commonly connected to input terminals IN− and IN +, respectively, and outputs taken out of nodes VON and VOP in a differential form are output to an output circuit 200A
Are input to the transistors P210 and N211. This differential amplifier circuit 100E is called a p-type n-type input complementary differential amplifier circuit. The p-type differential amplifier circuit is responsible for the input range on the VSS side, and the n-type differential amplifier circuit is VDD. The input range on the side is assigned.

However, since the p-type differential amplifier circuit and the n-type differential amplifier circuit have a switching point in the operation, the operation is discontinuous at the switching point. The input offset voltage characteristic is as shown in FIG. 18, and the input offset voltage changes at the switching point, and the accuracy is reduced.

[0017]

As is apparent from the above, as in the first and second prior arts, the differential amplifier circuit 100C, which uses a transistor having a small threshold voltage for the input differential pair,
In the case of 100C ′, there is a problem that the input offset voltage characteristic is deteriorated when the operating current is increased, so that the speed cannot be increased. Further, differential amplifier circuits 100D and 100D 'in which the inputs of an enhancement type input differential pair and a depletion type input differential pair are connected in parallel as in the third related art.
Or a differential amplifier circuit 100E in which inputs of a p-type differential amplifier circuit and an n-type differential amplifier circuit are connected in parallel as in the fourth prior art.
In this case, it is possible to increase the operating speed by increasing the operating current, but there is a problem that the input offset voltage characteristic is poor. As described above, conventionally, it has been difficult to realize a differential amplifier circuit capable of full swing of input / output and high-speed operation.

It is an object of the present invention to realize an input / output full swing and a high-speed operation over the entire power supply voltage range, and to improve the input offset voltage characteristic to improve the common mode signal rejection ratio. Another object of the present invention is to provide a differential amplifier circuit.

[0019]

According to a first aspect of the present invention, there is provided a first input differential pair comprising a first threshold voltage transistor pair having a gate connected to a differential input terminal. A second input differential pair comprising a transistor pair having a gate connected to the differential input terminal and having a second threshold voltage different from the first threshold voltage, and a current source transistor common to both input differential pairs A first active load including a transistor pair having a drain connected to a drain of each transistor of the first input differential pair, and a drain connected to a drain of each transistor of the second input differential pair And a second active load comprising a transistor pair having a drain connected to a source of each transistor of the first active load;
A gate of each transistor of the first and second active loads is connected to a drain of one transistor of the first input differential pair, and an output from a drain of the other transistor of the first input differential pair. Was configured to be taken out.

According to a second aspect based on the first aspect, the absolute values of the first and second threshold voltages are determined by comparing the absolute values of the threshold voltages of the current source transistor and the first and second active load transistors. Set to a value smaller than the value.

In a third aspect based on the first or second aspect, the absolute value of the second threshold voltage is set to a value smaller than the absolute value of the first threshold voltage.

In a fourth aspect based on the first, second or third aspect, a current source transistor is individually provided for each of the first and second input differential pairs in place of the common current source transistor. Provided.

[0023]

[First Embodiment] FIG. 1 is a diagram showing a differential amplifier circuit 100A according to a first embodiment of the present invention. P100 is a p-type MOS transistor as a current source, P101 and P102 are p-type MOS transistors having a threshold voltage VTP1 of FIG. 21 constituting a first input differential pair, and P103 and P104 are second input differential pairs. The p-type MOS transistor having the threshold voltage VTP2 shown in FIG. 21 is connected, N105 and N106 are current-mirror connected, and n-type MOS transistors functioning as active loads of the transistors P101 and P102. P10
3, an n-type MOS transistor acting as an active load of P104. Transistors P100, N105 to N10
The threshold voltages 8 are VTP and VTN in FIG.

That is, the transistors P101 and P10
3 are commonly connected to the input terminal IN−, and the gates of the transistors P102 and P104 are commonly connected to the input terminal IN +. Further, the transistors N105 and N1
The drain of transistor 06 is connected to the drains of transistors P101 and P102, and the drain of transistor N107 is connected to the drain of transistor P103 and transistor N
105 and a transistor N108
Are commonly connected to the drain of the transistor P104 and the source of the transistor N106. In addition,
Reference numeral 200 denotes an output circuit, and 300 denotes a bias circuit, which are the same as those shown in FIG.

Now, in the input differential pair of the transistors P101 and P102 whose threshold voltage is VTP1, when the current of the current source transistor P100 is increased for speeding up,
When the input voltage becomes close to VDD, its characteristics deteriorate, and the input offset voltage characteristics become worse than when the input voltage is on the VSS side. Conversely, in the input differential pair of the transistors P103 and P104 whose threshold voltage is VTP2, when the input voltage becomes close to VSS, the characteristics deteriorate, and the input offset voltage characteristics become worse than when the input voltage is on the VDD side. . In the present invention, the small threshold voltage V
The first and second input differential pairs of TP1 and VTP2 are combined.

First, when the input voltage is near VSS,
Transistors P101 and P102 whose threshold voltage is VTP1
In the differential circuit including the input differential pair and the transistors N105 and N106, the threshold voltage of the input differential pair operates normally similarly to the general differential amplifier circuit of VTP1. On the other hand, in a differential circuit including the input differential pair of the transistors P103 and P104 having the threshold voltage VTP2 and the transistors N107 and N108, the node TOP and the nodes A- and A-
+ Becomes small and operation becomes difficult, but the drains of the transistors N107 and N108 are connected to the transistor N107.
Since they are connected to the sources of the transistors 105 and N106, the voltages of the nodes A- and A + are lower than the voltages of the nodes VO- and VO + by the threshold voltage of the transistors N105 and N106. Is suppressed from being reduced. Also, the transistor N1
Since the gates of transistors N107 and N108 are connected to node VO-, the gate voltage thereof is higher than the drain voltage of node A- by the threshold voltage of transistor N105, so that the operating range of transistors N107 and N108 is expanded. Further, the nodes VO− and VO + are connected to the low threshold voltage V
Since this is the output section of the differential circuit having the differential pair of TP1, the gate voltages of the transistors N107 and N108 are supplemented, whereby the differential circuit having the differential pair of transistors having the threshold voltage of VTP2 also operates normally. become.

Next, when the input voltage is near VDD,
Transistors P103 and P104 whose threshold voltage is VTP2
In the differential circuit including the input differential pair and the transistors N107 and N108, the threshold voltage of the input differential pair operates normally similarly to the general differential amplifier circuit of VTP2. On the other hand, in the differential circuit including the input differential pair of the transistors P101 and P102 having the threshold voltage VTP1 and the transistors N105 and N106, the voltage of the node TOP normally approaches VDD, which makes it difficult to operate. The differential circuit having the differential pair of transistors P103 and P104 prevents the voltage of the node TOP from approaching VDD. Further, the voltages at the output nodes A− and A + of the differential circuit supplement the source voltages of the transistors N105 and N106, and the operating range is expanded. As a result, a differential circuit having a differential pair transistor whose threshold voltage is VTP1 also operates normally.

As described above, even when the input voltage range is full within the power supply voltage, the differential amplifier circuit having the threshold voltage of VTP1 and the differential circuit having the threshold voltage of VTP2 perform complementary operations. 100A output nodes VO-, VO
The normal operation of + is maintained. Further, the voltage of the node TOP has the characteristic of D in FIG. 19, the level on the VDD side is lower than the characteristic B of the differential amplifier circuit with the threshold voltage VTP1, and the differential amplifier circuit with the threshold voltage VTP2. The change on the VSS side is linear compared to the characteristic C of the above. This also indicates that the differential amplifier circuit 100A is performing a complementary operation, and the input offset voltage characteristic is shown in FIG.
As shown in (1), the characteristics within the full range of the power supply voltage are improved, thereby improving the common-mode signal rejection ratio. In addition, the AC operation is also an operation without distortion, as shown in FIG.
In addition, since the current of the current source can be increased, the frequency characteristic of the gain also becomes higher than the characteristic B of the differential amplifier circuit 100C shown in FIG.
High-speed operation becomes possible.

FIG. 3 shows the differential amplifier circuit 100A shown in FIG.
Amplifier 100 with inverted polarity of transistor
It is a figure which shows A '. N100 is an n-type M as a current source
The OS transistors N101 and N102 are the first input differential pair and have a threshold voltage of VTN1 shown in FIG.
The S transistors and N103 and N104 are n-type MOS transistors each having a threshold voltage VTN2 shown in FIG.
Transistors, P105 and P106 are p-type MOS transistors which are current mirror-connected and act as active loads of transistors N101 and N102, and P107 and P108 are current-mirror connected and transistors N101 and N1
02 and p-type M acting as active loads of N103 and N104
OS transistor. Transistors N100, P1
The threshold voltages of 05 to P108 are VTN and VTP in FIG.

That is, the transistors N101 and N10
3 are commonly connected to the input terminal IN−, and the gates of the transistors N102 and N104 are commonly connected to the input terminal IN +. Further, the transistors P105 and P1
06 is connected to the drains of the transistors N101 and N102, and the drain of the transistor P107 is connected to the drain of the transistor N103 and the transistor P102.
105, and is commonly connected to the source of
Are commonly connected to the drain of the transistor N104 and the source of the transistor P106. In addition,
200 ′ is an output circuit, 300 ′ is a bias circuit,
This is the same as that shown in FIG.

In the differential amplifier circuit 100A ', the operation when the input voltage is near VDD and the operation when the input voltage is near VSS are opposite to those of the differential amplifier circuit 100A. Further, the input offset voltage characteristics are as shown in FIG. The voltage of the node TOP has the characteristic of D in FIG.
Compared with the characteristic B of the differential amplifier circuit whose threshold voltage is VTN1, V
The level on the SS side is rising, and the threshold voltage is VTN
The change on the VDD side is more linear than the characteristic C of the differential amplifier circuit No. 2.

[Second Embodiment] FIG. 5 is a diagram showing a differential amplifier circuit 100B according to a second embodiment of the present invention. The difference from the differential amplifier circuit 100A of FIG. 1 is that the transistor P100 as a current source is used for the transistors P101 and P102 of the first input differential pair, and as the current source for the transistors P103 and P104 of the second input pair. The point is that a p-type MOS transistor P109 is newly connected.
The threshold voltage of this transistor P109 is VTP in FIG.
It is.

In the differential amplifier circuit 100B, since the current sources of the first and second differential pairs are separate, the node T
Although the input offset voltage characteristic is slightly inferior as shown in FIG.
The voltage change of −, VO + and the voltage change of A−, A + are the same as those of the above-described differential amplifier circuit 100A.

FIG. 7 shows the differential amplifier circuit 100B shown in FIG.
Amplifier 100 with inverted polarity of transistor
FIG. 4B is a diagram showing B ′, in which a transistor N100 as a current source is used for the transistors N101 and N102 of the first input differential pair as compared with the differential amplifier circuit 100A ′ of FIG.
The difference is that an n-type MOS transistor N109 is newly connected as a current source for the transistors N103 and N104 of the second input pair. The operation is performed by the differential amplifier circuit 100B shown in FIG.
And the opposite.

[0035]

As described above, according to the present invention, even if the input voltage range is full within the power supply voltage, the normal operation is maintained, the input offset voltage characteristic can be improved, and the common-mode signal can be removed. The ratio is also improved. Further, since the current of the current source can be increased, high-speed operation is also possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a differential amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram of an input offset voltage of the differential amplifier circuit of FIG. 1;

FIG. 3 is a circuit diagram of a differential amplifier circuit in which the polarity of the transistor in FIG. 1 is inverted.

FIG. 4 is a characteristic diagram of an input offset voltage of the differential amplifier circuit of FIG. 3;

FIG. 5 is a circuit diagram of a differential amplifier circuit according to a second embodiment of the present invention.

FIG. 6 is a characteristic diagram of an input offset voltage of the differential amplifier circuit of FIG. 5;

7 is a circuit diagram of a differential amplifier circuit in which the polarity of the transistor in FIG. 5 is inverted.

8 is a characteristic diagram of an input offset voltage of the differential amplifier circuit of FIG.

FIG. 9 is a circuit diagram of first and second prior art differential amplifier circuits.

FIG. 10 is a characteristic diagram of an input offset voltage of the differential amplifier circuit of FIG. 9;

11 is a circuit diagram of a differential amplifier circuit in which the polarity of the transistor in FIG. 9 is inverted.

12 is a characteristic diagram of an input offset voltage of the differential amplifier circuit of FIG.

FIG. 13 is a circuit diagram of a third conventional differential amplifier circuit.

14 is a characteristic diagram of an input offset voltage of the differential amplifier circuit of FIG.

FIG. 15 is a circuit diagram of a differential amplifier circuit in which the polarity of the transistor in FIG. 13 is inverted.

FIG. 16 is a characteristic diagram of an input offset voltage of the differential amplifier circuit of FIG.

FIG. 17 is a circuit diagram of a fourth conventional differential amplifier circuit.

18 is a characteristic diagram of an input offset voltage of the differential amplifier circuit of FIG.

FIG. 19 is a voltage characteristic diagram of a node TOP of each differential amplifier circuit having a differential pair of p-type MOS transistors.

FIG. 20 is a voltage characteristic diagram of a node TOP of each differential amplifier circuit having a differential pair of n-type MOS transistors.

FIG. 21 is a Vgs-Ids characteristic diagram of a MOS transistor.

FIG. 22 is a frequency characteristic diagram of the gain of the differential amplifier circuit.

FIG. 23 is an input / output waveform diagram of the differential amplifier circuit.

[Explanation of symbols]

100A, 100A ', 100B, 100B', 100
C, 100C ', 100D, 100D', 100E: Differential amplifier circuit 200, 200 ', 200A: Output circuit 300, 300': Bias circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J066 AA00 AA12 CA13 CA34 CA53 CA65 FA20 HA10 HA14 HA15 HA16 HA17 HA25 KA06 KA09 KA12 MA19 MA22 ND04 ND14 ND22 ND23 PD01 TA02 TA03 TA06 5J091 AA01 AA12 CA13 CA34 CA53 HA65 FA15 HA16 HA17 HA25 KA06 KA09 KA12 MA19 MA22 TA02 TA03 TA06

Claims (4)

[Claims] 1. A first input differential pair comprising a first threshold voltage transistor pair having a gate connected to a differential input terminal;
A second input differential pair having a gate connected to the differential input terminal and having a second threshold voltage different from the first threshold voltage, a current source transistor common to both input differential pairs, A first active load including a transistor pair having a drain connected to a drain of each transistor of the first input differential pair; a drain connected to a drain of each transistor of the second input differential pair; A second active load comprising a transistor pair having a drain connected to a source of each transistor of the first active load, and a gate of each transistor of the first and second active loads being connected to the first active load. A differential amplifier circuit connected to the drain of one of the transistors of the input differential pair, and taking out the output from the drain of the other transistor of the first input differential pair. 2. The differential amplifying circuit according to claim 1, wherein the absolute values of said first and second threshold voltages are determined by a threshold voltage of said current source transistor and said first and second active load transistors. A differential amplifier circuit characterized in that it is set to a value smaller than the absolute value of 3. The differential amplifier circuit according to claim 1, wherein an absolute value of said second threshold voltage is set to a value smaller than an absolute value of said first threshold voltage. Differential amplifier circuit. 4. The differential amplifier circuit according to claim 1, wherein a current source transistor is individually provided for each of said first and second input differential pairs in place of said common current source transistor. A differential amplifier circuit characterized by being provided.