JPH04114504A - Differential amplifier output buffer - Google Patents
Differential amplifier output bufferInfo
- Publication number
- JPH04114504A JPH04114504A JP23522390A JP23522390A JPH04114504A JP H04114504 A JPH04114504 A JP H04114504A JP 23522390 A JP23522390 A JP 23522390A JP 23522390 A JP23522390 A JP 23522390A JP H04114504 A JPH04114504 A JP H04114504A
- Authority
- JP
- Japan
- Prior art keywords
- differential amplifier
- stage
- npn transistor
- resistor
- common
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 title claims description 9
- 230000003321 amplification Effects 0.000 claims description 9
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は集積回路における差動増幅出力バッファに関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to differential amplification output buffers in integrated circuits.
第２図は従来の差動増幅回路の回路図で、図１こおいて
、（１）（２）（９）αＱ（７）は抵抗、（３）〜（６
）はＮＰＮ ｌ−ランジスタ、（１００）〜（１０２）
は定電流源である。Figure 2 is a circuit diagram of a conventional differential amplifier circuit. In Figure 1, (1) (2) (9) αQ (7) are resistors,
) are NPN l-transistors, (100) to (102)
is a constant current source.
従来の差動増幅出力バッファは図示の如く差動出力それ
ぞれに定電流源（１０１） （１０２）を用いていた。As shown in the figure, a conventional differential amplification output buffer uses constant current sources (101) and (102) for each differential output.
次に動作ｆこついて説明する。抵抗（４）に電圧振幅を
得ようとする場合、抵抗（１）に流れる電流以上の電流
を定電流源（１０１）、 （１０２）に流さなければ、
抵抗（イ）に設定値通りの出力電圧振幅を得る事ができ
ない。その為、定電流源（１０１）、 （１０２）それ
ぞれ、抵抗（７）に最大電圧を得られるような電流を流
していた。Next, the operation f will be explained. When trying to obtain voltage amplitude in the resistor (4), unless a current greater than the current flowing in the resistor (1) is passed through the constant current sources (101) and (102),
It is not possible to obtain the output voltage amplitude according to the set value for the resistor (A). For this reason, the constant current sources (101) and (102) each caused a current to flow through the resistor (7) to obtain the maximum voltage.
従来の差動増幅出力バッファは以上のように構成されて
いたので、抵抗に最大電圧振幅を得るため常に定電流源
に電流を流す必要があり、この抵抵が小さいと回路電流
が増加するという問題点があった。Conventional differential amplification output buffers were configured as described above, so in order to obtain the maximum voltage amplitude across the resistor, current must always flow through the constant current source, and if this resistor is small, the circuit current will increase. There was a problem.
この発明は上記のような問題点を解消するためｆこなさ
れたもので、定電流源を１つにしまた流す電流は従来の
回路と同じで従来の回路と同じ電圧振幅を得られる差動
増幅出力バッファを得る事を目的とする。This invention was developed to solve the above-mentioned problems, and it is a differential amplifier that uses only one constant current source, flows the same current as the conventional circuit, and obtains the same voltage amplitude as the conventional circuit. The purpose is to obtain an output buffer.
この発明に係る差動増幅出力バッファは、差動負荷段に
入力と同相の差動出力段を設け、出力の電流を切り換え
が必要な時、必要な方へ電流を流すようｉこしたもので
ある。The differential amplification output buffer according to the present invention has a differential output stage in phase with the input in the differential load stage, so that when the output current needs to be switched, the current flows in the required direction. be.
この発明ｉこおげろ差動出力段ｔ′−Ｌ、電流を切り換
える事ｆこより、従来回路と同じ出力振幅が由られ、出
力段の電流が半分子こなる。By switching the current in the differential output stage t'-L of the present invention, the same output amplitude as in the conventional circuit can be obtained, and the current in the output stage is reduced by half.
以下、この発明の一実施例を図ｉこついて説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図はこの発明の一実施例である差動増幅回路の回路
図で、図において、ｆｉｌ （２） ＋！ｌ）〜ａ２ｃ
ｉｏは抵抗、（３）〜（８）けＮＰＮ トランジスタ、
（１００） （１０１）は定電流源である。FIG. 1 is a circuit diagram of a differential amplifier circuit which is an embodiment of the present invention. In the figure, fil (2) +! l)～a2c
io is a resistor, (3) to (8) are NPN transistors,
(100) (101) are constant current sources.
図ｆこ示すように、ＮＰＮ トランジスタ（７） （８
）及び抵抗Ｑｌｌ Ｑ２１こよって差動増幅段を構成し
、入力信号と同相で電流を切り換えるよう１こしている
。その為、定電流源（１０１）に流れる電流だけで、抵
抗（イ）の両端に最大電圧振幅を得る事ができる。As shown in Figure f, NPN transistor (7) (8
) and resistors Qll and Q21 constitute a differential amplification stage, and are set so that the current is switched in phase with the input signal. Therefore, the maximum voltage amplitude can be obtained across the resistor (A) only by the current flowing through the constant current source (101).
第１図において例えば、 ＮＰＮ トランジスタ（３）
（４）の差動段でＮＰＮ ）ラノジスタ（３）のベー
ス電位がＮＰＮ ｌ−ランレスタ（４）のベース電位が
高くなると、差動増幅されＮＰＮ トランジスタ（５）
のベース電位が下がる。これと同時１こ、ＮＰＮ トラ
ンジスタ（７１（８）の差動増幅段が入力信号と同相で
動作しているので、ＮＰＮ ｌ−ランジスタ（７）のコ
レクタにＮＰＮ トランジスタ（８）のコレクタより電
流が多く流れる事になり、つまり、差動出力の電位が低
くなる方に多くの一流を流すことができるよう１こなり
、抵抗（イ）が十分小さくても抵抗（イ）の両端には最
大電圧振幅が持られるようになる。In Figure 1, for example, NPN transistor (3)
In the differential stage (4), the base potential of the NPN transistor (3) increases.
The base potential of decreases. At the same time, since the differential amplification stage of the NPN transistor (71 (8)) is operating in phase with the input signal, a current flows into the collector of the NPN transistor (7) from the collector of the NPN transistor (8). In other words, more current can flow in the direction where the potential of the differential output is lower, so even if the resistor (A) is small enough, the maximum voltage will be applied across the resistor (A). It will have amplitude.
なお、上記実施例では差動増幅回路の出力バッファの場
合；ごついて説明したが、差動で出力されるものであれ
ば同様の効果を奏する。例えばＥＣＬのフリ、プフロッ
プ等ｌこも適用できることはいうまでもない。Incidentally, in the above embodiment, the explanation has been made regarding the case of the output buffer of a differential amplifier circuit, but the same effect can be achieved as long as the output buffer is differentially output. For example, it goes without saying that it can also be applied to ECL flips, flipflops, etc.
ａｈのようにこの発明によれば、低出力インピーダンス
の回路が低消費電力で実現可能となるという効果がある
。According to the present invention, as shown in ah, a circuit with low output impedance can be realized with low power consumption.
第１図はこの発明の一実施例である差動増幅回路の回路
図、第２図は従来の差動増幅回路の回路図である。
図において、（＋１． （２１、（９）〜Ｑ２．ｇＪは
抵抗、（３）〜（８）はＮＰＮ トランジスタ、（１０
０）、 （１０１）は定電流源、ＶＣＣ、ＧＮＤは定電
圧源を示す。
なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a circuit diagram of a differential amplifier circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional differential amplifier circuit. In the figure, (+1. (21, (9) to Q2.gJ are resistors, (3) to (8) are NPN transistors, (10
0) and (101) are constant current sources, and VCC and GND are constant voltage sources. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
増幅段の共通の負荷定電流源を入力相に応じて切替える
ことにより、出力負荷段を低消費電力化したことを特徴
とする差動増幅出力バッファ。The output load stage is characterized by low power consumption by providing a differential amplification stage that is in phase with the input, and by switching the common load constant current source of this differential amplification stage according to the input phase. Differential amplification output buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23522390A JPH04114504A (en) | 1990-09-04 | 1990-09-04 | Differential amplifier output buffer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23522390A JPH04114504A (en) | 1990-09-04 | 1990-09-04 | Differential amplifier output buffer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04114504A true JPH04114504A (en) | 1992-04-15 |
Family
ID=16982908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23522390A Pending JPH04114504A (en) | 1990-09-04 | 1990-09-04 | Differential amplifier output buffer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04114504A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006245844A (en) * | 2005-03-02 | 2006-09-14 | Seiko Instruments Inc | Operational amplifier |
-
1990
- 1990-09-04 JP JP23522390A patent/JPH04114504A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006245844A (en) * | 2005-03-02 | 2006-09-14 | Seiko Instruments Inc | Operational amplifier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0259879A2 (en) | Operational amplifier circuit having wide operating range | |
| JPS6120427A (en) | Logic gate circuit connected at emitter | |
| US5389894A (en) | Power amplifier having high output voltage swing and high output drive current | |
| US5162751A (en) | Amplifier arrangement | |
| KR100217875B1 (en) | Collector dot and circuit with latched comparator | |
| US5066876A (en) | Circuit for converting ecl level signals to mos level signals | |
| US6417733B1 (en) | High output voltage swing class AB operational amplifier output stage | |
| JPH04114504A (en) | Differential amplifier output buffer | |
| JPH044768B2 (en) | ||
| JPS6331214A (en) | Variable delay circuit | |
| JP3130791B2 (en) | Level conversion circuit | |
| JPH08139531A (en) | Differential amplifier | |
| JPH10261950A (en) | Amplifier for active terminator | |
| JP3664224B2 (en) | Power drive circuit | |
| JP3172310B2 (en) | Buffer circuit | |
| JPH0740651B2 (en) | Amplifier circuit | |
| JP2902277B2 (en) | Emitter follower output current limiting circuit | |
| JP3349334B2 (en) | Differential amplifier | |
| JPH11136048A (en) | Btl amplifier circuit | |
| JPH04230120A (en) | Detection receiver of three states of differential ecl bus | |
| JP3043183B2 (en) | Current divider circuit | |
| JPH03162130A (en) | Semiconductor integrated circuit | |
| JPH03201809A (en) | Differential output circuit | |
| JP2589577Y2 (en) | Switch circuit | |
| JPH05218767A (en) | Variable gain amplifier circuit |