JP4500181B2 - Package for storing semiconductor element and watt hour meter - Google Patents

Package for storing semiconductor element and watt hour meter Download PDF

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JP4500181B2
JP4500181B2 JP2005051082A JP2005051082A JP4500181B2 JP 4500181 B2 JP4500181 B2 JP 4500181B2 JP 2005051082 A JP2005051082 A JP 2005051082A JP 2005051082 A JP2005051082 A JP 2005051082A JP 4500181 B2 JP4500181 B2 JP 4500181B2
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semiconductor element
recess
package
external lead
lead terminal
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JP2006237358A (en
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冬樹 黒川
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Toshiba Toko Meter Systems Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

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Description

本発明は、外部リード端子を備えた半導体素子収納用パッケージ及びこの半導体素子収納用パッケージを有する電力量計に関する。   The present invention relates to a package for housing a semiconductor element having an external lead terminal and a watt-hour meter having the package for housing a semiconductor element.

一般に、半導体素子、特にホール素子など応力の影響を受け易い半導体センサ素子を収納するための半導体素子収納用パッケージは、図5に示すように、セラミックス等の電気絶縁材料からなる。   In general, a package for housing a semiconductor element for housing a semiconductor element, particularly a semiconductor sensor element that is easily affected by stress, such as a Hall element, is made of an electrically insulating material such as ceramics as shown in FIG.

この半導体素子収納用パッケージは、上面の略中央部に半導体素子33を収容するための凹部31a及び凹部31a周辺から上面外両縁にかけて導出されたメタライズド配線層32が形成された絶縁基体31と、半導体素子33を外部電気回路に電気的に接続するためにメタライズド配線層32に銀ロウ等のロウ材を介してロウ付けされた外部リード端子34と、セラミックス等の電気絶縁材料からなる蓋体35とを有して構成されている。   The semiconductor element storage package includes a recess 31a for storing the semiconductor element 33 in a substantially central portion of the upper surface, and an insulating base 31 on which a metallized wiring layer 32 led out from the periphery of the recess 31a to both outer edges of the upper surface is formed, An external lead terminal 34 brazed to the metallized wiring layer 32 via a brazing material such as silver brazing to electrically connect the semiconductor element 33 to an external electric circuit, and a lid 35 made of an electrically insulating material such as ceramics. And is configured.

この半導体収納用パッケージは、次のような工程で製造される。まず、絶縁基体31の凹部31a底面に、半導体素子33を接着材を介して取着固定するとともに半導体素子33の各電極をボンディングワイヤ36を介してメタライズド配線層32に電気的に接続する。その後、絶縁基体31の上面に蓋体35を樹脂等の封止材37を介して接合させ、絶縁基体31と蓋体35とからなる容器内部に半導体素子33を封止することによって、最終製品としての半導体装置が得られる。   This semiconductor storage package is manufactured by the following process. First, the semiconductor element 33 is attached and fixed to the bottom surface of the recess 31a of the insulating base 31 via an adhesive, and each electrode of the semiconductor element 33 is electrically connected to the metallized wiring layer 32 via a bonding wire 36. Thereafter, the lid 35 is joined to the upper surface of the insulating base 31 via a sealing material 37 such as a resin, and the semiconductor element 33 is sealed inside the container composed of the insulating base 31 and the lid 35, thereby obtaining a final product. As a result, a semiconductor device can be obtained.

従来のこの種の半導体装置は、通常、外部電気回路を形成するプリント配線基板に貫通穴を形成しておき、貫通穴に半導体素子収納用パッケージの外部リード端子を挿入させて半田付けし、外部リード端子とプリント配線基板の配線とを電気的に接続させることによって内部に収容する半導体素子を外部電気回路に接続するようになっている。   In this type of conventional semiconductor device, a through hole is usually formed in a printed wiring board that forms an external electric circuit, and an external lead terminal of a package for housing a semiconductor element is inserted into the through hole and soldered. By electrically connecting the lead terminal and the wiring of the printed wiring board, the semiconductor element accommodated therein is connected to the external electric circuit.

しかし、この種の半導体装置は、半導体素子収納用パッケージの厚みが大きく、近時の表面実装及び薄型化に対応したものになっていない。   However, in this type of semiconductor device, the thickness of the semiconductor element storage package is large, and it has not been adapted to the recent surface mounting and thinning.

そこで、半導体素子収納用パッケージの表面実装及び薄型化を実現する技術として、外部リード端子を無くした技術が開示されている(特許文献1)。この特許文献1は、底面にメタライズ配線層の一部が導出した絶縁枠体の下方に金属製ベース部材を絶縁枠体の開孔部を塞ぐようにして、且つ金属製ベース部材の下面が絶縁枠体の下面より突出しないようにして取着させるとともに絶縁枠体の上面に金属製キャップ部材を絶縁枠体の開孔部を塞ぐようにして取着する。   Therefore, as a technique for realizing surface mounting and thinning of a semiconductor element storage package, a technique in which an external lead terminal is eliminated is disclosed (Patent Document 1). In this patent document 1, a metal base member is closed under the insulating frame body from which a part of the metallized wiring layer is led out on the bottom surface, and the opening of the insulating frame body is closed, and the lower surface of the metal base member is insulated. The metal cap member is attached to the upper surface of the insulating frame so as not to protrude from the lower surface of the frame so as to block the opening portion of the insulating frame.

また、外部リード端子の半導体素子収納用パッケージへの取付けが、ロウ付けにより行なわれる場合には、図6の絶縁基体の集合体のように、絶縁基体41に半導体素子43を実装するより前の工程で、格子状のリードフレーム42が付いた状態で、外部リード端子44が取付けられる。外部リード端子44の取付け方法には、図5に示すロウ付け以外に、図7のようなハイブリッドICで行なわれる半田接続が知られている。   Further, when the external lead terminals are attached to the semiconductor element storage package by brazing, the semiconductor element 43 is mounted before the semiconductor element 43 is mounted on the insulating base 41 as in the aggregate of insulating bases in FIG. In the process, the external lead terminals 44 are attached with the grid-like lead frame 42 attached. As a method for attaching the external lead terminal 44, solder connection performed by a hybrid IC as shown in FIG. 7 is known in addition to the brazing shown in FIG.

図7に示す半導体素子収納用パッケージは、下面全体にメタライズド配線層52が形成され、メタライズド配線層52表面の略中央部に半導体素子53が形成された絶縁基体51と、半導体素子53をメタライズド配線層52に接続するボンティングワイヤ55と、半導体素子53を外部電気回路に電気的に接続するためにメタライズド配線層52に半田付けされた外部リード端子54と、絶縁基体51とメタライズド配線層52と半導体素子53と外部リード線54とボンティングワイヤ55とをモールドする樹脂部材56とを有して構成されている。
特開平5−152460号公報、第1項、第1図
The semiconductor element storage package shown in FIG. 7 has an insulating base 51 in which a metallized wiring layer 52 is formed on the entire lower surface, and a semiconductor element 53 is formed at a substantially central portion of the surface of the metallized wiring layer 52. A bonding wire 55 connected to the layer 52, an external lead terminal 54 soldered to the metallized wiring layer 52 to electrically connect the semiconductor element 53 to an external electric circuit, an insulating substrate 51 and a metallized wiring layer 52, A semiconductor element 53, an external lead wire 54, and a resin member 56 for molding the bonding wire 55 are provided.
Japanese Patent Laid-Open No. 5-152460, Item 1, FIG.

このように、従来技術にあっては、表面実装工程では、外部電気回路を形成するプリント配線基板のパット(電極部分)に予め半田を塗布し、そのパット上に、実装する半導体装置を配置し、高温雰囲気中に投入する。そして、高温により半田が溶融し、パットと半導体装置の端子との半田接合が形成される。   Thus, in the conventional technology, in the surface mounting process, solder is applied in advance to a pad (electrode part) of a printed wiring board that forms an external electric circuit, and a semiconductor device to be mounted is placed on the pad. , Put in a high temperature atmosphere. Then, the solder melts due to the high temperature, and a solder joint between the pad and the terminal of the semiconductor device is formed.

しかしながら、セラミックス材とガラスエポキシ材などのプリント配線基板材料とでは熱膨張率に差があるため、外形が大きいセラミックス製の半導体素子収納用パッケージにおいて外部リード端子を無くした場合、半田接合部に応力によるクラックが発生する可能性がある。   However, since there is a difference in the coefficient of thermal expansion between ceramic materials and printed wiring board materials such as glass epoxy materials, if external lead terminals are lost in a ceramic element housing package with a large external shape, stress is applied to the solder joints. May cause cracks.

このクラックの発生を回避するためには、外部リード端子を備えることが有効であるが、従来のセラミックス製の半導体素子収納用パッケージにおいて、外部リード端子の付いたものは、外部リード端子の取付けをロウ付けにより行なうものが一般的であり、半導体素子収納用パッケージに半導体素子を実装する前に、この外部リード端子がリードフレームに付いた状態でロウ付けされる。このため、半導体素子収納用パッケージの輸送時や半導体素子の実装時にその外形が大きくなり、不利となる。   In order to avoid the occurrence of this crack, it is effective to provide an external lead terminal. However, in a conventional ceramic semiconductor element storage package with an external lead terminal, the external lead terminal must be attached. The soldering is generally performed by brazing, and the external lead terminals are brazed in a state of being attached to the lead frame before the semiconductor element is mounted on the semiconductor element housing package. For this reason, the outer shape becomes large when the semiconductor element storage package is transported or when the semiconductor element is mounted, which is disadvantageous.

また、図7に示すように、ハイブリッドICで行なわれる半田による外部リード端子54の接続では、半田ディップ時の半導体素子保護の目的により、半導体素子53がエポキシ材などの樹脂部材56で封止されている必要がある。この樹脂部材56により半導体素子53に加わる応力が、ホール素子など応力の影響を受け易い半導体センサ素子では、オフセット電圧など特性を悪化する原因となるため、無視できない。また、応力を回避するため、中空の樹脂封止とした場合には、薄型のパッケージを実現することは困難である。   Further, as shown in FIG. 7, in the connection of the external lead terminal 54 by solder performed in the hybrid IC, the semiconductor element 53 is sealed with a resin member 56 such as an epoxy material for the purpose of protecting the semiconductor element at the time of solder dipping. Need to be. In the semiconductor sensor element that is easily affected by the stress such as the Hall element, the stress applied to the semiconductor element 53 by the resin member 56 causes deterioration of characteristics such as an offset voltage, and thus cannot be ignored. In order to avoid stress, when a hollow resin seal is used, it is difficult to realize a thin package.

本発明は、表面実装における半田接合部のクラック発生を回避し、半導体素子に応力の加わらない構造を持つ低価格で薄型の半導体素子収納用パッケージ及び半導体素子収納用パッケージを有する電力量計を提供することにある。   The present invention provides a low-cost and thin semiconductor element housing package having a structure in which stress is not applied to a semiconductor element, avoiding the occurrence of cracks in a solder joint in surface mounting, and a watt-hour meter having a semiconductor element housing package There is to do.

上記課題を達成するために、請求項1の発明の半導体素子収納用パッケージは、第1凹部と第2凹部と前記第2凹部の深さと略等しい第3凹部とが形成された絶縁基体と、前記第1凹部に収納された半導体素子と、前記第2凹部に収納されて前記絶縁基体と樹脂接合され、前記半導体素子と対向する側に第4凹部が形成され、前記半導体素子を封止する蓋体と、前記絶縁基体に形成され、ボンディングワイヤを介して前記半導体素子に接続されるメタライズド配線層と、前記第3凹部に収納され、前記メタライズド配線層に半田層による半田付けにより接続される外部リード端子とを備えることを特徴とする。 In order to achieve the above object, a package for housing a semiconductor element according to claim 1 comprises an insulating substrate having a first recess, a second recess, and a third recess substantially equal to the depth of the second recess , The semiconductor element accommodated in the first recess and the second recess are resin-bonded to the insulating base, and a fourth recess is formed on the side facing the semiconductor element to seal the semiconductor element. A lid, a metallized wiring layer formed on the insulating base and connected to the semiconductor element via a bonding wire, and housed in the third recess and connected to the metallized wiring layer by soldering with a solder layer And an external lead terminal.

請求項2の発明の半導体素子収納用パッケージは、請求項1の発明の半導体素子収納用パッケージにおいて、前記外部リード端子は、外部の回路基板に半田付け可能にリード先端部がフォーミングされていることを特徴とする。   According to a second aspect of the present invention, there is provided a package for housing a semiconductor element in the package for housing a semiconductor element according to the first aspect, wherein the external lead terminal is formed with a lead tip so that it can be soldered to an external circuit board. It is characterized by.

請求項3の発明の電力量計は、電流検出部で検出された電流と電圧検出部で検出された電圧とに基づいて電力を演算する電力量計において、前記電流検出部は、
第1凹部と第2凹部と第3凹部とが形成された絶縁基体と、前記第1凹部に収納された半導体素子と、前記第2凹部に収納されて前記絶縁基体と樹脂接合され、前記半導体素子を封止する蓋体と、前記絶縁基体に形成され、ボンディングワイヤを介して前記半導体素子に接続されるメタライズド配線層と、前記第3凹部に収納され、前記メタライズド配線層に半田により接続される外部リード端子とを備える半導体素子収納用パッケージを有することを特徴とする。
The watt-hour meter of the invention of claim 3 is a watt-hour meter that calculates power based on the current detected by the current detection unit and the voltage detected by the voltage detection unit, wherein the current detection unit includes:
An insulating substrate having a first recess, a second recess, and a third recess; a semiconductor element received in the first recess; and a resin bonded to the insulating substrate received in the second recess; A lid for sealing the element, a metallized wiring layer formed on the insulating base and connected to the semiconductor element via a bonding wire, and housed in the third recess and connected to the metallized wiring layer by soldering And a package for housing a semiconductor element including an external lead terminal.

請求項1の発明によれば、メタライズド配線層に半田層による半田付けにより接続される外部リード端子を備えることにより、絶縁基体の表面実装における半田接合部のクラック発生を回避できる。また、絶縁基体と蓋体により形成された中空部に半導体素子が配置されることにより、半導体素子への応力を回避でき、絶縁基体と蓋体との樹脂接合により半導体素子を封止することにより、外部リード端子の半導体収納用パッケージへの接合を工程効率的に有利な後工程での半田接合とすることができる。また、絶縁基体に半導体素子、蓋体、外部リード端子をそれぞれ収納する第1凹部乃至第3凹部を備えることにより、半導体素子収納用パッケージの厚さを薄くできる。 According to the first aspect of the present invention, by providing the external lead terminal connected to the metallized wiring layer by soldering with a solder layer, it is possible to avoid the occurrence of cracks in the solder joint in the surface mounting of the insulating substrate. Also, by placing the semiconductor element in the hollow portion formed by the insulating base and the lid, stress on the semiconductor element can be avoided, and by sealing the semiconductor element by resin bonding between the insulating base and the lid The bonding of the external lead terminal to the package for housing the semiconductor can be performed as a solder bonding in a post-process that is advantageous in terms of process efficiency. In addition, by providing the insulating substrate with the first to third recesses for storing the semiconductor element, the lid, and the external lead terminals, the thickness of the semiconductor element storage package can be reduced.

請求項2の発明によれば、外部リード端子は、リード先端部がフォーミングされているので、外部の回路基板に容易に半田付けできる。   According to the second aspect of the present invention, since the lead tip portion of the external lead terminal is formed, it can be easily soldered to the external circuit board.

請求項3の発明によれば、請求項1記載の半導体素子を有する半導体素子収納用パッケージを用いた電流検出部により電流を検出し、電圧検出部で電圧を検出し、検出された電流と電圧とに基づいて電力を演算することができる。   According to the invention of claim 3, the current is detected by the current detection unit using the semiconductor element housing package having the semiconductor element of claim 1, the voltage is detected by the voltage detection unit, and the detected current and voltage are detected. The power can be calculated based on the above.

以下、本発明の半導体素子収納用パッケージ及び電力量計の実施の形態について図面を参照しながら詳細に説明する。   Hereinafter, embodiments of a semiconductor element storage package and a watt-hour meter according to the present invention will be described in detail with reference to the drawings.

図1は本発明の実施例1の半導体素子収納用パッケージの構成図である。図1に示す本発明の半導体素子収納用パッケージは、セラミックスなどの電気絶縁材料からなる。   1 is a configuration diagram of a package for housing a semiconductor element according to a first embodiment of the present invention. The semiconductor element storage package of the present invention shown in FIG. 1 is made of an electrically insulating material such as ceramics.

半導体素子収納用パッケージは、その下面略中央部に半導体素子13を収納するための第1凹部11aと第1凹部11a周辺に沿って設けられた第1凹部11aより深さの浅い第2凹部11bと下面片端部に設けられた第3凹部11cとが形成された絶縁基体11と、第2凹部11bに収納されて絶縁基体11と樹脂接合され、半導体素子13を封止するセラミックス等の電気絶縁材料からなる蓋体15と、絶縁基体11に形成され、ボンディングワイヤ16を介して半導体素子13に接続され、蓋体15と第1凹部11aの外片縁にかけて導出され、第3凹部11cと絶縁基体11上面へ貫通穴17を介して接続されるメタライズド配線層12と、メタライズド配線層12に電気的機械的に半田により接続され、第3凹部11cにその一端が収納される外部リード端子14とを有して構成されている。   The package for housing a semiconductor element has a first recess 11a for housing the semiconductor element 13 at a substantially central portion of the lower surface thereof, and a second recess 11b having a shallower depth than the first recess 11a provided along the periphery of the first recess 11a. And an insulating substrate 11 formed with a third recess 11c provided at one end of the lower surface, and an electrical insulator such as ceramics that is housed in the second recess 11b and is resin-bonded to the insulating substrate 11 to seal the semiconductor element 13. A lid 15 made of a material, formed on the insulating base 11, connected to the semiconductor element 13 via a bonding wire 16, led out over the outer edge of the lid 15 and the first recess 11a, and insulated from the third recess 11c. The metallized wiring layer 12 connected to the upper surface of the substrate 11 through the through-hole 17 is electrically and mechanically connected to the metallized wiring layer 12 by solder, and one end thereof is connected to the third recess 11c. It is configured to include an external lead terminal 14 to be accommodated.

この半導体収納用パッケージは、次のような工程で製造される。まず、絶縁基体11に形成された第1凹部11a底面に、半導体素子13を接着材を介して取付固定するとともに半導体素子13の各電極をボンディングワイヤ16を介してメタライズド配線層12に電気的に接続させる。   This semiconductor storage package is manufactured by the following process. First, the semiconductor element 13 is attached and fixed to the bottom surface of the first recess 11a formed in the insulating base 11 via an adhesive, and each electrode of the semiconductor element 13 is electrically connected to the metallized wiring layer 12 via bonding wires 16. Connect.

その後、絶縁基体11の第2凹部11bに蓋体15を樹脂等の封止材を介して接合させ、絶縁基体11と蓋体15とからなる容器内部に半導体素子13を封止する。   Thereafter, the lid 15 is joined to the second recess 11 b of the insulating base 11 via a sealing material such as a resin, and the semiconductor element 13 is sealed inside the container formed of the insulating base 11 and the lid 15.

この半導体収納用パッケージによれば、外部リード端子14を備えることにより、絶縁基体11の表面実装における半田接合部のクラック発生を回避できる。また、蓋体15の容器内部側中央部に第1凹部11a及び第2凹部11bを設けることにより、絶縁基体11と蓋体15により形成された中空部18の容積拡大をパッケージの厚さ19を増加させることなく実現できる。即ち、パッケージの厚さ19を薄くできるとともに、中空部18により半導体素子13への応力の発生を回避できる。   According to this semiconductor storage package, by providing the external lead terminals 14, it is possible to avoid the occurrence of cracks in the solder joints in the surface mounting of the insulating base 11. Further, by providing the first concave portion 11a and the second concave portion 11b in the container inner side central portion of the lid 15, the volume of the hollow portion 18 formed by the insulating base 11 and the lid 15 can be increased by increasing the thickness 19 of the package. It can be realized without increasing. That is, the thickness 19 of the package can be reduced and the occurrence of stress on the semiconductor element 13 can be avoided by the hollow portion 18.

また、絶縁基体11と蓋体15との樹脂接合により半導体素子13を封止することにより、外部リード端子14の半導体収納用パッケージへの接合を工程効率的に有利な後工程での半田接合とすることができる。   In addition, by sealing the semiconductor element 13 by resin bonding between the insulating base 11 and the lid 15, the bonding of the external lead terminal 14 to the semiconductor storage package can be achieved by solder bonding in a post-process that is advantageous in terms of process efficiency. can do.

また、外部リード端子14は、表面実装可能な形状にフォーミング加工され半導体最終製品となる。外部リード端子14のメタライズド配線層12及び外部のプリント配線基板は、半田により接合されるため、外部リード端子14の材料としては、リン青銅などのばね性のある材料を使用でき、ロウ付けの場合に使用される42アロイなどの材料と比べて、容易にフォーミングが可能である。このため、図1に示すように、外部リード線14は、両端部がフォーミングされ、一方の端部が第3凹部11cに収納されてメタライズド配線層12に電気的に接続され、他方の端部が半田付部14aとしてプリント配線基板に半田により接続される。即ち、第3凹部11cにその一端部が収納されるため、表面実装時にプリント配線基板に外部リード端子14が干渉することが回避される。   Further, the external lead terminals 14 are formed into a surface mountable shape to become a semiconductor final product. Since the metallized wiring layer 12 of the external lead terminal 14 and the external printed wiring board are joined by solder, a material having a spring property such as phosphor bronze can be used as the material of the external lead terminal 14, and brazing Compared with materials such as 42 alloy used in the above, forming can be easily performed. For this reason, as shown in FIG. 1, both ends of the external lead wire 14 are formed, one end is housed in the third recess 11c and is electrically connected to the metallized wiring layer 12, and the other end. Is connected to the printed wiring board by solder as the soldering portion 14a. That is, since the one end is housed in the third recess 11c, it is possible to avoid the external lead terminal 14 from interfering with the printed wiring board during surface mounting.

また、第3凹部11cと第2凹部11bの深さを略同一サイズにすることにより、絶縁基体11のセラミック層数を3層とすることができ、製造コストを低減できる。   Moreover, by making the depth of the third recess 11c and the second recess 11b substantially the same size, the number of ceramic layers of the insulating base 11 can be made three, and the manufacturing cost can be reduced.

図2は本発明の実施例1の半導体素子収納用パッケージの製造工程を示す図である。まず、セラミックス製の半導体素子収納用パッケージの絶縁基体21cは、図2(a)に示すように、より大きな絶縁基体の集合体21aとして成形される。   FIG. 2 is a diagram showing a manufacturing process of the package for housing a semiconductor element according to the first embodiment of the present invention. First, as shown in FIG. 2 (a), the insulating base 21c of the ceramic semiconductor device housing package is formed as a larger insulating base aggregate 21a.

絶縁基体の集合体21aは、図2(a)に示すように、行方向及び列方向に配列された複数の絶縁基体21cがフレーム20a上に形成され、複数の絶縁基体21cの各々は、V溝が形成されたミシン目20bで仕切られている。図2(a)に示す工程では、絶縁基体21c毎に、絶縁基体21cへの半導体素子の実装処理、ボンディングワイヤの接続処理、および蓋体22による半導体素子の封止処理が行われる。これらの処理を、テープ状外部リード端子23bの接続されない半導体素子収納用パッケージの外形の小さい状態で、実施することにより工程の効率化を図ることができる。 As shown in FIG. 2A, the aggregate of insulating bases 21a includes a plurality of insulating bases 21c arranged in a row direction and a column direction on a frame 20a. It is partitioned by a perforation 20b in which a groove is formed. In the step shown in FIG. 2A, a semiconductor element mounting process on the insulating base 21c, a bonding wire connecting process, and a semiconductor element sealing process using the lid 22 are performed for each insulating base 21c. By carrying out these processes in a state where the outer shape of the package for housing a semiconductor element to which the tape-like external lead terminal 23b is not connected is small, the efficiency of the process can be improved.

次に、蓋体22による半導体素子の封止が完了した後には、図2(b)に示すように、列方向のV溝のあるミシン目20bに沿って、絶縁基体の集合体21aを絶縁基体の短冊状集合体21bに分割する。絶縁基体の短冊状集合体21bの各々には、メタライズド配線層25が形成されている。   Next, after the sealing of the semiconductor element by the lid 22 is completed, as shown in FIG. 2B, the insulating base aggregate 21a is insulated along the perforations 20b having the V-grooves in the column direction. The substrate is divided into strip-shaped aggregates 21b. A metallized wiring layer 25 is formed on each of the strip-shaped aggregates 21b of the insulating base.

次に、図2(c)に示すようなテープ状に連なって成形されたテープ状の外部リード端子23aの先端部を、図2(b)に示す絶縁基体の短冊状集合体21bのメタライズド配線層25に接触させる。   Next, the tip of the tape-like external lead terminal 23a formed continuously in a tape shape as shown in FIG. 2C is used as the metallized wiring of the strip-like aggregate 21b of the insulating base shown in FIG. 2B. Contact layer 25.

次に、図2(d)に示すように、テープ状の外部リード端子23aと絶縁基体の短冊状集合体21bのメタライズド配線層25とを半田槽24に浸して、半田ディップによりテープ状の外部リード端子23aと絶縁基体の短冊状集合体21bとを半田により接続する。   Next, as shown in FIG. 2 (d), the tape-shaped external lead terminal 23a and the metallized wiring layer 25 of the strip-shaped aggregate 21b of the insulating base are immersed in a solder bath 24, and the tape-shaped external lead terminal 23a is dipped by solder dipping. The lead terminal 23a and the strip-like aggregate 21b of insulating base are connected by solder.

次に、図2(e)に示すように、絶縁基体の短冊状集合体21bを、テープ状外部リード端子23bを有する絶縁基体21cに分割する。さらに、図2(f)に示すように、テープ状外部リード端子23の先端部をフォーミングして、フォーミングリード端子23cを形成する。   Next, as shown in FIG. 2E, the strip-shaped aggregate 21b of the insulating base is divided into insulating bases 21c having tape-like external lead terminals 23b. Further, as shown in FIG. 2 (f), the leading end portion of the tape-like external lead terminal 23 is formed to form the forming lead terminal 23c.

図3は本発明の実施例2の半導体素子収納用パッケージを搭載した電力量計の構成図である。実施例2は、実施例1の半導体素子収納用パッケージを電力量計に搭載したことを特徴とする。   FIG. 3 is a configuration diagram of a watt hour meter equipped with a package for housing semiconductor elements according to the second embodiment of the present invention. The second embodiment is characterized in that the package for housing a semiconductor element of the first embodiment is mounted on a watt-hour meter.

図3に示す電力量計は、入力された電流を検出する電流検出部60と、入力された電圧を検出する電圧検出部70と、電流検出部60で検出された電流と電圧検出部70で検出された電圧とに基づいて電力を演算する電力演算部80と、電力演算部で得られた電力を表示する表示部90とを有して構成されている。   The watt-hour meter shown in FIG. 3 includes a current detection unit 60 that detects an input current, a voltage detection unit 70 that detects an input voltage, and a current detected by the current detection unit 60 and a voltage detection unit 70. The power calculation unit 80 calculates power based on the detected voltage, and the display unit 90 displays the power obtained by the power calculation unit.

電流検出部60は、略環状の磁性体からなり、僅かなギャップ62を有するコア61と、コア61に巻回された巻線63と、半導体素子13を有する半導体素子収納用パッケージが実装されたプリント基板64とを有し、半導体素子13がコア61のギャップ13に挿入されている。半導体素子13は、ホール素子からなる。   The current detection unit 60 is made of a substantially annular magnetic body, and a core 61 having a slight gap 62, a winding 63 wound around the core 61, and a semiconductor element storage package having the semiconductor element 13 are mounted. The semiconductor element 13 is inserted into the gap 13 of the core 61. The semiconductor element 13 is a Hall element.

このような構成において、巻線63に電流が流れると、流れた電流に比例した磁界がコア61を通り、この磁界がギャップ62に配置された半導体素子13であるホール素子を貫く。このため、ホール素子の両端には、磁界に比例した電圧が発生し、この電圧はプリント基板64を介して電力演算部80に入力される。   In such a configuration, when a current flows through the winding 63, a magnetic field proportional to the flowing current passes through the core 61, and this magnetic field penetrates the Hall element that is the semiconductor element 13 disposed in the gap 62. Therefore, a voltage proportional to the magnetic field is generated at both ends of the Hall element, and this voltage is input to the power calculation unit 80 via the printed circuit board 64.

即ち、半導体素子を有する半導体素子収納用パッケージを用いた電流検出部60により電流を検出し、電圧検出部70で電圧を検出し、検出された電流と電圧とに基づいて電力を演算することができる。 That is, a current is detected by the current detector 60 using a semiconductor element housing package having a semiconductor element, a voltage is detected by the voltage detector 70, and power is calculated based on the detected current and voltage. it can.

図4は外部リード端子14を絶縁基体11の片端にのみ配置することによる効果を説明するための図である。図4(c)、図4(d)は外部リード端子14が絶縁基体11の片端に配置される例を示している。図4(c)に示すように、外部リード端子14を片端にのみ配置した場合には、外部リード端子14の半田による接合工程が単純となる。また、図3に示す電力量計の電流検出部60において、磁界を確保する目的で、コア61のギャップ62を狭くするために、プリント基板64に穴65を設け、この穴65に跨るように、絶縁基体11を含む半導体素子収納用パッケージを実装している。図4(c)に示すように、外部リード端子14を片端にのみ配置した場合には、衝撃によるコア61の移動などによる外力が、半導体素子収納用パッケージに加わっても、図4(d)に示すように、半導体素子収納用パッケージは、プリント基板64から脱落しない。   FIG. 4 is a diagram for explaining the effect of disposing the external lead terminal 14 only at one end of the insulating base 11. 4C and 4D show an example in which the external lead terminal 14 is disposed at one end of the insulating base 11. As shown in FIG. 4C, when the external lead terminal 14 is arranged only at one end, the joining process of the external lead terminal 14 by solder becomes simple. Further, in the current detection unit 60 of the watt-hour meter shown in FIG. 3, a hole 65 is provided in the printed circuit board 64 in order to narrow the gap 62 of the core 61 for the purpose of securing a magnetic field so as to straddle the hole 65. A package for housing a semiconductor element including the insulating base 11 is mounted. As shown in FIG. 4C, when the external lead terminal 14 is arranged only at one end, even if an external force due to the movement of the core 61 due to impact is applied to the semiconductor element storage package, FIG. As shown, the semiconductor element storage package does not fall off the printed circuit board 64.

一方、図4(a)に示すように、絶縁基体11の両端に外部リード端子14が配置されて半田付けされている場合には、半田接合部に外力が全て加わり、図4(b)に示すように、半導体素子収納用パッケージが脱落するが、図4(d)に示すように、絶縁基体11の片側しか接続されていなければ、外部リード端子14が曲がるだけで済む。   On the other hand, as shown in FIG. 4A, when the external lead terminals 14 are disposed at both ends of the insulating base 11 and soldered, all external forces are applied to the solder joints, and FIG. As shown in FIG. 4, the package for housing the semiconductor element falls off. However, as shown in FIG. 4D, if only one side of the insulating substrate 11 is connected, the external lead terminal 14 only needs to be bent.

産業上の利用分野Industrial application fields

本発明は、ホール素子等の半導体素子を収納した半導体素子収納パッケージを搭載した電力量計などに適用可能である。   The present invention can be applied to a watt hour meter or the like equipped with a semiconductor element storage package that stores a semiconductor element such as a Hall element.

本発明の実施例1の半導体素子収納用パッケージの構成図である。It is a block diagram of the package for semiconductor element accommodation of Example 1 of this invention. 本発明の実施例1の半導体素子収納用パッケージの製造工程を示す図である。It is a figure which shows the manufacturing process of the package for semiconductor element accommodation of Example 1 of this invention. 本発明の実施例2の半導体素子収納用パッケージを搭載した電力量計の構成図である。It is a block diagram of the watt-hour meter carrying the semiconductor element accommodation package of Example 2 of this invention. 外部リード端子を絶縁基体の片端にのみ配置することによる効果を説明するための図である。It is a figure for demonstrating the effect by arrange | positioning an external lead terminal only to the one end of an insulation base | substrate. 従来の半導体素子収納用パッケージの構成図である。It is a block diagram of the conventional package for semiconductor element accommodation. 従来の半導体素子収納用パッケージの納入形態を示す図である。It is a figure which shows the delivery form of the conventional package for semiconductor element accommodation. 従来の半田によるリード接続の例を示す図である。It is a figure which shows the example of the lead connection by the conventional solder.

符号の説明Explanation of symbols

11,21c,31,41,51 絶縁基体
11a 第1凹部
11b 第2凹部
11c 第3凹部
12,25,32,52 メタライズド配線層
13,33,43,53 半導体素子
14,23a,34,44,54 外部リード端子
15,22,35 蓋体
16,36,55 ボンディングワイヤ
17 貫通穴
18 中空部
19 パッケージの厚さ
20a フレーム
20b ミシン目
21a 絶縁基体の集合体
21b 絶縁基体の短冊状集合体
23b テープ状外部リード端子
23c フォーミングリード端子
24 半田槽
37 封止材
42 リードフレーム
56 樹脂部材
60 電流検出部
61 コア
62 ギャップ
63 巻線
64 プリント基板
70 電圧検出部
80 電力演算部
90 表示部
11, 21c, 31, 41, 51 Insulating base
11a First recess 11b Second recess 11c Third recess 12, 25, 32, 52 Metallized wiring layers 13, 33, 43, 53 Semiconductor elements 14, 23a, 34, 44, 54 External lead terminals 15, 22, 35 Lid 16, 36, 55 Bonding wire 17 Through-hole 18 Hollow portion 19 Package thickness 20a Frame 20b Perforation 21a Insulation substrate assembly 21b Insulation substrate strip assembly 23b Tape-like external lead terminal 23c Forming lead terminal 24 Solder tank 37 Sealing material 42 Lead frame 56 Resin member 60 Current detection unit 61 Core 62 Gap 63 Winding 64 Printed circuit board 70 Voltage detection unit 80 Power calculation unit 90 Display unit

Claims (3)

第1凹部と第2凹部と前記第2凹部の深さと略等しい第3凹部とが形成された絶縁基体と、前記第1凹部に収納された半導体素子と、前記第2凹部に収納されて前記絶縁基体と樹脂接合され、前記半導体素子と対向する側に第4凹部が形成され、前記半導体素子を封止する蓋体と、前記絶縁基体に形成され、ボンディングワイヤを介して前記半導体素子に接続されるメタライズド配線層と、前記第3凹部に収納され、前記メタライズド配線層に半田層による半田付けにより接続される外部リード端子とを備えることを特徴とする半導体素子収納用パッケージ。 An insulating base having a first recess, a second recess, and a third recess substantially equal to the depth of the second recess, a semiconductor element stored in the first recess, and the second recess stored in the second recess. insulating base is a resin bonding, the fourth recess is formed on the side facing the semiconductor element, and a lid member for sealing the semiconductor element, it is formed on the insulating substrate, connected to the semiconductor element via the bonding wire A package for housing a semiconductor element, comprising: a metallized wiring layer that is formed; and an external lead terminal that is housed in the third recess and is connected to the metallized wiring layer by soldering using a solder layer . 前記外部リード端子は、外部の回路基板に半田付け可能にリード先端部がフォーミングされていることを特徴とする請求項1記載の半導体素子収納用パッケージ。   2. The package for housing a semiconductor element according to claim 1, wherein said external lead terminal has a lead tip formed so as to be solderable to an external circuit board. 電流検出部で検出された電流と電圧検出部で検出された電圧とに基づいて電力を演算する電力量計において、
前記電流検出部は、
第1凹部と第2凹部と第3凹部とが形成された絶縁基体と、前記第1凹部に収納された半導体素子と、前記第2凹部に収納されて前記絶縁基体と樹脂接合され、前記半導体素子を封止する蓋体と、前記絶縁基体に形成され、ボンディングワイヤを介して前記半導体素子に接続されるメタライズド配線層と、前記第3凹部に収納され、前記メタライズド配線層に半田により接続される外部リード端子とを備える半導体素子収納用パッケージを有することを特徴とする電力量計。
In a watt-hour meter that calculates power based on the current detected by the current detector and the voltage detected by the voltage detector,
The current detector is
An insulating substrate having a first recess, a second recess, and a third recess; a semiconductor element received in the first recess; and a resin bonded to the insulating substrate received in the second recess; A lid for sealing the element, a metallized wiring layer formed on the insulating base and connected to the semiconductor element via a bonding wire, and housed in the third recess and connected to the metallized wiring layer by soldering A watt-hour meter comprising a package for housing a semiconductor element including an external lead terminal.
JP2005051082A 2005-02-25 2005-02-25 Package for storing semiconductor element and watt hour meter Expired - Fee Related JP4500181B2 (en)

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SG149725A1 (en) 2007-07-24 2009-02-27 Micron Technology Inc Thin semiconductor die packages and associated systems and methods
SG149724A1 (en) 2007-07-24 2009-02-27 Micron Technology Inc Semicoductor dies with recesses, associated leadframes, and associated systems and methods

Citations (5)

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Publication number Priority date Publication date Assignee Title
JPS4978170A (en) * 1972-12-06 1974-07-27
JPS62155525A (en) * 1985-12-27 1987-07-10 Toshiba Corp Hybrid integrated circuit
JPH03250645A (en) * 1990-02-08 1991-11-08 Mitsubishi Materials Corp Ceramic package
JPH03285981A (en) * 1990-03-31 1991-12-17 Narumi China Corp Adhesive composition and ceramic package using the same
JPH06125030A (en) * 1992-10-12 1994-05-06 Fujitsu Ltd Semiconductor package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4978170A (en) * 1972-12-06 1974-07-27
JPS62155525A (en) * 1985-12-27 1987-07-10 Toshiba Corp Hybrid integrated circuit
JPH03250645A (en) * 1990-02-08 1991-11-08 Mitsubishi Materials Corp Ceramic package
JPH03285981A (en) * 1990-03-31 1991-12-17 Narumi China Corp Adhesive composition and ceramic package using the same
JPH06125030A (en) * 1992-10-12 1994-05-06 Fujitsu Ltd Semiconductor package

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