JP4496923B2 - Shared memory system - Google Patents

Description

  The present invention relates to a shared memory system in which a plurality of bus masters share a memory.

Generally, in a shared memory system, a system is adopted in which a plurality of bus masters access one memory by sharing one shared memory and shared bus. In such a shared memory system, the other bus masters wait until the bus becomes free, so that the bandwidth design of each bus master becomes difficult. As a conventional example that has been proposed to solve this problem, for example, a method of efficiently providing memory access control by providing a FIFO in a memory controller unit that controls a shared memory (see Patent Document 1 below) Even if DMA transfer control is performed by this DMAC, there is a method of allowing a bus request from another DMAC having a higher priority (see Patent Document 2 below).
JP 2001-282612 A (abstract) JP 2000-207352 A (Abstract)

  However, in the method described in Patent Document 1, the circuit scale required for the FIFO increases as the number of bus masters increases and as the maximum number of words per memory access determined by the system increases. Further, in the method as described in Patent Document 2, control of the bus master is complicated, and when a DRAM is used as a shared memory, overhead due to precharge and active command is increased, and can be used in the entire system. Bandwidth decreases.

  In addition, for example, in a system LSI that performs image encoding / decoding processing, processing that is performed on a single chip is particularly required for the amount of computation required for encoding / decoding of SD / HD image sizes, JPEG encoding / decoding processing, and the like. When the memory bandwidth has a wide range, multiple shared memories can be arranged inside / outside the LSI depending on the access speed and capacity, and the access destination mapping of the bus master can be freely changed, making it flexible and efficient. It is desirable to realize a good bandwidth design.

  An object of the present invention is to provide a shared memory system capable of realizing a flexible and efficient band design in view of the problems of the conventional example.

In order to achieve the above object, the present invention
A plurality of shared memories that are mapped without overlapping on one virtual address space, and each of which a start address and an end address on the virtual address space are set;
A plurality of bus masters independently requesting memory access by addresses in the virtual address space for the plurality of shared memories;
Each of the plurality of shared memories is defined by a start address and an end address in the virtual address space in which the requested address is set to itself when a memory access is requested by an address in the virtual address space. The memory access request is permitted when it is within the range.

  According to the present invention, since a plurality of shared memories are mapped on one virtual address space without overlapping, a plurality of bus masters can access in parallel, and a flexible and efficient bandwidth design is realized. be able to.

  Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an overall configuration of an embodiment of a shared memory system according to the present invention, FIG. 2 is an explanatory diagram showing address spaces of a plurality of shared memories in FIG. 1, and FIG. 3 is a plurality of shared in FIG. FIG. 4 is a timing chart illustrating a state in which a plurality of bus masters access a memory in parallel, FIG. 4 is a timing chart for explaining a clock change of the bus master in FIG. 1, and FIG. 5 is a state in which the bus master in FIG. It is a timing chart which shows. FIG. 3 shows an example in which a bus master 21 described later accesses an area of the shared memory 11 and a bus master 22 accesses an area of the shared memory 1m.

  In FIG. 1, m and n are integers of m> 1 and n> 0, respectively, m shared memories (11, 12 to 1 m), and n bus masters (21, 22 to 2n). The shared memories 11, 12-1m include a memory controller (not shown) that controls the memory. As shown in FIG. 2, each shared memory 11, 12-1m is mapped to one common virtual address space. As mapping information, a head address mapping register (STADRMAP1-STADRMAPm) and an end address mapping register (ENDADRMAP1-ENDADRMAPm) are stored. Have. A bus (not shown) for connecting the shared memories 11 and 12 to 1m and the bus masters 21 and 22 to 2n has a common signal set and communication protocol for all the shared memories 11 and 12 to 1m. Operate.

  The signals output to the memory controllers of the shared memories 11 and 12 to 1m in order for the bus masters 21 and 22 to 2n to acquire the bus right are the memory access request (REQ1 to REQm) and the virtual address space shown in FIG. This is the start address (STADR1 to STADRm) at the start of access. The REQ and STADR lines are connected in parallel from the bus masters 21, 22-2 n to all the shared memories 11, 12-1 m. Also, each memory controller compares the STADR output from the bus masters 21, 22-2n and the registers (STADRMAP1 to STADRMAPm and ENDADRMAP1 to ENDADRMAPm) by a comparison circuit (not shown), and is itself a memory controller indicated by REQ? Judge whether or not.

The determination method on the shared memory 11, 12-1m side is, for example, when REQi, STADRi is output from a certain bus master 2i (i = 1, 2-n) STADRMAP <STADRi and STADRi <ENDADRMAP
If this condition is satisfied, ACK is output to the bus master 2i to give the bus right. If a plurality of access requests indicate the same memory controller, an ACK is returned through bus arbitration such as a round robin algorithm.

  Even if REQs are output from a plurality of bus masters, for example, as shown in FIG. 2, the bus master 21 has an area of the shared memory 11 (STADR1 in the figure), and the bus master 22 has an area of the shared memory 1m (STADR2 in the figure). As shown in FIG. 3, the bus masters 21 and 22 can acquire independent bus rights and simultaneously access the memory as shown in FIG.

  The buses of the shared memories 11 to 1m have common specifications. The shared memory controller STADRMAP and ENDAMPMAP are determined by register settings from the host 3, and the STADR output by the bus masters 21 to 2n is also determined based on the addresses set by the host 3 to the bus masters 21 to 2n by register settings. The operations of the bus masters 21 to 2n do not depend on the shared memories 11 to 1m to be accessed. This simplifies the operation of the bus masters 21 to 2n and simplifies the design of the bus masters 21 to 2n.

  In addition, it has a clock generator (CLK) 4 for generating an operation clock of the shared memories 11 to 1m, and the operation clock of the bus masters 21 to 2n and the operation clock of the shared memories 11 to 1m are based on a common clock. If they are different from each other (for example, when a common clock tooth loss clock, multiplication, frequency division, etc. are used, and metastable measures are not required for data exchange between the bus masters 21 to 2n and the shared memory controller), FIG. As shown, the shared memory controller outputs a clock enable (CLK_EN) signal along with the bus right. As a result, the bus masters 21 to 2n operate by receiving the same clock as the operation clock of the access destination shared memories 11 to 1m from the clock generator (CLK) 4, thereby operating the access destination shared memories 11 to 1m. The timing can be controlled without being aware of the above.

  Further, when the bus masters 21 to 2n want to perform memory access continuously, as shown in FIG. 5, it is realized by changing the start address (STADR1 to STADRm) while outputting the access requests (REQ1 to REQm). To do. Further, when the access request (REQ1 to REQm) output during the acquisition of the bus right is for a memory different from the shared memory being accessed, there is a risk that the bus will be further acquired and the bus will collide. In order to prevent this, it is assumed that the shared memory to which access has been established can issue an ACK_DISABLE signal so that an access response is not returned from the other shared memory to the bus master. The logical sum of ACK_DISABLE for the bus master 2i is taken and used as a request mask. An address signal (ADR), transfer size (SIZE), read / write (RW), read data (RDATA), and the like may be added to the bus specification.

According to the present invention,
-Since the bus can be operated in parallel, the memory bandwidth is improved as compared with a single shared memory system.
Since the bus master access destination can be determined by changing the memory mapping of the shared memory, it is easy to allocate the bandwidth between the high-speed shared memory and the low-speed shared memory among the shared memories. Furthermore, when this system is realized as an image encoding / decoding system LSI, it can be used as a back-end LSI for many purposes.
A realistic configuration is possible in which the high-speed shared memory is inside the LSI and the low-speed and large-capacity shared memory is outside the LSI.
・ Bus master design is easy because the bus behavior is the same.
Since one bus master does not acquire a plurality of bus rights at the same time, an access request can be continuously issued when the bus master tries to acquire the bus rights continuously. In this respect, the bus master can be easily designed and the bus bandwidth performance is improved.
-Since the address comparison circuit is placed on the shared memory controller side, the circuit cost of the address mapping register and the comparison circuit is reduced, and the efficiency of register setting of the CPU is improved compared to the case where the bus master determines the shared memory to be accessed. Is possible.

1 is a block diagram showing an overall configuration of an embodiment of a shared memory system according to the present invention. It is explanatory drawing which shows the address space of the some shared memory of FIG. 2 is a timing chart illustrating a state in which a plurality of bus masters access a plurality of shared memories in FIG. 1 in parallel. 3 is a timing chart for explaining a clock change of the bus master of FIG. 1. 2 is a timing chart showing how the bus master of FIG. 1 continuously accesses.

Explanation of symbols

3 Host 4 Clock generator (CLK)
11, 12-1m shared memory 21, 22-2n bus master

Claims (1)

A plurality of shared memories that are mapped without overlapping on one virtual address space, and each of which a start address and an end address on the virtual address space are set;
A plurality of bus masters independently requesting memory access by addresses in the virtual address space for the plurality of shared memories;
Each of the plurality of shared memories is defined by a start address and an end address in the virtual address space in which the requested address is set to itself when a memory access is requested by an address in the virtual address space. A shared memory system that determines whether or not the memory access is within a range and permits the memory access request when the range is within the range.

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