JP4470231B2 - Manufacturing method of semiconductor silicon wafer - Google Patents
Manufacturing method of semiconductor silicon wafer Download PDFInfo
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- JP4470231B2 JP4470231B2 JP09282099A JP9282099A JP4470231B2 JP 4470231 B2 JP4470231 B2 JP 4470231B2 JP 09282099 A JP09282099 A JP 09282099A JP 9282099 A JP9282099 A JP 9282099A JP 4470231 B2 JP4470231 B2 JP 4470231B2
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Description
【０００１】
【発明の属する技術分野】
この発明は、両面同時研磨によるウェーハの高品質の平坦度を達成する半導体シリコンウェーハの製造方法において、表裏面の区別を明確にできる方法に係り、ウェーハの片面へ酸化膜を形成後、熱処理を施してこれを改質し、その研磨レイト低下させて、両面同時研磨後も所要厚みの酸化膜が残留して表裏面の区別を可能にし、またエピタキシャルシリコンを成膜する際にヘイズを高品位に保つことを可能にした半導体シリコンウェーハの製造方法に関する。
【０００２】
【従来の技術】
一般に、シリコンなどの半導体ウェーハの製造方法には、1)単結晶引上装置によって引き上げられた単結晶インゴットをスライスして薄円板状のウェーハを得るスライス工程と、2)ウェーハの欠けや割れを防ぐための面取り工程と、3)面取りされたウェーハを平坦化するためのラッピング工程と、4)前記加工によりウェーハに発生した加工歪み層を除去するエッチング工程と、5)面取り部を仕上研磨する面取り部研磨工程と、6)前記ウェーハを片面あるいは両面研磨する研磨工程と、7)前記ウェーハの仕上げ研磨を施した後、8)最終洗浄を経て最終製品とする、あるいは9)エピタキシャル成長を経て最終製品としていた。
【０００３】
低抵抗シリコンウェーハにエピタキシャルシリコンを成長させる場合には、シリコン基板よりのオートドープ(ドーパント濃度を変化させる)を低減させるために、エピタキシャル成長するウェーハの非成長面に化学蒸着(CVD)などの化学的気相成長法により成長させた酸化膜付けを施した後、エピタキシャル成長を施していた。
【０００４】
また近年は、半導体デバイス工程における酸化膜あるいは金属膜の平坦化技術として、CMP技術(Chemical Mechanical Polishing)が導入され、その膜厚精度が向上するに従い、シリコンウェーハの表面平坦性の向上要求も厳しくなっている。そこで、高品質の表面平坦性を有するシリコンウェーハを得るためには、表裏両面を基準に研磨可能な加工原理を有する両面同時研磨を施すと、上記の平坦性を達成できることが知られている。
【０００５】
しかしながら、従来は、デバイス形成面(おもて面)のみ鏡面研磨してあり、反対側の非鏡面研磨面(裏面)との区別が可能であったが、両面同時研磨を施すと前記の表裏面共に鏡面化され、表裏の区別が付け難くなり、例えば種々のプロセス装置においてウェーハ裏面からの反射光にて設定されるセンサー感度や、ウェーハ裏面の反射熱にて炉内の温度制御をする際の温度制御レベルなどの設定が、従来の裏面との差が生じて、所定の制御などが実施できなかったり、真空あるいは静電チャックからのウェーハの離脱時間等が異なってくるなどの問題がある。
【０００６】
そこで、上記の裏面に化学蒸着法にて所要厚みの酸化膜を成長させてから、両面同時研磨を施すことにより、裏面に酸化膜を残して表裏面の区別を可能にしながら高平坦化を達成する方法が提案(特開平9‐199465)されている。
【０００７】
【発明が解決しようとする課題】
上記提案方法において、スライス、ラッピング、エッチング工程を経た両面がエッチング面のシリコンウェーハの片面に化学蒸着法により酸化膜を、例えば8000〜10000Å厚みと比較的厚膜に成膜している。
【０００８】
ここで、両面同時研磨後に裏面側に前記エッチング面を残すためには、両面同時研磨後の酸化膜の残留厚みが例えば100〜1000Å程度必要になるが、両面同時研磨におけるこの酸化膜の研磨レイトが比較的速いため、高精度の研磨を実現するために研磨代を大きくすると酸化膜が消失し裏面側も研磨されてしまうことになり、前記のごとく酸化膜を厚く成膜しなければならない。
【０００９】
また、低抵抗シリコン基板(比抵抗1Ωcm以下)の「表」にエピタキシャルシリコンを成膜する場合、基板からのドーパントのオートドープを低減させるため、エピタキシャル成長しない裏面に化学蒸着法により酸化膜を保護膜として、例えば3000〜8000Å厚みに成膜している。
【００１０】
しかし、この化学的気相成長法による酸化膜は膜質がポーラスであり、その酸化膜中に水分が吸着されており、この状態でエピタキシャル成長を行うと、この水分がエピタキシャルシリコン成長表面に微小な酸化膜を形成し、表面のヘイズを悪化させという問題があった。このエピタキシャルシリコン表面のヘイズは当該酸化膜の厚さが増すに従って悪化する。
【００１１】
この発明は、半導体シリコンウェーハの製造方法において、鏡面研磨やエピタキシャルシリコン成膜を行うデバイス形成面とその裏面との区別や保護のために設けていた化学的気相成長法による酸化膜に関する上述の問題点を解消することを目的とし、酸化膜の成膜厚みを比較的薄くするあるいは研磨代を大きくとることが可能であり、またエピタキシャルシリコン表面のヘイズを良好に維持可能な半導体シリコンウェーハの製造方法の提供を目的としている。
【００１２】
【課題を解決するための手段】
発明者らは、半導体シリコンウェーハの両面同時研磨における裏面の酸化膜の研磨レイトを遅くでき、また膜中に水分を含まない性状を有する化学的気相成長法による酸化膜を目的に種々検討した結果、当該酸化膜の改質に着目して、酸化膜の成膜後に、例えば酸素雰囲気、窒素雰囲気あるいは酸素と窒素の混合雰囲気で熱処理を施すことにより、当該酸化膜が硬化しかつ保有水分が大幅に減少すること、従って、両面同時研磨時の研磨レイトが遅くなり、結果的に酸化膜の膜厚を薄くでき、またエピタキシャル成長時のエピタキシャルシリコンのヘイズを劣化させないことを知見し、この発明を完成した。
【００１３】
すなわち、この発明は、半導体シリコンウェーハの片面に常圧又は減圧化学的気相成長法により酸化膜を形成した後、熱処理を施して前記酸化膜を改質することを特徴とし、例えば、前記熱処理後に当該ウェーハに両面同時研磨を施して酸化膜の非搭載主面を鏡面研磨して仕上げたり、また、鏡面研磨面にエピタキシャルシリコンを成膜することにより、高度な平坦度と良好な表面性状を有するシリコンエピタキシャルウェーハを得る製造方法である。そして、前記熱処理温度は、650℃から1200℃の範囲内であることが好ましく、また、前記熱処理時間は、その熱処理温度が高いほど短時間であり、30分から180分の範囲内であることが好ましい。
【００１４】
【発明の実施の形態】
この発明は、公知の種々工程からなる半導体シリコンウェーハの製造方法において、化学的気相成長法により形成した酸化膜を熱処理して改質、硬化させることにより、研磨時の研磨速度を遅くでき、またエピタキシャル成長時など高温処理の際に酸化膜より放出する水分を低減する機能を付加するもので、この機能を種々工程で有効に活用できれば、公知のいずれの工程間にも適用可能である。
【００１５】
エピタキシャルウェーハを得る工程では、例えば、スライス、面取り、ラッピング、エッチングの各工程後に、この発明による片面酸化膜形成工程、熱処理工程を施し、必要に応じて両面同時研磨工程で高平坦度を確保したり、また「おもて面」を片面ポリッシング工程で仕上げ、洗浄工程を経てエピタキシャル成長を行う工程などが採用できる。
【００１６】
また、ウェーハのエッジ部には、公知の面取り研磨、ラッピング、ポリッシング、エッチング、ノジュール処理などの工程が必要に応じて施されるが、上述のごとくこの発明の酸化膜形成と熱処理工程とを、要求されるウェーハの仕様などに応じて適宜組み合せることができ、例えば、裏面側の酸化膜の形成時に表側のエッジ部にも成膜された場合にこれを適宜除去する工程を採用するとよい。
【００１７】
この発明による片面の酸化膜形成方法は、常圧CVDあるいは減圧CVDなどの化学的気相成長法により行う。また、成膜厚みは酸化膜の硬度が向上しているため、実施例に示すごとく従来より10%以上薄く成膜することが可能で、その後の両面同時研磨の研磨代に応じて、酸化膜成長条件、膜厚を適宜選定することができる。
【００１８】
この発明において、化学的気相成長法により形成した酸化膜の熱処理方法としては、公知のいずれの熱処理も採用できるが、例えば、一般的なチューブ炉やランプアニール炉を用いて、雰囲気としては酸素雰囲気、酸素含有雰囲気、窒素雰囲気あるいは酸素と窒素との混合ガス雰囲気が採用でき、熱処理温度としては、650℃から1200℃の範囲が必要で、好ましくは700℃から1000℃である。また、熱処理温度は高いほど短時間処理でき、保持時間は30分から180分である。
【００１９】
この発明において、片面酸化膜形成、改質のための熱処理後に施す両面同時研磨方法としては、1段又は2段階の両面同時ポリッシングなど公知のいずれの研磨方法も採用できる。
【００２０】
また、この発明において、エピタキシャルシリコンの成膜方法は、公知のいずれのエピタキシャル成長方法をも採用でき、要求されるエピタキシャルシリコンウェーハの仕様などに応じて成長条件を適宜選定することができる。
【００２１】
【実施例】
実施例1
スライス、面取り、ラッピング後にエッチング工程を経た両面がエッチング面を有する直径200mmのシリコンウェーハの片面に、常圧CVD法により酸化膜を10000Å厚みに成膜した。なお、酸化膜の成膜条件は、SiH4とO2の混合ガスを450℃の加熱下で反応させた。
【００２２】
片面に酸化膜処理を施した上記ウェーハをチューブ炉を用いて700℃、窒素雰囲気下にて120分処理した後、両面研磨装置にてシリコン面を5μmの研磨代を目標に鏡面研磨した。また、比較のため上記の熱処理を施さないで同条件で鏡面研磨した。
【００２３】
酸化膜の研磨代を測定したところ、この発明による成膜後に熱処理を施したウェーハでは5400Å程度であったが、熱処理なしの従来のウェーハの場合は6000Å程度であり、成膜後に熱処理を施した酸化膜は硬度が向上して熱処理のない場合に比較して約10%少なくなることを確認した。
【００２４】
実施例2
実施例1と同様方法で、片面に3000Å厚みの酸化膜を設けてから熱処理し、シリコンウェーハの非酸化膜搭載面を鏡面研磨し、その後、非酸化膜搭載面にエピタキシャルシリコンを成長させた。エピタキシャルシリコンは枚葉式エピタキシャルシリコン成長炉を用い、TCS、H2混合ガス雰囲気下にて約5μm成長させた。
【００２５】
また、比較のため、酸化膜厚みが3000Å、6000Å、8000Åの3種のシリコンウェーハを用い、上記の実施例2と同条件にて熱処理を施さず、鏡面研磨、エピタキシャルシリコンの成長を行った。
【００２６】
上記の4種のエピタキシャル表面のヘイズレベルを集光灯下にて、目視検査により相対的に比較したところ、この発明によるエピタキシャルシリコンウェーハのヘイズレベルを1とすると、比較の酸化膜厚みが3000Åのウェーハはヘイズレベルが2、同6000Åのウェーハはヘイズレベルが3、8000Åのウェーハはヘイズレベルが4と、順次ヘイズレベルが悪化していた。
【００２７】
すなわち、従来の酸化膜成長後に熱処理のないウェーハでは、酸化膜の厚さの増加に従いヘイズレベルが悪化するのが確認され、またこの発明により形成された酸化膜では、同等の酸化膜厚さのウェーハと比較し、エピタキシャルシリコン表面のヘイズレベルが改善されていることが確認された。
【００２８】
実施例3
実施例1において、片面に酸化膜を設けてから熱処理し、その後、両面同時鏡面研磨したシリコンウェーハの非酸化膜搭載面にエピタキシャルシリコンを成長させた。エピタキシャル成長は実施例2と同条件で実施した。なお、両面同時鏡面研磨後の酸化膜厚みは3000Åであった。実施例2と同様にヘイズレベルを目視検査したところ、実施例2と同様のヘイズレベル1の結果が確認された。
【００２９】
実施例4
両面がエッチング面の直径200mmのシリコンウェハの片面に化学的気相成長法により酸化膜を3000Å厚みを目標に成膜した。酸化膜の成膜条件はSiH4とO2の混合ガスを加熱下に反応させた。片面に酸化膜処理を施したウェーハの酸化膜の非搭載面を鏡面研磨した後、チューブ炉を用いて1000℃、窒素雰囲気下にて30分処理した後、非酸化膜面にエピタキシャルシリコンを成長させた。エピタキシャルシリコンは枚葉式エピタキシャルシリコン成長炉を用い、TCS、H2混合ガス雰囲気下にて約5μm厚みに成長させた。
【００３０】
エピタキシャルシリコン表面のヘイズレベルを、集光灯下にて目視検査した結果、実施例2と同様のヘイズレベル改善の効果が確認された。
【００３１】
【発明の効果】
この発明は、化学的気相成長法により成長させた酸化膜に熱処理を施して酸化膜を改質することにより、その後の両面同時研磨時の酸化膜の研磨量を低減し、両面同時研磨による高精度の平坦度を維持したまま、裏面に酸化膜を残留させて表裏の区別が目視並びにセンサーにて容易に実施でき、高品質のシリコンウェーハを提供できる。
【００３２】
さらにこの発明は、化学的気相成長法により成長させた酸化膜を有するシリコンウェーハの非酸化膜搭載面にエピタキシャルシリコンを成長させた際に、裏面の酸化膜からの水分の放出が少なく、エピタキシャルシリコン表面のヘイズが優れた高品位のシリコンウェーハを製造することが可能になる。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor silicon wafer that achieves high-quality flatness of a wafer by simultaneous double-side polishing, and relates to a method capable of clearly distinguishing between the front and back surfaces. After forming an oxide film on one side of the wafer, heat treatment is performed. To improve the polishing rate and reduce the polishing rate so that the oxide film with the required thickness remains even after simultaneous polishing on both sides, making it possible to distinguish between the front and back surfaces, and high-quality haze when forming epitaxial silicon The present invention relates to a method for manufacturing a semiconductor silicon wafer that can be maintained at a high level.
[0002]
[Prior art]
In general, a method for manufacturing a semiconductor wafer such as silicon includes 1) a slicing process in which a single crystal ingot pulled by a single crystal pulling apparatus is sliced to obtain a thin disk-shaped wafer, and 2) chipping or cracking of the wafer. Chamfering process for preventing chamfering, 3) lapping process for flattening the chamfered wafer, 4) etching process for removing the processing strain layer generated on the wafer by the processing, and 5) finish polishing the chamfered portion. A chamfered portion polishing step, 6) a polishing step for polishing the wafer on one or both sides, 7) after the final polishing of the wafer, 8) a final product through final cleaning, or 9) through epitaxial growth It was the final product.
[0003]
When epitaxial silicon is grown on a low-resistance silicon wafer, chemical vapor deposition (CVD) or other chemicals are used on the non-growth surface of the epitaxially grown wafer to reduce autodoping (changing the dopant concentration) from the silicon substrate. After applying an oxide film grown by vapor deposition, epitaxial growth was performed.
[0004]
In recent years, CMP (Chemical Mechanical Polishing) has been introduced as a planarization technique for oxide films or metal films in the semiconductor device process, and as the film thickness accuracy has improved, the demand for improved surface flatness of silicon wafers has become severe. It has become. In order to obtain a silicon wafer having high-quality surface flatness, it is known that the above-described flatness can be achieved by performing double-sided simultaneous polishing having a processing principle capable of polishing on both front and back surfaces.
[0005]
Conventionally, however, only the device forming surface (front surface) is mirror-polished, and it is possible to distinguish it from the opposite non-mirror-polished surface (back surface). Both the back and back surfaces are mirrored, making it difficult to distinguish between the front and back surfaces. For example, when controlling the temperature in the furnace using the sensor sensitivity set by the reflected light from the back surface of the wafer or the reflected heat from the back surface of the wafer in various process equipment. There is a problem that the setting of temperature control level and the like is different from the conventional backside, so that the predetermined control cannot be performed or the time for detaching the wafer from the vacuum or electrostatic chuck is different. .
[0006]
Therefore, by growing an oxide film of the required thickness on the back surface by chemical vapor deposition, and then performing double-sided polishing, high planarization is achieved while leaving the oxide film on the back surface and enabling discrimination between the front and back surfaces. A method has been proposed (Japanese Patent Laid-Open No. 9-199465).
[0007]
[Problems to be solved by the invention]
In the proposed method, an oxide film is formed in a relatively thick film, for example, a thickness of 8000 to 10,000 mm on one side of a silicon wafer that has been etched, sliced, lapped, and etched by chemical vapor deposition.
[0008]
Here, in order to leave the etched surface on the back side after the double-sided simultaneous polishing, the residual thickness of the oxide film after the double-sided simultaneous polishing is required to be, for example, about 100 to 1000 mm. However, if the polishing allowance is increased in order to realize high-precision polishing, the oxide film disappears and the back side is also polished, and the oxide film must be formed thick as described above.
[0009]
In addition, when epitaxial silicon is deposited on the “table” of a low-resistance silicon substrate (with a specific resistance of 1 Ωcm or less), a protective film is formed on the back surface that is not epitaxially grown by chemical vapor deposition to reduce autodoping of dopant from the substrate. For example, the film is formed to a thickness of 3000 to 8000 mm.
[0010]
However, the oxide film formed by this chemical vapor deposition method has a porous film quality, and moisture is adsorbed in the oxide film. When epitaxial growth is performed in this state, the moisture is minutely oxidized on the epitaxial silicon growth surface. There was a problem of forming a film and deteriorating the haze of the surface. The haze on the surface of the epitaxial silicon deteriorates as the thickness of the oxide film increases.
[0011]
The present invention relates to an oxide film formed by a chemical vapor deposition method provided for the purpose of distinguishing and protecting a device forming surface for mirror polishing or epitaxial silicon film formation and its back surface in a method for manufacturing a semiconductor silicon wafer. Aiming to eliminate the problems, it is possible to reduce the thickness of the oxide film or increase the polishing allowance, and to produce a semiconductor silicon wafer that can maintain good haze on the epitaxial silicon surface The purpose is to provide a method.
[0012]
[Means for Solving the Problems]
The inventors of the present invention have been able to slow down the polishing rate of the oxide film on the back surface in simultaneous double-side polishing of a semiconductor silicon wafer, and have studied variously for the purpose of an oxide film formed by chemical vapor deposition having properties that do not contain moisture in the film. As a result, paying attention to the modification of the oxide film, after the oxide film is formed, for example, by performing a heat treatment in an oxygen atmosphere, a nitrogen atmosphere, or a mixed atmosphere of oxygen and nitrogen, the oxide film is cured and the retained moisture is reduced. As a result, it was found that the polishing rate at the time of simultaneous double-side polishing is delayed, the oxide film thickness can be reduced, and the haze of epitaxial silicon during epitaxial growth is not deteriorated. completed.
[0013]
That is, the present invention is characterized in that an oxide film is formed on one surface of a semiconductor silicon wafer by atmospheric pressure or reduced pressure chemical vapor deposition, and then the oxide film is modified by heat treatment, for example, the heat treatment Later, the wafer is subjected to simultaneous double-side polishing to finish the non-mounting main surface of the oxide film by mirror polishing, and by forming epitaxial silicon on the mirror polishing surface, high flatness and good surface properties are achieved. It is a manufacturing method which obtains the silicon epitaxial wafer which has. The heat treatment temperature is preferably in the range of 650 ° C. to 1200 ° C., and the heat treatment time is shorter as the heat treatment temperature is higher, and is in the range of 30 minutes to 180 minutes. preferable.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
This invention is a method for manufacturing a semiconductor silicon wafer comprising various known processes, by heat-treating and modifying an oxide film formed by chemical vapor deposition, the polishing rate during polishing can be reduced, Further, it adds a function of reducing moisture released from the oxide film during high temperature processing such as epitaxial growth, and can be applied between any known processes as long as this function can be effectively utilized in various processes.
[0015]
In the process of obtaining an epitaxial wafer, for example, after each process of slicing, chamfering, lapping, and etching, a single-sided oxide film forming process and a heat treatment process according to the present invention are performed, and high flatness is ensured by a double-sided simultaneous polishing process if necessary. Alternatively, a process of finishing the “front surface” by a single-side polishing process and performing epitaxial growth through a cleaning process can be employed.
[0016]
In addition, the edge portion of the wafer is subjected to known chamfering polishing, lapping, polishing, etching, nodule treatment, and the like as necessary, but as described above, the oxide film formation and heat treatment step of the present invention are performed. For example, it is preferable to adopt a process of appropriately removing the oxide film on the front side when the back side oxide film is formed.
[0017]
The single-side oxide film forming method according to the present invention is performed by chemical vapor deposition such as atmospheric pressure CVD or low pressure CVD. In addition, since the thickness of the oxide film is improved, as shown in the examples, it is possible to form a film that is 10% or less thinner than the conventional film. Growth conditions and film thickness can be selected as appropriate.
[0018]
In the present invention, any known heat treatment can be adopted as a heat treatment method for an oxide film formed by chemical vapor deposition. For example, a general tube furnace or lamp annealing furnace is used, and the atmosphere is oxygen. An atmosphere, an oxygen-containing atmosphere, a nitrogen atmosphere, or a mixed gas atmosphere of oxygen and nitrogen can be employed, and the heat treatment temperature needs to be in the range of 650 ° C. to 1200 ° C., preferably 700 ° C. to 1000 ° C. Further, the higher the heat treatment temperature, the shorter the treatment time is, and the holding time is 30 minutes to 180 minutes.
[0019]
In this invention, as the double-sided simultaneous polishing method applied after the heat treatment for forming and modifying the single-sided oxide film, any known polishing method such as one-step or two-step double-sided simultaneous polishing can be employed.
[0020]
In the present invention, any known epitaxial growth method can be employed as the epitaxial silicon film forming method, and the growth conditions can be appropriately selected according to the required specifications of the epitaxial silicon wafer.
[0021]
【Example】
Example 1
After slicing, chamfering, and lapping, an oxide film was formed to a thickness of 10,000 mm on one side of a 200 mm diameter silicon wafer having an etched surface on both sides by an atmospheric pressure CVD method. The oxide film was formed by reacting a mixed gas of SiH 4 and O 2 with heating at 450 ° C.
[0022]
The wafer having an oxide film treated on one side was treated in a tube furnace at 700 ° C. in a nitrogen atmosphere for 120 minutes, and then the silicon surface was mirror-polished with a double-side polishing apparatus targeting a polishing allowance of 5 μm. For comparison, mirror polishing was performed under the same conditions without performing the above heat treatment.
[0023]
When measuring the polishing allowance of the oxide film, it was about 5400 mm in the wafer subjected to the heat treatment after the film formation according to the present invention, but about 6000 mm in the case of the conventional wafer without the heat treatment, and was subjected to the heat treatment after the film formation. It was confirmed that the oxide film was improved in hardness and decreased by about 10% compared to the case without heat treatment.
[0024]
Example 2
In the same manner as in Example 1, an oxide film having a thickness of 3000 mm was provided on one side and then heat-treated, the non-oxide film mounting surface of the silicon wafer was mirror-polished, and then epitaxial silicon was grown on the non-oxide film mounting surface. Epitaxial silicon was grown by using a single-wafer epitaxial silicon growth furnace in a TCS and H 2 mixed gas atmosphere at a thickness of about 5 μm.
[0025]
For comparison, three types of silicon wafers having an oxide film thickness of 3000 mm, 6000 mm, and 8000 mm were used, and mirror polishing and epitaxial silicon growth were performed without heat treatment under the same conditions as in Example 2 above.
[0026]
When the haze levels of the above four types of epitaxial surfaces were relatively compared by visual inspection under a condenser lamp, when the haze level of the epitaxial silicon wafer according to the present invention was 1, the comparative oxide film thickness was 3000 mm. Wafers had a haze level of 2, wafers of 6000 mm had a haze level of 3, wafers of 8000 mm had a haze level of 4, and the haze level gradually deteriorated.
[0027]
That is, it is confirmed that the haze level deteriorates as the thickness of the oxide film increases in the wafer without heat treatment after the conventional oxide film growth, and the oxide film formed according to the present invention has an equivalent oxide film thickness. Compared with the wafer, it was confirmed that the haze level of the epitaxial silicon surface was improved.
[0028]
Example 3
In Example 1, after providing an oxide film on one surface, heat treatment was performed, and thereafter, epitaxial silicon was grown on the non-oxide film mounting surface of the silicon wafer subjected to double-sided mirror polishing. Epitaxial growth was performed under the same conditions as in Example 2. The oxide film thickness after double-sided simultaneous mirror polishing was 3000 mm. When the haze level was visually inspected in the same manner as in Example 2, the result of haze level 1 similar to that in Example 2 was confirmed.
[0029]
Example 4
An oxide film was formed on one side of a 200 mm diameter silicon wafer on both sides by a chemical vapor deposition method with a target thickness of 3000 mm. The oxide film was formed by reacting a mixed gas of SiH 4 and O 2 with heating. After mirror-polishing the non-mounting surface of the oxide film on one side of the wafer that was treated with oxide film, it was treated in a tube furnace at 1000 ° C in a nitrogen atmosphere for 30 minutes, and then epitaxial silicon was grown on the non-oxide film surface I let you. Epitaxial silicon was grown to a thickness of about 5 μm in a TCS and H 2 mixed gas atmosphere using a single wafer epitaxial silicon growth furnace.
[0030]
As a result of visual inspection of the haze level of the epitaxial silicon surface under a condenser lamp, the same effect of improving the haze level as in Example 2 was confirmed.
[0031]
【The invention's effect】
In this invention, the oxide film grown by chemical vapor deposition is subjected to a heat treatment to modify the oxide film, thereby reducing the amount of polishing of the oxide film during subsequent double-side simultaneous polishing, and by double-sided simultaneous polishing. While maintaining a high degree of flatness, an oxide film remains on the back surface, and the front and back surfaces can be easily distinguished visually and with a sensor, and a high-quality silicon wafer can be provided.
[0032]
Furthermore, according to the present invention, when epitaxial silicon is grown on a non-oxide film mounting surface of a silicon wafer having an oxide film grown by chemical vapor deposition, there is little release of moisture from the oxide film on the back surface, It becomes possible to manufacture a high-quality silicon wafer having excellent haze on the silicon surface.
Claims (3)
内である、請求項１又は２に記載の半導体シリコンウェーハの製造方法。The method of manufacturing a semiconductor silicon wafer according to claim 1 or 2 , wherein a heat treatment temperature applied to modify the oxide film is in a range of 650 ° C to 1200 ° C.
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| JP2002164286A (en) * | 2000-11-27 | 2002-06-07 | Shin Etsu Handotai Co Ltd | Method of manufacturing silicon single-crystal substrate and silicon epitaxial wafer |
| JP2006190703A (en) * | 2004-12-28 | 2006-07-20 | Shin Etsu Handotai Co Ltd | Method of manufacturing epitaxial wafer and epitaxial wafer |
| JP2007080958A (en) * | 2005-09-12 | 2007-03-29 | Shin Etsu Handotai Co Ltd | Method of manufacturing epitaxial wafer and epitaxial wafer manufactured therewith |
| US8603908B2 (en) * | 2011-05-06 | 2013-12-10 | Lam Research Corporation | Mitigation of silicide formation on wafer bevel |
| JP5845143B2 (en) | 2012-06-29 | 2016-01-20 | 株式会社Sumco | Epitaxial silicon wafer manufacturing method and epitaxial silicon wafer |
| JP2021130579A (en) * | 2020-02-19 | 2021-09-09 | グローバルウェーハズ・ジャパン株式会社 | Method for manufacturing semiconductor silicon wafer |
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