JP4467963B2 - Regulator device and backflow prevention diode circuit used therefor - Google Patents

Description

  The present invention relates to a regulator device, and more particularly to a regulator device having a structure suitable for integration. The present invention also relates to a backflow prevention diode circuit suitable for integration.

  Conventionally, many integrated regulator devices have an external power transistor so that a large current can flow with a high breakdown voltage (see, for example, Patent Document 1). The regulator device disclosed in Patent Document 1 will be described with reference to the drawings. FIG. 9 is a diagram showing the regulator device 101, and shows a part where the broken line frame a is integrated.

  As shown in FIG. 9, the regulator device 101 has a drain connected to a power source Vhv, a source connected to a capacitor Cext1 having one end grounded, and a source connected to the source of the power transistor 102. A voltage dividing circuit 103 in which R11 and a resistor R12 are connected in series, a differential amplifier 104 having a voltage divided by the voltage dividing circuit 103 as one input and a reference voltage Vref as the other input, and a gate having a differential The MOS transistor 106 is connected to the output of the amplifier 104 and the drain is connected to the output terminal 105 through the gate of the power transistor 102 and the resistor R10.

  In the regulator device 101, feedback control is performed so that the input voltages of the differential amplifier 104 become equal, and the adjusted output voltage Vreg is obtained from the drain of the power transistor 102.

  Capacitor Cext1 is used to lower the gain in the high frequency range because if the gain of power transistor 102 is too large, the feedback loop may become positive feedback and oscillate. As the capacitor Cext1, a capacitor having an appropriate capacity according to the amplification factor of the power transistor 102, for example, about 1 to 100 μF is used.

  Although not shown in Patent Document 1, generally, the current of the power transistor 102 is monitored by an external resistor. For example, when an abnormal current flows due to a ground fault in the source, the comparator operates and the differential amplifier 104 The output is limited to prevent the power transistor 102 from being thermally destroyed.

  However, the regulator device disclosed in Patent Document 1 has a problem that it is difficult to reduce the size and the space because the power transistor 102 and the current monitoring resistor are externally attached.

  On the other hand, a regulator device in which an external resistor and an external power transistor are integrated is known. FIG. 10 is a diagram showing a regulator device in which an external resistor and an external PNP bipolar transistor are integrated.

  As shown in FIG. 10, the regulator device 201 includes a PNP bipolar transistor Q21 having an emitter connected to a power source Vin via a resistor RL and a collector connected to a capacitor Cext2 whose other end is grounded, and a PNP bipolar transistor Q21. And a differential circuit 202 having a resistor R21 and a resistor R22 connected in series, and an output voltage divided by the voltage divider circuit 202 as one input and a reference voltage Vbg as the other input. The transconductance amplifier 203 and a comparator 204 that receives as input the voltage difference between the potential difference across the resistor RL and the reference voltage Voff.

  However, in the case of the integrated PNP transistor Q21, in particular, in the case of a lateral structure PNP bipolar transistor, the current amplification factor varies greatly depending on the manufacturing lot. In an integrated transistor, since the absolute accuracy is generally not good, the current amplification factor varies greatly.

  Therefore, it is necessary to attach an external capacitor Cext2 having a large capacity in advance in consideration of variations in the current amplification factor. In general, a large-capacity capacitor is large in shape and high in cost.

  Further, since the lateral PNP bipolar transistor has a small effective transistor junction area and a small current capacity per transistor, it is necessary to integrate many lateral PNP transistors in parallel to increase the current. There is a problem that the chip size becomes large.

  Further, in order to improve this problem, the PNP transistor Q21 may be composed of a composite PNP transistor in which an NPN transistor and a PNP transistor are combined. However, when the power supply Vin decreases due to integration, for example, the power supply Vin In a vehicle-mounted regulator device supplied from a battery, when the battery switch is turned off and the power supply Vin decreases, current may flow backward from the output voltage Vreg through the parasitic circuit of the composite PNP bipolar transistor Q21.

For this reason, it is necessary to externally attach the backflow prevention diode 205, which hinders miniaturization and space saving.
JP 2003-67061 A (page 5, FIG. 2)

  The regulator device disclosed in Patent Document 1 has a problem that it is difficult to improve the function and downsize because the resistor and the power transistor are externally attached.

  Also, in the conventional regulator device in which the resistor and the power transistor are integrated, the variation of the current amplification factor is expected, so that the capacity of the external capacitor becomes excessive, and a backflow prevention diode is required, which prevents miniaturization. There's a problem.

  The present invention has been made to solve the above problems, and an object thereof is to provide a regulator device having a structure suitable for integration and a backflow prevention diode circuit used therefor.

In order to achieve the above object, a regulator device of one embodiment of the present invention includes a backflow prevention diode including an N-type MOS transistor in which a first gate, a first source, and a first back gate are connected in common. A first P-type MOS transistor having a circuit, a second source connected to a power source input from the outside via a first drain of the backflow prevention diode circuit, and a second drain connected to an output terminal; The third gate and the third source are connected to the second gate and the second source of the first P-type MOS transistor, respectively, and the third drain and the third gate are short-circuited. Current mirror circuit composed of two P-type MOS transistors, the second P-type MOS transistor, the fourth gate and the fourth source are the second P-type MOS transistors. A second current mirror circuit composed of a third P-type MOS transistor connected to each of the third gate and the third source of the transistor and a predetermined first voltage by dividing the output voltage of the output terminal. Feedback control means for inputting an output proportional to the difference to the reference voltage of the second P-type MOS transistor to the second P-type MOS transistor, and an output of the third P-type MOS transistor constituting the second current mirror circuit Current limiting means for limiting the output of the feedback control means when the converted voltage is larger than the second reference voltage. The drain current of the first P-type MOS transistor is monitored by the mirror ratio of the second current mirror circuit, and the drain current of the first P-type MOS transistor is limited. It is characterized by a door.

  In the backflow prevention diode circuit used in the regulator device of one embodiment of the present invention, the gate and the source of the insulated gate field effect transistor whose back gate is connected to the source are short-circuited, and the back gate is used as an anode and the drain is used as a cathode. A parasitic diode is used to allow a current to flow from the back gate to the drain through the region where the insulated gate field effect transistor is formed.

  According to the present invention, a power regulator, a resistor, and a backflow prevention diode can be integrated to provide a small regulator device.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a regulator device according to Embodiment 1 of the present invention. The present embodiment is an example in the case of integrating a power transistor which has been conventionally externally attached.

  As shown in FIG. 1, the regulator circuit 11 includes a MOS transistor M1 in which the source S1 is connected to the input terminal IN and the drain D1 is connected to the output terminal OUT, and the gate G2 and the source S2 are the gate G1 and the source of the MOS transistor M1. A current mirror circuit 14 composed of a MOS transistor M2 connected to S1 is formed.

  The MOS transistors M1 and M2 are, for example, high breakdown voltage p-type MOS transistors or p-type DMOS (Double Diffused MOS) transistors.

  Further, the voltage dividing circuit 12 that divides the output voltage at the output terminal OUT, and the difference between the output voltage divided by the voltage dividing circuit 12 and the predetermined reference voltage Vbg and outputting a current proportional to the difference. The dynamic transconductance amplifier 13 is integrated on a single chip.

  A power supply Vin is connected to the input terminal IN, and a regulated voltage Vreg is output to the output terminal OUT via the MOS transistor M1. A capacitor C1 is connected to the output terminal OUT.

  The voltage dividing circuit 12 includes, for example, a series connection of a resistor R1 and a resistor R2. The voltage dividing circuit 12 divides the output voltage Vreg and outputs a divided voltage. Here, “resistance” in this specification is not a parasitic resistance due to wiring, but, for example, a resistance formed by an impurity diffusion region or a resistor film.

  The differential transconductance amplifier 13 compares the output voltage divided by the voltage dividing circuit 12 with a predetermined reference voltage Vbg, for example, a constant voltage of a band gap reference voltage generation circuit, and outputs a current proportional to the difference. To do.

  When the output of the differential transconductance amplifier 13 is input to the connection point between the gate G2 and the drain D2 of the MOS transistor M2, which is the input terminal of the current mirror circuit 14, the drain equal to the output current of the differential transconductance amplifier 13 is input to the MOS transistor M2. Current flows.

  As a result, a drain current that is double the mirror ratio of the current mirror circuit 14 flows through the MOS transistor M1, and thus the voltage divided by the voltage dividing circuit 12 is adjusted to be equal to the reference voltage Vbg at the output terminal OUT. A voltage Vreg is obtained.

  Here, the mirror ratio is determined by the ratio of the ratio W1 / L1 of the gate width W1 and the gate length L1 of the MOS transistor M1 and the ratio W2 / L2 of the gate width W2 and the gate length L2 of the MOS transistor M2. Therefore, the mirror ratio can be set to an arbitrary value, and the fluctuation is very small because it is not affected by the manufacturing process.

  For example, in order to obtain a power transistor whose current amplification factor is controlled to be constant at 100, the gate length L1 and the gate length L2 are made equal, the gate width W1 is made 100 times larger than the gate width W2, and the mirror ratio is set to 100. It ’s fine.

  As a result, the fluctuation of the gain of the feedback control loop composed of the voltage dividing circuit 12, the differential transconductance amplifier 13, and the current mirror circuit 14 is also reduced, so that the external capacitor C1 expects variation in the current amplification factor of the power transistor. It is not necessary to use a larger capacity, and it is possible to use a capacitor having a capacity corresponding to the current amplification factor.

  As described above, according to the regulator device 11 of the present embodiment, since the power transistors are integrated as a current mirror circuit composed of a high breakdown voltage p-type MOS transistor, variation in the current amplification factor can be suppressed, and The excessive capacity of the attached capacitor can be reduced.

  Further, the chip size can be reduced as compared with the case where the current mirror circuit is configured by the lateral PNP type bipolar transistor. Therefore, a small and space-saving regulator device can be obtained.

(Modification 1 of Example 1)
FIG. 2 is a diagram illustrating a current mirror circuit according to the first modification of the first embodiment. This modification is different from the first embodiment in that a resistor that absorbs the off-leakage current is provided when the off-leakage current of the differential conductance amplifier 13 is generated.

  That is, as shown in FIG. 2, in the current mirror circuit 17 of this modification, the MOS transistor M1, the gate G2, and the source S2 are connected to the gate G1 and the source S1 of the MOS transistor M1, respectively, and the drain D2 and the gate G2 are connected. The MOS transistor M2 is short-circuited.

  Furthermore, one end of the resistor R3 is connected to the connection portion between the gate G1 of the MOS transistor M1 and the gate G2 of the MOS transistor M2, and the other end is connected to the connection portion between the source S1 of the MOS transistor M1 and the source S2 of the MOS transistor M2. It consists of

  The off-leakage current means a minute current that flows out to the reverse-biased parasitic element of the differential conductance amplifier 13 when the temperature of the regulator device 11 rises to a high temperature, for example, about 120 ° C. or higher.

  When an off-leakage current is generated, the off-leakage current flows into the MOS transistor M2 even though the differential conductance amplifier 13 is off, so that a current also flows through the MOS transistor M1 constituting the current mirror circuit 14. End up.

  As a result, when the MOS transistor M1 is turned on, the output voltage Vreg rises to the input voltage Vin when the output terminal OUT is in a no-load state, and exceeds the maximum rated voltage of the low withstand voltage circuit connected to the output terminal OUT. Circuit elements may be destroyed.

  In the current mirror circuit 17, it is possible to prevent the MOS transistor M1 from being turned on by absorbing the off-leakage current by the resistor R3. The resistor R3 only needs to be able to absorb a minute off-leakage current, and is preferably about 100 KΩ, for example.

  As described above, in the above-described modification, the resistor R3 that can absorb the off-leakage current is provided, so that a margin for the temperature rise of the regulator device 11 can be further ensured.

(Modification 2 of Example 1)
FIG. 3 is a diagram illustrating a current mirror circuit according to the second modification of the first embodiment. This modification differs from the first embodiment in that the gate and the source are changed when the voltage at the input terminal IN suddenly increases due to ESD (Electro Static Discharge) or when the voltage at the output terminal OUT suddenly decreases. A constant voltage diode, for example, a Zener diode is provided to prevent the gate voltage from becoming excessively high and breaking the gate.

  That is, as shown in FIG. 3, in the current mirror circuit 19 of this modification, the MOS transistor M1, the gate G2, and the source S2 are connected to the gate G1 and the source S1 of the MOS transistor M1, respectively, and the drain D2 and the gate G2 are connected. The MOS transistor M2 is short-circuited.

  Further, one end of the Zener diode ZD is connected to the connection portion between the gate G1 of the MOS transistor M1 and the gate G2 of the MOS transistor M2, and the other end is connected to the connection portion between the source S1 of the MOS transistor M1 and the source S2 of the MOS transistor M2. It consists of and.

  The voltage between the gate G1 and the source S1 of the MOS transistor M1 and between the gate G2 and the source S2 of the MOS transistor M2 can be limited to a predetermined value or less by the Zener diode ZD. Can be prevented from being destroyed.

  As described above, since the Zener diode that absorbs excess voltage is provided in the above-described modification, a margin for ESD can be further ensured.

  Although the case where only the Zener diode ZD is connected to the gate and the source has been described here, the off-leakage current absorbing resistor R3 described in the first modification may be further connected in parallel.

  FIG. 4 is a circuit diagram showing a configuration of the regulator device according to the second embodiment of the present invention. This embodiment is an example in the case of integrating a power transistor and a current monitor resistor, which are conventionally externally attached. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Different parts will be described.

  This embodiment differs from the first embodiment in that an insulated gate field effect transistor that monitors the current of the power transistor is integrated instead of an external resistor.

  That is, as shown in FIG. 4, the regulator device 21 includes an insulated gate field effect transistor in which the gate G3 and the source S3 are connected to the gate G2 and the source S2 of the MOS transistor M2, respectively, and the drain D3 is grounded through the resistor R4. Comparing M3, the voltage at the end of the resistor R4 and the reference voltage Voff, and when the voltage at the end of the resistor R4 is larger than the reference voltage Voff, a comparator 22 that outputs a signal for limiting the output of the differential transconductance amplifier 13; Is integrated.

  The insulated gate field effect transistor M3 is, for example, a high breakdown voltage p-type MOS transistor or p-type DMOS transistor, and forms a current mirror circuit 24 with the MOS transistor M2.

  When the output of the differential transconductance amplifier 13 is input to the connection point between the gate G2 and the drain D2 of the MOS transistor M2, which is the input terminal of the current mirror circuit 24, the MOS transistor M3 has a mirror ratio times the current mirror circuit 24, for example, When the mirror ratio is 1, a drain current equal to the drain current of the MOS transistor M2 flows.

  Since the drain current of the MOS transistor M3 flows through the resistor R4, the drain current of the MOS transistor M1 can be monitored as the voltage at the end of the resistor R4.

  The comparator 22 compares the voltage at the end of the resistor R4 with the reference voltage Voff. If the voltage at the end of the resistor R4 is larger than the reference voltage Voff, the comparator 22 controls the output current of the differential transconductance amplifier 13 to control the drain current of the MOS transistor M1. Can be limited.

  As a result, voltage loss due to the current monitoring resistor connected in series with the MOS transistor M1 is eliminated, so that the regulator circuit 21 having a lower minimum operating voltage is obtained. In addition, since it is not necessary to consider the variation due to the manufacturing process of the current monitoring resistor, it is easy to set the reference voltage Voff.

  As described above, according to the regulator device 21 of the present embodiment, since the MOS transistor M3 constituting the current mirror circuit 24 is integrated, the drain current of the MOS transistor M1 can be monitored. This eliminates the need for a current monitoring resistor, and the minimum operating voltage can be lowered accordingly. Therefore, a small and space-saving regulator device can be obtained.

(Modification of Example 2)
FIG. 5 is a diagram illustrating a current mirror circuit according to a modification of the second embodiment. This modification is different from the second embodiment in that the mirror ratio of the current mirror circuit 24 composed of the MOS transistor M2 and the MOS transistor M3 is the ratio of W2 / L2 of the MOS transistor M2 and W3 / L3 of the MOS transistor M3. This is because it can be set by both resistance values.

  That is, as shown in FIG. 5, in the current mirror circuit 27 of this modification, the MOS transistor M2, the gate G3 are connected to the gate G2 of the MOS transistor M2, and the source S3 is connected to the source of the MOS transistor M2 via the resistor R5. It is composed of a MOS transistor M3 connected to S2.

  Since the mirror ratio of the current mirror circuit 27 varies depending on the driving capability of the differential transconductance amplifier 13 and the comparator 22, the mirror ratio of the current mirror circuit 14, and the like, for example, the mirror ratio of the current mirror circuit 27 is smaller than 1. May be required.

  In this case, even if W2 / L2 of the MOS transistor M2 is equal to W3 / L3 of the MOS transistor M3, the current flowing through the MOS transistor M3 can be limited by the resistor R5, so that the mirror ratio of the current mirror circuit 27 is 1 or less. It is possible to adjust to.

  Thereby, W3 / L3 of the MOS transistor M3 is made smaller than W2 / L2 of the MOS transistor M2, or W2 / L2 of the MOS transistor M2 is made larger than W3 / L3 of the MOS transistor M3 to adjust the mirror ratio each time. There is no need.

  As described above, in the above-described modification, the resistor R5 capable of adjusting the mirror ratio is provided, so that the design of the MOS transistor M2 and the MOS transistor M3 can be made uniform, which is suitable for integration.

  FIG. 6 is a circuit diagram showing a configuration of a regulator device according to Embodiment 3 of the present invention. This embodiment is an example in which a power transistor, a current monitoring resistor, and a backflow prevention diode, which are conventionally externally mounted, are integrated. The same components as those in the second embodiment are denoted by the same reference numerals, and the portions Will be omitted, and only different parts will be described.

  This embodiment is different from the second embodiment in that a backflow prevention diode that prevents a current from flowing back from the output voltage at the output end through the parasitic circuit of the power transistor when the power supply voltage at the input end is reduced is integrated. It is to have done.

  First, the backflow prevention diode will be described. 7A and 7B are diagrams showing a backflow prevention diode according to Embodiment 3 of the present invention. FIG. 7A is an equivalent circuit thereof, FIG. 7B is a plan view thereof, and FIG. 7C is a sectional view thereof. .

  As shown in FIG. 7A, the backflow prevention diode circuit 41 has a back gate by short-circuiting the gate G4 and the source S4 of the insulated gate field effect transistor M4 in which the back gate B4 for fixing the potential is connected to the source S4. A parasitic diode Dp4 having B4 as an anode and drain D4 as a cathode allows a current to flow from the back gate B4 to the drain D4 via the bulk.

  That is, as shown in FIGS. 7B and 7C, the insulated gate field effect transistor M4 is, for example, a high breakdown voltage n-type MOS transistor or n-type DMOS transistor, and is formed on a substrate, for example, a p-type silicon substrate 42. The p-type silicon substrate 42 is insulated and separated by the formed n-type buried region 43.

  A p-type well region 44 is formed inside the n-type buried region 43. Using the p-type well region 44 surrounded by the n-type buried region 43 as a bulk, a back gate B4, a source S4, a drain D4, and a gate G4 are provided in predetermined regions, respectively, thereby forming a MOS transistor M4.

  The back gate B4, the source S4, the gate G4, and the n-type buried region 43 are connected to the power source Vin, and the drain D4 is connected to the source S1 of the MOS transistor M1.

  Next, the regulator device 31 using the backflow prevention diode circuit 41 will be described. As shown in FIG. 6, the regulator device 31 has a MOS transistor M4 in which the gate G4 and the source S4 are short-circuited and the back gate B4 is connected to the source S4 connected between the input terminal IN and the source S1 of the MOS transistor M1. It is a thing.

  As a result, the reverse current prevention diode circuit 41 can be used up to the same reverse bias voltage as the breakdown voltage BVdss between the drain D4 and the source S4 of the MOS transistor M4.

  Further, a parasitic PNP transistor is formed by the p-type well region 44, the n-type buried region 43, and the p-type silicon substrate 42. However, since the n-type buried region 43 serving as a base layer is thick, the current amplification factor is small. Therefore, even if a large current is passed, the leakage current to the p-type silicon substrate 42 is suppressed, and the wasteful current consumption can be suppressed.

  Further, even if the backflow prevention diode circuit 41 is used, since there is no current monitoring resistor connected in series with the MOS transistor M1, the minimum operating voltage can be made lower than that of the conventional regulator device 201 to which the backflow prevention diode 205 is externally attached. It is.

  As described above, according to the regulator device 31 of this embodiment, the parasitic diode circuit 41 having the back gate of the high breakdown voltage n-type MOS transistor as the anode and the drain as the cathode is integrated as the backflow prevention diode. Sufficient reverse withstand voltage can be obtained, and unnecessary current consumption can be suppressed. Therefore, a small and space-saving regulator device can be provided.

(Modification of Example 3)
FIG. 8 is a circuit diagram showing a configuration of a regulator device according to a modification of the third embodiment of the present invention. In this modification, the same components as those in the third embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

  This modification is different from the third embodiment in that the bipolar transistor for monitoring the drain current of the MOS transistor M1 is integrated in place of the MOS transistor M3.

  That is, as shown in FIG. 8, in the regulator device 51, the emitter E1 is connected to the input terminal IN via the resistor R6, the base B1 is connected to the drain D4 of the MOS transistor M4 of the backflow prevention circuit, and the collector Ct1 is connected to the resistor R4. The bipolar transistor Q1 is grounded via the.

  The bipolar transistor Q1 is, for example, a laterally-structured PNP-type bipolar transistor, and includes a forward voltage Vf of the backflow prevention diode circuit 41, a base-emitter voltage Vbe of the PNP-type bipolar transistor Q1, and a drop voltage ΔV due to an emitter current Ie flowing through the resistor R6. = The operation is performed so that the sum of Ie × R6 is equal.

  The drain current of the MOS transistor M1 and the drain current of the MOS transistor M2 each flow in the backflow prevention diode circuit 41, and most of them are the drain current of the MOS transistor M1. Accordingly, since the forward voltage Vf of the backflow prevention diode circuit 41 is substantially determined by the drain current of the MOS transistor M1, the drain current of the MOS transistor M1 can be monitored by the collector current Ic of the PNP bipolar transistor Q1.

  As described above, according to the regulator device 51 according to the modification of the third embodiment, the PNP bipolar transistor Q1 is integrated so that the drain current of the MOS transistor M1 can be monitored. It is suitable for integration into a chip, for example, a BiCMOS integrated circuit device.

  In the above-described embodiment, the case where the backflow prevention diode circuit 41 is connected to the current mirror circuit 14 having the MOS transistor M1 and the MOS transistor M2 has been described. However, the present invention is not limited to this and any power You may connect to a transistor, for example, a bipolar transistor.

1 is a circuit diagram showing a configuration of a regulator device according to Embodiment 1 of the present invention. The circuit diagram which shows the structure of the current mirror circuit concerning the modification 1 of Example 1 of this invention. The circuit diagram which shows the structure of the current mirror circuit concerning the modification 2 of Example 1 of this invention. The circuit diagram which shows the structure of the regulator apparatus concerning Example 2 of this invention. The circuit diagram which shows the structure of the current mirror circuit concerning the modification of Example 2 of this invention. The circuit diagram which shows the structure of the regulator apparatus concerning Example 3 of this invention. 7A and 7B are diagrams showing a backflow prevention diode circuit according to a third embodiment of the present invention, in which FIG. 7A is an equivalent circuit thereof, FIG. 7B is a plan view thereof, and FIG. The circuit diagram which shows the structure of the regulator apparatus concerning the modification of Example 3 of this invention. The circuit diagram which shows the structure of the conventional regulator apparatus. The circuit diagram which shows the structure of the other conventional regulator apparatus.

Explanation of symbols

11, 21, 31, 51 Regulator device 12 Voltage divider circuit 13 Differential transconductance amplifiers 14, 17, 19, 24, 27 Current mirror circuit 22 Comparator 23 Current limiting circuit 41 Backflow prevention diode circuit 42 p-type silicon substrate 43 n-type Embedded region 44 p-type well regions M1, M2, M3 p-type MOS transistor M4 n-type MOS transistor Q1 PNP-type bipolar transistors R1, R2, R3, R4, R5, R6 resistor C1 capacitor Vin power supply Vbg, Voff reference voltage Dp4 parasitic diode IN input terminal OUT output terminal ZD Zener diode

Claims (10)

A backflow prevention diode circuit having an N-type MOS transistor in which a first gate, a first source, and a first back gate are connected in common;
Is connected to a power input from the first external via the drain of the second source is the blocking diode circuit, the first and the P-type MOS transistor in which the second drain is connected to the output terminal, the third connected gates, and the third source of the second gate and a second source of the first P-type MOS transistor, a second P of the third drain and the third gate is short-circuited A first current mirror circuit composed of a type MOS transistor;
The second P-type MOS transistor, a third P-type MOS transistor having a fourth gate and a fourth source of which are connected respectively to the third gate and a third source of said second P-type MOS transistor A second current mirror circuit comprising:
Feedback control means for dividing the output voltage of the output terminal and comparing it with a predetermined first reference voltage and inputting an output proportional to the difference to the second P-type MOS transistor;
The output of the third P-type MOS transistor constituting the second current mirror circuit is converted into a voltage and compared with a predetermined second reference voltage, and the converted voltage is compared with the second reference voltage. Current limiting means for limiting the output of the feedback control means, if larger,
Comprising
Regulator apparatus characterized by monitoring the drain current of the first P-type MOS transistor by the mirror ratio of the second current mirror circuit, for limiting the drain current of the first P-type MOS transistor. The feedback control means is provided with the predetermined first reference voltage as one input, the divided voltage of the output terminal as the other input, and outputs the output to the second P-type MOS transistor. It consists of a differential transconductance amplifier to input,
The current limiting means is provided with the predetermined second reference voltage as one input, the output of the third P-type MOS transistor as the other input, and the output as the differential transconductance amplifier The regulator device according to claim 1, further comprising a comparator that inputs to the input. To claim 1 or claim 2, characterized in that the fourth source of the third source and the third P-type MOS transistor of the second P-type MOS transistor is connected via a resistor The regulator apparatus as described. First gate, a blocking diode circuit having an N-type MOS transistor having a first source, and a first back gate are commonly connected,
Is connected to a power input from the first external via the drain of the second source is the blocking diode circuit, the first and the P-type MOS transistor in which the second drain is connected to the output terminal, the third connected gates, and the third source of the second gate and a second source of the first P-type MOS transistor, a second P of the third drain and the third gate is short-circuited A first current mirror circuit composed of a type MOS transistor;
The output voltage at the output terminal is divided and compared with a predetermined first reference voltage, and an output proportional to the difference is fed back to the second P-type MOS transistor constituting the first current mirror circuit. Control means;
A bipolar transistor having an emitter connected to the input terminal directly or through a resistor, and a base connected to a first drain of the backflow prevention diode circuit;
The output of the bipolar transistor is converted into a voltage and compared with a predetermined second reference voltage, and when the converted voltage is larger than the predetermined second reference voltage, the output of the feedback control means is limited. Current limiting means;
The regulator apparatus characterized by having. The feedback control means is provided with the predetermined first reference voltage as one input, the divided voltage of the output terminal as the other input, and outputs the output to the second P-type MOS transistor. It consists of a differential transconductance amplifier to input,
The current limiting means is provided with a comparator that receives the predetermined second reference voltage as one input, receives the output of the bipolar transistor as the other input, and inputs the output to the differential transconductance amplifier. The regulator device according to claim 4 , wherein the regulator device is provided. Has a resistance element, one end of the resistance element is connected to the common connection of the third gate of the second gate and the second P-type MOS transistor of the first P-type MOS transistor, the resistor and the other end of the element is connected to the common connection between the third source of the second source and said second P-type MOS transistor of the first P-type MOS transistor, according to claim The regulator apparatus of any one of Claim 1 or Claim 4 . Has a Zener diode, one end of the Zener diode is connected to the common connection between the third gate of the second gate and the second P-type MOS transistor of the first P-type MOS transistor, the Zener and the other end of the diode is connected to the common connection between the third source of the second source and said second P-type MOS transistor of the first P-type MOS transistor, according to claim The regulator apparatus of any one of Claim 1 or Claim 4 . A resistor element and a Zener diode, wherein the resistor element and the Zener diode are connected in parallel, and one end of a common connection point of the resistor element and the Zener diode is a second gate of the first P-type MOS transistor; the second is connected to the common connection between the third gate of the P-type MOS transistor, a second source common connecting point and the other end of the first P-type MOS transistor of said resistance element and said Zener diode and characterized in that it is connected to the common connection between the third source of the second P-type MOS transistor, the regulator device according to any one of claims 1 or claim 4. The N-type MOS transistor is formed on an n-type buried region formed on a p-type semiconductor substrate and further on a p-type well region formed inside the n-type buried region,
The blocking diode circuit, said to the back gate of the N-type MOS transistor and an anode, wherein the N-type MOS transistor the drain of the parasitic diode to the cathode of the drain through the p-type well region from the back gate regulator device according to claim 1 or claim 4, characterized in that the flow a current to. 5. The regulator device according to claim 1, wherein the N-type MOS transistor is a high breakdown voltage N-type MOS transistor or an N-type DMOS transistor.

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