JP4462663B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a plurality of memory blocks arranged in a matrix.
[0002]
[Prior art]
FIG. 20 shows a main part of a memory mat of a conventional dynamic random access memory (hereinafter referred to as DRAM). Referring to FIG. 20, the memory mat includes a plurality (16 in the figure) of memory blocks M11 to M44 arranged in a plurality of rows and a plurality of columns (in the figure, 4 rows and 4 columns).
[0003]
Two sets of global IO line pairs GIOP1, GIOP2 and GIOP3, GIOP4 are arranged on both sides of each of memory block columns M11 to M41;... M14 to M44. Each global IO line pair GIOP is shared by four memory blocks in the same column.
[0004]
Two sets of local IO line pairs LIOP1, LIOP2 and LIOP3, LIOP4 are alternately arranged between the upper and lower sides and between each of first memory block columns M11-M41. In the figure, a local IO line pair LIOP between two memory blocks adjacent in the vertical direction is shared by two memory blocks adjacent in the vertical direction. The same applies to the other memory block columns.
[0005]
Block selection switches BS (indicated by □ in the figure) are arranged at the intersections of GIOP1 and LIOP3, GIOP2 and LIOP4, GIOP3 and LIOP1, and GIOP4 and LIOP2.
[0006]
Any one of the four memory block rows (for example, M31 to M34), and odd or even numbered block columns (for example, M11 to M41 and M13 to M43) of the four memory block columns; Are selected, and the four block selection switches BS at the upper right and lower left of each of the two memory blocks (in this case, M31 and M33) located at the intersection between them are turned on. In each of memory blocks M31 and M33, 4-bit data can be read / written.
[0007]
FIG. 21 shows a main part of a memory mat of another conventional DRAM. Referring to FIG. 21, the memory mat includes 16 memory blocks M11 to M44 arranged in 4 rows and 4 columns, as in the DRAM of FIG.
[0008]
Two sets of global IO line pairs GIOP1, GIOP2 and GIOP3, GIOP4 are alternately arranged between the left and right sides of each of the four memory block rows M11 to M41;. Global IO line pair GIOP1, GIOP2 is shared by the block columns on both sides. Global IO line pairs GIOP3 and GIOP4 are shared by blocks in the same column.
[0009]
Two sets of local IO line pairs LIOP1, LIOP2 and LIOP3, LIOP4 are alternately arranged between the upper and lower sides of the four central memory block rows M12, M13;. Block selection switches BS are arranged at the intersections of GIOP1 and LIOP4, GIOP2 and LIOP1, GIOP3 and LIOP2, and GIOP4 and LIOP3. In the vertical and horizontal directions, the local IO line pairs LIOP1 to LIOP4 and the block selection switch BS are arranged with the same cycle.
[0010]
Similarly to the DRAM of FIG. 20, for example, when memory blocks M31 and M33 are selected, each of memory blocks M31 and M33 is connected to global IO line pairs GIOP1 to GIOP1 through local IO line pairs LIOP1 to LIPO4 and block selection switch BS. Connected to GIOP4. Thus, 4-bit data can be read / written in each of the memory blocks M31 and M33.
[0011]
[Problems to be solved by the invention]
However, the DRAM of FIG. 20 has a problem that the area penalty is large because four global IO line pairs GIOP are provided between two adjacent memory block columns. In each read / write cycle, half of the entire local IO line pair LIOP and global IO line pair GIOP are not used, and the local IO line pair LIOP and global IO line pair GIOP are not effectively utilized. It was.
[0012]
On the other hand, in the DRAM of FIG. 21, since two sets of global IO line pairs GIOP are provided between two adjacent memory blocks, the problem of the DRAM of FIG. 20 is solved. However, there are cases where the block selection switch BS is located at the center of the local IO line pair LIOP and cases where the block selection switch BS is located at the end of the local IO line pair LIOP. There is a problem that the route becomes long and the data transfer speed becomes slow.
[0013]
Therefore, a main object of the present invention is to provide a semiconductor memory device having a small area penalty and capable of high-speed data transfer.
[0014]
[Means for Solving the Problems]
  thisinventionSemiconductor memory device according toIs a semiconductor memory device having a plurality of memory blocks arranged in a matrix,~First4First global IO line pair, first~First4First local IO line pair, first~First4Switch means, row selection means, column selection means, control means, and data input / output means. The first and second global IO line pairs are:N-th column (where N is a natural number) memory block column and N + 1-th columnMemory block sequenceWithIt is provided in the area between.The third and fourth global IO line pairs are provided in an area between the memory block column of the (N + 1) th column and the memory block column of the (N + 2) th column.The first local IO line pair isM-th memory block row (where M is a natural number) and M + 1-th rowMemory block rowsWithBetween the Nth andThe memory block of the Mth row in the number column,N + 1The Mth row in the columnMemory blockA memory block of the (M + 1) th row in the Nth column, a memory block of the (M + 1) th row in the (N + 1) th column, andAre provided in common. The second local IO line pair isM-th memory block row and M + 1-th rowMemory block rowsWithBetween the N + 1thThe memory block of the Mth row in the number column,N + 2 columnAt line MMemory blockA memory block in the (M + 1) th row in the (N + 1) th column, a memory block in the (M + 1) th row in the (N + 2) th column, andAre provided in common.The third local IO line pair is provided in an area between the memory block row of the (M + 1) th row and the memory block row of the (M + 2) th row, and the memory of the (M + 1) th row in the Nth column. A memory block in the (M + 1) th row in the (N + 1) th column, a memory block in the (M + 2) th row in the Nth column, a memory block in the (M + 2) th row in the (N + 1) th column, Are provided in common. The fourth local IO line pair is provided in an area between the memory block row of the (M + 1) th row and the memory block row of the (M + 2) th row, and the memory of the (M + 1) th row in the (N + 1) th column. A memory block in the (M + 2) th row in the (N + 2) th column, a memory block in the (M + 2) th row in the (N + 1) th column, and a memory block in the (M + 2) th row in the (N + 2) th column. Are provided in common.The first switch means, FirstLocal IO linePair andProvided at each intersection of the first global IO line pair. The second switch meansThe second2 local IO linesPair andFirst3Provided at each intersection with global IO line pairBe.The third switch means is provided at each intersection of the third local IO line pair and the second global IO line pair. The fourth switch means is provided at each intersection of the fourth local IO line pair and the fourth global IO line pair.The row selection means selects any one of the plurality of memory block rows according to the row address signal. The column selection means selects any one of the plurality of memory block columns according to the column address signal. The control means is the first~First4By controlling the switch means, the row selection means and the column selection meansThe memory block in the (M + 1) th row in the (N + 1) th column ischosenIn case,First1'sLocal IO line pairAnd firstGlobal IO line pair, Second local IO line and third global IO line, third local IO line and second global IO line, fourth local IO line and fourth global IO lineTheRespectivelyCombine. The data input / output means is the first~First4Are connected to the global IO line pair for data input / output.
[0015]
  Preferably,The first switch means1'sA pair of transfer gates connected between the central portion of the local IO line pair and the first global IO line pair is included. The second switch meansThe secondThe central part of the second local IO line pair and the second3A pair of transfer gates connected between the pair of global IO lines.The third switch means includes a pair of transfer gates connected between the central portion of the third local IO line pair and the second global IO line pair. The fourth switch means includes a pair of transfer gates connected between the central portion of the fourth local IO line pair and the fourth global IO line pair.
[0016]
  Also preferably,The first switch means is the firstNoAn amplifier that amplifies the potential difference of the local IO line pair and applies it to the first global IO line pair. The second switch meansThe secondAn amplifier that amplifies the potential difference between the two local IO line pairs and applies the amplified difference to the second global IO line pair.The third switch means includes an amplifier that amplifies the potential difference of the third local IO line pair and applies it to the second global IO line pair. The fourth switch means includes an amplifier that amplifies the potential difference of the fourth local IO line pair and applies it to the fourth global IO line pair.
[0017]
  Also preferablyFurthermore, the first local IO line pairInFirst5And second6Switch meansButFirst1Switch meansSandwiched betweenA second local IO line pair providedInFirst7And second8Switch meansButFirst2Switch meansSandwiched betweenProvided.The third local IO line pair is provided with ninth and tenth switch means with the third switch means in between, and the fourth local IO line pair has eleventh and twelfth switch means. Is provided with a fourth switch means in between.The control means further includes5First12The first switch means to control the first~First4Of the local IO line pair corresponding to the memory block selected by the row selecting means and the column selecting meansCorresponding to eachFirst~First4The first global IO line pair is coupled to the first~First4Other parts of the local IO line pairCorresponding to eachFirst~First4Disconnect the global IO line pair.
[0018]
  Also preferably,Each memory blockMultiple rows multiple columnsA plurality of memory cells arranged in aMultiple eachProvided for each rowpluralWord lines, andMultiple eachProvided for each columnMultipleIncludes bit line pairs.The plurality of bit line pairs are divided into a plurality of bit line pair groups each including four bit line pairs.The semiconductor memory device further includesProvided corresponding to each memory block columnBelongs to memory block columnpluralCommon to memory blocksAnd a plurality of column selection lines for selecting any one of the plurality of bit line pair groups in each corresponding memory block.TheAt least one of the plurality of column selection linesThe column selection line isUsed as a spare column selection line for replacement with a defective column selection line. The semiconductor memory device further includesProvided corresponding to each spare column selection line, NoThe column address signal assigned to the good column selection line is programmed, and the corresponding spare column selection line is selected in response to the match between the input address signal and the programmed column address signal.With address comparator. The column selection means further selects any column selection line other than the defective column selection line programmed in the address comparator among the plurality of column selection lines corresponding to the selected memory block column. The row selection means further includes a spare column selection line or a column selection line selected by the address comparator or the column selection means in the selected memory block row.Multiple word linesSelect one of the word lines. The control means further includes a bit line pair group corresponding to the spare column selection line or the column selection line selected by the address comparator or the column selection means.4 bit line pairsAnd the word line selected by the row selection meansFourFirst corresponding memory cell~First4To the local IO line pair.
[0019]
  Also preferably,Each address comparator is programmed with a column address signal of a defective column selection line belonging to the memory block column to which the corresponding spare column selection line belongs.
[0020]
  Also preferably,The column selection means selects one of a plurality of odd-numbered memory block columns and a plurality of even-numbered memory block columns. Each address comparator is programmed with a column address signal of a memory block column to which a corresponding spare column selection line belongs or a defective column selection line belonging to a memory block column adjacent to the memory block column. Each address comparator is provided in common to a plurality of odd-numbered memory block columns or a plurality of even-numbered memory block columns.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
FIG. 1 is a block diagram showing the overall structure of a DRAM according to the first embodiment of the present invention. Referring to FIG. 1, this DRAM includes a clock generation circuit 1, a row and column address buffer 2, a row decoder 3, a column decoder 4, a memory mat 5, an input buffer 8 and an output buffer 9, and the memory mat 5 is a memory. An array 6 and a sense amplifier + input / output control circuit 7 are included.
[0025]
Clock generation circuit 1 selects a predetermined operation mode based on control signals / RAS, / CAS, / W given from the outside, and controls the entire DRAM.
[0026]
Row and column address buffer 2 generates row address signals RA0 to RAi and column address signals CA0 to CAi based on externally applied address signals A0 to Ai (where i is an integer of 0 or more). Signals RA0-RAi and CA0-CAi are applied to row decoder 3 and column decoder 4, respectively.
[0027]
Memory array 6 includes a plurality of memory cells each storing 1-bit data. Each memory cell is arranged at a predetermined address determined by a row address and a column address.
[0028]
Row decoder 3 designates a row address of memory array 6 in response to row address signals RA0-RAi applied from row and column address buffer 2. Column decoder 4 designates a column address of memory array 6 in response to column address signals CA0-CAi applied from row and column address buffer 2.
[0029]
Sense amplifier + input / output control circuit 7 connects a memory cell at an address designated by row decoder 3 and column decoder 4 to one end of global IO line pair GIOP. The other end of global IO line pair GIOP is connected to input buffer 8 and output buffer 9. Input buffer 8 selected externally input data Dj (where j is an integer of 0 or more) via global IO line pair GIOP in response to control signal / W in the write mode. Give to memory cell. Output buffer 9 outputs the read data Dj from the selected memory cell to the outside in response to control signal / OE input from the outside in the read mode.
[0030]
FIG. 2 is a diagram showing a chip layout of the DRAM shown in FIG. Referring to FIG. 2, memory mat 5 is divided into four rectangular memory mats 5a-5d. The memory mats 5a to 5d are arranged at the four corners of the rectangular semiconductor substrate 10, respectively. The row decoder 3 is divided into four row decoders 3a to 3d, and the row decoders 3a to 3d are arranged along the long sides on the chip center side of the memory mats 5a to 5d, respectively. The column decoder 4 is divided into four column decoders 4a to 4d, and the column decoders 4a to 4d are arranged along the short sides on the chip center side of the memory mats 5a to 5d, respectively.
[0031]
The clock generation circuit 1, the row and column address buffer 2, the input buffer 8, and the output buffer 9 of FIG. 1 are arranged in the peripheral circuit region 11 in the center of the chip.
[0032]
In each of memory mats 5a to 5d, a column selection line CSL and a global IO line pair GIOP extending in the same direction as the long side of the memory mat, and a main word line MWL extending in the same direction as the short side of the memory mat are arranged. The
[0033]
FIG. 3 is an enlarged view of a portion X in FIG. Referring to FIG. 3, memory mat 5a includes a plurality (16 in the figure) of memory blocks M11 to M44 arranged in a plurality of rows and a plurality of columns (in the figure, 4 rows and 4 columns).
[0034]
Four sets of global IO lines GIOP1, GIOP2 and GIOP3, GIOP4 are alternately arranged between the left and right sides and between each of the four memory block columns M11 to M41; The global IO line pair GIOP is shared by two memory block columns on both the left and right sides.
[0035]
Local IO line pairs LIOP1 and LIOP3 are alternately arranged between the upper and lower sides of the four central memory block rows M12, M13;. Local memory line pairs LIOP2 and LIOP4 are alternately arranged between the upper and lower sides of the four left memory block rows M11, M12;. Local memory line pairs LIOP2 and LIOP4 are alternately arranged between the upper and lower sides of the four right memory block rows M13, M12;. That is, the local IO line pairs LIOP1 and LIOP2 and LIOP3 and LIOP4 have a so-called nested structure. The local IO line pair LIOP is shared by two memory blocks on both the upper and lower sides.
[0036]
Block selection switches BS are arranged at the intersections of GIOP1 and LIOP3, GIOP2 and LIOP1, GIOP3 and LIOP4, and GIOP4 and LIOP2. Also in the vertical and horizontal directions, global IO line pairs GIOP1 to GIOP4, local IO line pairs LIOP1 to LIOP4, and block selection switch BS are arranged with the same cycle.
[0037]
Any one of the four memory block rows (for example, M31 to M34) and odd or even numbered memory block columns (for example, M11 to M41 and M13 to M43) of the four memory block columns Are selected, and the four block selection switches BS around each of the two memory blocks (in this case, M31 and M33) located at the intersection thereof are turned on. In each of memory blocks M31 and M33, 4-bit data can be read / written.
[0038]
FIG. 4 is an enlarged view of a Y portion in FIG. Referring to FIG. 4, this memory mat has a so-called alternate shared sense amplifier configuration. That is, the sense amplifier SA shared by the memory blocks M23 and M33 is arranged between the memory blocks M23 and M33, and the sense amplifier SA shared by the memory blocks M33 and M43 is arranged between the memory blocks M33 and M43. .
[0039]
The sense amplifier SA between the memory blocks M23 and M33 is provided corresponding to the odd-numbered bit line pair BLP of the memory blocks M223 and M33, and the sense amplifier SA between the memory blocks M33 and M43 is provided for the memory blocks M33 and M43. It is provided corresponding to even-numbered bit line pairs BLP.
[0040]
For example, when the memory block M33 is selected, each sense amplifier SA is connected to a corresponding bit line pair BLP of the memory block M33 as shown in FIG. Four selected sense amplifiers SA in memory block M33 are connected to local IO line pairs LIOP1 to LIOP4, respectively, and further connected to global IO line pairs GIOP1 to GIOP4 via four block selection switches BS.
[0041]
FIG. 5 is a diagram showing in detail a portion related to odd-numbered bit line pair BL, / BL of memory block M33 shown in FIG. Referring to FIG. 5, memory block M33 includes a plurality of memory cells MC arranged in a matrix, sub-word lines SWL provided corresponding to each row, and bit lines provided corresponding to each column. The pair BL, / BL is included. Memory cell MC is a well-known one including an information storage capacitor and an access N-channel MOS transistor.
[0042]
Corresponding to the memory block M33, the sub word driver 12 is provided in an area between the adjacent memory block M32. The sub word driver 12 is activated in response to the selection of the column selection line CSL corresponding to the corresponding memory block M33, and sets the sub word line SWL in the same row as the main word line MWL selected by the row decoder 3a. The selected level is set to “H” level.
[0043]
A transfer gate 13 is provided between the bit line pair BL, / BL and the sense amplifier SA. Transfer gate 13 includes a plurality of N-channel MOS transistors. Each N channel MOS transistor is connected between a bit line and a sense amplifier, and its gate receives signal φ33. When the memory block M33 is selected, the signal φ33 becomes “H” level and the transfer gate 13 becomes conductive, and the bit line pair BL, / BL of the memory block M33 and the sense amplifier SA are coupled.
[0044]
Two sense amplifiers SA are grouped in advance, and each group of sense amplifiers SA is connected to a local IO line pair LIO1, / LIO1 or LIO2, / LIO2 via a column selection gate CSG. Column select gate CSG includes four N-channel MOS transistors. Each N channel MOS transistor is connected between sense amplifier SA and a local IO line, and its gate is connected to a corresponding column selection line CSL. When the corresponding column selection line CSL becomes the “H” level of the selection level, the column selection gate CSG is turned on and the sense amplifier SA is connected to the local IO line pair.
[0045]
As shown in FIG. 6, the block selection switch BS includes transfer gates 14 and 15 and an inverter 16. Transfer gates 14 and 15 are connected between global IO lines GIO and / GIO and local IO lines LIO and / LIO, respectively. Block selection signal φB is input to the gates of transfer gates 14 and 15 on the P-channel MOS transistor side via inverter 16 and directly input to the gates of transfer gates 14 and 15 on the N-channel MOS transistor side. Each block selection switch BS is assigned a unique block selection signal φB in advance. Block selection signal φB is generated based on the address signal. When block select signal φB attains the “H” level of the activation level, transfer gates 14 and 15 are turned on to couple local IO line pair LIO, / LIO and global IO lines GIO, / GIO.
[0046]
Next, the operation of the DRAM shown in FIGS. 1 to 6 will be described. In the write mode, the group column selection line SCL corresponding to the column address signals CA0 to CAi is raised to the “H” level of the selection level by the column decoder 4, and the column selection gate CSG of the group is turned on.
[0047]
Next, the write data applied through input buffer 8 is applied to bit line pair BL, / BL of the selected group through global IO line pair GIOP, block select line switch BS and local IO line pair LIOP. . Next, sub word line SWL corresponding to row address signals RA0-RAi is raised to "H" level of the selection level by row decoder 3 and sub word driver 12, and memory cell MC corresponding to sub word line SWL is activated. It becomes. In the activated memory cell MC, the data of the corresponding bit lines BL and / BL are written in the form of charge.
[0048]
In the read mode, after the potentials between the bit line pairs BL and / BL are equalized, the sub word line SWL corresponding to the row address signals RA0 to RAi is selected by the row decoder 3 and the sub word driver 12 at the selection level “H”. To the level. The potentials of the bit lines BL and / BL change by a minute amount according to the data of the activated memory cell MC. Next, the sense amplifier SA is activated, and the bit line with the higher potential of the bit lines BL and / BL is pulled up to the power supply potential VCC, and the other bit line is pulled down to the ground potential GND.
[0049]
Next, the column selection line CSL of the group corresponding to the column address signals CA0 to CAi is raised to the “H” level of the selection level by the column decoder 4, and the column selection gate CSG of that group is turned on. Data of the bit line pair BL, / BL of the selected group is applied to the output buffer 9 via the column selection gate CSG, the local IO line pair LIOP, the block selection switch BS, and the global IO line pair GIOP. Output buffer 9 outputs read data applied through global IO line pair GIOP to the outside.
[0050]
In this embodiment, two sets of global IO line pairs GIOP are arranged between two adjacent memory block columns, and local IO lines having a length equivalent to two memory blocks are arranged between two adjacent memory block rows. The pairs LIOP are arranged in a nested structure, and a block selection switch BS is provided at the intersection between the central portion of each local IO line pair LIOP and the global IO line pair GIOP. Therefore, the area penalty is smaller than that of the conventional example 1 in which four sets of global IO line pairs GIOP are provided between each of a plurality of memory block columns, and the end or center of the local IO line pair LIOP is reduced. Thus, the data transfer speed can be increased compared to the conventional example 2 in which the block selection switch is arranged.
[0051]
(Modification 1)
FIG. 7 is a circuit diagram showing a DRAM block selection switch BS and its peripheral circuit according to the first modification of the first embodiment. Referring to FIG. 7, block select switch BS includes N channel MOS transistors 21-27.
[0052]
N channel MOS transistors 21 and 22 are connected between global IO lines GIO and / GIO and local I / O lines LIO and / LIO, respectively, and each gate receives block select signal φBw. When block selection signal φBw attains the “H” level of the activation level in the write mode, N channel MOS transistors 21 and 22 are turned on, and global IO lines GIO and / GIO and local I / O lines LIO and / LIO are connected. Combined.
[0053]
N channel MOS transistors 23, 24 and 25, 26 are connected in series between global IO lines GIO, / GIO and node N27, respectively. N channel MOS transistor 27 is connected between node N27 and a line of ground potential GND. The gates of N channel MOS transistors 23, 25 and 27 receive block selection signal φBr, and the gates of N channel MOS transistors 24 and 26 are connected to local IO lines LIO and / LIO, respectively. Block selection signal φBr attains the “H” level of the activation level in the read mode. The operation of this part will be described later.
[0054]
An equalizer 28 is provided on the local I / O lines LIO and / LIO. Equalizer 28 includes P channel MOS transistors 29-31. P channel MOS transistor 29 is connected between local IO lines LIO and / LIO. P channel MOS transistors 30 and 31 are connected between local IO lines LIO and / LIO and a power supply potential VCC line, respectively. The gates of P channel MOS transistors 29-31 receive equalize signal LIOEQ. When equalize signal LIOEQ attains the “L” level of the activation level, P channel MOS transistors 29-31 are rendered conductive, and local I / O lines LIO and / LIO are equalized to power supply potential VCC.
[0055]
An equalizer 32 is provided in the global IO line pair GIO, / GIO. Equalizer 32 includes P channel MOS transistors 33-35. P channel MOS transistor 33 is connected between global IO lines GIO and / GIO. P-channel MOS transistors 34 and 35 are connected between global IO lines GIO and / GIO and the power supply potential VCC line, respectively. The gates of P channel MOS transistors 33-35 receive equalize signal GIOEQ. When equalize signal GIOEQ attains the “L” level of the activation level, P channel MOS transistors 33-35 are rendered conductive, and global IO lines GIO and / GIO are equalized to power supply potential VCC.
[0056]
Charging circuit 36 is provided for global IO line pair GIO, / GIO. Charging circuit 36 includes P channel MOS transistors 37 and 38 having a relatively small gate width. P-channel MOS transistors 37 and 38 are connected between global IO lines GIO and / GIO and the power supply potential VCC line, respectively, and each gate receives signal CLP. When signal CLP attains the “L” level of the activation level, P channel MOS transistors 37 and 38 are rendered conductive and global IO lines GIO and / GIO are charged to power supply potential VCC.
[0057]
Next, the operation of the circuit shown in FIG. 7 will be described. In write mode, local IO lines LIO, / LIO and global IO line pair GIO, / GIO are equalized to "H" level (power supply potential VCC) by equalizers 28, 32, and then block selection signal φBw is activated. At the “H” level, global IO line pair GIO, / GIO and local IO line pair LIO, / LIO are coupled.
[0058]
Next, input buffer 8 lowers one of global IO lines GIO and / GIO to "L" level in accordance with the write data. Thus, the write data is applied to the selected memory cell MC via the global IO line pair GIO, / GIO and the local IO line pair LIO, / LIO.
[0059]
In the read mode, as shown in FIG. 8, signal CLP is fixed at “L” level, and global IO lines GIO, / GIO are charged to “H” level by a minute current. The equalizers 28 and 32 equalize the local IO line pair LIO and / LIO and the global IO line pair IO and / GIO to the “H” level, and then the equalize signals LIOEQ and GIOEQ are set to the “H” level which is the inactivation level. And equalization is stopped.
[0060]
Next, at time t0, the selected column selection line CSL is raised to the “H” level of the activation level, and the potential of one of the local IO lines LIO and / LIO (/ LIO in the figure) in the read data gradually increases. Descend.
Next, at time t1, block selection signal φBr is raised to the “L” level of the activation level. As a result, the N-channel MOS transistors 23, 25 and 27 of the block switch BS become conductive. At this time, the potential of the local IO line / LIO is lower than the potential of the local IO line LIO, and the N channel MOS transistor 26 has a higher resistance than the N channel MOS transistor 24. Therefore, the potential of the global IO line GIO gradually increases. To descend. Data is read when the potential difference between global IO lines GIO and / GIO reaches a predetermined value. At time t2, block selection signal φBr becomes “L” level, which is a non-selection level, and equalization signals LIOEQ, GIOEQ are activated levels “ At the “L” level, data reading ends.
[0061]
The read data is inverted when transmitted from the local IO line pair LIO, / LIO to the global IO line pair GIO, / GIO. This data is inverted again by an inversion circuit (not shown) and then output to the outside. The
[0062]
In this embodiment, since there is no need to drive the global IO line pair GIO, / GIO by the sense amplifier SA, the drive capability of the sense amplifier SA can be small.
[0063]
(Modification 2)
FIG. 9 is a block diagram showing a redundant configuration of the DRAM according to the second modification of the first embodiment. Referring to FIG. 9, in this DRAM, a plurality (two in the figure) of spare column selection lines SCSL are provided for each memory block column, and corresponding to each spare column selection line SCSL of each memory block column. An address comparator 40 is provided, and column decoder blocks DB1 to DB4 are provided corresponding to the four block columns, respectively. The defective column selection line CSL is replaced with a spare column selection line SCSL in the same memory block column.
[0064]
The address comparator 40 is programmed with a column address signal of a defective column selection line CSL (marked with x in the figure) of the corresponding memory block column. In FIG. 9, the column selection line CSL0 of the first memory block column, the column selection lines CSL1 and CSL2 of the second memory block column, the column selection line CSL3 of the third memory block column, and the column selection line CSL4 of the fourth memory block column An example in which the column address signal is programmed is shown. The address comparator 40 receives the column address signals CA0 to CAi, and responds to the corresponding column column signals CA0 to CAi corresponding to the programmed column address signal of the defective column selection line CSL in accordance with the corresponding spare column selection line. SCSL is raised to the “H” level of the selected level.
[0065]
The column decoder block DB receives the column address signals CA0 to CAi and selects the column selection line CSL corresponding to the column address signals CA0 to CAi. When the spare column selection line SCSL of the corresponding memory block is raised to the “H” level of the selection level, the column decoder block DB removes the defective column selection line CSL replaced by the spare column selection line SCSL. The selection level is fixed to the “L” level.
[0066]
(Modification 3)
FIG. 10 is a block diagram showing a redundant configuration of the DRAM according to the third modification of the first embodiment. Referring to FIG. 10, in this DRAM, a plurality of spare column selection lines SCSL are provided for each memory block column (four in the figure), and four spare column selections of the first and third block columns are selected. Four address comparators 41 are provided in common to the line SCSL, and four address comparators 41 are provided in common to the four spare column selection lines SCSL of the second and fourth block columns, corresponding to the four memory block columns. Thus, four column decoder blocks DB1 to DB4 are provided.
[0067]
In this DRAM, the defective column selection line CSL is replaced with a spare column selection line SCSL in the same memory block or an adjacent memory block. Although up to eight defective column selection lines CSL can be replaced in two memory blocks, each memory block cannot be programmed independently, and simultaneous replacement is performed in units of two memory blocks.
[0068]
The reason for simultaneous replacement in this manner is that when data reading / writing is performed in two adjacent memory block columns, data collision occurs in global IO line pair GIOP between the two memory block columns. It is.
[0069]
The address comparator 41 is programmed with a column address signal of the defective column selection line CSL of the corresponding memory block column. FIG. 9 shows an example in which the column selection lines CSL0 and CSL1 of the second memory block column, the column selection line CSL2 of the third memory block column, and the column selection line CSL3 of the fourth memory block column are programmed. The address comparator 41 receives the column address signals CA0 to CAi, and two corresponding spares in response to the input column address signals CA0 to CAi and the column address signal of the programmed defective column selection line CSL matching. Column select line SCSL is raised to the “H” level of the activation level.
[0070]
The column decoder block DB receives the column address signals CA0 to CAi and selects the column selection line CSL corresponding to the column address signals CA0 to CAi. In addition, when the spare column selection line SCSL is selected, the column decoder block DB fixes the defective column selection line CSL replaced with the spare column selection line SCSL to the “L” level of the inactivation level.
[0071]
In this DRAM, the defective column selection line CSL is replaced with a spare column selection line CSL in the same memory block column or in an adjacent memory block column. Up to eight defective column select lines CSL can be replaced with spare column select lines SCSL in two memory block columns, but each memory block column cannot be programmed independently and replaced with two block columns simultaneously. The When spare column select line SCSL hits, replaced normal column select line CSL is inactivated.
[0072]
[Embodiment 2]
FIG. 11 is a diagram showing a main part of a memory mat of a DRAM according to the second embodiment of the present invention, which is compared with FIG. Referring to FIG. 11, this DRAM is different from the DRAM of FIG. 3 in that each local IO line pair LIOP is provided with a block selection switch BS '(indicated by a circle in the figure) on both sides of block selection switch BS. Is a point. FIG. 11 shows a total of eight block selection switches BS ′, one on each side of each memory block column. Eight columns of block selection switches BS ′ are controlled by signals φa to φh, respectively.
[0073]
For example, in the region between the first and second memory block columns, as shown in FIG. 12, for example, local IO line pair LIO2, / LIO2 is disconnected at two locations near one side and the other side of block selection switch BS. Is done. Block selection switch BS ′ includes a pair of N-channel MOS transistors 43 and 44. N channel MOS transistors 43 and 44 are respectively connected between disconnected local IO lines LIO2 and LIO2, / LIO2 and / LIO2. Gates of N channel MOS transistors 43 and 44 included in block selection switch BS ′ on one side of block selection switch BS receive signal φb. The gates of N channel MOS transistors 43 and 44 included in block select switch BS ′ on the other side of block select switch BS receive signal φc. The same applies to the other block selection switches BS ′.
[0074]
FIG. 13 is a time chart showing the operation of the DRAM shown in FIG. When the column selection line CSL corresponding to the odd-numbered memory block column becomes the selection level “H” level, the signals φa, φb, φe, φf are maintained at the “H” level, and the signals φc, φd, φg , Φh are at “L” level. Block selection switches BS ′ corresponding to signals φa, φb, φe, and φf are turned on, and block selection switches BS ′ corresponding to signals φc, φd, φg, and φh are turned off. As a result, the unnecessary portion of the local IO line pair LIOP in the current read / write cycle is disconnected from the block selection switch BS and the global IO line pair GIOP. For this reason, the capacity of the local IO line pair LIOP is halved, and the data transfer speed is further increased.
[0075]
In this embodiment, the signals φa to φh are normally maintained at the “H” level, but as shown in FIG. 14, φa to φh are normally maintained at the “L” level. Needless to say.
[0076]
[Embodiment 3]
FIG. 15 is a diagram showing a main part of a memory mat of a DRAM according to the third embodiment of the present invention, which is compared with FIG.
[0077]
Referring to FIG. 15, this DRAM is different from the DRAM of FIG. 11 in that a plurality of (two in the figure) spare column selection lines SCSL are provided in each memory block column, and a local IO line pair. Two local IO line pairs LIOP1 and LIOP1, LIOP2 and LIOP2, LIOP3 and LIOP3, and LIOP4 and LIOP4 adjacent to each other in the extending direction of the LIOP are smaller than the block selection switch BS ″ (smaller than BS ′ in the figure). 15, a total of three block selection switches BS ″ are shown, one in each of the four memory block columns. The three rows of block selection switches BS ″ are controlled by signals φi to φh, respectively.
[0078]
As shown in FIG. 16, block select switch BS ″ between the first and second memory block columns includes a pair of N channel MOS transistors 45 and 46. N channel MOS transistors 45 and 46 are, for example, local IOs. Lines LIO1 and / LIO1 are connected between one end of local IO lines LIO1 and / LIO1 adjacent in the extending direction thereof, and each gate receives signal φi, and signal φi is at an activation level. N level MOS transistors 45 and 46 are rendered conductive, and two local IO line pairs LIOP1 are connected to each other. The same applies to the other block selection switches BS ″.
[0079]
FIG. 17 is a time chart showing the operation of the DRAM shown in FIG. FIG. 17 shows a case where the normal column selection line CSL1 of the first memory block column and the normal column selection line CSL2 of the third memory block column are simultaneously selected. In this case, only the signals φa, φb, φe, and φf among the signals φa to φh become the “H” level of the activation level. As a result, the block selection switch BS ′ on both sides of the first memory block column and the block selection switch BS ′ on both sides of the third memory block column are conducted, and data is read to the left eight global IO line pairs GIOP. . In FIG. 17, signals read to 10 global IO line pairs GIOP in FIG. 15 are indicated by A to J, respectively.
[0080]
FIG. 18 is another time chart showing the operation of the DRAM shown in FIG. FIG. 17 shows a case where the defective column selection line CSL1 of the first memory block column and the defective column selection line CSL2 of the third memory block column are simultaneously selected. The column selection lines CSL1 and CSL2 can be replaced with any spare column selection line among the eight spare column selection lines SCSL1 to SCSL8. Column selection lines CSL1 and CSL2 are replaced with spare column selection lines SCSL2 and SCSL3, for example. The replaced column selection lines CSL1 and CSL2 are maintained at the “L” level of the inactivation level. Of the signals φa to φh, the signals φa, φb, φd, φf, and φj become the “H” level of the activation level. 4-bit signals read from the first memory block column when spare column select line SCSL2 is set to "H" level are signals AD. The 4-bit signal read from the second memory block column with spare column select line SCSL3 set to "H" level becomes signals E to H. Signals I and J are maintained at the “H” level.
[0081]
(Example of change)
FIG. 19 is a time chart showing the operation of the DRAM according to the modification of the third embodiment, which is compared with FIG.
[0082]
In this modification, the normal column selection lines CSL1 and CSL2 in FIG. 15 can be replaced with any one of the spare column selection lines SCSL3, SCSL4, SCSL7, and SCSL8. However, column spare column selection lines SCSL3 and SCSL4 and SCSL7 and SCSL8 cannot be used simultaneously.
[0083]
FIG. 19 shows an example in which the column selection line CSL1 is replaced with the spare column selection line SCSL3 and the column selection line CSL2 is used as it is. In this modification, it is not necessary to deactivate the replaced column selection line CSL1.
[0084]
In this case, only the signals φc, φd, φf, φh, and φk among the signals φa to φk become the “H” level of the activation level. The 4-bit signal read from the first memory block column with the column selection line CSL1 set to "H" level is blocked by the block selection switch BS 'on both sides of the first memory block column, and is applied to the global IO line pair GIOP. Does not appear. The 4-bit signal read from the second memory block column when spare column select line SCSL3 is set to "H" level becomes signals CF. The 4-bit signal read from the third memory block column with column select line CSL2 set to "H" level becomes signals G to J.
[0085]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0086]
【The invention's effect】
  As abovethisinventionAccording to,Nth column memory block column and N + 1th columnMemory block sequenceWithA first and second global IO line pair is provided between them,Third and fourth global IO line pairs are provided between the memory block column of the (N + 1) th column and the memory block column of the (N + 2) th column. In addition, between the memory block row of the Mth row and the memory block row of the M + 1th row,NthThe memory block of the Mth row in the number column,N + 1th rowThe memory block in the Mth row, the memory block in the (M + 1) th row in the Nth column, and the M + 1th row in the (N + 1) th column.Memory blockWhenAre commonly provided with the first local IO line pair.The In addition, between the memory block row of the Mth row and the memory block row of the M + 1th row,N + 1The memory block of the Mth row in the number column,N + 2 columnThe memory block in the Mth row, the memory block in the (M + 1) th row in the (N + 1) th column, and the M + 1th row in the (N + 2) th column.Memory blockWhenHave a second local IO line pair in common.The Further, between the memory block row of the (M + 1) th row and the memory block row of the (M + 2) th row, the memory block of the (M + 1) th row and the (M + 1) th row of the (N + 1) th column. The third local IO line pair is shared by the memory block in the No. row, the memory block in the (M + 2) th row in the Nth column, and the memory block in the (M + 2) th row in the (N + 1) th column. Provided. Further, between the memory block row of the (M + 1) th row and the memory block row of the (M + 2) th row, the memory block of the (M + 1) th row in the (N + 1) th column and the (M + 1) th row in the (N + 2) th column. The fourth local IO line pair is shared by the memory block in the No. row, the memory block in the (M + 1) th row in the (N + 1) th column, and the memory block in the (M + 2) th row in the (N + 2) th column. Provided. FirstLocal IO linePair and firstIntersection of global IO line pairEach ofOn the second1'sSwitch means are providedThe second switch means is provided at each of the intersections between the second local IO line pair and the third global IO line pair. A third switch means is provided at each of the intersections of the third local IO line pair and the second global IO line pair, and each of the intersections of the fourth local IO line pair and the fourth global IO line pair. The fourth switch means is provided.And the control means is the first~First4The switch means is controlled to couple the local IO line pair and the global IO line pair corresponding to the memory block selected by the row selecting means and the column selecting means. Therefore, the area penalty is smaller than that in the conventional example 1 in which four global IO line pairs are provided between each of a plurality of memory block columns, and the end or center of the local IO line pair is global. The data transfer speed can be increased as compared with the conventional example 2 connected to the IO line pair.
[0087]
  Preferably,First~First4Each of the switching means includes a pair of transfer gates. In this case, the first~First4The switch means can be easily configured.
[0088]
  Also preferably,First~First4Each of the switching means includes an amplifier that amplifies the potential difference of the local IO line pair and applies it to the global IO line pair. In this case, the potential difference of the local IO line pair is amplified and applied to the global IO line pair, so that the data transfer speed can be further increased.
[0089]
  Also preferably,First local IO line pairIncludes fifth and sixth switch means.First1Switch meansSandwiched betweenSeventh and eighth switch means are provided in the second local IO line pair.2Switch meansSandwiched betweenProvided.The third local IO line pair is provided with ninth and tenth switch means with the third switch means in between, and the fourth local IO line pair has eleventh and twelfth switch means. Is provided with a fourth switch means in between.The control means5First12The first switch means is also controlled to~First4Of the local IO line pair corresponding to the selected memory blockAnd the first to fourth global IO line pairs corresponding to the first to fourth global IO line pairs, respectively, and the first to fourth global IO lines corresponding to the other parts of the first to fourth local IO line pairs, respectively. Pair andDisconnect. In this case, the first~First4The capacity of the local IO line pair can be halved, and the data transfer speed can be further increased.
[0090]
  Also preferably,Each memory block column is further provided with a spare column selection line and an address comparator. In this case, a defective column selection line can be replaced with a spare column selection line.
[0091]
  Also preferably,Each address comparator is programmed with a column address signal of a defective column selection line belonging to the memory block column to which the corresponding spare column selection line belongs. In this case, the control operation of the control means can be simplified.
[0092]
  Also preferably,The column selection means selects one of a plurality of odd-numbered memory block columns and a plurality of even-numbered memory block columns, and each address comparator has a memory block column to which a corresponding spare column selection line belongs. Alternatively, a column address signal of a defective column selection line belonging to a memory block column adjacent to the memory block column is programmed, and an address comparator is provided in common to a plurality of odd-numbered memory block columns or a plurality of even-numbered memory block columns. It is done. In this case, more defective column selection lines can be relieved.
[Brief description of the drawings]
1 is a block diagram showing an overall configuration of a DRAM according to a first embodiment of the present invention;
FIG. 2 is a diagram showing a chip layout of the DRAM shown in FIG. 1;
FIG. 3 is an enlarged view of a portion X in FIG. 2;
FIG. 4 is an enlarged view of a Y part in FIG. 3;
5 is a diagram showing in detail a portion related to an odd-numbered bit line pair in the memory block shown in FIG. 4;
6 is a circuit diagram showing a configuration of a block selection switch shown in FIG. 5. FIG.
7 is a circuit diagram showing a first modification of the first embodiment. FIG.
FIG. 8 is a time chart showing an operation in a read mode of the first modification shown in FIG. 7;
FIG. 9 is a block diagram showing a second modification of the first embodiment.
FIG. 10 is a block diagram showing a third modification of the first embodiment.
FIG. 11 is a circuit block diagram showing a main part of a memory mat of a DRAM according to a second embodiment of the present invention.
12 is a circuit block diagram showing a configuration of a block selection switch BS ′ shown in FIG. 11. FIG.
13 is a time chart showing the operation of the DRAM shown in FIG.
FIG. 14 is a time chart showing a modification of the second embodiment.
FIG. 15 is a circuit block diagram showing a main part of a memory mat of a DRAM according to a third embodiment of the present invention.
FIG. 16 is a circuit diagram showing a configuration of a block selection switch BS ″ shown in FIG. 15;
FIG. 17 is a time chart showing an operation of the DRAM shown in FIG. 15;
FIG. 18 is another time chart showing the operation of the DRAM shown in FIG. 15;
FIG. 19 is a time chart showing a modification of the DRAM shown in FIG. 15;
FIG. 20 is a circuit block diagram showing a main part of a memory mat of a conventional DRAM.
FIG. 21 is a circuit block diagram showing a main part of a memory mat of another conventional DRAM.
[Explanation of symbols]
1 clock generation circuit, 2 row and column address buffer, 3 row decoder, 4 column decoder, 5 memory mat, 6 memory array, 7 sense amplifier + input / output control circuit, 8 input buffer, 9 output buffer, 10 semiconductor substrate, 11 Peripheral circuit area, 12 sub-word driver, 13 transfer gate, 14, 15 transfer gate, 16 inverter, 21-27, 43-46 N-channel MOS transistor, 28, 32 equalizer, 29-31, 33-35, 37, 38 P-channel MOS transistor, 36 charging circuit, 40, 41 address comparator, M memory block, LIOP local IO line pair, GIOP global IO line pair, BS, BS ′, BS ″ block selection switch, MC memory cell, WL word line, BLP bit Pair, SA the sense amplifier, CSL column selection line, SCSL spare column select lines, CSLG column selection gate, DB column decoder block.

Claims (7)

A semiconductor memory device comprising a plurality of memory blocks arranged in a matrix,
First and second global IO line pairs provided in an area between the memory block column of the Nth column (where N is a natural number) and the memory block column of the (N + 1) th column,
Third and fourth global IO line pairs provided in an area between the memory block column of the (N + 1) th column and the memory block column of the (N + 2) th column;
The memory in the Mth row (where M is a natural number) is provided in an area between the memory block row of the Mth row (where M is a natural number) and the memory block row of the (M + 1) th row. A memory block in the Mth row in the (N + 1) th column, a memory block in the (M + 1) th row in the Nth column, a memory block in the (M + 1) th row in the (N + 1) th column, A first local IO line pair provided in common,
Provided in an area between the memory block row of the Mth row and the memory block row of the (M + 1) th row, the memory block of the Mth row in the (N + 1) th column, and the column of the (N + 2) th row A second memory block provided in common for the memory block in the Mth row, the memory block in the (M + 1) th row in the (N + 1) th column, and the memory block in the (M + 1) th row in the (N + 2) th column. Local IO line pair,
It is provided in an area between the memory block row of the (M + 1) th row and the memory block row of the (M + 2) th row, the memory block of the (M + 1) th row and the (N + 1) th column in the Nth column. A third memory block commonly provided for the memory block in the (M + 1) th row, the memory block in the (M + 2) th row in the Nth column, and the memory block in the (M + 2) th row in the (N + 1) th column. Local IO line pair,
It is provided in an area between the memory block row of the (M + 1) th row and the memory block row of the (M + 2) th row, and the memory block of the (M + 1) th row and the (N + 2) th column in the (N + 1) th column. A fourth memory block provided in common to the memory block in the (M + 1) th row, the memory block in the (M + 2) th row in the (N + 1) th column, and the memory block in the (M + 2) th row in the (N + 2) th column. Local IO line pair,
First switch means provided at each intersection of the first local IO line pair and the first global IO line pair;
Second switch means provided at each of intersections of the second local IO line pair and the third global IO line pair;
Third switch means provided at each of the intersections of the third local IO line pair and the second global IO line pair;
A fourth switch means provided at each of intersections of the fourth local IO line pair and the fourth global IO line pair;
A row selection means for selecting any one of the plurality of memory block rows according to a row address signal;
Column selecting means for selecting any one of the plurality of memory block columns in accordance with a column address signal;
The first to fourth switching means are controlled, and when the memory block of the (M + 1) th row is selected in the (N + 1) th column by the row selection means and the column selection means, The local IO line pair and the first global IO line pair, the second local IO line and the third global IO line, the third local IO line and the second global IO line, the fourth A semiconductor memory device comprising: control means for coupling a local IO line and the fourth global IO line respectively; and a data input / output means connected to the first to fourth global IO line pairs for inputting / outputting data . The first switch means includes a pair of transfer gates connected between a central portion of the first local IO line pair and the first global IO line pair,
The second switch means includes a pair of transfer gates connected between a central portion of the second local IO line pair and the third global IO line pair,
The third switch means includes a pair of transfer gates connected between a central portion of the third local IO line pair and the second global IO line pair,
2. The semiconductor according to claim 1, wherein the fourth switch means includes a pair of transfer gates connected between a central portion of the fourth local IO line pair and the fourth global IO line pair. Storage device. The first switch means includes an amplifier that amplifies a potential difference of the first local IO line pair and gives the first global IO line pair to the first global IO line pair;
The second switch means includes an amplifier that amplifies the potential difference of the second local IO line pair and applies the amplified difference to the third global IO line pair.
The third switch means includes an amplifier that amplifies a potential difference of the third local IO line pair and applies the amplified difference to the second global IO line pair,
2. The semiconductor memory device according to claim 1, wherein the fourth switch means includes an amplifier that amplifies a potential difference of the fourth local IO line pair and applies the amplified difference to the fourth global IO line pair. Further, the first local IO line pair is provided with fifth and sixth switch means sandwiching the first switch means,
The second local IO line pair is provided with seventh and eighth switch means sandwiching the second switch means,
The third local IO line pair is provided with ninth and tenth switch means sandwiching the third switch means,
The fourth local IO line pair is provided with eleventh and twelfth switch means sandwiching the fourth switch means therebetween,
The control means further controls the fifth to twelfth switch means to select the memory block selected by the row selection means and the column selection means of the first to fourth local IO line pairs. And the first to fourth global IO line pairs corresponding to each of the first to fourth local IO line pairs corresponding to the first and fourth local IO line pairs respectively. The semiconductor memory device according to any one of claims 1 to 3, wherein the fourth global IO line pair is separated. Each memory block
Multiple memory cells arranged in multiple rows and multiple columns,
Each including a plurality of word lines provided corresponding to the plurality of rows, and a plurality of bit line pairs provided corresponding to the plurality of columns, respectively.
The plurality of bit line pairs are divided into a plurality of bit line pair groups each including four bit line pairs;
The semiconductor memory device is further provided corresponding to each memory block column and commonly provided to a plurality of memory blocks belonging to the corresponding memory block column, and the plurality of bit line pair groups of each corresponding memory block are provided. It has a plurality of column selection lines for selecting one of the bit line pair groups,
At least one of the plurality of column selection lines is used as a spare column selection line for replacing a defective column selection line;
The semiconductor memory device is further provided corresponding to each spare column selection line, the column address signal assigned to the defective column selection line is programmed, and the input address signal matches the programmed column address signal. In response, the address comparator for selecting the corresponding spare column selection line is provided,
The column selection means further selects any column selection line other than the defective column selection line programmed in the address comparator among the plurality of column selection lines corresponding to the selected memory block column,
The row selecting means further includes a spare column selection line selected by the address comparator or the column selection means in the selected memory block row or a plurality of word lines of the memory block corresponding to the column selection line. Select one of the word lines,
The control means further includes four bit line pairs of a bit line pair group corresponding to a spare column selection line or a column selection line selected by the address comparator or the column selection means, and selected by the row selection means. 4. The semiconductor memory device according to claim 1, wherein four memory cells corresponding to a word line are coupled to corresponding first to fourth local IO line pairs.   6. The semiconductor memory device according to claim 5, wherein each address comparator is programmed with a column address signal of a defective column selection line belonging to a memory block column to which a corresponding spare column selection line belongs. The column selection means selects one of a plurality of odd-numbered memory block columns and a plurality of even-numbered memory block columns,
Each address comparator is programmed with a column address signal of a memory block column to which a corresponding spare column selection line belongs or a defective column selection line belonging to a memory block column adjacent to the memory block column,
6. The semiconductor memory device according to claim 5, wherein each address comparator is provided in common to a plurality of odd-numbered memory block columns or a plurality of even-numbered memory block columns.

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