JP4462250B2 - Ceramic circuit board and semiconductor device using the same - Google Patents
Ceramic circuit board and semiconductor device using the same Download PDFInfo
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- JP4462250B2 JP4462250B2 JP2006216323A JP2006216323A JP4462250B2 JP 4462250 B2 JP4462250 B2 JP 4462250B2 JP 2006216323 A JP2006216323 A JP 2006216323A JP 2006216323 A JP2006216323 A JP 2006216323A JP 4462250 B2 JP4462250 B2 JP 4462250B2
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Description
この発明は、この発明は、セラミックス回路基板およびそれを用いた電力用のパワー半導体モジュールに関する。 The present invention relates to a ceramic circuit board and a power semiconductor module for electric power using the same.
頭記したパワー半導体モジュール用のセラミックス回路基板として、放熱性,電気絶縁性,高周波数特性の優れたアルミナ系,窒化アルミニウムなどのセラミックス基板の表面に導体パターンとなる銅回路板を接合し、同じく裏面に銅板を接合してなるセラミックス回路基板が広く採用されている。
このセラミックス回路基板は、銅ベース板(ヒートシンク板)に搭載して半田付けし、セラミックス回路基板の銅回路板上に複数個のパワー半導体素子などを実装した上で外囲樹脂ケース,外部導出端子を組合せてパワー半導体モジュールの製品を構成している。
This ceramic circuit board is mounted on a copper base plate (heat sink plate) and soldered, and a plurality of power semiconductor elements are mounted on the copper circuit board of the ceramic circuit board, and then the surrounding resin case and external lead-out terminal A power semiconductor module product is configured by combining the above.
ところで、セラミックス回路基板は放熱性,電気絶縁性などの面で優れた特性を有するものの、セラミックス基板自身は脆くて曲げ強度が小さく、昨今のセラミックス基板の薄形化によりパワー半導体モジュール製品としての実使用状態で通電制御に伴うヒートサイクル,放熱フィンへ取付ける際のねじ締結などに伴って熱的,機械的なストレスが加わると、その応力が集中する箇所でセラミックス基板にクラック,割れが生じやすい。 By the way, although ceramic circuit boards have excellent characteristics in terms of heat dissipation, electrical insulation, etc., ceramic boards themselves are brittle and have low bending strength. Due to the recent thinning of ceramic boards, they have become practical as power semiconductor module products. If a thermal or mechanical stress is applied in connection with the heat cycle associated with energization control in the state of use or the screw fastening when attaching to the radiating fin, cracks and cracks are likely to occur in the ceramic substrate where the stress is concentrated.
しかも、セラミックス基板にクラック,割れが発生すると、その部分が絶縁不良となって地絡などのダメージに進展するおそれがあって製品の信頼性が低下する。
そこで、パワー半導体モジュールとしての実使用時にセラミックス基板にクラック,割れが生じた場合でも、絶縁不良のダメージに進展しないようにする対策として、セラミックス基板上の銅回路板(導体パターン)の領域から外れた箇所に沿って基板表面にあらかじめスナップラインを形成しておき、製品の実使用時に加わる熱的,機械的応力を意図的にこのスナップラインに集中させ、この部分にクラックが生じてもパワー半導体モジュールとして絶縁不良のダメージに進展しないようにした構成のものが、先に提案されている(特開平9−312357号:特許文献1参照)。
In addition, when cracks or cracks occur in the ceramic substrate, the portion may be poorly insulated and may develop damage such as a ground fault, resulting in reduced product reliability.
Therefore, if the ceramic substrate is cracked or cracked during actual use as a power semiconductor module, as a measure to prevent it from developing into damage due to defective insulation, the copper circuit board (conductor pattern) on the ceramic substrate is removed. A snap line is formed in advance on the substrate surface along the part where the thermal and mechanical stress applied during actual use of the product is intentionally concentrated on this snap line, and even if a crack occurs in this part, the power semiconductor As a module, a structure in which the module does not progress to damage due to insulation failure has been proposed (see JP-A-9-31357: Patent Document 1).
しかしながら、前記提案は、その後に行った数多くの製品テスト結果から必ずしも期待通りの成果が得られず、特にセラミックス基板のクラック発生箇所を通じて銅ベース(アース電位)と銅回路板(充電部)との間の沿面絶縁強度が決まってしまい、耐電圧の向上が図れないなどの不具合の生じることが判明した。
また、銅貼りセラミックス回路基板では、銅回路板のパターン形状を工夫するなどしてクラック,割れを防ぐようにした対策も知られているが、この方法では回路パターンが制約を受けるなど、回路設計,コスト面の問題点が残る。
However, the above proposal does not always give the expected results from the results of many product tests conducted thereafter. In particular, the copper base (ground potential) and the copper circuit board (charged part) are connected to each other through the crack occurrence point of the ceramic substrate. It was found that the creepage insulation strength was determined during this period, causing problems such as failure to improve withstand voltage.
In addition, for copper-clad ceramic circuit boards, there are known measures to prevent cracks and cracks by devising the pattern shape of the copper circuit board. However, this method limits the circuit pattern and circuit design. , Cost problems remain.
この発明は上記の点にかんがみなされたものであり、その目的は前記課題を解決し、回路面での設計変更を要することなく、クラック,割れに対してより信頼性の高いパワー半導体モジュール用のセラミックス回路基板を提供することにある。 The present invention has been considered in view of the above points. The object of the present invention is to solve the above-mentioned problems, and for a power semiconductor module with higher reliability against cracks and cracks without requiring a design change on the circuit surface. The object is to provide a ceramic circuit board.
上記目的を達成するために、この発明によれば、セラミックス基板に銅回路板を接合したパワー半導体モジュール用のセラミックス回路基板において、パワー半導体モジュールとしての実使用状態で熱的,機械的応力が加わるセラミックス基板に対し、該セラミックス基板の前記応力集中が予測される箇所の表面と、該応力集中が予測される箇所を挟んで対向する銅回路板の縁とに絶縁物の補強材を接着剤で接合するものとする(請求項1,2)。
In order to achieve the above object, according to the present invention, in a ceramic circuit board for a power semiconductor module in which a copper circuit board is bonded to a ceramic board, thermal and mechanical stress is applied in an actual use state as a power semiconductor module. An insulator reinforcement material is bonded to the surface of the ceramic substrate where the stress concentration is predicted and the edge of the copper circuit board facing the portion where the stress concentration is predicted with an adhesive. It shall join (Claims 1 and 2).
パワー半導体モジュールとしての実使用状態でセラミックス基板に加わる熱的,機械的応力の集中箇所は、数多くの製品テストの結果から得た知見,コンピュータのシミュレーション手法などで予測が可能である。そこで、セラミックス基板の前記応力集中が予測される箇所の表面と、該応力集中が予測される箇所を挟んで対向する銅回路板の縁とに絶縁物の補強材を接合することにより、セラミックス基板としての曲げ強度が高まり、パワー半導体モジュール製品の実使用状態で加わる熱的,機械的応力に起因するセラミックス基板のクラック,割れの発生を未然に防ぐことができる。 The concentration of thermal and mechanical stress applied to the ceramic substrate in actual use as a power semiconductor module can be predicted by knowledge obtained from the results of many product tests, computer simulation methods, and the like. Therefore, the ceramic substrate is bonded to the surface of the ceramic substrate where the stress concentration is predicted and the edge of the copper circuit board facing the portion where the stress concentration is predicted. As a result, the bending strength of the ceramic substrate can be increased, and the occurrence of cracks and cracks in the ceramic substrate due to the thermal and mechanical stress applied in the actual use state of the power semiconductor module product can be prevented.
なお、参考として、パワー半導体モジュールとしての実使用状態で熱的,機械的応力が加わるセラミックス基板に対し、その応力集中が予測される箇所に沿ってセラミックス基板の表面に高粘着性,高伸び率を有するシリコーン系樹脂を塗布,キュアする構成がある。
これにより、パワー半導体モジュール製品の実使用時に加わる熱的,機械的応力に起因してセラミックス基板に万一クラック,割れが生じても、この部分にはあらかじめ電気絶縁性に優れたシリコーン系樹脂が盛り付けてあるので回路(充電部)に対する絶縁不良(沿面絶縁強度の劣化)を引き起こすことがなく、製品としての耐電圧低下が効果的に防げる。
For reference, a ceramic substrate to which thermal and mechanical stress is applied in the actual use state as a power semiconductor module has high adhesion and high elongation on the surface of the ceramic substrate along the location where the stress concentration is predicted. There is a configuration in which a silicone resin having a coating is applied and cured.
As a result, even if a ceramic substrate is cracked or cracked due to thermal or mechanical stress applied during actual use of a power semiconductor module product, a silicone resin with excellent electrical insulation is preliminarily applied to this part. Since it is installed, it does not cause insulation failure (deterioration of creeping insulation strength) to the circuit (charged part) and can effectively prevent a reduction in withstand voltage as a product.
この発明によるセラミックス回路基板を用いてパワー半導体モジュールの製品を組立てることにより、補強材の接合によりセラミックス基板の曲げ強度が増強し、製品の実使用状態でセラミックス基板に熱的,機械的応力が加わっても、セラミックス基板にクラック,割れの生じるのを効果的に防止でき、製品の信頼性向上化が図れる。 By assembling a power semiconductor module product using the ceramic circuit board according to the present invention, the bending strength of the ceramic substrate is enhanced by joining the reinforcing material, and thermal and mechanical stress is applied to the ceramic substrate in the actual use state of the product. However, cracks and cracks can be effectively prevented from occurring in the ceramic substrate, and the reliability of the product can be improved.
以下、この発明の実施の形態を図1に示す実施例に基づいて説明する。 Hereinafter, an embodiment of the present invention will be described based on the embodiment shown in FIG.
図1はこの発明の請求項1に対応する実施例を示すものである。図において、1はセラミックス基板1aの主表面に導体パターンを形成する銅回路板1bを接合し、同じく裏面に銅板1cを接合したセラミックス回路基板、2は銅回路板1aにマウントしたパワー半導体素子、3はセラミックス回路基板1を搭載した銅ベース板(ヒートシンク)であり、銅ベース板3に対してセラミックス回路基板1の銅板1cが半田4で接合されている。
FIG. 1 shows an embodiment corresponding to claim 1 of the present invention. In the figure, 1 is a ceramic circuit board in which a
ここで、前記セラミックス基板1aに対しては、パワー半導体モジュール製品としての実使用状態で熱的,機械的な応力の集中が予測される箇所Pに沿って、セラミックス基板の表面に絶縁物の補強材5が接着剤6により接合されている。なお、補強材5の接合はパワー半導体モジュールの組立工程の途中で行うものとする。
なお、応力集中の予測される箇所Pは、数多くの製品テスト結果から得た知見,コンピユータのシミュレーションなどから、セラミックス基板1aの上に接合した銅回路板1bの相互間に沿って銅回路板で覆われてない部分に多く発生することが判明しており、この検証結果を基に絶縁物の補強材5を図示のように銅回路板1bの相互間の縁に沿って敷設し、接着剤6によりセラミックス基板1aの表面に接合するようにしている。
Here, for the ceramic substrate 1a, the surface of the ceramic substrate is reinforced with an insulator along the portion P where the concentration of thermal and mechanical stress is predicted in the actual use state as a power semiconductor module product. The material 5 is joined by an adhesive 6. In addition, joining of the reinforcing material 5 shall be performed in the middle of the assembly process of a power semiconductor module.
It should be noted that the point P where stress concentration is predicted is determined by the copper circuit board along the gap between the
かかる構成によれば、補強材5を接合したことでその部分におけるセラミックス基板1aの曲げ強度が増強され、パワー半導体モジュールとしての実使用時に加わる熱的,機械的応力に対してクラック,割れが生じない強度を確保することができる。
[参考例]
According to such a configuration, by joining the reinforcing material 5, the bending strength of the ceramic substrate 1a at that portion is enhanced, and cracks and cracks are generated due to thermal and mechanical stress applied during actual use as a power semiconductor module. No strength can be ensured.
[Reference example]
図2はこの参考例を示すものである。この実施例においては、パワー半導体モジュールとしての実使用状態で熱的,機械的な応力の集中が予測される箇所P(図1と同一箇所)に沿ってセラミックス基板1aの表面には、銅回路板1bの相互間の間隙を埋めるように盛り付けて高粘着性,高伸び率(ゴム性)を有するシリコーン系樹脂(コンパンウンド)7が塗布,キュアされている。
FIG. 2 shows this reference example. In this embodiment, a copper circuit is formed on the surface of the ceramic substrate 1a along a location P (the same location as in FIG. 1) where thermal and mechanical stress concentration is predicted in the actual use state as a power semiconductor module. A silicone resin (compound) 7 having high adhesion and high elongation (rubber property) is applied and cured so as to fill the gap between the
これにより、パワー半導体モジュール製品としての実使用状態でセラミックス基板1aに加わる熱的,機械的な応力集中で前記箇所Pにクラック,割れ8が発生した場合でも、その周域がシリコーン系樹脂7で覆われているので、銅ベース板(アース電位)3と銅回路板(充電部)1bとの間の沿面絶縁強度,耐電圧の低下を防ぎ、製品の高い信頼性を維持できる。 As a result, even if cracks or cracks 8 occur in the portion P due to thermal and mechanical stress concentration applied to the ceramic substrate 1a in the actual use state as a power semiconductor module product, the peripheral area is made of the silicone resin 7. Since it is covered, it is possible to prevent a decrease in creeping insulation strength and withstand voltage between the copper base plate (earth potential) 3 and the copper circuit plate (charging part) 1b, and maintain high reliability of the product.
1 セラミックス回路基板
1a セラミックス基板
1b 銅回路板
1c 銅板
2 パワー半導体素子
3 銅ベース板
5 補強材
6 接着剤
7 シリコーン系樹脂
8 クラック,割れ
P 応力集中の予測箇所
DESCRIPTION OF SYMBOLS 1 Ceramic circuit board 1a
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JP2006216323A JP4462250B2 (en) | 2006-08-09 | 2006-08-09 | Ceramic circuit board and semiconductor device using the same |
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JP2006216323A JP4462250B2 (en) | 2006-08-09 | 2006-08-09 | Ceramic circuit board and semiconductor device using the same |
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JP20493598A Division JP3861465B2 (en) | 1998-07-21 | 1998-07-21 | Ceramic circuit board and semiconductor device using the same |
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JP4462250B2 true JP4462250B2 (en) | 2010-05-12 |
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