JP4461227B1 - Manufacturing method of semiconductor substrate - Google Patents

Abstract

[PROBLEMS] To reduce the occurrence of cracks when growing a crystal of a group III nitride semiconductor.
A semiconductor substrate manufacturing method includes a metal layer forming step of forming a metal layer on a base substrate, a plurality of openings exposing the metal layers, and a non-opening portion not exposing the metal layers. A mask forming step of forming a mask; a nitriding step of forming a plurality of first buffer layers of metal nitride by nitriding a plurality of regions exposed by the plurality of openings in the metal layer; A second buffer layer forming step of forming a plurality of group III nitride semiconductor buffer layers on the first buffer layer; and a group III nitride semiconductor crystal on the plurality of second buffer layers Each of the plurality of openings has a shape along a hexagon, and in the mask formation step, a minimum width of each opening in the plurality of openings is 5 μm. Above 25μm or less and becomes the between adjacent said opening such that the width of the non-opening portion is 1.5μm or more 8μm or less, to form the mask.
[Selection] Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor substrate.

  An electronic element such as an LED (Light Emitting Diode) may be formed on a semiconductor substrate including a gallium nitride crystal. Here, in order to improve the characteristics of the electronic element, it is necessary to improve the crystallinity of the gallium nitride crystal. In order to improve the crystallinity of a gallium nitride crystal, a gallium nitride crystal is not formed directly on the base substrate, but a low temperature buffer layer is formed on the base substrate, It is common to form a gallium nitride crystal on top (see Patent Document 1). The low-temperature buffer layer is a layer obtained by growing gallium nitride at a temperature lower than the temperature for forming the gallium nitride crystal.

  In general, the base substrate includes a sapphire crystal. In this case, the lattice mismatch is large between the base substrate (sapphire) and the low-temperature buffer layer (gallium nitride), and the difference in thermal expansion coefficient is large. As a result, dislocations and internal stress are generated in the low-temperature buffer layer grown on the base substrate, so that there is a possibility that the crystallinity of the gallium nitride crystal grown thereon is not improved.

  In recent years, as a method for reducing the density of defects generated due to lattice mismatch between a base substrate (sapphire) and a low-temperature buffer layer (gallium nitride), ELO (see Non-Patent Document 1) or FIELO ( Non-patent document 2) and pendeo epitaxy (see non-patent document 3) have been developed. However, until the crystallinity of the gallium nitride crystal grown on the low-temperature buffer layer is sufficiently improved. It has not reached.

  A technique for mitigating lattice mismatch and thermal expansion coefficient difference between the base substrate (sapphire) and the low-temperature buffer layer (gallium nitride) is desired.

  On the other hand, the inventor has proposed a technique in which a chromium layer is formed on a base substrate and the chromium layer is nitrided to form a chromium nitride buffer layer (see Patent Document 2). In the technique of Patent Document 2, the structure of the base substrate / chromium nitride buffer layer / initial growth layer / GaN single crystal layer is formed. In this structure, the lattice spacing of the chromium nitride buffer layer has a value between the lattice spacing of the base substrate (sapphire) and the lattice spacing of the initial growth layer (gallium nitride). The thermal expansion coefficient of the chromium nitride buffer layer has a value between the thermal expansion coefficient of the base substrate (sapphire) and the thermal expansion coefficient of the initial growth layer (gallium nitride).

Japanese Unexamined Patent Publication No. 63-188983 International Publication No. WO2006 / 126330 Pamphlet

Appl. Phys. Lett. 71 (18) 2638 (1997) Jpn. J. et al. Appl. Phys. 38, L184 (1999) MRS Internet J.M. Nitride Semicond. Res. 4S1, G3.38 (1999)

  In Patent Document 2, the thermal expansion coefficient of the chromium nitride buffer layer has a value between the thermal expansion coefficient of the base substrate (sapphire) and the thermal expansion coefficient of the GaN single crystal layer (gallium nitride). It is said that the occurrence of cracks due to the difference in thermal expansion coefficient between the base substrate and the GaN single crystal layer can be reduced when the temperature is lowered after the crystal layer is grown.

  Here, if the generation of cracks during the growth of the GaN single crystal layer can be further reduced, it is considered that the cracks contained in the GaN single crystal layer can be further reduced. If the number of cracks contained in the GaN single crystal layer is very small, the leakage current through the cracks when an electronic element is formed on a semiconductor substrate including the GaN single crystal layer can be reduced.

  Patent Document 2 does not disclose the use of a mask including a plurality of openings, and furthermore, in what shape and dimensions each of the plurality of openings is formed, cracks are generated when the GaN single crystal layer is grown. There is no disclosure about whether or not A method for further reducing the generation of cracks when growing a GaN single crystal layer is desired.

  An object of the present invention is to reduce the occurrence of cracks when growing a crystal of a group III nitride semiconductor.

The method for manufacturing a semiconductor substrate according to the first aspect of the present invention includes a metal layer forming step of forming a metal layer on a base substrate, a plurality of openings exposing the metal layers, and a non-opening not exposing the metal layers. A mask forming step of forming a mask including a portion, and a nitriding step of forming a plurality of first buffer layers of metal nitride by nitriding a plurality of regions exposed by the plurality of openings in the metal layer, A second buffer layer forming step of forming a plurality of second buffer layers of a group III nitride semiconductor on the plurality of first buffer layers; and a group III nitride on the plurality of second buffer layers. Each of the plurality of openings has a shape along a hexagon, and in the mask formation step, a maximum of each of the openings in the plurality of openings is formed. Wherein as the width of the non-opening portion is 1.5μm or more 8μm or less between the opening width adjacent becomes 5μm or 25μm or less, to form the mask, wherein in the second buffer layer forming step, 850 ° C. or higher The plurality of second buffer layers are formed at a first temperature of 950 ° C. or lower, and the growth step includes a first growth step of growing the crystal body at a second temperature higher than the first temperature, A second growth step of growing the crystal body at a third temperature higher than the second temperature, or growing the crystal body at a second temperature higher than the first temperature. And a third growth step of growing the crystal body at a fourth temperature between the first temperature and the second temperature .

  A method for manufacturing a semiconductor substrate according to a second aspect of the present invention is a method for manufacturing a semiconductor substrate according to the first aspect of the present invention, wherein the base substrate is a hexagonal crystal or pseudo-hexagonal crystal. Each side of the hexagon has a structure, the direction to be along the [10-10] direction of the crystal in the base substrate, the direction to be along the [01-10] direction, and the [-1100] direction. It extends along one of the directions that should be along.

  A method for manufacturing a semiconductor substrate according to a third aspect of the present invention is a method for manufacturing a semiconductor substrate according to the first aspect or the second aspect of the present invention, wherein the mask forming step includes a mask layer on the metal layer. A mask layer forming step for forming the mask, and an opening forming step for forming the mask by forming the plurality of openings in the mask layer.

A method for manufacturing a semiconductor substrate according to a fourth aspect of the present invention is a method for manufacturing a semiconductor substrate according to any one of the first to third aspects of the present invention, comprising: a mask removing step for removing the mask; And a separation step of separating the crystal body from the base substrate by selectively etching the first buffer layer.

A method for manufacturing a semiconductor substrate according to a fifth aspect of the present invention includes a first buffer layer forming step of forming a first buffer layer on a base substrate, a plurality of openings exposing the first buffer layer, and the first buffer layer. A mask forming step of forming a mask including a non-opening that does not expose one buffer layer; and a plurality of regions of the group III nitride semiconductor in a plurality of regions exposed by the plurality of openings on the surface of the first buffer layer. A second buffer layer forming step of forming a second buffer layer; and a growth step of growing a group III nitride semiconductor crystal on the plurality of second buffer layers, each of the plurality of openings being And having a shape along a hexagon, and in the mask forming step, the minimum width of each of the plurality of openings is 5 μm or more and 25 μm or less, and the adjacent openings are The mask is formed so that the width of the non-opening portion is 1.5 μm or more and 8 μm or less in the second buffer layer forming step, and in the second buffer layer forming step, the plurality of the second openings are performed at a first temperature of 850 ° C. or more and 950 ° C. or less. Two buffer layers are formed, and the growth step includes a first growth step of growing the crystal body at a second temperature higher than the first temperature, and a third temperature higher than the second temperature. A first growth step for growing the crystal body at a second temperature higher than the first temperature, the first temperature, and the second temperature. And a third growth step of growing the crystal body at a fourth temperature between .

A method for manufacturing a semiconductor substrate according to a sixth aspect of the present invention is a method for manufacturing a semiconductor substrate according to the fifth aspect of the present invention, wherein the base substrate is a hexagonal crystal or pseudo-hexagonal crystal. Each side of the hexagon has a structure, a direction along the [10-10] direction of the crystal in the base substrate, a direction along the [01-10] direction, and a [-1100] direction. It extends along one of the directions to be along.

A method for manufacturing a semiconductor substrate according to a seventh aspect of the present invention is a method for manufacturing a semiconductor substrate according to the fifth aspect or the sixth aspect of the present invention, wherein the first buffer layer includes a metal nitride. Features.

A method for manufacturing a semiconductor substrate according to an eighth aspect of the present invention is a method for manufacturing a semiconductor substrate according to any of the fifth to seventh aspects of the present invention, wherein the mask forming step includes the first buffer layer. A mask layer forming step for forming a mask layer on the mask layer; and an opening forming step for forming the mask by forming the plurality of openings in the mask layer.

A method for manufacturing a semiconductor substrate according to a ninth aspect of the present invention is a method for manufacturing a semiconductor substrate according to any one of the fifth aspect to the eighth aspect of the present invention, the mask removing step for removing the mask, And a separation step of separating the crystal body from the base substrate by selectively etching the first buffer layer.

  According to the present invention, it is possible to reduce the occurrence of cracks when growing a crystal of a group III nitride semiconductor.

Process sectional drawing which shows the manufacturing method of the semiconductor substrate of the group III nitride semiconductor which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor substrate of the group III nitride semiconductor which concerns on 1st Embodiment of this invention. The top view of the structure obtained by the process shown in FIG.2 (b). Process sectional drawing which shows the manufacturing method of the semiconductor substrate of the group III nitride semiconductor which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor substrate of the group III nitride semiconductor which concerns on 1st Embodiment of this invention. The figure which shows the relationship between the opening width W [micrometer] of each opening, the arrangement pitch P [micrometer] of opening, and the width G [micrometer] of the non-opening part between adjacent openings. The figure which shows the preferable area | region in a WG plane. The figure which shows the preferable area | region in a PG plane. The figure which shows the relationship between the width | variety G of a non-opening part, and a merge rate. The figure which shows the XRD analysis result of the sample obtained by performing the process of FIGS. A photograph of a crystal obtained under the condition of (W, G) = (18, 2). A photograph of a crystal obtained under the condition of (W, G) = (28, 2). A photograph of a crystal obtained under the condition of (W, G) = (48, 2). Sectional drawing which shows the manufacturing method of the semiconductor substrate of the group III nitride semiconductor which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor substrate of the group III nitride semiconductor which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor substrate of the group III nitride semiconductor which concerns on 2nd Embodiment of this invention.

  In this specification, the “film” may be a continuous film or a discontinuous film. The “film” represents a state where the film is formed with a thickness.

  The present invention relates to a method for selectively growing a crystal body applicable to a semiconductor substrate such as an LED (Light Emitting Diode).

  A method for manufacturing a group III nitride semiconductor substrate according to a first embodiment of the present invention will be described with reference to FIGS. 1, 2, 4 and 5 are process cross-sectional views illustrating a method for manufacturing a semiconductor substrate. FIG. 3 is a plan view of the structure obtained by the process shown in FIG. 1, 2, 4, and 5 correspond to a cross section along A-A ′ in FIG. 3. Hereinafter, gallium nitride will be mainly described as an example of a group III nitride semiconductor, but the same applies to other group III nitride semiconductors.

In the step shown in FIG. 1A, a base substrate 10 is prepared. The base substrate 10 has a crystal structure of either hexagonal system or pseudo-hexagonal system. The upper surface 10a of the base substrate 10 has a (0001) plane in either a hexagonal system or a pseudo-hexagonal crystal structure. The material of the base substrate 10 is, for example, Al ₂ O ₃ (sapphire), GaN (gallium nitride), or AlN (aluminum nitride).

  In the step shown in FIG. 1B, a chromium layer (metal layer) 20 is formed on the base substrate 10 by sputtering or the like. The thickness of the chromium layer 20 to be formed is 20 nm, for example.

  Here, the chromium layer 20 is formed because the atomic distance of chromium nitride formed by nitriding after that is close to that of gallium nitride, and the lattice mismatch with gallium nitride is small.

  In the step shown in FIG. 2A, a mask layer 40 i is formed on the chromium layer 20. The thickness of the mask layer 40i to be formed is 100 nm, for example. The material of the mask layer 40i is, for example, either silicon oxide or silicon nitride.

  Here, the steps of FIGS. 1A to 2A are preferably performed continuously in the same chamber. In this case, the formation of a natural oxide film at the interface of each layer can be reduced.

  In the step shown in FIG. 2B, the mask 40 is formed by forming a plurality of openings 40a1 to 40an in the mask layer 40i by lithography or the like.

  The formed mask 40 includes an opening array 40a and a non-opening 40k as shown in FIG. In the opening array 40a, a plurality of openings 40a1,..., 40an are two-dimensionally arranged. Each opening 40a1,..., 40an exposes the chromium layer 20. Each of the openings 40a1, ..., 40an has a shape along a hexagon. Each side of the hexagon is in a direction along the [10-10] direction, a direction along the [01-10] direction, and a direction along the [-1100] direction of a crystal body 60 to be described later on the base substrate 10. It extends along either. The non-opening 40k does not expose the chromium layer 20. The non-opening 40k extends in a honeycomb shape between the plurality of openings 40a1, ..., 40an.

  In addition to the hexagonal shape, the shape along the above hexagonal shape includes a shape having rounded corners while maintaining the basic shape of the hexagon. In addition, each side of the above hexagon is, for example, when the material of the base substrate 10 is Al2O3 (sapphire), the [11-20] direction, the [1-210] direction, and the [-2110] direction of the base substrate 10. Extending along one of the For example, when the material of the base substrate 10 is GaN (gallium nitride) or AlN (aluminum nitride), each side of the hexagon has a [10-10] direction, a [01-10] direction, and a [- 1100] direction. In this way, since there is an orientation relationship between the base substrate 10 and the crystal body 60 to be grown thereon, a hexagonal mask orientation may be determined accordingly.

Here, when the minimum width of each opening in the plurality of openings 40a1 to 40an is W [μm] and the width of the non-opening portion 40k between adjacent openings is G [μm] (see FIG. 6), W -G plane (see FIG. 7) 5 ≦ W ≦ 25 Formula 1
1.5 ≦ G ≦ 8 Equation 2
A mask 40 is formed so as to satisfy the above. A region satisfying Equations 1 and 2 is a region PR indicated by hatching in FIG.

  In the region on the left side of the region PR shown in FIG. 7 (0 ≦ W <5), the width of the region exposed by the opening is reduced, so that the nitriding gas is applied to the chromium layer 20 in the step shown in FIG. It becomes difficult to make sufficient contact, and it becomes difficult to form the first buffer layer. In the region on the right side of the region PR shown in FIG. 7 (W> 25), the width of the region exposed by the opening is increased. Therefore, a plurality of first buffer layers and a plurality of second buffer layers formed thereon are provided. Accordingly, it is impossible to reduce the propagation of internal stress in the crystal body described later, and there is a possibility that a crack is generated in the crystal grown on the second buffer layer. In the region below the region PR shown in FIG. 7 (0 ≦ G <1.5), the exposure limit of the exposure apparatus for patterning the mask layer 40i is about 1 μm, and is affected by process variations. Adjacent openings may be connected. In the region (G> 8) above the region PR shown in FIG. 7, the width G [μm] (see FIG. 6) of the non-opening between the adjacent openings becomes large, so that the gallium nitride grown from the adjacent openings May be difficult to merge between adjacent openings, and a crystal may not be obtained.

  In the step shown in FIG. 2 (c), a plurality of regions 20a1 to 20an exposed by the plurality of openings 40a1 to 40an in the chromium layer 20 are nitrided at a temperature of 1000 ° C. or higher and 1300 ° C. or lower, thereby forming chromium nitride ( A plurality of first buffer layers 30a1 to 30an of (metal nitride) are formed. That is, the base substrate 10 is heated to a temperature of 1000 ° C. or more and 1300 ° C., and the surface of the chromium layer 20 is made an ammonia gas atmosphere. Accordingly, the plurality of regions 20a1 to 20an in the chromium layer 20 are nitrided to become the plurality of first buffer layers 30a1 to 30an.

  Here, the plurality of first buffer layers 30a1 to 30an are separated from each other by a chromium layer 20 having a crystal orientation different from that of the first buffer layer. As a result, if the width W of each opening satisfies Equation 1, it is possible to reduce the propagation of internal stress through the plurality of first buffer layers, which will be described later.

  In addition, the crystal structure of chromium nitride is a hexagonal system while the crystal structure of chromium nitride is a cubic system. When the chromium layer 20 is nitrided, it is considered that a certain amount of energy is required in order for the chromium crystal lattice to rearrange into the chromium nitride crystal lattice.

  If the nitridation temperature of the chromium layer 20 is less than 1000 ° C., sufficient energy is not given to the chromium layer 20 to rearrange the chromium crystal lattice into the chromium nitride crystal lattice, so that the chromium layer 20 is nitrided. The crystallinity of the formed first buffer layer 30 is deteriorated.

  On the other hand, in this embodiment, since the nitriding temperature of the chromium layer 20 is 1000 ° C. or higher, sufficient energy is given to the chromium layer 20 to rearrange the chromium crystal lattice into the chromium nitride crystal lattice. It is done. Thereby, the crystallinity of the first buffer layer 30 of chromium nitride formed by nitriding the chromium layer 20 is improved.

  However, nitriding at an excessively high temperature causes problems such as deterioration of members of the apparatus due to an increase in thermal load, and problems such as mutual thermal diffusion between the formed first buffer layer and the underlying substrate. For this reason, the nitriding temperature is preferably 1300 ° C. or lower.

  In addition, chromium nitride, which is a material of the first buffer layer 30, has an interatomic distance between the base substrate (sapphire) and gallium nitride, and therefore has a small lattice mismatch with the base substrate. Also from this point, the crystallinity of the first buffer layer 30 is improved.

  In the step shown in FIG. 4A, a plurality of second buffer layers 50a1 to 50an of gallium nitride are grown from the plurality of first buffer layers 30a1 to 30an exposed by the plurality of openings 40a1 to 40an.

  Here, the plurality of second buffer layers 50a1 to 50an are separated from each other by the non-opening portion 40k in the mask 40 having a crystal orientation different from that of the second buffer layer. For example, the plurality of second buffer regions 50a1 to 50an in the second buffer layer 50a are separated from each other by the non-opening portion 40k in the mask 40 having a crystal orientation different from that of the second buffer region. Thereby, it can reduce that an internal stress propagates in the below-mentioned crystal body via a some 2nd buffer layer.

  The plurality of second buffer layers 50a1 to 50an can be composed of, for example, a single crystal body, a polycrystalline body, or an amorphous body of GaN. The thicknesses of the plurality of second buffer layers 50a1 to 50an are preferably several tens to several tens of micrometers, respectively. The growth temperatures of the plurality of second buffer layers 50a1 to 50an are preferably first temperatures of 850 ° C. or more and 950 ° C. or less, respectively.

  If the growth temperature of the second buffer layers 50a1 to 50an is lower than 850 ° C., epitaxial growth becomes difficult, and a plane orientation different from an appropriate plane orientation with respect to the base substrate tends to occur. The second buffer layers 50a1 to 50an have a hexagonal crystal structure, and it is appropriate that the {1-100} plane group extends along the {11-20} plane group of the base substrate. is there. If there is a portion where the {1-100} plane group in the second buffer layers 50a1 to 50an extends in different orientations, the interior caused by lattice distortion between the portion and a portion having an appropriate plane orientation. Since stress is generated, there is a possibility that cracks may occur in each of the second buffer layers 50a1 to 50an. If the growth temperature of the second buffer layers 50a1 to 50an is higher than 950 ° C., the growth of the second buffer layers 50a1 to 50an is difficult to occur.

  In the step shown in FIG. 4B, a gallium nitride crystal body 60 is grown on the plurality of second buffer layers 50a1 to 50an by HVPE or MOCVD. That is, if the width G of the non-opening portion between adjacent openings in the plurality of openings of each opening satisfies Equation 2, gallium nitride grown from the surfaces of the plurality of second buffer regions in each second buffer layer Crystals 60 grow by merging with each other between adjacent openings.

  Here, the crystal body 60 may be composed of a single crystal body of GaN, for example. The thickness of the crystal body 60 is preferably several tens of μm to several tens of μm. The growth temperature of the crystal body 60 is higher than the growth temperature of the plurality of second buffer layers 50a1 to 50an, for example, about 1080 ° C.

  The plurality of second buffer layers 50 a 1 to 50 an are formed in the plurality of regions 30 a 1 to 30 an exposed by the plurality of openings 40 a 1 to 40 an of the mask 40 on the surface of the first buffer layer 30. Since the crystal orientation of the mask 40 is different from the crystal orientations of the plurality of second buffer layers 50a1 to 50an, dislocations existing at any specific location in the plurality of second buffer layers 50a1 to 50an are transferred to other second buffer layers 50a1. Difficult to propagate to ~ 50an. Thereby, the crystallinity of the plurality of second buffer layers 50a1 to 50an is improved as a whole. As a result, the crystallinity of the crystal body 60 grown on the plurality of second buffer layers 50a1 to 50an is also improved. That is, the crystallinity at the time of growing a group III nitride semiconductor crystal can be improved.

  Furthermore, chromium nitride, which is the material of the first buffer layer 30, has an interatomic distance between the base substrate (sapphire) and gallium nitride, so that the lattice mismatch with gallium nitride is small. For example, the interatomic distance in the (0001) plane direction of sapphire rotated by 30 ° is 2.747 mm. The interatomic distance in the (0001) plane direction of gallium nitride is 3.188 mm. The interatomic distance in the (111) plane direction of chromium nitride is 2.927 mm, which is a value between the interatomic distance of sapphire and the interatomic distance of gallium nitride. Thereby, the crystallinity of the plurality of second buffer layers 50a1 to 50an and the crystal body 60 grown on the first buffer layer 30 is improved.

  In addition, chromium nitride, which is the material of the first buffer layer 30, has a thermal expansion coefficient between the base substrate (sapphire) and gallium nitride. For example, the thermal expansion coefficient in the (0001) plane direction of sapphire is 7.50. The thermal expansion coefficient in the (0001) plane direction of gallium nitride is 5.45. The thermal expansion coefficient in the (111) plane direction of chromium nitride is 6.00, which is a value between the thermal expansion coefficient of sapphire and the thermal expansion coefficient of gallium nitride. Thereby, the internal stress generated based on the difference in thermal expansion coefficient between the base substrate 10, the plurality of second buffer layers 50 a 1 to 50 an and the crystal body 60 can be relaxed by the first buffer layer 30. For this reason, since the internal stress of each of the plurality of second buffer layers 50a1 to 50an and the crystal body 60 is reduced, the thermal expansion coefficient with the base substrate in each of the plurality of second buffer layers 50a1 to 50an and the crystal body 60 is reduced. It is possible to reduce the occurrence of cracks due to the difference. Also from this point, the crystallinity of the plurality of second buffer layers 50a1 to 50an and the crystal body 60 is improved.

  In the step shown in FIG. 4B, the first growth step of growing the crystal body 60 at a second temperature higher than the first temperature, and the crystal body 60 at a third temperature higher than the second temperature. And a second growth step for growing the substrate. The second temperature is, for example, 1040 ° C., and the third temperature is, for example, 1080 ° C. According to an experiment conducted by the present inventor, when a crystal was grown by heating at 1080 ° C. and then heating at 1080 ° C. (two-step heating), heating at 1080 ° C. (one-step heating is performed) The crystallinity of the obtained crystal was improved by about 5% as compared with the case where the crystal was grown.

  Alternatively, the process illustrated in FIG. 4B includes a first growth process in which the crystal body 60 is grown at a second temperature higher than the first temperature, and a first temperature between the first temperature and the second temperature. And a third growth step of growing the crystal body 60 at a temperature of 4. The second temperature is, for example, 1080 ° C., and the fourth temperature is, for example, 1040 ° C. According to experiments conducted by the present inventors, when a crystal is grown by heating at 1080 ° C. and then at 1040 ° C. (two-stage heating), it is heated at 1080 ° C. (one-step heating is performed). As a result, the crystallinity of each obtained crystal was improved by about 10% compared to the case where the crystal was grown.

  In the step shown in FIG. 5A, the mask 40 is removed. For example, the mask 40 is selectively removed by etching. For example, when the material of the mask 40 is silicon oxide, the mask 40 can be selectively etched by using an HF solution or a BOE (buffered HF) solution. At this time, the non-opening 40k that separates the plurality of openings 40a1 to 40an in the mask 40 is removed.

  5B, the chromium layer 20 and the plurality of first buffer layers 30a1 to 30an are selectively etched to separate the crystal body 60 from the base substrate 10. Thereby, the semiconductor substrate 70 can be obtained.

  Here, the semiconductor substrate 70 includes a plurality of second buffer layers 50 a 1 to 50 an and a crystal body 60. Each of the plurality of second buffer layers 50a1 to 50an has a hexagonal shape corresponding to the shape of the opening (see FIG. 3).

  In this way, a mask including a plurality of openings is formed before nitriding the chromium layer, and a plurality of first regions are selectively nitrided on a plurality of regions exposed by the plurality of openings on the surface of the chromium layer. A buffer layer is formed. The plurality of first buffer layers are separated from each other by a chromium layer having a different crystal orientation from the first buffer layer. Thereby, it can reduce that an internal stress propagates in each crystal body 60 via a plurality of 1st buffer layers.

  A plurality of second buffer regions are formed on the plurality of first buffer layers. The plurality of second buffer layers 50a1 to 50an are separated from each other by a mask having a different crystal orientation from the second buffer layer. Thereby, it is possible to reduce internal stress from propagating in the crystal body 60 through the plurality of second buffer layers.

  Therefore, propagation of internal stress in the crystal body 60 can be reduced, and the occurrence of cracks in the crystal body 60 can be reduced. That is, according to the present embodiment, it is possible to reduce the occurrence of cracks when growing a group III nitride semiconductor crystal.

  Next, in order to clarify the effect of this embodiment, the results of experiments will be described with reference to FIGS. FIG. 6 is a diagram illustrating the relationship among the opening width W [μm] of each opening in the plurality of openings, the arrangement pitch P [μm] of the openings, and the width G [μm] of the non-opening between adjacent openings. .

As shown in FIG. 6, the opening width W is the minimum width of each opening, and is defined as the width between two sides S1 and S2 facing each other through the center C1 in the opening OP1. The arrangement pitch P is defined as the distance between the centers C1 and C2 of the adjacent openings OP1 and OP2. The width G of the non-opening is defined as the width of the non-opening 40k (see FIG. 3) that separates the adjacent openings OP1 and OP2. Between these variables,
Non-opening width G = arrangement pitch P−opening width W Equation 3
There is a relationship.

  FIG. 7 is a diagram showing a preferred region PR in the WG plane. In FIG. 7, a preferred region PR in the present embodiment is indicated by hatching. Moreover, the dashed-dotted line shown in FIG. 7 shows the boundary of the area | region PR.

  The inventor performs the steps shown in FIGS. 1A to 2A, and then in the step shown in FIG. 2B, the condition in the first embodiment is (W, G) = (6 .5,3.5), (8,2), (13,2), (18,2), (5,5), (10,5) conditions (conditions indicated by ● in FIG. 7). Formed. Thereafter, the surface of the crystal obtained by performing the steps shown in FIGS. 2C to 5B was observed with a microscope. As a result, no cracks were observed on the surface of the crystal (see FIG. 11).

  Moreover, after performing the process shown in FIGS. 1A to 2A by the present inventor, in the process shown in FIG. 2B, the condition in the comparative example is (W, G) = (2, 2), (10, 10), (28, 2), (48, 2) (conditions indicated by ▲ in FIG. 7) were formed. Under the condition of (W, G) = (2, 2) (condition indicated by ▲ on the left side of the region PR), gallium nitride did not grow. Under the condition of (W, G) = (10, 10) (condition indicated by ▲ above the region PR), the gallium nitride grown on each adjacent second buffer layer merges on the non-opening portion therebetween. It was confirmed that they did not (see FIG. 9). Under the conditions (W, G) = (28, 2), (48, 2) (conditions indicated by ▲ on the right side of the region PR), cracks were observed as a result of microscopic observation of the obtained crystal ( (See FIG. 12 and FIG. 13). From these results, the present inventor has derived that a region PR indicated by hatching in FIG. 7 is a preferable region.

  FIG. 8 is a diagram showing a preferred region PR in the PG plane. The PG plane shown in FIG. 8 is obtained by converting the WG plane shown in FIG. Also in FIG. 8, the preferable region PR is indicated by hatching.

  FIG. 9 is a diagram illustrating the relationship between the width G of the non-opening and the merge rate. The merge rate was determined as a ratio of the area of the region covered with the crystal in the non-opening. In FIG. 9, the merge rate of the conditions (W, G) = (6.5, 3.5), (8, 2), (13, 2), (18, 2) in the first embodiment is ●. The merging rate under unfavorable conditions (W, G) = (10, 10) is indicated by ▲. As shown in FIG. 9, it was found that when the width G of the non-opening portion is too long, the merge rate tends to decrease from 100%. For example, when the width G of the non-opening is 10 μm, the merging rate is about 80% because the crystal is extended by about 4 μm from both ends of the non-opening toward the center of the non-opening. It was.

  FIG. 10 is a diagram showing a result of XRD analysis of a sample obtained by performing the steps of FIGS. X-ray diffraction (XRD) analysis was performed on one of the samples obtained by performing the steps of FIGS. That is, the peak half width of the (01-12) plane in the XRD profile of the crystal was 700 to 850 [arcsec]. In FIG. 10, this result is shown as a bar graph as “this embodiment”.

  For comparison, FIG. 10 shows the expected value of the peak half-value width of the (01-12) plane in the case where a crystal is obtained by the method of the embodiment shown in Patent Document 2. It is shown as a bar graph as “2”.

  According to the method of the embodiment disclosed in Patent Document 2, a CrN buffer layer is formed by forming a metal layer such as Cr on a base substrate and nitriding the metal layer. Then, after forming a GaN buffer layer on the CrN buffer layer, a GaN single crystal layer is grown on the GaN buffer layer. In this case, dislocation propagation occurs in the CrN buffer layer or the GaN buffer layer.

  On the other hand, according to the present embodiment, the plurality of first buffer layers are separated from each other by the chromium layer having a crystal orientation different from that of the first buffer layer. As a result, dislocations existing at specific locations in the plurality of first buffer layers are unlikely to propagate to other first buffer layers. As a result, since dislocations can be prevented from propagating in the crystal body 60 through the plurality of first buffer layers, it is considered that the crystallinity of the crystal body is improved as compared with the embodiment of Patent Document 2.

  The plurality of second buffer layers are separated from each other by a mask having a different crystal orientation from the second buffer layer. As a result, dislocations existing at specific locations in the plurality of second buffer layers are unlikely to propagate to other second buffer layers. As a result, since dislocations can be reduced from propagating in the crystal body 60 through the plurality of second buffer layers, it is considered that the crystallinity of the crystal body is improved as compared with the embodiment of Patent Document 2.

  Therefore, in FIG. 10, the XRD half-value width of “this embodiment” is smaller than the XRD half-value width of “Patent Document 2” and the crystallinity is good.

  FIG. 11 shows a photograph of the crystal obtained under the condition of (W, G) = (18, 2). FIG. 11A shows the appearance of the crystal, and FIGS. 11B and 11C show the microscopic observation results. No cracks were observed on the surface of the crystal obtained under the condition of (W, G) = (18, 2).

  FIG. 12 shows a photograph of the crystal obtained under the condition of (W, G) = (28, 2). FIG. 12A shows the appearance of the crystal, and FIGS. 12B and 12C show the microscopic observation results. Cracks were observed on the surface of the crystal obtained under the condition of (W, G) = (28, 2). In addition, the crystal was broken into two.

  FIG. 13 shows a photograph of the crystal obtained under the condition of (W, G) = (48, 2). FIG. 13A shows the appearance of the crystal, and FIGS. 13B and 13C show the microscopic observation results. Cracks were observed on the surface of the crystal obtained under the condition of (W, G) = (48, 2). In addition, the crystal was broken into two.

  Next, a method for manufacturing a group III nitride semiconductor substrate according to a second embodiment of the present invention will be described with reference to FIGS. 14 to 16 are process cross-sectional views illustrating a method for manufacturing a semiconductor substrate. In the following, description will be made centering on differences from the first embodiment.

  The process shown in FIG. 14A is performed after the process shown in FIG. In the step shown in FIG. 14A, the first buffer layer 130 of chromium nitride (metal nitride) is formed by nitriding the chromium layer 20 at a temperature of 1000 ° C. or higher and 1300 ° C. or lower (1273K or higher and 1573K or lower). To do.

  In the step shown in FIG. 14B, the mask layer 140 i is formed on the first buffer layer 130.

  In the step shown in FIG. 15A, as in the step shown in FIG. 2B, the mask 140 is formed by forming a plurality of openings 140a1 to 140an in the mask layer 140i by lithography or the like. The surface of the first buffer layer 130 has a plurality of regions 130a1 to 130an exposed by the plurality of openings 140a1 to 140an.

  The formed mask 140 includes an opening array 140a and a non-opening 140k. In the opening array 140a, a plurality of openings 140a1,..., 140an are two-dimensionally arranged. Each of the openings 140a1, ..., 140an exposes the first buffer layer 130. Each opening 140a1, ..., 140an has a shape along a hexagon. Each side of the hexagon is in a direction along the [10-10] direction, a direction along the [01-10] direction, and a direction along the [-1100] direction of a crystal body 60 to be described later on the base substrate 10. It extends along either. Each side of the hexagon extends, for example, along any one of the [11-20] direction, the [1-210] direction, and the [-2110] direction of the base substrate 10. The non-opening 140k does not expose the first buffer layer 130. The non-opening 140k extends in a honeycomb shape between the plurality of openings 140a1, ..., 140an.

  In the step shown in FIG. 15B, a plurality of gallium nitride first layers are formed from a plurality of regions 130a1 to 130an exposed by the plurality of openings 140a1 to 140an on the surface of the first buffer layer 130 by the HVPE method or the MOCVD method. Two buffer layers 150a1-150an are grown.

  In the step shown in FIG. 16A, a gallium nitride crystal 160 is grown on the plurality of second buffer layers 150a1 to 150an by the HVPE method, the MOCVD method, or the like.

  In the step shown in FIG. 16B, the mask 140 is removed. For example, the mask 140 is removed by selective etching. For example, when the material of the mask 140 is silicon oxide, the mask 140 can be selectively etched by using an HF solution or a BOE (buffered HF) solution.

  In the step shown in FIG. 16C, the first buffer layer 130 is selectively etched to separate the crystal body 160 from the base substrate 10. Thereby, the semiconductor substrate 170 can be obtained.

  In this manner, after forming the first buffer layer by nitriding the chromium layer, a mask including a plurality of openings is formed, and a plurality of regions exposed from the plurality of openings are exposed on the surface of the first buffer layer. A second buffer layer is grown. Accordingly, the plurality of second buffer layers 150a1 to 150an are separated from each other by the mask having a different crystal orientation from the second buffer layer. Thereby, it is possible to reduce propagation of internal stress in the crystal body 160 through the plurality of second buffer layers.

  Therefore, the generation of cracks in the crystal body 160 can be reduced. That is, according to the present embodiment, the generation of cracks when growing a group III nitride semiconductor crystal can be reduced.

10 Substrate 20 Chrome layer (metal layer)
30a1 to 30an, 130 First buffer layer 40 Mask 50a1 to 50an, 150a1 to 150an Second buffer layer 60, 160 Crystal 70, 170 Semiconductor substrate

Claims (9)

A metal layer forming step of forming a metal layer on the base substrate;
A mask forming step of forming a mask including a plurality of openings exposing each of the metal layers and a non-opening that does not expose the metal layers;
Nitriding a plurality of first buffer layers of metal nitride by nitriding a plurality of regions exposed by the plurality of openings in the metal layer; and
A second buffer layer forming step of forming a plurality of second buffer layers of a group III nitride semiconductor on the plurality of first buffer layers;
A growth step of growing a group III nitride semiconductor crystal on the plurality of second buffer layers;
With
Each of the plurality of openings has a shape along a hexagon,
In the mask formation step, the mask is formed so that the minimum width of each opening in the plurality of openings is 5 μm or more and 25 μm or less, and the width of the non-opening portion between adjacent openings is 1.5 μm or more and 8 μm or less. Forming ,
In the second buffer layer forming step, the plurality of second buffer layers are formed at a first temperature of 850 ° C. or more and 950 ° C. or less,
The growth step includes a first growth step for growing the crystal body at a second temperature higher than the first temperature, and a second growth step for growing the crystal body at a third temperature higher than the second temperature. Or a fourth step between the first temperature and the second temperature, the first growth step including growing the crystal at a second temperature higher than the first temperature. And a third growth step of growing the crystal body at a temperature . The base substrate has a crystal structure of either hexagonal system or pseudo-hexagonal system,
Each side of the hexagon is one of a direction to be along the [10-10] direction, a direction to be along the [01-10] direction, and a direction to be along the [-1100] direction of the crystal in the base substrate. The method of manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate extends along the line. The mask forming step includes
A mask layer forming step of forming a mask layer on the metal layer;
Forming the mask by forming the plurality of openings in the mask layer; and
The method for manufacturing a semiconductor substrate according to claim 1, wherein: A mask removal step of removing the mask;
A separation step of separating the crystal from the base substrate by selectively etching the first buffer layer;
Further semiconductor substrate manufacturing method according to any one of claims 1 to 3, further comprising a. A first buffer layer forming step of forming a first buffer layer on the base substrate;
Forming a mask including a plurality of openings exposing each of the first buffer layers and a non-opening not exposing the first buffer layers;
A second buffer layer forming step of forming a plurality of second buffer layers of a group III nitride semiconductor in a plurality of regions exposed by the plurality of openings on the surface of the first buffer layer;
A growth step of growing a group III nitride semiconductor crystal on the plurality of second buffer layers;
With
Each of the plurality of openings has a shape along a hexagon,
In the mask forming step, the mask is formed such that the minimum width of each opening in the plurality of openings is 5 μm or more and 25 μm or less, and the width of the non-opening portion between adjacent openings is 1.5 μm or more and 8 μm or less. Forming ,
In the second buffer layer forming step, the plurality of second buffer layers are formed at a first temperature of 850 ° C. or more and 950 ° C. or less,
The growth step includes a first growth step for growing the crystal body at a second temperature higher than the first temperature, and a second growth step for growing the crystal body at a third temperature higher than the second temperature. Or a fourth step between the first temperature and the second temperature, the first growth step including growing the crystal at a second temperature higher than the first temperature. And a third growth step of growing the crystal body at a temperature . The base substrate has a crystal structure of either hexagonal system or pseudo-hexagonal system,
Each side of the hexagon is one of a direction to be along the [10-10] direction, a direction to be along the [01-10] direction, and a direction to be along the [-1100] direction of the crystal in the base substrate. The method of manufacturing a semiconductor substrate according to claim 5 , wherein the semiconductor substrate extends along the line. Wherein the first buffer layer, a semiconductor substrate manufacturing method according to claim 5 or 6, characterized in that it comprises a metal nitride. The mask forming step includes
A mask layer forming step of forming a mask layer on the first buffer layer;
Forming the mask by forming the plurality of openings in the mask layer; and
Method for manufacturing a semiconductor substrate according to any one of claims 5 7, characterized in that it comprises a. A mask removal step of removing the mask;
A separation step of separating the crystal from the base substrate by selectively etching the first buffer layer;
Further semiconductor substrate manufacturing method according to any one of claims 5 to 8, comprising the.