JP4454183B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

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JP4454183B2
JP4454183B2 JP2001157697A JP2001157697A JP4454183B2 JP 4454183 B2 JP4454183 B2 JP 4454183B2 JP 2001157697 A JP2001157697 A JP 2001157697A JP 2001157697 A JP2001157697 A JP 2001157697A JP 4454183 B2 JP4454183 B2 JP 4454183B2
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wiring layer
wiring
layer
copper
gold plating
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JP2002353376A (en
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隆志 奥ノ薗
晶 芹野
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Description

【０００１】
【発明の属する技術分野】
本発明は、酸化アルミニウム質焼結体等のセラミックスを絶縁基体とする配線基板に関し、詳細には、銅を主成分とする低抵抗導体から成り、かつ絶縁基体と同時焼成によって形成された表面配線層を具備した配線基板に関するものである。
【０００２】
【従来の技術】
近年、半導体素子の高集積化に伴い、半導体装置から発生する熱も増加している。半導体装置の誤作動をなくすためには、このような熱を装置外に放出可能な配線基板が必要とされている。一方、電気的な特性としては、演算速度の高速化により、信号の遅延が問題となり、導体損失の小さい、つまり低抵抗の導体を用いることが要求されてきた。
【０００３】
このような半導体素子を搭載した配線基板としては、その信頼性の点から、アルミナセラミックスを絶縁基体とし、その表面あるいは内部にタングステンやモリブデンなどの高融点金属からなる配線層を被着形成したセラミック配線基板が多用されている。ところが、従来から多用されている高融点金属からなる配線層では、抵抗を高々８ｍΩ／□程度までしか低くできなかった。
【０００４】
これに対して、近年に至り、低抵抗導体である銅や銀と同時焼成可能な、いわゆるガラスセラミックスを用いた配線基板が提案されている。ところが、ガラスセラミックスの熱伝導率は高々数Ｗ／ｍ・Ｋしかなく、前記熱的問題を解決することが難しくなってきている。
【０００５】
そこで、この熱的問題と、電気的問題点を同時に解決する方法として、本出願人は先に酸化アルミニウムを主成分とし、マンガン化合物をＭｎＯ2換算で２．０〜６．０重量％の割合で含有する相対密度が９５％以上のセラミックスからなる絶縁基体と、該絶縁基体の少なくとも表面に該絶縁基体との同時焼成によって形成され、銅（Ｃｕ）を１０〜７０体積％、タングステン（Ｗ）及び／またはモリブデン（Ｍｏ）を３０〜９０体積％の割合で含有し、かつ銅からなるマトリックス中にタングステン及び／またはモリブデンが平均粒径１〜１０μｍの粒子として分散含有してなる配線層とから成る配線基板を提案した（特開平１０−２４４２３７号参照）。
【０００６】
この配線基板によれば、絶縁基体が酸化アルミニウム質焼結体等から成り、かつ相対密度が高く緻密であるため熱伝導性が、１０Ｗ／ｍ・ｋ以上と高く、また、配線層が低抵抗の銅を含有するためシート抵抗を約４ｍΩ／□と低くすることができる。
【０００７】
このような配線基板は、例えば、酸化アルミニウムを主成分とし、酸化マンガン（ＭｎＯ2）を２．０〜６．０重量％の割合で含有するセラミック成分を含有するグリーンシートの表面に、銅粉末を１０〜７０体積％、平均粒径が１〜１０μｍのタングステン及び／またはモリブデンを３０〜９０体積％の割合で含有してなる導体ペーストを回路パターン状に印刷塗布した後、該グリーンシートを積層し、非酸化性雰囲気中で最高焼成温度が１２００℃〜１５００℃となる条件で焼成することによって製作される。
【０００８】
【発明が解決しようとする課題】
しかしながら、上記配線基板は配線層のシート抵抗が約４ｍΩ／□と従来品に比し低いものの、ミリ波帯、マイクロ波帯の高周波信号を使用する半導体素子が搭載され、配線層に高周波信号が伝播された場合には電気抵抗はまだまだ大きく、伝播する高周波信号にロスを発生させてしまうためより一層低抵抗とする必要がある。
【０００９】
また上記配線層がタングステン及び／またはモリブデンと、銅とから成り酸化しやすいことから、配線層の露出表面から酸化が進行して配線層（特に表面領域）の電気抵抗が経時的に増大し、配線層に高周波信号が伝播された場合の高周波信号のロスをより一層大きなものとしてしまうため、この配線層の抵抗増大を抑える必要もある。
【００１０】
そこで配線層の表面に低電気抵抗で、かつ耐食性に優れた金から成るめっき層を被着させておくことが考えられる。
【００１１】
しかしながら、配線層の表面に金めっき層を被着させた場合、配線層にはタングステンやモリブデンといった金めっき層に対して密着性の悪い金属が含有されており、配線層と金めっき層との密着強度が弱いこと、金は半田等の低融点ロウ材に対して拡散し易いこと等から配線層に半導体素子を錫−鉛半田等の低融点ロウ材を介して接合したり、配線層を外部電気回路基板の配線導体に低融点ロウ材を介して接合したりする際、金めっき層が低融点ロウ材に容易に拡散吸収されて低融点ロウ材と接する配線層表面に前記低融点ロウ材と接合性の悪いタングステンやモリブデンが現われてしまい、その結果、低融点ロウ材の配線層に対する接合強度が劣化し、接合の信頼性が大きく低下するという欠点が誘発されてしまう。
【００１２】
本発明は上記欠点に鑑み案出されたもので、その目的は配線基板の熱伝導性を高くし、かつ電気抵抗を高周波信号の伝播においても問題とならないような小さな値としたミリ波帯、マイクロ波帯の高周波信号を使用する半導体素子の搭載が可能な量産性に優れた配線基板を提供することにある。
【００１３】
【課題を解決するための手段】
本発明の配線基板の製造方法は、熱伝導率が１０Ｗ／ｍ・Ｋ以上のセラミックス焼結体から成る絶縁基体に、該絶縁基体との同時焼成により一体的にタングステンおよび／またはモリブデンと銅とから成る配線層を形成する工程と、該配線層の露出表面に金めっき層を被着させる工程と、非酸化雰囲気中で、９００℃〜１１００℃の温度で熱処理して、前記配線層と前記金めっき層とを拡散接合させる工程とを具備することを特徴とするものである。
【００１４】
本発明の配線基板の製造方法によれば、絶縁基体を熱伝導率が１０Ｗ／ｍ・Ｋ以上のセラミックス焼結体で形成することから、得られる配線基板は熱伝導率が良好で、半導体装置の熱を装置外に効率よく放散させることができ、半導体装置を常に適温として半導体装置を長期間にわたり正常、かつ安定に作動させることができる。
【００１５】
また本発明の配線基板の製造方法によれば、配線層をタングステンおよび／またはモリブデンと銅とで形成し、かつ表面に金めっき層を被着させることから、電気抵抗が極めて小さな値となるとともに、配線層の酸化を効果的に防止することができ、その結果、ミリ波帯やマイクロ波帯の高周波信号も、常に、ほとんどロスを発生させることなく伝播させることができる。
【００１６】
更に本発明の配線基板の製造方法によれば、非酸化雰囲気中で、９００℃〜１１００℃の温度で熱処理して、配線層と金めっき層とを拡散接合させることから、金めっき層の配線層に対する接合強度が極めて強く、そのため配線層に半導体素子を錫−鉛半田等の低融点ロウ材を介して接合したり、配線層を外部電気回路基板の配線導体に低融点ロウ材を介して接合したりしても金めっき層が低融点ロウ材に拡散吸収されて該低融点ロウ材が接する配線層表面にタングステンやモリブデンが現われることはほとんどなく、その結果、低融点ロウ材の配線層に対する接合強度が極めて強く、接合の信頼性を極めて良好なものとなすことができる。
【００１７】
【発明の実施の形態】
以下に、本発明の配線基板の製造方法の一実施例について、添付の図面を基に説明する。
【００１８】
図１は本発明の製造方法によって得られる配線基板を使用した半導体素子収納用パッケージの一実施例を示す断面図であり、１は絶縁基体、２は配線層である。この絶縁基体１と配線層２とで半導体素子３を搭載する配線基板４が構成される。
【００１９】
（絶縁基体）
本発明において、絶縁基体１は半導体素子を搭載、支持する基体として作用し、酸化アルミニウム質焼結体、窒化アルミニウム質焼結体、炭化珪素質焼結体、等の熱伝導率が１０Ｗ／ｍ・Ｋ以上のセラミック焼結体により形成されている。
【００２０】
また前記絶縁基体１は、その熱伝導性および高強度化を達成する上では、相対密度９５％以上の高緻密体から構成されるものであることが望ましい。
【００２１】
更に本発明では、前記絶縁基体１は、配線層２との同時焼結時による保形性を達成する上では、１２００℃〜１５００℃の低温で焼成することが必要となるが、本発明によれば、このような低温での焼成においても相対密度９５％以上に緻密化することが必要となる。
【００２２】
かかる観点から、本発明における絶縁基体１は、例えば、酸化アルミニウムを主成分とするもの、具体的には酸化アルミニウムを９０重量％以上の割合で含有するものが好適に使用され、第２の成分として、Ｍｎ化合物をＭｎＯ2換算で２．０〜６．０重量％の割合で含有することが望ましい。即ち、マンガン化合物が２．０重量％よりも少ないと、１２００℃〜１５００℃での緻密化が達成されにくく、また６．０重量％よりも多いと絶縁基体１の絶縁性が低下する。マンガン化合物の最適な範囲は、ＭｎＯ2換算で３〜５重量％である。
【００２３】
また、この絶縁基体１中には、第３の成分として、ＳｉＯ2およびＭｇＯ、ＣａＯ、ＳｒＯ等のアルカリ土類元素酸化物を銅含有導体との同時焼結性を高める上で合計で０．４〜８重量％の割合で含有せしめることが望ましい。
【００２４】
さらに第４の成分としてタングステン、モリブデンなどの金属を着色成分として２重量％以下の割合で含んでもよい。
【００２５】
上記酸化アルミニウム以外の成分は、酸化アルミニウム主結晶相の粒界に非晶質相あるいは結晶相として存在するが、熱伝導性を高める上で粒界中に助剤成分を含有する結晶相が形成されていることが望ましい。
【００２６】
また前記絶縁基体１を、酸化アルミニウムを主成分として形成した場合、酸化アルミニウム主結晶相は、粒状または柱状の結晶として存在するが、これら主結晶相の平均結晶粒径は、１．５〜５．０μｍであることが望ましい。
【００２７】
なお、主結晶相が柱状結晶からなる場合、上記平均結晶粒径は、短軸径に基づくものである。この主結晶相の平均結晶粒径が１．５μｍよりも小さいと、高熱伝導化が難しく、平均粒径が５．０μｍよりも大きいと基板材料として用いる場合に要求される十分な強度が得られにくくなるためである。
【００２８】
（配線層）
前記配線層２は、配線基板４に搭載された半導体素子３の電極をボンディングワイヤ５等を介して接続させる接続パッドとして作用するとともに、この半導体素子３の電極を外部電気回路基板に錫−鉛半田等の低融点ロウ材を介して接続させるための導電路として作用する。
【００２９】
前記配線層２は、銅を１０〜７０体積％、タングステン及び／またはモリブデンを３０〜９０体積％の割合で含有することが必要である。これは、配線層２の低抵抗化と、上記絶縁基体１との同時焼結性を達成するとともに、表面の配線層２の同時焼成後の保形性を維持するためであり、上記銅が１０体積％よりも少なく、タングステンやモリブデン量が９０体積％よりも多いと、配線層のシート抵抗が高くなる。また、銅量が７０体積％よりも多く、タングステンやモリブデン量が３０体積％よりも少ないと、表面の配線層２の同時焼成後の保形性が低下し、表面の配線層２においてにじみなどが発生したり、溶融した銅によって表面の配線層２が凝集して断線が生じるとともに、絶縁基体１と配線層２の熱膨張係数差により配線層２の剥離が発生するためである。最適な組成範囲は、銅を４０〜６０体積％、タングステン及び／またはモリブデンを６０〜４０体積％である。
【００３０】
また本発明においては、前記タングステン及び／またはモリブデンは、平均粒径１〜１０μｍの球状あるいは数個の粒子による凝集粒子として銅からなるマトリックス中に分散含有していることが望ましい。これは、上記平均粒径が１．０μｍよりも小さい場合、表面の配線層２の保形性が悪くなるとともに組織が多孔質化し配線層２の抵抗も高くなり、１０μｍを超えると銅のマトリックスがタングステンやモリブデンの粒子によって分断されてしまい配線層２の抵抗が高くなったり、銅成分が分離してにじみなどが発生するためである。タングステン及び／またはモリブデンは平均粒径１．３〜５μｍ、特に１．３〜３μｍの大きさで分散されていることが最も望ましい。
【００３１】
また、上記配線層２中には、絶縁基体１との密着性を改善するために、酸化アルミニウム、または絶縁基体と同じ成分のセラミックスを０．０５〜２体積％の割合で含有させることも可能である。
【００３２】
さらに、本発明の配線基板４においては、酸化アルミニウムとの銅の融点を超える温度での同時焼成によって、配線層２中の銅成分が絶縁基体１中に拡散する場合があるが、本発明によれば、上記少なくとも銅を含む配線層２の周囲の絶縁基体１のセラミックスへの銅の拡散距離が２０μｍ以下、特に１０μｍ以下であることが望ましい。これは、銅のセラミックス中への拡散距離が２０μｍを超えると、配線層２間の絶縁性が低下し、配線基板としての信頼性が低下するためである。
【００３３】
この銅の拡散距離を２０μｍ以下とすることにより、前記配線層２のうち、同一平面内に形成された配線層２間の最小線間距離を１００μｍ以下、特に９０μｍ以下の高密度配線化を図ることができる。また、同様に図１に示すように、１つの絶縁層内に複数のビアホール導体６が形成される場合、そのビアホール導体６間の最小離間距離も上記と同様な理由から１００μｍ以下、特に９０μｍ以下に制御することが可能である。
【００３４】
さらにまた、本発明の配線基板４は、焼成温度及び雰囲気を制御して焼成することによって、絶縁基体１の表面の平均表面粗さＲａを１μｍ以下、特に０．７μｍ以下の平滑性に優れた表面を形成できるものであり、その結果、絶縁基体１の表面に配線層２を形成する場合、絶縁基体１表面を研磨加工等を施す必要がないことも大きな特徴である。
【００３５】
（配線基板４の形成方法）
上記配線基板４は、例えば酸化アルミニウムを主成分とするセラミックス焼結体から成る場合、以下のようにして形成される。即ち、
（１）まず、絶縁基体１を形成するために、セラミックス焼結体の主成分となる酸化アルミニウム原料粉末として、平均粒径が０．５〜２．５μｍ、特に０．５μｍ〜２．０μｍの粉末を用いる。これは、平均粒径は０．５μｍよりも小さいと、粉末の取扱が難しく、また粉末のコストが高くなり、２．５μｍよりも大きいと、１５００℃以下の温度で焼成することが難しくなるためである。
【００３６】
そして、上記酸化アルミニウム粉末に対して、第２成分として、ＭｎＯ2を２．０〜６．０重量％、特に３．０〜５．０重量％の割合で添加する。また適宜、第３の成分として、ＳｉＯ2、ＭｇＯ、ＣａＯ、ＳｒＯ2粉末等を０．４〜８重量％、第４の成分として、Ｗ、Ｍｏ、Ｃｒなどの遷移金属の金属粉末や酸化物粉末を着色成分として金属換算で２重量％以下の割合で添加する。
【００３７】
なお、上記酸化物の添加にあたっては、酸化物粉末以外に、焼成によって酸化物を形成し得る炭酸塩、硝酸塩、酢酸塩などとして添加してもよい。
【００３８】
そして次に、この混合粉末を用いて絶縁基体１を形成するためのシート状成形体を作製する。シート状成形体は、周知の成形方法によって作製することができる。例えば、上記混合粉末に有機バインダーや溶媒を添加してスラリーを調整した後、ドクターブレード法によって形成したり、混合粉末に有機バインダーを加え、プレス成形、圧延成形等により所定の厚みのシート状成形体を作製できる。
【００３９】
このようにして作製したシート状成形体に対して、導体成分として、平均粒径が１〜１０μｍの銅含有粉末を１０〜７０体積％、特に４０〜６０体積％、平均粒径が１〜１０μｍのタングステン及び／またはモリブデンを３０〜９０体積％、特に４０〜６０体積％の割合で含有してなる導体ペーストを調整し、このペーストを各シート状絶縁層にスクリーン印刷、グラビア印刷等の手法によって印刷塗布する。
【００４０】
なお、前記導体ペースト中には、絶縁層との密着性を高めるために、酸化アルミニウム粉末や、絶縁層を形成する酸化物セラミックス成分と同一の組成物粉末を０．０５〜２体積％の割合で添加することも可能である。
【００４１】
そして最後に、導体ペーストを印刷塗布したシート状成形体を位置合わせして積層圧着した後、この積層体を、非酸化性雰囲気中、焼成最高温度が１２００〜１５００℃の温度となる条件で焼成する。
【００４２】
このときの焼成温度が１２００℃より低いと、通常の原料を用いた場合において、酸化アルミニウム絶縁基体が相対密度９５％以上まで緻密化できず、熱伝導性や強度が低下し、１５００℃よりも高いと、タングステンあるいはモリブデン自体の焼結が進み、銅との均一組織を維持できなく、ひいては低抵抗を維持することが困難となりシート抵抗が高くなってしまう。また、酸化物セラミックスの主結晶相の粒径が大きくなり異常粒成長が発生したり、銅がセラミックス中へ拡散するときのパスである粒界の長さが短くなるとともに拡散速度も速くなる結果、拡散距離を３０μｍ以下に制御することが困難となるためである。好適には１２５０〜１４００℃の範囲がよい。
【００４３】
また、この焼成時の非酸化性雰囲気としては、窒素、あるいは窒素と水素との混合雰囲気であることが望ましいが、特に、配線層中の銅の拡散を制御する上では、水素及び窒素を含み露点＋１０℃以下、特に−１０℃以下の非酸化性雰囲気であることが望ましい。なお、この雰囲気には所望により、アルゴンガス等の不活性ガスを混入してもよい。焼成時の露点が＋１０℃より高いと、焼成中に酸化物セラミックスと雰囲気中の水分とが反応し酸化膜を形成し、この酸化膜と銅含有導体の銅が反応してしまい、導体の低抵抗化の妨げとなるのみでなく、銅の拡散を助長してしまうためである。
【００４４】
また前記配線基板４は、図２に示す如く、配線層２の露出表面に金めっき層７が被着され配線層２と金めっき層７とは拡散接合されている。拡散接合させることにより、配線層２と金めっき層７との間に金／銅の拡散層７ａが形成され、この拡散層７ａを介して配線層２と金めっき層７とが強固に接合する。
【００４５】
前記金めっき層７、および金／銅の拡散層７ａは、この配線基板４の配線層２に、電気信号を伝播させる主導体として作用し、低抵抗の金または金／銅から成ることから、配線層２の電気抵抗を、ミリ波帯、マイクロ波帯の高周波信号を伝播させる場合であっても問題とならないような小さな値となす作用を有する。
【００４６】
また同時に、前記金めっき層７は、配線層２および金／銅拡散層７ａの銅が酸化することを防止する作用をなし、配線層２が酸化することにともなう電気抵抗の増大を有効に防止することができる。
【００４７】
なお、前記金めっき層７および金／銅拡散層７ａは、その合計の厚みが０．５μｍ以上、かつ金めっき層の厚みが０．１μｍ以上と成るように形成しておくと、配線層２を十分に低抵抗とすることができるとともに、配線層２の酸化をより一層効果的に防止することができる。従って、前記金めっき層７および金／銅拡散層７ａは、その合計の厚みが０．５μｍ以上、かつ金めっき層の厚みが０．１μｍ以上と成るように形成しておくことが好ましく、経済性を考慮すれば、合計厚みが２μｍ以下となるように形成しておくことがより一層好ましい。
【００４８】
前記金めっき層７は、例えば、シアン化金カリウムを主成分とし、電気伝導塩類、ｐＨ調整剤等を添加してなる周知のシアン系電解金めっき液中に配線層２を浸漬するとともに所定の電流密度・時間でめっき用電力を供給することにより、配線層２の露出面に所定厚みに被着される。
【００４９】
なお、前記金めっきの際、予め、配線層２の表面に露出しているタングステンおよび／またはモリブデンを水酸化カリウムおよびフェリシアン化物を主成分とする水溶液等の強アルカリ性溶液でエッチング除去し、配線層２の表面に主として銅が露出するようにしておくことが好ましく、金めっき層７の配線層２表面への析出形成を容易とし、同時に、金めっき層７の被着強度を強くすることができる。
【００５０】
また、このような配線層２と金めっき層７との間の拡散接合は、配線層２の表面に金めっき層７を被着させたあと、配線基板４を、非酸化雰囲気中、金（融点：約１０６０℃）および銅（融点：約１０９０℃）の融点付近の温度、例えば９００℃〜１１００℃、より好ましくは９５０℃〜１０４０℃で熱処理することにより行なう。
【００５１】
また、この熱処理条件、例えば最高処理温度のキープ時間を適宜調整することにより、金／銅拡散層７ａの厚みを制御することができる。
【００５２】
かくして本発明の製造方法によって得られる配線基板によれば、絶縁基体１の半導体素子搭載部１ａ上に半導体素子３を搭載するとともにこの半導体素子３の各電極を配線層２にボンディングワイヤ５を介して電気的に接続し、しかる後、絶縁基体１の上面に金属やセラミックスから成る椀状の蓋体８をガラスや樹脂、ロウ材等の封止材を介して接合させ、絶縁基体１と蓋体８とから成る容器内部に半導体素子３を気密に収容することによって製品としての半導体装置が完成し、半導体素子３は配線層２等を介して外部電気回路に接続されることとなる。
【００５３】
なお本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば、上述の実施例では金めっき層７を電解めっき法により形成したが、これを、置換型の無電解金めっき液と、還元型の無電解金めっき液とに配線層２を順次浸漬する無電解めっき法により形成してもよい。
【００５４】
また上述の実施例では本発明の製造方法によって得られる配線基板を半導体素子収納用パッケージに適用したが、混成集積回路基板等の他の用途に適用してもよい。
【００５５】
【発明の効果】
本発明の配線基板の製造方法によれば、絶縁基体を熱伝導率が１０Ｗ／ｍ・Ｋ以上のセラミックス焼結体で形成することから、得られる配線基板は熱伝導率が良好で、半導体装置の熱を装置外に効率よく放散させることができ、半導体装置を常に適温として半導体装置を長期間にわたり正常、かつ安定に作動させることができる。
【００５６】
また本発明の配線基板の製造方法によれば、配線層をタングステンおよび／またはモリブデンと銅とで形成し、かつ表面に金めっき層を被着させることから、電気抵抗が極めて小さな値となるとともに、配線層の酸化を効果的に防止することができ、その結果、ミリ波帯やマイクロ波帯の高周波信号も、常に、ほとんどロスを発生させることなく伝播させることができる。
【００５７】
更に本発明の配線基板の製造方法によれば、非酸化雰囲気中で、９００℃〜１１００℃の温度で熱処理して、配線層と金めっき層とを拡散接合させることから、金めっき層の配線層に対する接合強度が極めて強く、そのため配線層に半導体素子を錫−鉛半田等の低融点ロウ材を介して接合したり、配線層を外部電気回路基板の配線導体に低融点ロウ材を介して接合したりしても金めっき層が低融点ロウ材に拡散吸収されて該低融点ロウ材が接する配線層表面にタングステンやモリブデンが現われることはほとんどなく、その結果、低融点ロウ材の配線層に対する接合強度が極めて強く、接合の信頼性を極めて良好なものとなすことができる。
【図面の簡単な説明】
【図１】本発明の製造方法によって得られる配線基板を半導体素子を収容する半導体素子収納用パッケージに適用した場合の一実施例を示す断面図である。
【図２】本発明の製造方法によって得られる配線基板の要部断面図である。
【符号の説明】
１・・・・・絶縁基体
２・・・・・配線層
３・・・・・半導体素子
４・・・・・配線基板
５・・・・・ボンディングワイヤ
６・・・・・ビアホール導体
７・・・・・金めっき層
７ａ・・・・金／銅拡散接合層
８・・・・・蓋体[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board having an insulating base made of ceramics such as an aluminum oxide sintered body, and more specifically, a surface wiring made of a low-resistance conductor mainly composed of copper and formed by simultaneous firing with the insulating base. The present invention relates to a wiring board having a layer.
[0002]
[Prior art]
In recent years, heat generated from a semiconductor device has been increased with higher integration of semiconductor elements. In order to eliminate the malfunction of the semiconductor device, a wiring substrate capable of releasing such heat to the outside of the device is required. On the other hand, as an electrical characteristic, signal delay becomes a problem due to an increase in calculation speed, and it has been required to use a conductor having a small conductor loss, that is, a low resistance.
[0003]
As a wiring board on which such a semiconductor element is mounted, a ceramic in which alumina ceramics is used as an insulating base and a wiring layer made of a refractory metal such as tungsten or molybdenum is deposited on the surface or inside thereof from the viewpoint of reliability. Wiring boards are frequently used. However, in a wiring layer made of a refractory metal that has been widely used in the past, the resistance can only be lowered to about 8 mΩ / □.
[0004]
On the other hand, in recent years, a wiring substrate using so-called glass ceramics that can be fired simultaneously with copper and silver which are low resistance conductors has been proposed. However, since the thermal conductivity of glass ceramics is only a few W / m · K, it is difficult to solve the thermal problem.
[0005]
Therefore, as a method for simultaneously solving the thermal problem and the electrical problem, the present applicant has previously made aluminum oxide as a main component and manganese compound in a ratio of 2.0 to 6.0% by weight in terms of MnO 2. And an insulating substrate made of ceramics having a relative density of 95% or more, and at least the surface of the insulating substrate is formed by co-firing with the insulating substrate, and contains 10 to 70% by volume of copper (Cu) and tungsten (W). And / or a wiring layer containing molybdenum (Mo) in a proportion of 30 to 90% by volume and containing tungsten and / or molybdenum dispersed in a matrix made of copper as particles having an average particle diameter of 1 to 10 μm. A wiring board was proposed (see Japanese Patent Laid-Open No. 10-244237).
[0006]
According to this wiring board, the insulating base is made of an aluminum oxide sintered body and the like, and since the relative density is high and dense, the thermal conductivity is as high as 10 W / m · k or more, and the wiring layer has a low resistance. Therefore, the sheet resistance can be lowered to about 4 mΩ / □.
[0007]
Such a wiring board has, for example, copper powder on the surface of a green sheet containing a ceramic component containing aluminum oxide as a main component and manganese oxide (MnO 2 ) in a proportion of 2.0 to 6.0% by weight. A conductive paste containing 10 to 70% by volume of tungsten and / or molybdenum having an average particle diameter of 1 to 10 μm in a proportion of 30 to 90% by volume is printed and applied in a circuit pattern, and then the green sheet is laminated. Then, it is manufactured by firing in a non-oxidizing atmosphere under conditions where the maximum firing temperature is 1200 ° C to 1500 ° C.
[0008]
[Problems to be solved by the invention]
However, although the wiring board has a sheet resistance of about 4 mΩ / □, which is lower than that of the conventional product, a semiconductor element using high-frequency signals in the millimeter wave band and microwave band is mounted, and the high-frequency signal is transmitted to the wiring layer. When propagated, the electrical resistance is still large, and a loss is generated in the propagating high-frequency signal. Therefore, it is necessary to further reduce the resistance.
[0009]
In addition, since the wiring layer is made of tungsten and / or molybdenum and copper and easily oxidizes, oxidation proceeds from the exposed surface of the wiring layer, and the electrical resistance of the wiring layer (particularly the surface region) increases with time. In order to further increase the loss of the high frequency signal when the high frequency signal is propagated to the wiring layer, it is necessary to suppress an increase in resistance of the wiring layer.
[0010]
Therefore, it is conceivable to deposit a plating layer made of gold having low electrical resistance and excellent corrosion resistance on the surface of the wiring layer.
[0011]
However, when a gold plating layer is deposited on the surface of the wiring layer, the wiring layer contains a metal having poor adhesion to the gold plating layer, such as tungsten or molybdenum. Since the adhesion strength is weak and gold is easy to diffuse into a low melting point solder such as solder, a semiconductor element is joined to the wiring layer via a low melting point solder such as tin-lead solder, or the wiring layer is When bonding to the wiring conductor of the external electric circuit board via the low melting point brazing material, the gold plating layer is easily diffused and absorbed by the low melting point brazing material, and the low melting point brazing material is formed on the surface of the wiring layer in contact with the low melting point brazing material. As a result, tungsten or molybdenum having poor bonding properties to the material appears, and as a result, the bonding strength of the low melting point brazing material to the wiring layer is deteriorated, and the defect that the reliability of bonding is greatly reduced is induced.
[0012]
The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to increase the thermal conductivity of the wiring board, and to set the electrical resistance to a small value that does not cause a problem in the propagation of high-frequency signals, An object of the present invention is to provide a wiring substrate excellent in mass productivity that can be mounted with a semiconductor element using a high frequency signal in a microwave band.
[0013]
[Means for Solving the Problems]
A method for manufacturing a wiring board of the present invention, the insulating base thermal conductivity consisting of 10 W / m · K or more ceramic sintered body, one body to data tungsten Ri by the simultaneous firing of the insulating substrate and / or A step of forming a wiring layer made of molybdenum and copper , a step of depositing a gold plating layer on the exposed surface of the wiring layer, and a heat treatment at a temperature of 900 ° C. to 1100 ° C. in a non-oxidizing atmosphere, and the gold plating layer and a wiring layer in which characterized that you and a step of diffusion bonding.
[0014]
According to the method for manufacturing a wiring board of the present invention, since the insulating base is formed of a ceramic sintered body having a thermal conductivity of 10 W / m · K or more , the obtained wiring board has a good thermal conductivity, and the semiconductor device This heat can be efficiently dissipated outside the device, and the semiconductor device can be operated normally and stably over a long period of time by keeping the semiconductor device at an appropriate temperature.
[0015]
According to the method for manufacturing a wiring board of the present invention, a wiring layer is formed by tungsten and / or molybdenum and copper, and since the gold plating layer Ru is deposited on the surface, the electric resistance is extremely small value At the same time, oxidation of the wiring layer can be effectively prevented, and as a result, high-frequency signals in the millimeter wave band and microwave band can always be propagated with almost no loss.
[0016]
Further, according to the manufacturing method of the wiring substrate of the present invention, in a non-oxidizing atmosphere, it was heat-treated at a temperature of 900 ° C. C. to 1100 ° C., since the wiring layer and a gold plating layer Ru are diffused junction, a gold plating layer Bonding strength to the wiring layer is extremely strong, so that a semiconductor element is bonded to the wiring layer via a low melting point solder such as tin-lead solder, or the wiring layer is connected to a wiring conductor of an external electric circuit board via a low melting point brazing material. Even if they are joined together, the gold plating layer is diffused and absorbed by the low melting point brazing material, and tungsten or molybdenum hardly appears on the surface of the wiring layer where the low melting point brazing material is in contact. The bonding strength to the layer is extremely strong, and the bonding reliability can be made extremely good.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to the accompanying drawings.
[0018]
Figure 1 is a view to a cross-sectional view of one embodiment of a package for housing semiconductor chip using a wiring substrate obtained by the production method of the present invention, 1 denotes an insulating substrate, 2 denotes a wiring layer. The insulating substrate 1 and the wiring layer 2 constitute a wiring board 4 on which the semiconductor element 3 is mounted.
[0019]
(Insulating substrate)
In the present invention, the insulating substrate 1 acts as a substrate for mounting and supporting a semiconductor element, and the thermal conductivity of an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, etc. is 10 W / m. -It is formed of a ceramic sintered body of K or more.
[0020]
Further, in order to achieve the thermal conductivity and high strength, the insulating substrate 1 is preferably composed of a highly dense body having a relative density of 95% or more.
[0021]
Furthermore, in the present invention, the insulating substrate 1 needs to be fired at a low temperature of 1200 ° C. to 1500 ° C. in order to achieve shape retention by simultaneous sintering with the wiring layer 2. Therefore, it is necessary to densify to a relative density of 95% or higher even in such low-temperature firing.
[0022]
From this point of view, the insulating base 1 in the present invention is preferably, for example, one having aluminum oxide as a main component, specifically, one containing aluminum oxide in a proportion of 90% by weight or more. as the Mn compound is desirably contained in an amount of 2.0-6.0% by weight MnO 2 basis. That is, when the manganese compound is less than 2.0% by weight, densification at 1200 ° C. to 1500 ° C. is difficult to achieve, and when it is more than 6.0% by weight, the insulating property of the insulating substrate 1 is lowered. The optimum range of the manganese compound is 3 to 5% by weight in terms of MnO 2 .
[0023]
In addition, in this insulating base 1, as a third component, an alkaline earth element oxide such as SiO 2 and MgO, CaO, SrO, etc. is added in a total amount of 0. It is desirable to make it contain in the ratio of 4-8 weight%.
[0024]
Furthermore, a metal such as tungsten or molybdenum may be contained as a coloring component in a proportion of 2% by weight or less as the fourth component.
[0025]
Components other than the above-mentioned aluminum oxide exist as an amorphous phase or a crystalline phase at the grain boundary of the aluminum oxide main crystal phase, but a crystal phase containing an auxiliary component is formed in the grain boundary in order to improve thermal conductivity. It is desirable that
[0026]
When the insulating substrate 1 is formed with aluminum oxide as a main component, the aluminum oxide main crystal phase exists as a granular or columnar crystal, and the average crystal grain size of these main crystal phases is 1.5 to 5 It is desirable that the thickness is 0.0 μm.
[0027]
In addition, when the main crystal phase is composed of columnar crystals, the average crystal grain size is based on the minor axis diameter. When the average crystal grain size of the main crystal phase is smaller than 1.5 μm, it is difficult to achieve high thermal conductivity, and when the average grain size is larger than 5.0 μm, sufficient strength required for use as a substrate material can be obtained. This is because it becomes difficult.
[0028]
(Wiring layer)
The wiring layer 2 functions as a connection pad for connecting the electrode of the semiconductor element 3 mounted on the wiring board 4 via the bonding wire 5 and the like, and the electrode of the semiconductor element 3 is tin-leaded to the external electric circuit board. It acts as a conductive path for connection via a low melting point solder such as solder.
[0029]
The wiring layer 2 needs to contain 10 to 70% by volume of copper and 30 to 90% by volume of tungsten and / or molybdenum. This is to reduce the resistance of the wiring layer 2 and to achieve simultaneous sintering with the insulating base 1 and to maintain the shape retention after simultaneous firing of the wiring layer 2 on the surface. If the amount is less than 10% by volume and the amount of tungsten or molybdenum is more than 90% by volume, the sheet resistance of the wiring layer is increased. On the other hand, if the amount of copper is more than 70% by volume and the amount of tungsten or molybdenum is less than 30% by volume, the shape retention after the co-firing of the surface wiring layer 2 is reduced, and the surface wiring layer 2 is smudged. This is because the wiring layer 2 on the surface is agglomerated due to the molten copper and disconnection occurs due to the molten copper, and peeling of the wiring layer 2 occurs due to a difference in thermal expansion coefficient between the insulating base 1 and the wiring layer 2. The optimum composition range is 40-60% by volume of copper and 60-40% by volume of tungsten and / or molybdenum.
[0030]
In the present invention, the tungsten and / or molybdenum is preferably dispersed and contained in a matrix made of copper as spherical particles having an average particle diameter of 1 to 10 μm or agglomerated particles of several particles. This is because when the average particle size is smaller than 1.0 μm, the shape retention of the wiring layer 2 on the surface is deteriorated, the structure becomes porous, and the resistance of the wiring layer 2 is increased. This is because the resistance of the wiring layer 2 is increased due to being divided by tungsten or molybdenum particles, and the copper component is separated and bleeding occurs. Most preferably, the tungsten and / or molybdenum is dispersed with an average particle size of 1.3 to 5 μm, particularly 1.3 to 3 μm.
[0031]
Further, in order to improve the adhesion to the insulating substrate 1, the wiring layer 2 can contain aluminum oxide or ceramics having the same component as that of the insulating substrate in a ratio of 0.05 to 2% by volume. It is.
[0032]
Furthermore, in the wiring board 4 of the present invention, the copper component in the wiring layer 2 may diffuse into the insulating substrate 1 by simultaneous firing at a temperature exceeding the melting point of copper with aluminum oxide. Therefore, it is desirable that the copper diffusion distance to the ceramic of the insulating base 1 around the wiring layer 2 containing at least copper is 20 μm or less, particularly 10 μm or less. This is because if the diffusion distance of copper into the ceramic exceeds 20 μm, the insulation between the wiring layers 2 is lowered and the reliability as a wiring board is lowered.
[0033]
By setting the copper diffusion distance to 20 μm or less, the wiring layer 2 has a minimum wiring distance of 100 μm or less, particularly 90 μm or less between the wiring layers 2 formed in the same plane. be able to. Similarly, as shown in FIG. 1, when a plurality of via-hole conductors 6 are formed in one insulating layer, the minimum separation distance between the via-hole conductors 6 is also 100 μm or less, particularly 90 μm or less for the same reason as described above. It is possible to control.
[0034]
Furthermore, the wiring board 4 of the present invention is excellent in smoothness with an average surface roughness Ra of 1 μm or less, particularly 0.7 μm or less, by firing by controlling the firing temperature and atmosphere. The surface can be formed, and as a result, when the wiring layer 2 is formed on the surface of the insulating base 1, it is not necessary to polish the surface of the insulating base 1 or the like.
[0035]
(Method for forming wiring board 4)
For example, when the wiring substrate 4 is made of a ceramic sintered body mainly composed of aluminum oxide, the wiring substrate 4 is formed as follows. That is,
(1) First, in order to form the insulating substrate 1, the aluminum oxide raw material powder as the main component of the ceramic sintered body has an average particle size of 0.5 to 2.5 μm, particularly 0.5 to 2.0 μm. Use powder. This is because if the average particle size is smaller than 0.5 μm, it is difficult to handle the powder, and the cost of the powder becomes high, and if it is larger than 2.5 μm, it is difficult to fire at a temperature of 1500 ° C. or less. It is.
[0036]
Then, with respect to the aluminum oxide powder, as a second component, the addition of MnO 2 2.0 to 6.0 wt%, in particular in a proportion of 3.0 to 5.0 wt%. In addition, SiO 3 , MgO, CaO, SrO 2 powder or the like is 0.4 to 8% by weight as the third component, and transition metal metal powder or oxide such as W, Mo, or Cr is used as the fourth component. Powder is added as a coloring component in a proportion of 2% by weight or less in terms of metal.
[0037]
In addition to the oxide powder, the oxide may be added as carbonate, nitrate, acetate, or the like that can form an oxide by firing.
[0038]
Next, a sheet-like molded body for forming the insulating substrate 1 is produced using this mixed powder. The sheet-like molded body can be produced by a known molding method. For example, after adjusting the slurry by adding an organic binder or solvent to the above mixed powder, it is formed by a doctor blade method, or an organic binder is added to the mixed powder, and sheet-like molding with a predetermined thickness is performed by press molding, rolling molding, etc. The body can be made.
[0039]
The copper-containing powder having an average particle size of 1 to 10 μm as the conductor component is 10 to 70% by volume, particularly 40 to 60% by volume, and the average particle size is 1 to 10 μm as a conductor component. A conductor paste containing 30 to 90% by volume, especially 40 to 60% by volume of tungsten and / or molybdenum is prepared, and this paste is applied to each sheet-like insulating layer by a method such as screen printing or gravure printing. Apply printing.
[0040]
In addition, in the said conductor paste, in order to improve adhesiveness with an insulating layer, the ratio of 0.05-2 volume% of aluminum oxide powder and the same composition powder as the oxide ceramic component which forms an insulating layer It is also possible to add at.
[0041]
And finally, after aligning and laminating and pressure-bonding the sheet-like molded body on which the conductive paste is printed and applied, the laminated body is fired in a non-oxidizing atmosphere under conditions where the firing maximum temperature is 1200 to 1500 ° C. To do.
[0042]
If the firing temperature at this time is lower than 1200 ° C., when an ordinary raw material is used, the aluminum oxide insulating substrate cannot be densified to a relative density of 95% or more, the thermal conductivity and strength are reduced, and the temperature is higher than 1500 ° C. If it is high, the sintering of tungsten or molybdenum itself proceeds, so that a uniform structure with copper cannot be maintained, and as a result, it is difficult to maintain low resistance, and sheet resistance becomes high. In addition, the grain size of the main crystal phase of the oxide ceramics increases and abnormal grain growth occurs, and the grain boundary length, which is the path when copper diffuses into the ceramics, becomes shorter and the diffusion speed increases. This is because it becomes difficult to control the diffusion distance to 30 μm or less. The range of 1250-1400 ° C is preferred.
[0043]
Further, the non-oxidizing atmosphere at the time of firing is preferably nitrogen or a mixed atmosphere of nitrogen and hydrogen. However, particularly in controlling the diffusion of copper in the wiring layer, it contains hydrogen and nitrogen. A non-oxidizing atmosphere with a dew point of + 10 ° C. or lower, particularly −10 ° C. or lower is desirable. In addition, you may mix inert gas, such as argon gas, in this atmosphere if desired. If the dew point during firing is higher than + 10 ° C., oxide ceramics react with moisture in the atmosphere during firing to form an oxide film, and this oxide film reacts with copper in the copper-containing conductor, resulting in a low conductor. This is because it not only prevents resistance, but also promotes copper diffusion.
[0044]
Further, as shown in FIG. 2, the wiring substrate 4 has a gold plating layer 7 deposited on the exposed surface of the wiring layer 2, and the wiring layer 2 and the gold plating layer 7 are diffusion bonded. By diffusion bonding, a gold / copper diffusion layer 7a is formed between the wiring layer 2 and the gold plating layer 7, and the wiring layer 2 and the gold plating layer 7 are firmly bonded via the diffusion layer 7a. .
[0045]
The gold plating layer 7 and the gold / copper diffusion layer 7a act as a main conductor for propagating an electric signal to the wiring layer 2 of the wiring board 4, and are made of low resistance gold or gold / copper. The electric resistance of the wiring layer 2 has a function of reducing the electrical resistance of the wiring layer 2 so as not to cause a problem even when a high frequency signal in the millimeter wave band or microwave band is propagated.
[0046]
At the same time, the gold plating layer 7 acts to prevent the copper in the wiring layer 2 and the gold / copper diffusion layer 7a from being oxidized, and effectively prevents an increase in electrical resistance due to the wiring layer 2 being oxidized. can do.
[0047]
If the total thickness of the gold plating layer 7 and the gold / copper diffusion layer 7a is 0.5 μm or more and the thickness of the gold plating layer is 0.1 μm or more, the wiring layer 2 is formed. Can be made sufficiently low resistance, and oxidation of the wiring layer 2 can be more effectively prevented. Accordingly, the gold plating layer 7 and the gold / copper diffusion layer 7a are preferably formed so that the total thickness thereof is 0.5 μm or more and the thickness of the gold plating layer is 0.1 μm or more. In consideration of the properties, it is more preferable to form the film so that the total thickness is 2 μm or less.
[0048]
The gold plating layer 7 is formed by immersing the wiring layer 2 in a well-known cyan electrolytic gold plating solution containing, for example, potassium gold cyanide as a main component and adding an electrically conductive salt, a pH adjusting agent, or the like. By supplying power for plating at a current density / time, the exposed surface of the wiring layer 2 is deposited to a predetermined thickness.
[0049]
In the gold plating, tungsten and / or molybdenum exposed on the surface of the wiring layer 2 is previously removed by etching with a strong alkaline solution such as an aqueous solution mainly composed of potassium hydroxide and ferricyanide, It is preferable that copper is mainly exposed on the surface of the layer 2, facilitating the formation of precipitation on the surface of the wiring layer 2 of the gold plating layer 7, and at the same time increasing the adhesion strength of the gold plating layer 7. it can.
[0050]
The diffusion bonding between such wiring layer 2 and the gold plating layer 7 is, after allowed deposited gold plating layer 7 on the surface of the wiring layer 2, the wiring board 4, in a non-oxidizing atmosphere, gold (melting point: about 1060 ° C.) and copper (melting point: about 1090 ° C.) temperatures near the melting point of, for example, 900 ° C. C. to 1100 ° C., row by heat treatment at more preferably 950 ℃ ~1040 ℃.
[0051]
Further, the thickness of the gold / copper diffusion layer 7a can be controlled by appropriately adjusting the heat treatment conditions, for example, the keeping time of the maximum treatment temperature.
[0052]
Thus, according to the wiring board obtained by the manufacturing method of the present invention, the semiconductor element 3 is mounted on the semiconductor element mounting portion 1a of the insulating base 1, and each electrode of the semiconductor element 3 is connected to the wiring layer 2 via the bonding wires 5. After that, a hook-like lid 8 made of metal or ceramics is joined to the upper surface of the insulating base 1 via a sealing material such as glass, resin, brazing material, etc. A semiconductor device as a product is completed by airtightly housing the semiconductor element 3 in a container formed of the body 8, and the semiconductor element 3 is connected to an external electric circuit via the wiring layer 2 and the like.
[0053]
Note that the present invention is not limited to the above-described embodiments, and various modifications are possible within a range not departing from the gist of the present invention. For example, in the above-described embodiments, the gold plating layer 7 is electroplated. However, it may be formed by an electroless plating method in which the wiring layer 2 is sequentially immersed in a replacement type electroless gold plating solution and a reduction type electroless gold plating solution.
[0054]
In the above embodiment, the wiring board obtained by the manufacturing method of the present invention is applied to a package for housing a semiconductor element. However, it may be applied to other uses such as a hybrid integrated circuit board.
[0055]
【The invention's effect】
According to the method for manufacturing a wiring board of the present invention, since the insulating base is formed of a ceramic sintered body having a thermal conductivity of 10 W / m · K or more , the obtained wiring board has a good thermal conductivity, and the semiconductor device This heat can be efficiently dissipated outside the device, and the semiconductor device can be operated normally and stably over a long period of time by keeping the semiconductor device at an appropriate temperature.
[0056]
According to the method for manufacturing a wiring board of the present invention, a wiring layer is formed by tungsten and / or molybdenum and copper, and since the gold plating layer Ru is deposited on the surface, the electric resistance is extremely small value At the same time, oxidation of the wiring layer can be effectively prevented, and as a result, high-frequency signals in the millimeter wave band and microwave band can always be propagated with almost no loss.
[0057]
Further, according to the manufacturing method of the wiring substrate of the present invention, in a non-oxidizing atmosphere, it was heat-treated at a temperature of 900 ° C. C. to 1100 ° C., since the wiring layer and a gold plating layer Ru are diffused junction, a gold plating layer Bonding strength to the wiring layer is extremely strong, so that a semiconductor element is bonded to the wiring layer via a low melting point solder such as tin-lead solder, or the wiring layer is connected to a wiring conductor of an external electric circuit board via a low melting point brazing material. Even if they are joined together, the gold plating layer is diffused and absorbed by the low melting point brazing material, and tungsten or molybdenum hardly appears on the surface of the wiring layer where the low melting point brazing material is in contact. The bonding strength to the layer is extremely strong, and the bonding reliability can be made extremely good.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment in which a wiring board obtained by a manufacturing method of the present invention is applied to a package for housing a semiconductor element that houses a semiconductor element.
FIG. 2 is a fragmentary cross-sectional view of a wiring board obtained by the manufacturing method of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Insulation base | substrate 2 ... Wiring layer 3 ... Semiconductor element 4 ... Wiring board 5 ... Bonding wire 6 ... Via-hole conductor 7- .... Gold plating layer 7a ... Gold / copper diffusion bonding layer 8 ... Lid

Claims (1)

熱伝導率が１０Ｗ／ｍ・Ｋ以上のセラミックス焼結体から成る絶縁基体に、該絶縁基体との同時焼成により一体的にタングステンおよび／またはモリブデンと銅とから成る配線層を形成する工程と、
該配線層の露出表面に金めっき層を被着させる工程と、
非酸化雰囲気中で、９００℃〜１１００℃の温度で熱処理して、前記配線層と前記金めっき層とを拡散接合させる工程と
を具備することを特徴とする配線基板の製造方法。 The insulating base thermal conductivity consisting of 10 W / m · K or more ceramic sintered body, forming a wiring layer consisting of a co-fired by the Ri one body to data tungsten and / or molybdenum and copper and the insulating substrate And a process of
Depositing a gold plating layer on the exposed surface of the wiring layer;
In a non-oxidizing atmosphere, it was heat-treated at a temperature of 900 ° C. C. to 1100 ° C., the step of diffusion bonding and the gold-plated layer and the wiring layer
Method for manufacturing a wiring substrate, characterized that you include a.
JP2001157697A 2001-05-25 2001-05-25 Wiring board manufacturing method Expired - Fee Related JP4454183B2 (en)

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JP4454183B2 true JP4454183B2 (en) 2010-04-21

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