JP4447308B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having gate insulating films with different thicknesses and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device that can prevent damage or contamination of a semiconductor layer and a manufacturing method thereof. In addition, the present invention relates to a semiconductor device and a manufacturing method thereof in which the process can be simplified by doping impurities in a lump.

  FIG. 12 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device. In this semiconductor device, a TFT (thin film transistor) having a gate insulating film having a different thickness on the same substrate, that is, a TFT having a gate insulating film having a different thickness from the TFT manufactured on the CPU side is paneled. It was produced on the side.

  First, a base insulating film 101 is formed on a glass substrate (not shown), and island-shaped semiconductor layers (active layers) 102 and 103 are formed on the base insulating film 101. Next, a first gate insulating film 104 is formed over the semiconductor layers 102 and 103 and the base insulating film 101, and the first gate insulating film is etched. As a result, the first gate insulating film 104 on the CPU-side semiconductor layer 102 is removed, and the first gate insulating film 104 is left on the panel-side semiconductor layer 103.

  Next, a second gate insulating film 105 is formed over the semiconductor layer 102 and the first gate insulating film 104. Next, the gate electrode 108 is formed on the semiconductor layer 102 on the CPU side via the second gate insulating film 105, and the first and second gate insulating films 104 and 105 are formed on the semiconductor layer 103 on the panel side. Thus, the gate electrode 109 is formed. The gate electrodes 108 and 109 have a structure in which a first conductive film 106 and a second conductive film 107 are stacked.

  Next, the semiconductor layer 103 and the gate electrode 109 on the panel side are covered with a resist mask (not shown), and the semiconductor layer 102 on the CPU side is doped with an impurity, whereby an LDD (lightly doped drain) region is formed in the semiconductor layer 102. 110 and 111, and source and drain regions 112 and 113 are formed.

  Next, the semiconductor layer 102 and the gate electrode 108 on the CPU side are covered with a resist mask (not shown), and the semiconductor layer 103 on the panel side is doped with impurities, whereby the LDD regions 114 and 115, the source and the semiconductor layer 103 are formed in the semiconductor layer 103. Drain regions 116 and 117 are formed.

  In the conventional method for manufacturing a semiconductor device, when the gate insulating films having different thicknesses are manufactured as described above, the first gate insulating film 104 is made to be the active layer on the panel side by etching the first gate insulating film. When left on 103, the active layer 102 on the CPU side is exposed to the etching atmosphere. For this reason, etching damage and contamination may occur in the active layer 102 on the CPU side.

  Further, since TFTs having gate insulating films with different thicknesses are formed on the CPU side and the panel side on the same substrate, a resist mask is required when doping the semiconductor layers 102 and 103 with impurities, and the number of steps is reduced. Become more.

The present invention has been made in consideration of the above-described circumstances, and a purpose thereof is a semiconductor device capable of suppressing the occurrence of damage or contamination in a semiconductor layer even when a gate insulating film having a different thickness is manufactured, and the semiconductor device It is to provide a manufacturing method.
Another object of the present invention is to provide a semiconductor device capable of simplifying the process by doping impurities in a lump and a manufacturing method thereof.

In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a first semiconductor layer formed over a substrate,
A second semiconductor layer formed on the substrate;
A first insulating film formed on each of the first semiconductor layer and the second semiconductor layer;
A second insulating film formed on the second semiconductor layer via the first insulating film;
A third insulating film formed on the second insulating film;
Comprising
The first insulating film formed on the first semiconductor layer constitutes a first gate insulating film;
The first to third insulating films formed on the second semiconductor layer constitute a second gate insulating film.

  According to the semiconductor device, the first gate insulating film is composed of the first insulating film, and the second gate insulating film is composed of the first to third insulating films, so that different films are formed on the same substrate. Even when a thick gate insulating film is formed, the first and second semiconductor layers are not exposed to the etching atmosphere, so that the first and second semiconductor layers can be prevented from being damaged or contaminated. .

A semiconductor device according to the present invention includes a first semiconductor layer formed on a substrate,
A second semiconductor layer formed on the substrate;
A first insulating film formed on each of the first semiconductor layer and the second semiconductor layer;
A second insulating film formed on the second semiconductor layer via the first insulating film;
A third insulating film formed on the second insulating film;
A first gate electrode formed on the first semiconductor layer via the first insulating film and comprising a first conductive film and a second conductive film, and a part of the first conductive film A first gate electrode having a shape exposed from the second conductive film;
A second gate electrode formed on the second semiconductor layer via the first to third insulating films and comprising the first conductive film and the second conductive film; A second gate electrode having a shape in which a part of the conductive film is exposed from the second conductive film;
Comprising
The first insulating film formed on the first semiconductor layer constitutes a first gate insulating film;
The first to third insulating films formed on the second semiconductor layer constitute a second gate insulating film.

A semiconductor device according to the present invention includes a first semiconductor layer formed on a substrate,
A first high-concentration impurity region formed in the first semiconductor layer;
A first low-concentration impurity region formed in the first semiconductor layer and formed inside the first high-concentration impurity region;
A second semiconductor layer formed on the substrate;
A second high-concentration impurity region formed in the second semiconductor layer;
A second low-concentration impurity region formed in the second semiconductor layer and formed inside the second high-concentration impurity region;
A first insulating film formed on each of the first semiconductor layer and the second semiconductor layer;
A second insulating film formed on the second semiconductor layer via the first insulating film;
A third insulating film formed on the second insulating film;
A first gate electrode formed on the first semiconductor layer via the first insulating film and comprising a first conductive film and a second conductive film, and a part of the first conductive film A first gate electrode having a shape exposed from the second conductive film;
A second gate electrode formed on the second semiconductor layer via the first to third insulating films and comprising the first conductive film and the second conductive film; A second gate electrode having a shape in which a part of the conductive film is exposed from the second conductive film;
Comprising
The first insulating film formed on the first semiconductor layer constitutes a first gate insulating film;
The first to third insulating films formed on the second semiconductor layer constitute a second gate insulating film.

  In the semiconductor device according to the present invention, it is preferable that the first insulating film and the second insulating film have different etching rates, and the second insulating film and the third insulating film have different etching rates. . Thus, when the third insulating film is etched, the etching can be performed using the second insulating film therebelow as an etching stopper, and when the second insulating film is etched, the first insulating film therebelow is etched. Etching can be performed using the insulating film as an etching stopper. Therefore, the first and second semiconductor layers are not exposed to the etching atmosphere, and etching damage and contamination can be prevented from occurring in the semiconductor layers.

  In the semiconductor device according to the present invention, the first insulating film may be a SiON film, the second insulating film may be a SiN film, and the third insulating film may be a SiON film. is there.

A semiconductor device according to the present invention includes a first semiconductor layer formed on a substrate,
A second semiconductor layer formed on the substrate;
A first insulating film formed on each of the first semiconductor layer and the second semiconductor layer;
A second insulating film formed on the second semiconductor layer via the first insulating film;
Comprising
The first insulating film formed on the first semiconductor layer constitutes a first gate insulating film;
The first and second insulating films formed on the second semiconductor layer constitute a second gate insulating film.

  According to the semiconductor device, even when the gate insulating films having different thicknesses are formed on the same substrate, the first and second semiconductor layers are not exposed to the etching atmosphere. Etching damage and contamination can be prevented from occurring in the semiconductor layer.

A semiconductor device according to the present invention includes a first semiconductor layer formed on a substrate,
A second semiconductor layer formed on the substrate;
A first insulating film formed on each of the first semiconductor layer and the second semiconductor layer;
A second insulating film formed on the second semiconductor layer via the first insulating film;
A first gate electrode formed on the first semiconductor layer via the first insulating film and comprising a first conductive film and a second conductive film, and a part of the first conductive film A first gate electrode having a shape exposed from the second conductive film;
A second gate electrode formed on the second semiconductor layer with the first and second insulating films interposed therebetween, and comprising the first conductive film and the second conductive film; A second gate electrode having a shape in which a part of the conductive film is exposed from the second conductive film;
Comprising
The first insulating film formed on the first semiconductor layer constitutes a first gate insulating film;
The first and second insulating films formed on the second semiconductor layer constitute a second gate insulating film.

A semiconductor device according to the present invention includes a first semiconductor layer formed on a substrate,
A first high-concentration impurity region formed in the first semiconductor layer;
A first low-concentration impurity region formed in the first semiconductor layer and formed inside the first high-concentration impurity region;
A second semiconductor layer formed on the substrate;
A second high-concentration impurity region formed in the second semiconductor layer;
A second low-concentration impurity region formed in the second semiconductor layer and formed inside the second high-concentration impurity region;
A first insulating film formed on each of the first semiconductor layer and the second semiconductor layer;
A second insulating film formed on the second semiconductor layer via the first insulating film;
A first gate electrode formed on the first semiconductor layer via the first insulating film and comprising a first conductive film and a second conductive film, and a part of the first conductive film A first gate electrode having a shape exposed from the second conductive film;
A second gate electrode formed on the second semiconductor layer with the first and second insulating films interposed therebetween, and comprising the first conductive film and the second conductive film; A second gate electrode having a shape in which a part of the conductive film is exposed from the second conductive film;
Comprising
The first insulating film formed on the first semiconductor layer constitutes a first gate insulating film;
The first and second insulating films formed on the second semiconductor layer constitute a second gate insulating film.

  In the semiconductor device according to the present invention, the second low concentration impurity region has two impurity concentrations divided into the second high concentration impurity region side and the channel formation region side of the second semiconductor layer. The impurity concentration region on the second high concentration impurity region side may be higher in impurity concentration than the impurity concentration region on the channel formation region side of the second semiconductor layer.

  In the semiconductor device according to the present invention, it is preferable that the first insulating film and the second insulating film have different etching rates.

  In the semiconductor device according to the present invention, the first insulating film can be made of a SiON film, and the second insulating film can be made of a SiN film.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. Forming a second gate insulating film made of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer. Features.

  According to the above method for manufacturing a semiconductor device, when the third insulating film is etched, etching is performed using the second insulating film therebelow as an etching stopper, and when the second insulating film is etched, Etching is performed using the first insulating film as an etching stopper. Therefore, the first and second semiconductor layers are not exposed to the etching atmosphere, and etching damage and contamination can be prevented from occurring in the semiconductor layers.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. Forming a first gate electrode having a shape exposed from the second conductive film on the first semiconductor layer via the first gate insulating film; and A second gate electrode made of the first conductive film and having a shape in which a part of the first conductive film is exposed from the second conductive film is used as the second semiconductor. It is characterized by being formed on the layer via the second gate insulating film.

  In the method for manufacturing a semiconductor device according to the present invention, after the first gate electrode and the second gate electrode are formed, the first gate electrode and the second gate electrode are used as a mask. It is also possible to dope impurities into one semiconductor layer and the second semiconductor layer through the first gate insulating film and the second gate insulating film.

  As described above, the process can be simplified by doping the first semiconductor layer and the second semiconductor layer together.

  In the method for manufacturing a semiconductor device according to the present invention, after the first gate electrode and the second gate electrode are formed, the first gate electrode and the second gate electrode are used as a mask. An impurity is doped into one semiconductor layer and the second semiconductor layer through an exposed portion of the first conductive film, the first gate insulating film, and the second gate insulating film.

  In the method for manufacturing a semiconductor device according to the present invention, after doping through the second gate insulating film, the second gate electrode and the second gate electrode are formed on the first semiconductor layer. A resist mask is formed to cover the periphery, and impurities are doped into the second semiconductor layer through the second gate insulating film using the resist mask as a mask.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. Forming a first gate electrode having a shape exposed from the second conductive film on the first semiconductor layer via the first gate insulating film; and A second gate electrode made of the first conductive film and having a shape in which a part of the first conductive film is exposed from the second conductive film is used as the second semiconductor. Forming on the layer via the second gate insulating film;
Forming a resist mask covering the second gate electrode and the periphery of the second gate electrode on the first semiconductor layer;
Doping the second semiconductor layer with the first impurity through the second gate insulating film using the resist mask as a mask,
Removing the resist mask;
Using the first gate electrode and the second gate electrode as a mask, a second impurity is introduced into the first semiconductor layer and the second semiconductor layer, the exposed portion of the first conductive film, and the first gate. Doping is performed through the insulating film and the second gate insulating film.

  According to the above method for manufacturing a semiconductor device, when the third insulating film is etched, etching is performed using the second insulating film therebelow as an etching stopper, and when the second insulating film is etched, Etching is performed using the first insulating film as an etching stopper. For this reason, the first and second semiconductor layers are not exposed to the etching atmosphere, and etching damage and contamination can be prevented from occurring in the semiconductor layers. Further, since the second impurity is collectively doped in the first and second semiconductor layers, the process can be simplified.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. Forming a first gate electrode having a shape exposed from the second conductive film on the first semiconductor layer via the first gate insulating film; and A second gate electrode made of the first conductive film and having a shape in which a part of the first conductive film is exposed from the second conductive film is used as the second semiconductor. Forming on the layer via the second gate insulating film;
Forming a first resist mask covering the periphery of the second gate electrode and the second gate electrode;
Using the first resist mask and the first gate electrode as a mask, impurities are introduced into the first semiconductor layer and the second semiconductor layer, the exposed portion of the first conductive film, the first gate insulating film, Doping is performed through the second gate insulating film.

  In the method for manufacturing a semiconductor device according to the present invention, after doping through the second gate insulating film, the first resist mask is removed, and a second semiconductor layer covering the first semiconductor layer is covered. A resist mask is formed, and impurities are introduced into the second semiconductor layer through the exposed portions of the second gate insulating film and the first conductive film using the second resist mask and the second gate electrode as a mask. It is also possible to dope.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. Forming a first gate electrode having a shape exposed from the second conductive film on the first semiconductor layer via the first gate insulating film; and A second gate electrode made of the first conductive film and having a shape in which a part of the first conductive film is exposed from the second conductive film is used as the second semiconductor. Forming on the layer via the second gate insulating film;
Forming a first resist mask covering the first semiconductor layer;
Using the first resist mask and the second gate electrode as a mask, the second semiconductor layer is doped with a first impurity through the exposed portions of the second gate insulating film and the first conductive film. ,
Removing the first resist mask;
Forming a second resist mask covering the second gate electrode and the periphery of the second gate electrode;
Using the second resist mask and the first gate electrode as a mask, a second impurity is added to the first semiconductor layer and the second semiconductor layer as an exposed portion of the first conductive film, and the first gate. Doping is performed through the insulating film and the second gate insulating film.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. Forming a first gate electrode having a shape exposed from the second conductive film on the first semiconductor layer via the first gate insulating film; and A second gate electrode made of the first conductive film and having a shape in which a part of the first conductive film is exposed from the second conductive film is used as the second semiconductor. Forming on the layer via the second gate insulating film;
Forming a first resist mask so as to cover the second semiconductor layer;
Using the first resist mask and the first gate electrode as a mask, the first semiconductor layer is doped with an impurity through the exposed portion of the first conductive film and the first gate insulating film. And

  Further, in the method for manufacturing a semiconductor device according to the present invention, after doping through the first gate insulating film, the first resist mask is removed, and the second semiconductor layer covering the first semiconductor layer is covered. Forming a resist mask, and using the second resist mask and the second gate electrode as a mask, impurities are introduced into the second semiconductor layer through the exposed portion of the first conductive film and the second gate insulating film; It is also possible to dope.

  In the method for manufacturing a semiconductor device according to the present invention, after doping through the second gate insulating film, the second resist mask is removed, and the second semiconductor layer is formed on the first semiconductor layer. A third resist mask that covers the periphery of the gate electrode and the second gate electrode is formed, and impurities are introduced into the second semiconductor layer through the second gate insulating film using the third resist mask as a mask. It is also possible to dope.

  In the method for manufacturing a semiconductor device according to the present invention, the first insulating film is made of a SiON film, the second insulating film is made of a SiN film, and the third insulating film is made of a SiON film. Is also possible.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And a second gate insulating film formed of the first insulating film and the second insulating film is formed on the second semiconductor layer.

  According to the method for manufacturing a semiconductor device, when the second insulating film is etched, the first insulating film below the second insulating film is etched as an etching stopper, so that the first and second semiconductor layers are exposed to the etching atmosphere. Therefore, etching damage and contamination can be prevented from occurring in the semiconductor layer.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film made of the first insulating film and the second insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. Forming a first gate electrode having a shape exposed from the second conductive film on the first semiconductor layer via the first gate insulating film; and A second gate electrode made of the first conductive film and having a shape in which a part of the first conductive film is exposed from the second conductive film is used as the second semiconductor. It is characterized by being formed on the layer via the second gate insulating film.

  In the method for manufacturing a semiconductor device according to the present invention, after the first gate electrode and the second gate electrode are formed, the first gate electrode and the second gate electrode are used as a mask. It is also possible to dope impurities into one semiconductor layer and the second semiconductor layer through the first gate insulating film and the second gate insulating film.

  As described above, since the impurities are collectively doped into the first and second semiconductor layers, the process can be simplified.

  In the method for manufacturing a semiconductor device according to the present invention, after doping through the second gate insulating film, the second gate electrode and the second gate electrode are formed on the first semiconductor layer. It is also possible to form a resist mask that covers the periphery, and to dope impurities into the second semiconductor layer through the second gate insulating film using the resist mask as a mask.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film made of the first insulating film and the second insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. Forming a first gate electrode having a shape exposed from the second conductive film on the first semiconductor layer via the first gate insulating film; and A second gate electrode made of the first conductive film and having a shape in which a part of the first conductive film is exposed from the second conductive film is used as the second semiconductor. Forming on the layer via the second gate insulating film;
Forming a first resist mask covering the periphery of the second gate electrode and the second gate electrode;
Using the first resist mask and the first gate electrode as a mask, impurities are introduced into the first semiconductor layer and the second semiconductor layer, the exposed portion of the first conductive film, the first gate insulating film, Doping is performed through the second gate insulating film.

  In the method for manufacturing a semiconductor device according to the present invention, after doping through the second gate insulating film, the first resist mask is removed, and a second semiconductor layer covering the first semiconductor layer is covered. A resist mask is formed, and impurities are introduced into the second semiconductor layer through the exposed portions of the second gate insulating film and the first conductive film using the second resist mask and the second gate electrode as a mask. It is also possible to dope.

In a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer and a second semiconductor layer are formed over a substrate,
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film made of the first insulating film and the second insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. Forming a first gate electrode having a shape exposed from the second conductive film on the first semiconductor layer via the first gate insulating film; and A second gate electrode made of the first conductive film and having a shape in which a part of the first conductive film is exposed from the second conductive film is used as the second semiconductor. Forming on the layer via the second gate insulating film;
Forming a first resist mask so as to cover the second semiconductor layer;
Using the first resist mask and the first gate electrode as a mask, the first semiconductor layer is doped with an impurity through the exposed portion of the first conductive film and the first gate insulating film. And

  Further, in the method for manufacturing a semiconductor device according to the present invention, after doping through the first gate insulating film, the first resist mask is removed, and the second semiconductor layer covering the first semiconductor layer is covered. Forming a resist mask, and using the second resist mask and the second gate electrode as a mask, impurities are introduced into the second semiconductor layer through the exposed portion of the first conductive film and the second gate insulating film; And doping.

  In the method for manufacturing a semiconductor device according to the present invention, after doping through the second gate insulating film, the second resist mask is removed, and the second semiconductor layer is formed on the first semiconductor layer. A third resist mask that covers the periphery of the gate electrode and the second gate electrode is formed, and impurities are introduced into the second semiconductor layer through the second gate insulating film using the third resist mask as a mask. It is also possible to dope.

  As described above, according to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can prevent the semiconductor layer from being damaged or contaminated even when gate insulating films having different thicknesses are manufactured. In addition, according to the present invention, it is possible to provide a semiconductor device and a manufacturing method thereof that can simplify the process by doping impurities in a lump.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
1 to 4 are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, a base insulating film 2 is formed on a substrate (not shown). As the substrate, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

  As the base insulating film 2, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used. Here, an example in which a single-layer structure of one layer is used as the base insulating film 2 is shown, but a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. Note that the base insulating film is not necessarily formed.

  Next, island-shaped semiconductor layers (active layers) 3 a and 3 b are formed on the base insulating film 2. The semiconductor layers 3a and 3b are formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, etc.) and then known crystallization treatment (laser crystallization method, heat A crystalline semiconductor film obtained by performing a crystallization method or a thermal crystallization method using a catalyst such as nickel) is formed by patterning into a desired shape using a first photomask. The semiconductor layers 3a and 3b are formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

  Next, the first insulating film 4 is formed on the semiconductor layers 3 a and 3 b and the base insulating film 2. The first insulating film 4 becomes a gate insulating film on the CPU side. As the first insulating film 4, a single layer SiON film is used by plasma CVD or sputtering.

  Thereafter, a second insulating film 5 is formed on the first insulating film 4, and a third insulating film 6 is formed on the second insulating film 5. The second insulating film 5 is a single layer SiN film using plasma CVD or sputtering. As the third insulating film 6, a single layer SiON film is used by plasma CVD or sputtering. The first to third insulating films 4 to 6 are gate insulating films on the panel side, and this gate insulating film has a three-layer structure (ONO structure) of SiON—SiN—SiON.

  Next, as illustrated in FIG. 1B, a resist mask 7 is formed over the third insulating film 6 using a second photomask. Next, the third insulating film 6 is etched using the resist mask 7 as a mask and the second insulating film 5 as an etching stopper. At this time, the difference in etching rate between the second insulating film 5 made of SiN film and the third insulating film 6 made of SiON film is used. Thereby, the third insulating film 6 located above the semiconductor layer 3a on the CPU side is removed. At this time, since the semiconductor layer 3a is covered with the first and second insulating films 4 and 5, and the semiconductor layer 3a is not exposed to the etching atmosphere, etching damage and contamination occur in the semiconductor layer. Can be prevented.

  Thereafter, as shown in FIG. 1C, the second insulating film 5 is etched using the resist mask 7 as a mask and the first insulating film 4 as an etching stopper. At this time, the difference in etching rate between the first insulating film 4 made of the SiON film and the second insulating film 5 made of the SiN film is used. As a result, the second insulating film 5 located above the semiconductor layer 3a on the CPU side is removed. At this time, since the semiconductor layer 3a is covered with the first insulating film 4 and the semiconductor layer 3a is not exposed to the etching atmosphere, it is possible to prevent the semiconductor layer from being etched or contaminated. In this way, the gate insulating film made of the first insulating film 4 is formed on the CPU-side semiconductor layer 3a, and the first to third insulating films 4 to 6 are made on the panel-side semiconductor layer 3b. A gate insulating film having an ONO structure is formed.

  Next, as shown in FIG. 2A, after removing the resist mask 7, the first conductive film 8 having a thickness of 20 to 100 nm is formed on the first insulating film 4 and the third insulating film 6. Then, a second conductive film 9 having a thickness of 100 to 400 nm is stacked. Here, a first conductive film 8 made of a TaN film and a second conductive film 9 made of a W film are stacked by sputtering, and the film thickness of the first conductive film 8 is set to 30 nm. The film thickness of the conductive film 9 was 370 nm. Here, the first conductive film 8 is a TaN film and the second conductive film 9 is a W film. However, these materials are not particularly limited, and all of them are Ta, W, Ti, Mo, Al, You may form with the element selected from Cu, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used.

  Next, as shown in FIG. 2B, a resist mask 10 is formed on the second conductive film 9 using a third photomask, and etching using inductively coupled plasma (ICP) is performed. A first etching step is performed using the apparatus. By this first etching step, the second conductive film 9 is etched to obtain a second conductive film 9a having a tapered portion at the end (tapered portion).

  Next, a second etching process is performed using the resist mask 10 as it is and using an ICP etching apparatus. In this second etching process, the first conductive film 8 is etched to form a first conductive film 8a as shown in FIG. That is, the first conductive film 8a and the second conductive film 9a are formed on the semiconductor layer 3a via the first insulating film 4, and the first conductive film 8a and the second conductive film 9a are formed on the semiconductor layer 3b. A first to third insulating films 4 to 6 are formed thereon. In the second etching step, the resist mask, the second conductive film, and the first and third insulating films are slightly etched.

  Here, in order to suppress the film loss of the first insulating film 4, two etchings (a first etching process and a second etching process) were performed, but as shown in FIG. There is no particular limitation as long as an electrode structure (a stack of the second conductive film 9a and the first conductive film 8a) can be formed, and the etching may be performed in one etching step.

  Next, a third etching process is performed by an ICP etching apparatus using the resist mask 10. In the third etching step, the second conductive film 9a is etched to form a second conductive film 9b as shown in FIG. Thereby, the first gate electrode 11 composed of the first and second conductive films 9b and 8a is formed on the semiconductor layer 3a on the CPU side via the gate insulating film (first insulating film 4). A second gate electrode 12 made of first and second conductive films 9b and 9a is formed on the semiconductor layer 3b on the side through a gate insulating film (first to third insulating films 4 to 6). . A part of the first conductive film 8a is exposed from the second conductive film 9b. As described above, since the first gate electrode 11 on the CPU side and the second gate electrode 12 on the panel side are simultaneously formed in the same etching process, the process can be simplified.

  During the third etching step, the resist mask, the first conductive film, and the first and third insulating films are also slightly etched.

  Next, as shown in FIG. 3A, the resist mask 10 is removed.

  Thereafter, as shown in FIG. 3B, a first doping process is performed. Through the first doping step, through doping is performed through the gate insulating film (first to third insulating films 4 to 6) using the first and second gate electrodes 11 and 12 as a mask. That is, on the CPU side, through doping is performed through the exposed portions of the first insulating film 4 and the first conductive film 8a using the first gate electrode 11 as a mask, and on the panel side, the second gate electrode 12 is masked. Through-doping is performed through the exposed portions of the first to third insulating films 4 to 6 and the first conductive film 8a. As a result, as shown in FIG. 3B, on the CPU side, the high concentration impurity regions (source and drain regions) 13 and 14 of the semiconductor layer 3a have a high concentration in a self-aligned manner via the first insulating film. Impurities are introduced, and low concentration impurities are introduced into the low concentration impurity regions (LDD regions) 15 and 16 of the semiconductor layer 3a in a self-aligned manner through the exposed portions of the first conductive film 8a and the first insulating film. The Further, on the panel side, the first low-concentration impurity regions 17 and 18 of the semiconductor layer 3b are in a self-aligned manner through the exposed portion of the first conductive film 8a and the first to third insulating films. Low-concentration impurities are introduced, and second low-concentration impurities are introduced into the second low-concentration impurity regions 19 and 20 of the semiconductor layer 3b through the first to third insulating films in a self-aligning manner. The first low-concentration impurity regions 17 and 18 have a lower impurity concentration than the second low-concentration impurity regions 19 and 20. As described above, the high-concentration impurity regions 13 and 14 and the low-concentration impurity regions 15 and 16 on the CPU side, the first low-concentration impurity regions 17 and 18 and the second low-concentration impurity regions 19 and 20 on the panel side are collectively doped. Since impurities are introduced in the process, the process can be simplified.

  Note that the conditions in the first doping step are controlled so that the doping amount implanted into the semiconductor layers 3a and 3b becomes a desired value.

  Next, as shown in FIG. 3C, using a fourth photomask, the resist mask 23 covers the upper side of the semiconductor layer 3a on the CPU side and covers the second gate electrode 12 on the panel side and the periphery thereof. To form.

  Next, a second doping process is performed. Through the second doping step, through doping is performed through the gate insulating film (first to third insulating films 4 to 6) using the resist mask 23 as a mask. Thereby, as shown in FIG. 3C, the high-concentration impurity regions (source and drain regions) 21 and 22 of the semiconductor layer 3b on the panel side are self-aligned through the first to third insulating films. High concentration impurities are introduced.

  In this embodiment, the second doping step shown in FIG. 3C is performed after the first doping step shown in FIG. 3B, but the second doping step shown in FIG. It is also possible to perform the first doping step shown in FIG. 3B after performing the second doping step.

  In the present embodiment, the first doping process and the second doping process are performed. However, the present invention is not limited to this, and the doping process can be changed as follows. is there. Through-doping is performed through the first conductive film 8a and the gate insulating films (first to third insulating films 4 to 6) in a self-aligning manner using the second gate electrode on the panel side as a mask, thereby A low concentration impurity is introduced into the low concentration impurity region of the semiconductor layer 3b (first doping step). Next, through doping is performed through the first conductive film 8a and the gate insulating film (first insulating film 4) in a self-aligning manner using the first gate electrode on the CPU side as a mask, a semiconductor layer on the CPU side A low concentration impurity is introduced into the low concentration impurity region 3a (second doping step). Next, through doping is performed through the gate insulating film (first insulating film 4) in a self-aligned manner with low acceleration using the first gate electrode on the CPU side as a mask, the high concentration of the semiconductor layer 3a on the CPU side A high concentration impurity is introduced into the impurity region (third doping step). Next, through doping is performed through the gate insulating film (first to third insulating films 4 to 6) in a self-aligning manner with high acceleration by using the second gate electrode on the panel side as a mask, the semiconductor on the panel side A high concentration impurity is introduced into the high concentration impurity region of the layer 3b (fourth doping step).

  Thereafter, as shown in FIG. 4, the resist mask 23 is removed.

  Thus, on the substrate, the CPU side thin film transistor constituted by the first gate electrode 11, the gate insulating film made of the first insulating film 4, the source and drain regions 13 and 14, and the LDD regions 15 and 16 is provided. Produced. Further, on the substrate, a second gate electrode 12, a gate insulating film composed of first to third insulating films 4 to 6, source and drain regions 21, 22, first low-concentration impurity regions 17, 18, A thin film transistor on the panel side constituted by the second low-concentration impurity regions 19 and 20 is manufactured.

  According to the first embodiment, the gate insulating film on the CPU side is formed with the first insulating film 4 and the gate insulating film on the panel side is formed with the first to third insulating films 4 to 6. Even when gate insulating films having different film thicknesses are formed on the same substrate, the semiconductor layer 3a is not exposed to the etching atmosphere, so that etching damage and contamination of the semiconductor layer can be prevented. That is, the first insulating film 4 and the second insulating film 5 are formed of insulating films having different etching rates, and the second insulating film 5 and the third insulating film 6 are formed of insulating films having different etching rates. Thus, when the third insulating film 6 on the CPU side is etched, the etching is performed using the second insulating film 5 therebelow as an etching stopper, and when the second insulating film on the CPU side is etched, Etching can be performed using the first insulating film 4 as an etching stopper. Therefore, the semiconductor layer 3a is not exposed to the etching atmosphere, and etching damage and contamination can be prevented from occurring in the semiconductor layer.

  Further, since the first gate electrode 11 on the CPU side and the second gate electrode 12 on the panel side are formed in the same etching process, the process can be simplified.

  Further, the high concentration impurity regions 13 and 14 and the low concentration impurity regions 15 and 16 of the thin film transistor on the CPU side, the first low concentration impurity regions 17 and 18 and the second low concentration impurity regions 19 and 20 of the thin film transistor on the panel side are provided. Since impurities are introduced in a batch doping process, the process can be simplified.

  In the present embodiment, the second low-concentration impurity regions 19 and 20 located inside the source and drain regions 21 and 22 are formed in the active layer 3b of the thin film transistor on the panel side, and the second low-concentration impurity regions 19 and 20 are formed in the active layer 3b. First low-concentration impurity regions 17 and 18 located inside two low-concentration impurity regions are formed, and the impurity concentration of the first low-concentration impurity regions 17 and 18 is set to be lower than that of the second low-concentration impurity regions 19 and 20 It is low. Thereby, hot carrier deterioration can be reduced, and higher reliability can be obtained in the thin film transistor on the panel side.

(Embodiment 2)
FIGS. 5A and 5B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. The same parts as those in FIGS. Only explained.

  First, the steps shown in FIGS. 1 to 3A in Embodiment Mode 1 are performed.

  Next, as shown in FIG. 5A, a resist mask 24 is formed using a fourth photomask so as to cover the second gate electrode 12 on the panel side and the periphery thereof.

  Next, a first doping process is performed. Through the first doping step, through-doping is performed through the gate insulating film (first to third insulating films 4 to 6) using the resist mask 24 and the gate electrode 11 as a mask. That is, on the CPU side, through doping is performed through the exposed portions of the first insulating film 4 and the first conductive film 8a using the first gate electrode 11 as a mask, and on the panel side, the first mask is used as the first mask using the resist mask 24 as a mask. Through-doping is performed through the third insulating films 4 to 6. As a result, as shown in FIG. 5A, on the CPU side, the high concentration impurity regions (source and drain regions) 13 and 14 of the semiconductor layer 3a have a high concentration in a self-aligned manner via the first insulating film. Impurities are introduced, and low concentration impurities are introduced into the low concentration impurity regions (LDD regions) 15 and 16 of the semiconductor layer 3a in a self-aligned manner through the exposed portions of the first conductive film 8a and the first insulating film. The Further, high-concentration impurities are introduced into the high-concentration impurity regions (source and drain regions) 21 and 22 of the semiconductor layer 3b on the panel side in a self-aligned manner through first to third insulating films.

  As described above, the impurities are introduced into the high-concentration impurity regions 13 and 14 and the low-concentration impurity regions 15 and 16 on the CPU side and the high-concentration impurity regions 21 and 22 on the panel side in a collective doping process, thereby simplifying the process. Can be achieved.

  Thereafter, as shown in FIG. 5B, after removing the resist mask 24, a resist mask 25 is formed using a fifth photomask so as to cover the upper portion of the semiconductor layer 3a on the CPU side.

  Next, a second doping process is performed. Through this second doping step, the resist mask 25 and the second gate electrode 12 are used as a mask through the gate insulating film (first to third insulating films 4 to 6) and the exposed portion of the first conductive film 8a. Through dope. As a result, as shown in FIG. 5B, the exposed portion of the first conductive film 8a and the first to third insulating films are formed in the first low-concentration impurity regions 17 and 18 of the semiconductor layer 3b on the panel side. The first low-concentration impurities are introduced in a self-aligned manner through the second low-concentration impurity regions 19 and 20 of the semiconductor layer 3b, and the second low-concentration impurity regions 19 and 20 are in a self-aligned manner through the first to third insulating films. Low concentration impurities are introduced.

  In this embodiment, the second doping step shown in FIG. 5B is performed after the first doping step shown in FIG. 5A, but the first doping step shown in FIG. 5B is performed. It is also possible to perform the first doping step shown in FIG. 5A after performing the second doping step.

  Next, the resist mask 25 is removed. In this way, thin film transistors as shown in FIG. 4 are fabricated on the CPU side and the panel side.

  In the second embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
6A to 6C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention. The same reference numerals are given to the same parts as those in FIGS. Only explained.

  First, the steps shown in FIGS. 1 to 3A in Embodiment Mode 1 are performed.

  Next, as shown in FIG. 6A, a resist mask 26 is formed so as to cover the semiconductor layer 3b on the panel side using a fourth photomask.

  Next, a first doping process is performed. Through the first doping process, through-doping is performed through the exposed portion of the first conductive film 8a and the gate insulating film (first insulating film 4) using the resist mask 26 and the first gate electrode 11 as a mask. As a result, as shown in FIG. 6A, on the CPU side, the high concentration impurity regions (source and drain regions) 13 and 14 of the semiconductor layer 3a have a high concentration in a self-aligned manner via the first insulating film. Impurities are introduced, and low concentration impurities are introduced into the low concentration impurity regions (LDD regions) 15 and 16 of the semiconductor layer 3a in a self-aligned manner through the exposed portions of the first conductive film 8a and the first insulating film. The

  Thereafter, as shown in FIG. 6B, after removing the resist mask 26, a resist mask 27 is formed using a fifth photomask so as to cover the upper part of the semiconductor layer 3a on the CPU side.

  Next, a second doping process is performed. Through this second doping step, the resist mask 27 and the second gate electrode 12 are used as a mask through the gate insulating film (first to third insulating films 4 to 6) and the exposed portion of the first conductive film 8a. Through dope. Thereby, as shown in FIG. 6B, the exposed portion of the first conductive film 8a and the first to third insulating films are formed in the first low-concentration impurity regions 17 and 18 of the semiconductor layer 3b on the panel side. The first low-concentration impurities are introduced in a self-aligned manner through the second low-concentration impurity regions 19 and 20 of the semiconductor layer 3b, and the second low-concentration impurity regions 19 and 20 are in a self-aligned manner through the first to third insulating films. Low concentration impurities are introduced.

  Next, as shown in FIG. 6C, after the resist mask 27 is removed, the resist mask 28 is covered with the sixth photomask to cover the upper side of the semiconductor layer 3a on the CPU side and the second mask on the panel side. It is formed so as to cover the gate electrode 12 and its periphery.

  Next, a third doping process is performed. Through the third doping step, through-doping is performed through the gate insulating film (first to third insulating films 4 to 6) using the resist mask 28 as a mask. Thus, as shown in FIG. 6C, the high-concentration impurity regions (source and drain regions) 21 and 22 of the semiconductor layer 3b on the panel side are self-aligned via the first to third insulating films. High concentration impurities are introduced.

  In this embodiment mode, the first doping step shown in FIG. 6A is performed, the second doping step shown in FIG. 6B is performed, and then the third doping step shown in FIG. 6C is performed. Although the steps are performed, the order of these doping steps can be changed. For example, the order of the first doping process, the third doping process, and the second doping process may be used, or the order of the second doping process, the first doping process, and the third doping process may be used. The order of the doping process, the third doping process, and the first doping process, or the order of the third doping process, the first doping process, and the second doping process, or the third doping process, The order of the second doping step and the first doping step may be used.

  Next, the resist mask 28 is removed. In this way, thin film transistors as shown in FIG. 4 are fabricated on the CPU side and the panel side.

  In the third embodiment, the same effect as in the first embodiment can be obtained.

  That is, even when gate insulating films having different thicknesses are formed on the same substrate, the semiconductor layer 3a is not exposed to the etching atmosphere, and therefore, it is possible to prevent etching damage and contamination of the semiconductor layer.

  Further, since the first gate electrode 11 on the CPU side and the second gate electrode 12 on the panel side are formed in the same etching process, the process can be simplified.

  In the present embodiment, the second low-concentration impurity regions 19 and 20 located inside the source and drain regions 21 and 22 are formed in the active layer 3b of the thin film transistor on the panel side, and the second low-concentration impurity regions 19 and 20 are formed in the active layer 3b. First low-concentration impurity regions 17 and 18 located inside two low-concentration impurity regions are formed, and the impurity concentration of the first low-concentration impurity regions 17 and 18 is set to be lower than that of the second low-concentration impurity regions 19 and 20. It is low. Thereby, hot carrier deterioration can be reduced, and higher reliability can be obtained in the thin film transistor on the panel side.

(Embodiment 4)
7 and 8 are cross-sectional views showing a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention. The same reference numerals are given to the same portions as those in FIGS.

  Since the process up to the step of forming the second insulating film 5 made of the SiN film on the one insulating film 4 made of the SiON film is the same as that of the first embodiment, the description thereof is omitted. The first insulating film 4 is a gate insulating film on the CPU side, and the first and second insulating films 4 and 5 are gate insulating films on the panel side.

  Thereafter, as shown in FIG. 7A, a resist mask 7 is formed over the second insulating film 5 using a second photomask. Next, the second insulating film 5 is etched using the resist mask 7 as a mask and the first insulating film 4 as an etching stopper. At this time, the difference in etching rate between the second insulating film 5 made of SiN film and the first insulating film 4 made of SiON film is used. As a result, the second insulating film 5 located above the semiconductor layer 3a on the CPU side is removed. At this time, since the semiconductor layer 3a is covered with the first insulating film 4 and the semiconductor layer 3a is not exposed to the etching atmosphere, it is possible to prevent the semiconductor layer from being damaged or contaminated.

  Next, as shown in FIG. 7B, after removing the resist mask 7, a first conductive film having a thickness of 20 to 100 nm is formed on the first insulating film 4 and the second insulating film 5, and A second conductive film with a thickness of 100 to 400 nm is stacked. Here, a first conductive film made of a TaN film and a second conductive film made of a W film are stacked by sputtering, the first conductive film has a thickness of 30 nm, and the second conductive film is formed. The film thickness was 370 nm. Here, the first conductive film is a TaN film and the second conductive film is a W film. However, these materials are not particularly limited, and any of these materials can be Ta, W, Ti, Mo, Al, or Cu. You may form with the selected element or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used.

  Next, a resist mask 10 is formed over the second conductive film using a third photomask, and a first etching process is performed using an ICP etching apparatus. By this first etching step, the second conductive film is etched to obtain a second conductive film 9a having a tapered portion at the end (tapered portion).

  Next, a second etching process is performed using the resist mask 10 as it is and using an ICP etching apparatus. In this second etching step, the first conductive film is etched to form a first conductive film 8a as shown in FIG. 7B. That is, the first conductive film 8a and the second conductive film 9a are formed on the semiconductor layer 3a via the first insulating film 4, and the first conductive film 8a and the second conductive film 9a are formed on the semiconductor layer 3b. A first insulating film 4 and a second insulating film 5 are formed thereon.

  Next, a third etching process is performed by an ICP etching apparatus using the resist mask 10. In the third etching step, the second conductive film 9a is etched to form a second conductive film 9b as shown in FIG. Thereby, the first gate electrode 11 composed of the first and second conductive films 9b and 8a is formed on the semiconductor layer 3a on the CPU side via the gate insulating film (first insulating film 4). A second gate electrode 12 made of first and second conductive films 9b, 9a is formed on the semiconductor layer 3b on the side through a gate insulating film (first and second insulating films 4, 5). . A part of the first conductive film 8a is exposed from the second conductive film 9b. As described above, since the first gate electrode 11 on the CPU side and the second gate electrode 12 on the panel side are simultaneously formed in the same etching process, the process can be simplified.

  Next, the resist mask 10 is removed. In this way, the state of FIG. 7C is obtained.

  Thereafter, as shown in FIG. 8A, a first doping process is performed. Through the first doping step, through doping is performed through the gate insulating films (first and second insulating films 4 and 5) using the first and second gate electrodes 11 and 12 as a mask. That is, on the CPU side, through doping is performed through the exposed portions of the first insulating film 4 and the first conductive film 8a using the first gate electrode 11 as a mask, and on the panel side, the second gate electrode 12 is masked. Through-doping is performed through the exposed portions of the first and second insulating films 4 and 5 and the first conductive film 8a. As a result, as shown in FIG. 8A, on the CPU side, the high concentration impurity regions (source and drain regions) 13 and 14 of the semiconductor layer 3a have high concentration in a self-aligned manner via the first insulating film. Impurities are introduced, and low concentration impurities are introduced into the low concentration impurity regions (LDD regions) 15 and 16 of the semiconductor layer 3a in a self-aligned manner through the exposed portions of the first conductive film 8a and the first insulating film. The Further, on the panel side, the first low-concentration impurity regions 17 and 18 of the semiconductor layer 3b are in a self-aligned manner through the exposed portions of the first conductive film 8a and the first and second insulating films. A low-concentration impurity is introduced, and the second low-concentration impurity is introduced into the second low-concentration impurity regions 19 and 20 of the semiconductor layer 3b through the first and second insulating films in a self-aligning manner. The first low-concentration impurity regions 17 and 18 have a lower impurity concentration than the second low-concentration impurity regions 19 and 20. As described above, the high-concentration impurity regions 13 and 14 and the low-concentration impurity regions 15 and 16 on the CPU side, the first low-concentration impurity regions 17 and 18 and the second low-concentration impurity regions 19 and 20 on the panel side are collectively doped. Since impurities are introduced in the process, the process can be simplified.

  Note that the conditions in the first doping step are controlled so that the doping amount implanted into the semiconductor layers 3a and 3b becomes a desired value.

  Next, as shown in FIG. 8B, using a fourth photomask, a resist mask 29 covers the semiconductor layer 3a on the CPU side and covers the second gate electrode 12 on the panel side and the periphery thereof. To form.

  Next, a second doping process is performed. Through this second doping step, through-doping is performed through the gate insulating film (first and second insulating films 4 and 5) using the resist mask 29 as a mask. As a result, as shown in FIG. 8B, the high-concentration impurity regions (source and drain regions) 21 and 22 of the semiconductor layer 3b on the panel side are self-aligned via the first and second insulating films. High concentration impurities are introduced.

  In this embodiment mode, the second doping step shown in FIG. 8B is performed after the first doping step shown in FIG. 8A, but the second doping step shown in FIG. 8B is performed. It is also possible to perform the first doping step shown in FIG. 8A after performing the second doping step.

  Thereafter, as shown in FIG. 8C, the resist mask 29 is removed.

  Thus, on the substrate, the CPU side thin film transistor constituted by the first gate electrode 11, the gate insulating film made of the first insulating film 4, the source and drain regions 13 and 14, and the LDD regions 15 and 16 is provided. Produced. Further, on the substrate, a second gate electrode 12, a gate insulating film made up of first and second insulating films 4 and 5, source and drain regions 21, 22, first low-concentration impurity regions 17, 18, A thin film transistor on the panel side constituted by the second low-concentration impurity regions 19 and 20 is manufactured.

  In the fourth embodiment, the same effect as in the first embodiment can be obtained.

  That is, the gate insulating film on the CPU side is formed of the first insulating film 4, and the gate insulating film on the panel side is formed of the first and second insulating films 4 and 5, so that different thicknesses are formed on the same substrate. Even when the gate insulating film is formed, since the semiconductor layer 3a is not exposed to the etching atmosphere, the semiconductor layer can be prevented from being etched or contaminated. That is, when the second insulating film 5 on the CPU side is etched by forming the first insulating film 4 and the second insulating film 5 with insulating films having different etching rates, the first insulating film therebelow is formed. Etching can be performed using the film 4 as an etching stopper. Therefore, the semiconductor layer 3a is not exposed to the etching atmosphere, and etching damage and contamination can be prevented from occurring in the semiconductor layer.

  Further, since the first gate electrode 11 on the CPU side and the second gate electrode 12 on the panel side are formed in the same etching process, the process can be simplified.

  Further, the high concentration impurity regions 13 and 14 and the low concentration impurity regions 15 and 16 of the thin film transistor on the CPU side, the first low concentration impurity regions 17 and 18 and the second low concentration impurity regions 19 and 20 of the thin film transistor on the panel side are provided. Since impurities are introduced in a batch doping process, the process can be simplified.

  In the present embodiment, the second low-concentration impurity regions 19 and 20 located inside the source and drain regions 21 and 22 are formed in the active layer 3b of the thin film transistor on the panel side, and the second low-concentration impurity regions 19 and 20 are formed in the active layer 3b. First low-concentration impurity regions 17 and 18 located inside two low-concentration impurity regions are formed, and the impurity concentration of the first low-concentration impurity regions 17 and 18 is set to be lower than that of the second low-concentration impurity regions 19 and 20 It is low. Thereby, hot carrier deterioration can be reduced, and higher reliability can be obtained in the thin film transistor on the panel side.

(Embodiment 5)
9A and 9B are cross-sectional views showing a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention. The same parts as those in FIGS. Only explained.

  First, the steps shown in FIGS. 1 to 3A in Embodiment Mode 1 are performed.

  Next, as shown in FIG. 9A, a resist mask 24 is formed using a fourth photomask so as to cover the second gate electrode 12 on the panel side and the periphery thereof.

  Next, a first doping process is performed. Through the first doping step, through-doping is performed through the gate insulating film (first and second insulating films 4 and 5) using the resist mask 24 and the gate electrode 11 as a mask. That is, on the CPU side, through doping is performed through the exposed portions of the first insulating film 4 and the first conductive film 8a using the first gate electrode 11 as a mask, and on the panel side, the first mask is used as the first mask using the resist mask 24 as a mask. Through doping is performed through the second insulating films 4 and 5. As a result, as shown in FIG. 9A, on the CPU side, the high concentration impurity regions (source and drain regions) 13 and 14 of the semiconductor layer 3a have a high concentration in a self-aligned manner via the first insulating film. Impurities are introduced, and low concentration impurities are introduced into the low concentration impurity regions (LDD regions) 15 and 16 of the semiconductor layer 3a in a self-aligned manner through the exposed portions of the first conductive film 8a and the first insulating film. The Further, high-concentration impurities are introduced into the high-concentration impurity regions (source and drain regions) 21 and 22 of the semiconductor layer 3b on the panel side in a self-aligned manner through the first and second insulating films.

  As described above, the impurities are introduced into the high-concentration impurity regions 13 and 14 and the low-concentration impurity regions 15 and 16 on the CPU side and the high-concentration impurity regions 21 and 22 on the panel side in a collective doping process, thereby simplifying the process. Can be achieved.

  Thereafter, as shown in FIG. 9B, after removing the resist mask 24, a resist mask 25 is formed using a fifth photomask so as to cover the upper side of the CPU-side semiconductor layer 3a.

  Next, a second doping process is performed. By this second doping step, the resist mask 25 and the second gate electrode 12 are used as a mask through the gate insulating film (first and second insulating films 4 and 5) and the exposed portion of the first conductive film 8a. Through dope. As a result, as shown in FIG. 9B, the exposed portion of the first conductive film 8a and the first and second insulating films are formed in the first low-concentration impurity regions 17 and 18 of the semiconductor layer 3b on the panel side. The first low-concentration impurities are introduced in a self-aligned manner through the first and second low-concentration impurity regions 19 and 20 of the semiconductor layer 3b. Low concentration impurities are introduced.

  In this embodiment mode, the second doping step shown in FIG. 9B is performed after the first doping step shown in FIG. 9A, but the second doping step shown in FIG. 9B is performed. It is also possible to perform the first doping step shown in FIG. 9A after performing the second doping step.

  Next, the resist mask 25 is removed. In this way, thin film transistors as shown in FIG. 4 are fabricated on the CPU side and the panel side.

  In the fifth embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 6)
10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. The same parts as those in FIGS. Only explained.

  First, the steps shown in FIGS. 1 to 3A in Embodiment Mode 1 are performed.

  Next, as shown in FIG. 10A, a resist mask 26 is formed so as to cover the semiconductor layer 3b on the panel side using a fourth photomask.

  Next, a first doping process is performed. Through the first doping process, through-doping is performed through the exposed portion of the first conductive film 8a and the gate insulating film (first insulating film 4) using the resist mask 26 and the first gate electrode 11 as a mask. As a result, as shown in FIG. 10A, on the CPU side, the high concentration impurity regions (source and drain regions) 13 and 14 of the semiconductor layer 3a are highly concentrated in a self-aligned manner via the first insulating film. Impurities are introduced, and low concentration impurities are introduced into the low concentration impurity regions (LDD regions) 15 and 16 of the semiconductor layer 3a in a self-aligned manner through the exposed portions of the first conductive film 8a and the first insulating film. The

  Thereafter, as shown in FIG. 10B, after removing the resist mask 26, a resist mask 27 is formed so as to cover the upper side of the semiconductor layer 3a on the CPU side using a fifth photomask.

  Next, a second doping process is performed. By this second doping step, the resist mask 27 and the second gate electrode 12 are used as a mask through the gate insulating film (first and second insulating films 4 and 5) and the exposed portion of the first conductive film 8a. Through dope. As a result, as shown in FIG. 10B, the exposed portion of the first conductive film 8a and the first and second insulating films are formed in the first low-concentration impurity regions 17 and 18 of the semiconductor layer 3b on the panel side. The first low-concentration impurities are introduced in a self-aligned manner through the first and second low-concentration impurity regions 19 and 20 of the semiconductor layer 3b. Low concentration impurities are introduced.

  Next, as shown in FIG. 10C, after removing the resist mask 27, the sixth photomask is used to cover the resist mask 28 over the semiconductor layer 3a on the CPU side and the second photomask on the panel side. It is formed so as to cover the gate electrode 12 and its periphery.

  Next, a third doping process is performed. Through the third doping step, through-doping is performed through the gate insulating film (first and second insulating films 4 and 5) using the resist mask 28 as a mask. As a result, as shown in FIG. 10C, the high-concentration impurity regions (source and drain regions) 21 and 22 of the semiconductor layer 3b on the panel side are self-aligned via the first and second insulating films. High concentration impurities are introduced.

  In this embodiment mode, the first doping step shown in FIG. 10A is performed, the second doping step shown in FIG. 10B is performed, and then the third doping step shown in FIG. 10C is performed. Although the steps are performed, the order of these doping steps can be changed. For example, the order of the first doping process, the third doping process, and the second doping process may be used, or the order of the second doping process, the first doping process, and the third doping process may be used. The order of the doping process, the third doping process, and the first doping process, or the order of the third doping process, the first doping process, and the second doping process, or the third doping process, The order of the second doping step and the first doping step may be used.

  Next, the resist mask 28 is removed. In this way, thin film transistors as shown in FIG. 4 are fabricated on the CPU side and the panel side.

  In the sixth embodiment, the same effect as in the first embodiment can be obtained.

  That is, even when gate insulating films having different thicknesses are formed on the same substrate, the semiconductor layer 3a is not exposed to the etching atmosphere, and therefore, it is possible to prevent etching damage and contamination of the semiconductor layer.

  Further, since the first gate electrode 11 on the CPU side and the second gate electrode 12 on the panel side are formed in the same etching process, the process can be simplified.

  In the present embodiment, the second low-concentration impurity regions 19 and 20 located inside the source and drain regions 21 and 22 are formed in the active layer 3b of the thin film transistor on the panel side, and the second low-concentration impurity regions 19 and 20 are formed in the active layer 3b. First low-concentration impurity regions 17 and 18 located inside two low-concentration impurity regions are formed, and the impurity concentration of the first low-concentration impurity regions 17 and 18 is set to be lower than that of the second low-concentration impurity regions 19 and 20 It is low. Thereby, hot carrier deterioration can be reduced, and higher reliability can be obtained in the thin film transistor on the panel side.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention can be applied to a thin film transistor having a GOLD (Gate-drain Overlapped LDD) structure (see Japanese Patent Application Laid-Open No. 2001-210833).

  In the above embodiment, the present invention is applied to the thin film transistor formed on the CPU side and the thin film transistor formed on the panel side. However, the present invention is not limited to this, and the thin film transistor formed on other than the CPU and the panel. The present invention can also be applied to.

  Further, the structure of the TFT is not limited to the above embodiment mode, and the present invention can be applied to a bottom gate type TFT as shown in FIG.

  As shown in FIG. 11, first, gate electrodes 30 and 31 are formed on a glass substrate 1 through a base insulating film 2. Next, the first insulating film 4 is formed on the entire surface including the gate electrodes 30 and 31, the second insulating film 5 is formed on the first insulating film 4, and the second insulating film 5 is formed on the second insulating film 5. A third insulating film 6 is formed. Next, after etching the third insulating film 6 using the second insulating film 5 as an etching stopper, the second insulating film 5 is etched using the first insulating film 4 as an etching stopper. As a result, a gate insulating film made of the first insulating film 4 is formed on the gate electrode 30 on the CPU side, and a gate made of the first to third insulating films 4 to 6 is formed on the gate electrode 31 on the panel side. An insulating film is formed. Next, island-shaped semiconductor layers 32a and 32b are formed on the gate insulating films on the CPU side and the panel side, respectively. Next, source and drain regions 33 to 36 and LDD regions 37 to 40 are formed in the semiconductor layers 32a and 32b. Next, an interlayer insulating film 41 is formed on the entire surface including the semiconductor layers 32a and 32b.

(A)-(C) are sectional drawings which show the manufacturing method of the semiconductor device by Embodiment 1 of this invention. (A)-(C) show the manufacturing method of the semiconductor device by Embodiment 1 of this invention, and are sectional drawings which show the process following FIG.1 (C). (A)-(C) show the manufacturing method of the semiconductor device by Embodiment 1 of this invention, and are sectional drawings which show the process following FIG.2 (C). FIG. 4 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention and illustrating the next step of FIG. (A), (B) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 2 of this invention. (A)-(C) are sectional drawings which show the manufacturing method of the semiconductor device by Embodiment 3 of this invention. (A)-(C) are sectional drawings which show the manufacturing method of the semiconductor device by Embodiment 4 of this invention. (A)-(C) are the manufacturing methods of the semiconductor device by Embodiment 4 of this invention, and are sectional drawings which show the process following FIG.7 (C). (A), (B) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 5 of this invention. (A)-(C) are sectional drawings which show the manufacturing method of the semiconductor device by Embodiment 6 of this invention. It is sectional drawing which shows the bottom gate type TFT by the modification of this invention. It is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

2, 101 ... Underlying insulating film 3a, 3b, 32a, 32b, 102, 103 ... Semiconductor layer (active layer)
4, 104 ... first insulating film 5, 105 ... second insulating film 6 ... third insulating film 7 ... resist mask 8, 8a, 106 ... first conductive film 9, 9a, 9b, 107 ... second Conductive film 10 ... resist mask 8,108 ... first gate electrode 9,109 ... second insulating film 10 ... resist mask 11 ... first gate electrode 12 ... second gate electrodes 13,14, 21,22 , 33 to 36... High concentration impurity regions (source and drain regions)
15, 16, 37-40 ... Low concentration impurity region (LDD region)
17, 18 ... first low-concentration impurity regions 19, 20 ... second low-concentration impurity regions 23 to 29 ... resist masks 30, 31 ... gate electrodes 41 ... interlayer insulating film

Claims (16)

A first semiconductor layer formed on a substrate;
A second semiconductor layer formed on the substrate;
A first insulating film formed on each of the first semiconductor layer and the second semiconductor layer;
A second insulating film formed on the second semiconductor layer via the first insulating film;
A third insulating film formed on the second insulating film;
Comprising
The first insulating film formed on the first semiconductor layer constitutes a first gate insulating film;
The first to third insulating films formed on the second semiconductor layer constitute a second gate insulating film ;
The first insulating film comprises a SiON film;
The second insulating film comprises a SiN film;
The semiconductor device, wherein the third insulating film is made of a SiON film . A first semiconductor layer formed on a substrate;
A second semiconductor layer formed on the substrate;
A first insulating film formed on each of the first semiconductor layer and the second semiconductor layer;
A second insulating film formed on the second semiconductor layer via the first insulating film;
A third insulating film formed on the second insulating film;
A first gate electrode formed on the first semiconductor layer via the first insulating film and comprising a first conductive film and a second conductive film, and a part of the first conductive film said first gate electrode but having a shape exposed from the second conductive film,
A second gate electrode formed on the second semiconductor layer via the first to third insulating films and comprising the first conductive film and the second conductive film; said second gate electrode part has a shape that is exposed from the second conductive film of the conductive film,
Comprising
The first insulating film formed on the first semiconductor layer constitutes a first gate insulating film;
The first to third insulating films formed on the second semiconductor layer constitute a second gate insulating film ;
The first insulating film comprises a SiON film;
The second insulating film comprises a SiN film;
The semiconductor device, wherein the third insulating film is made of a SiON film . A first semiconductor layer formed on a substrate;
A first high-concentration impurity region formed in the first semiconductor layer;
A first low-concentration impurity region formed in the first semiconductor layer and formed inside the first high-concentration impurity region;
A second semiconductor layer formed on the substrate;
A second high-concentration impurity region formed in the second semiconductor layer;
A second low-concentration impurity region formed in the second semiconductor layer and formed inside the second high-concentration impurity region;
A first insulating film formed on each of the first semiconductor layer and the second semiconductor layer;
A second insulating film formed on the second semiconductor layer via the first insulating film;
A third insulating film formed on the second insulating film;
A first gate electrode formed on the first semiconductor layer via the first insulating film and comprising a first conductive film and a second conductive film, and a part of the first conductive film said first gate electrode but having a shape exposed from the second conductive film,
A second gate electrode formed on the second semiconductor layer via the first to third insulating films and comprising the first conductive film and the second conductive film; said second gate electrode part has a shape that is exposed from the second conductive film of the conductive film,
Comprising
The first insulating film formed on the first semiconductor layer constitutes a first gate insulating film;
The first to third insulating films formed on the second semiconductor layer constitute a second gate insulating film ;
The first insulating film comprises a SiON film;
The second insulating film comprises a SiN film;
The semiconductor device, wherein the third insulating film is made of a SiON film . 4. The second low-concentration impurity region according to claim 3 , comprising two impurity concentration regions divided into the second high-concentration impurity region side and the channel formation region side of the second semiconductor layer, A semiconductor device, wherein the impurity concentration region on the second high concentration impurity region side has a higher impurity concentration than the impurity concentration region on the channel formation region side of the second semiconductor layer. Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And a second gate insulating film formed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer. A manufacturing method of
The first insulating film comprises a SiON film;
The second insulating film comprises a SiN film;
The method for manufacturing a semiconductor device, wherein the third insulating film is made of a SiON film . Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. the first gate electrode part has a shape that is exposed from the second conductive film, thereby forming through said first gate insulating film on the first semiconductor layer, the second conductive film And the second gate electrode made of the first conductive film, wherein the second gate electrode has a shape in which a part of the first conductive film is exposed from the second conductive film. A method of manufacturing a semiconductor device formed on the semiconductor layer via the second gate insulating film ,
The first insulating film comprises a SiON film;
The second insulating film comprises a SiN film;
The method for manufacturing a semiconductor device, wherein the third insulating film is made of a SiON film . 7. The method according to claim 6 , wherein after forming the first gate electrode and the second gate electrode, the first semiconductor layer and the second gate electrode using the first gate electrode and the second gate electrode as a mask. A method for manufacturing a semiconductor device, wherein an impurity is doped into a semiconductor layer through the first gate insulating film and the second gate insulating film. 7. The method according to claim 6 , wherein after forming the first gate electrode and the second gate electrode, the first semiconductor layer and the second gate electrode using the first gate electrode and the second gate electrode as a mask. A method for manufacturing a semiconductor device, wherein an impurity is doped into a semiconductor layer through an exposed portion of the first conductive film, the first gate insulating film, and the second gate insulating film. 9. The resist mask according to claim 7 or 8 , wherein after the doping through the second gate insulating film, a resist mask is formed on the first semiconductor layer so as to cover the second gate electrode and the periphery of the second gate electrode. Then, a method for manufacturing a semiconductor device, wherein an impurity is doped into the second semiconductor layer through the second gate insulating film using the resist mask as a mask. Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. the first gate electrode part has a shape that is exposed from the second conductive film, thereby forming through said first gate insulating film on the first semiconductor layer, the second conductive film And the second gate electrode made of the first conductive film, wherein the second gate electrode has a shape in which a part of the first conductive film is exposed from the second conductive film. Formed on the semiconductor layer via the second gate insulating film,
Forming a resist mask covering the second gate electrode and the periphery of the second gate electrode on the first semiconductor layer;
Doping the second semiconductor layer with the first impurity through the second gate insulating film using the resist mask as a mask,
Removing the resist mask;
Using the first gate electrode and the second gate electrode as a mask, a second impurity is introduced into the first semiconductor layer and the second semiconductor layer, the exposed portion of the first conductive film, and the first gate. A method for manufacturing a semiconductor device in which doping is performed through an insulating film and the second gate insulating film ,
The first insulating film comprises a SiON film;
The second insulating film comprises a SiN film;
The method for manufacturing a semiconductor device, wherein the third insulating film is made of a SiON film . Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. the first gate electrode part has a shape that is exposed from the second conductive film, thereby forming through said first gate insulating film on the first semiconductor layer, the second conductive film And the second gate electrode made of the first conductive film, wherein the second gate electrode has a shape in which a part of the first conductive film is exposed from the second conductive film. Formed on the semiconductor layer via the second gate insulating film,
Forming a first resist mask covering the periphery of the second gate electrode and the second gate electrode;
Using the first resist mask and the first gate electrode as a mask, impurities are introduced into the first semiconductor layer and the second semiconductor layer, the exposed portion of the first conductive film, the first gate insulating film, A method for manufacturing a semiconductor device in which doping is performed through the second gate insulating film ,
The first insulating film comprises a SiON film;
The second insulating film comprises a SiN film;
The method for manufacturing a semiconductor device, wherein the third insulating film is made of a SiON film . 12. The method according to claim 11 , wherein after doping through the second gate insulating film, the first resist mask is removed, a second resist mask is formed to cover the first semiconductor layer, and the second resist mask is formed. An impurity is doped into the second semiconductor layer through the exposed portion of the second gate insulating film and the first conductive film using the resist mask and the second gate electrode as a mask. Device fabrication method. Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. the first gate electrode part has a shape that is exposed from the second conductive film, thereby forming through said first gate insulating film on the first semiconductor layer, the second conductive film And the second gate electrode made of the first conductive film, wherein the second gate electrode has a shape in which a part of the first conductive film is exposed from the second conductive film. Formed on the semiconductor layer via the second gate insulating film,
Forming a first resist mask covering the first semiconductor layer;
Using the first resist mask and the second gate electrode as a mask, the second semiconductor layer is doped with a first impurity through the exposed portions of the second gate insulating film and the first conductive film. ,
Removing the first resist mask;
Forming a second resist mask covering the second gate electrode and the periphery of the second gate electrode;
Using the second resist mask and the first gate electrode as a mask, a second impurity is introduced into the first semiconductor layer and the second semiconductor layer, the exposed portion of the first conductive film, and the first gate. A method for manufacturing a semiconductor device in which doping is performed through an insulating film and the second gate insulating film ,
The first insulating film comprises a SiON film;
The second insulating film comprises a SiN film;
The method for manufacturing a semiconductor device, wherein the third insulating film is made of a SiON film . Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming a second insulating film on the first insulating film;
Forming a third insulating film on the second insulating film;
Etching the third insulating film located on the first semiconductor layer using the second insulating film as an etching stopper,
By etching the second insulating film located on the first semiconductor layer using the first insulating film as an etching stopper, the first insulating film formed on the first semiconductor layer is made of the first insulating film. And forming a second gate insulating film composed of the first insulating film, the second insulating film, and the third insulating film on the second semiconductor layer,
Forming a first conductive film on the first gate insulating film and the second gate insulating film;
Forming a second conductive film on the first conductive film;
By processing the second conductive film and the first conductive film, the first conductive film is a first gate electrode made of the second conductive film and the first conductive film. the first gate electrode part has a shape that is exposed from the second conductive film, thereby forming through said first gate insulating film on the first semiconductor layer, the second conductive film And the second gate electrode made of the first conductive film, wherein the second gate electrode has a shape in which a part of the first conductive film is exposed from the second conductive film. Formed on the semiconductor layer via the second gate insulating film,
Forming a first resist mask so as to cover the second semiconductor layer;
A semiconductor device in which an impurity is doped into the first semiconductor layer through the exposed portion of the first conductive film and the first gate insulating film using the first resist mask and the first gate electrode as a mask . A production method comprising:
The first insulating film comprises a SiON film;
The second insulating film comprises a SiN film;
The method for manufacturing a semiconductor device, wherein the third insulating film is made of a SiON film . 15. The method according to claim 14 , wherein after doping through the first gate insulating film, the first resist mask is removed, and a second resist mask is formed to cover the first semiconductor layer, and the second resist mask is formed. An impurity is doped into the second semiconductor layer through the exposed portion of the first conductive film and the second gate insulating film using the resist mask and the second gate electrode as a mask. Device fabrication method. 16. The method according to claim 15 , wherein after doping through the second gate insulating film, the second resist mask is removed, and the second gate electrode and the second gate electrode are formed on the first semiconductor layer. Forming a third resist mask covering the periphery of the semiconductor substrate, and doping the second semiconductor layer with an impurity through the second gate insulating film using the third resist mask as a mask Manufacturing method.

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