JP4434036B2 - Level shift circuit, electro-optical device using the same, and electronic apparatus - Google Patents

Description

  The present invention relates to a level shift circuit that converts a logic signal into a logic signal having a different amplitude, and is used in, for example, an electro-optical device and an electronic apparatus.

  In recent years, electro-optical devices that perform display by electro-optical changes in electro-optical materials such as liquid crystal and organic EL (electroluminescence) have been used as display devices in place of cathode ray tubes (CRT) as various information processing equipment and televisions. Is being widely used.

  Such electro-optical devices are classified according to driving methods, etc., and are roughly classified into an active matrix type in which pixels are driven by nonlinear elements such as transistors and diodes, and a passive matrix type in which pixels are driven without using nonlinear elements. can do. Among these, the active matrix type electro-optical device can drive each pixel independently, so that display with high display quality is possible.

  Here, the active matrix type electro-optical device has the following configuration. In an active matrix electro-optical device, pixel electrodes are formed corresponding to intersections between scanning lines extending in the row direction and data lines extending in the column direction. In addition, a non-linear element such as a thin film transistor (hereinafter referred to as TFT) that is turned on and off in accordance with a scanning signal supplied to the scanning line is interposed between the pixel electrode and the data line at the intersection. Has a configuration in which the counter electrode is opposed to the electro-optical material.

  Now, in order to drive an electro-optic material or a nonlinear element, a relatively high voltage is required. On the other hand, an external control circuit that supplies a clock signal, a control signal, or the like that serves as a driving reference to the electro-optical device is usually composed of a CMOS circuit, so that the amplitude of the logical input signal is relatively small. Therefore, an electro-optical device includes an amplitude conversion circuit that converts a low-amplitude logic input signal into a high-amplitude logic output signal at an output portion of a drive circuit that drives scanning lines and data lines and an input portion such as a clock signal. (Hereinafter simply referred to as “level shift circuit”) is generally provided.

Here, as the configuration of the level shift circuit, the first and second capacitive elements that input signals to one end, the offset circuit that offsets the voltage at the other end of these capacitive elements, and the other end of these capacitive elements are connected. In addition, a device including the first and second switching elements is known (see, for example, Patent Document 1). According to this configuration, high-speed operation is possible with a simple configuration.
JP 2003-110419 A

The input sensitivity of the level shift circuit having such a configuration is determined by the threshold voltages of the first and second switching elements.
On the other hand, the amplitude of the logic input signal input to the level shift circuit varies depending on the application circuit of the level shift circuit. In addition, noise is usually superimposed on the logic input signal, but the level of this noise also varies depending on the application circuit and operating conditions. Therefore, the input sensitivity of the level shift circuit is preferably suitable for the signal amplitude and noise level of the input logic input signal.
However, since the input sensitivity of the level shift circuit of Patent Document 1 is fixed to a specific range by the threshold voltage, which is a characteristic unique to the switching element, it is necessary to appropriately correspond to various logic input signals and noise levels. I could not.

  An object of the present invention is to provide a level shift circuit capable of appropriately dealing with a logic input signal and a noise level.

  The level shift circuit of the present invention has a capacitive element to which a logical input signal having a first logical amplitude is inputted at one end, and a first logical inversion level with respect to an input connected to the other end of the capacitive element. And a second logic inversion circuit having a second logic inversion level with respect to an input connected to the other end of the capacitive element, the first logic inversion circuit and A logic output circuit that inverts a logic output signal having a second logic amplitude by matching the output polarity of the second logic inverting circuit; and one end of an input connected to the other end of the capacitive element; A third logic inversion circuit having a third logic inversion level lower than the first logic inversion level and higher than the second logic inversion level with respect to an input connected to the other end of the element; A first logic inversion circuit and said first And at least one of the first logic inversion level and the second logic inversion level is connected to at least one of the logic inversion circuits and a power supply corresponding to the second logic amplitude. Inversion level setting means.

Here, the logic inversion level is a logic threshold voltage for the input signal for the logic inversion circuit to invert the logic level of the output signal. When the voltage of the input signal is lower than the logic inversion level of the logic inversion circuit, each logic inversion circuit drives the output signal to the H level assuming that the logic level of the input signal is L level. On the other hand, when the voltage of the input signal is higher than the logic inversion level of the logic inversion circuit, the output signal is driven to L level assuming that the logic level of the input signal is H level.
In this level shift circuit, the inputs of the first and second logic inverting circuits are connected to the other end of the capacitive element, and the inputs and outputs of the third logic inverting circuit are connected to the other end. The logic output circuit inverts the logic output signal when the output polarities of the first and second logic inversion circuits match. Here, the third logic inversion level is set lower than the first logic inversion level in the first logic inversion circuit and higher than the second logic inversion level in the second logic inversion circuit. Therefore, when a logic input signal is input to one end of the capacitive element and the voltage at the other end exceeds the first logic inversion level, the output polarities of the first and second logic inversion circuits match, and the logic output signal is Invert. Next, when the voltage at the other end falls below the second logic inversion level, the output polarities of the first and second logic inversion circuits match, and the logic output signal is further inverted. In this way, a logic output signal having a logic amplitude different from that of the input signal is output.
According to the present invention, the logic inversion level setting means for connecting at least one of the first logic inversion circuit and the second logic inversion circuit and the power supply corresponding to the second logic amplitude includes: By changing the resistance value, the first logic inversion level and / or the second logic inversion level can be changed. Therefore, the sensitivity suitable for the logical input signal and noise can be set by adjusting the sensitivity of the level shift circuit.

  According to another aspect of the present invention, there is provided a level shift circuit including: a first capacitive element that receives a logic input signal having a first logic amplitude at one end; and a second capacitor that receives the logic input signal at one end. A capacitive element, a first logic inverting circuit having a first logic inversion level with respect to an input connected to the other end of the first capacitive element, and connected to the other end of the second capacitive element A second logic inversion circuit having a second logic inversion level with respect to the input, and the output logic of the first logic inversion circuit and the second logic inversion circuit coincide with each other so that the second logic amplitude A logic output circuit for inverting a logic output signal, and one input and an output connected to the other end of the first capacitive element, and an input connected to the other end of the first capacitive element, Having a third logic inversion level lower than the first logic inversion level; 3 and the other end of the second capacitive element, and one input and an output are connected to the other end of the second capacitive element, and a second logical inversion level is applied to the input connected to the other end of the second capacitive element. A fourth logic inversion circuit having a higher fourth logic inversion level, the first logic inversion circuit, the second logic inversion circuit, the third logic inversion circuit, and the fourth logic inversion circuit. Are connected to a power supply corresponding to the second logic amplitude, the first logic inversion level, the second logic inversion level, the third logic inversion level, and the fourth logic inversion level. Logic inversion level setting means for setting at least one of the logic inversion levels.

  According to the present invention, the sensitivity of the level shift circuit is determined by the difference between the first logic inversion level and the third logic inversion level and the difference between the second logic inversion level and the fourth logic inversion level. Is done. Therefore, the logic inversion level setting means for connecting the logic inversion circuit and the power supply can change the logic inversion level and adjust the sensitivity of the level shift circuit. Therefore, it is possible to set a sensitivity suitable for a logical input signal and noise.

  Here, in the level shift circuit, the logic inversion level setting unit includes a plurality of circuit elements having a resistance value, and a circuit element selection unit that selects an effective circuit element among the plurality of circuit elements. It is preferable.

  According to these inventions, the circuit element selection means changes the resistance value of the connection by selecting an effective circuit element and changes the logic inversion level, so that the input sensitivity of the level shift circuit is adjusted. Can do.

  In the level shift circuit, the circuit element is preferably a transistor.

  According to these inventions, the logic inversion level of each logic inversion circuit is the shape or dimension of the transistor element provided in the logic inversion circuit and the transistor element provided in the logic inversion level setting means connected to the logic inversion circuit. It is determined by the number of parallel stages. Therefore, the input sensitivity of the level shift circuit can be adjusted at the stage of circuit or layout design. In addition, the relationship between the logic inversion levels adjusted in this way is less affected by variations in the manufacturing process.

  In addition, for example, by providing the level shift circuit in an electro-optical device such as a liquid crystal display device, an electro-optical device that displays a high-quality image with little influence of noise can be provided.

  Further, by providing the electronic apparatus with the electro-optical device, it is possible to provide an electronic apparatus with little influence of noise.

<1. First Embodiment>
First, the structure of the level shift circuit 100 which is 1st Embodiment of this invention is demonstrated with reference to figures.
<1-1: Configuration>

FIG. 1 is a circuit diagram showing a configuration of the level shift circuit 100.
In this figure, an input terminal IN inputs a low-amplitude logic input signal as a first logic amplitude before conversion, and an output terminal OUT has a high-amplitude signal as a second logic amplitude after conversion. A logic output signal is output. Here, as a power supply corresponding to the amplitude of the high-amplitude logic output signal, the potential of the negative (reference) power supply is expressed as VSS, and the potential of the positive power supply is expressed as VDD. Accordingly, the high-amplitude logic output signal output from the level shift circuit 100 operating under the voltage supplied from the power supply has a low potential (reference) potential corresponding to the L level of approximately VSS, and corresponds to the H level. The higher potential on the side becomes approximately VDD. As an example of the logic inversion circuit, an inverter circuit having a complementary transistor circuit including a P-channel transistor and an N-channel transistor is illustrated and described. As the P-channel transistor and the N-channel transistor, a P-channel TFT and An example of an N-channel TFT will be described.

In FIG. 1, a level shift circuit 100 includes a capacitor (capacitance element) 110 that allows only an AC component of an input signal to pass therethrough, and a third logic inversion circuit serving as a bias circuit that supplies a bias voltage V _B to the other end of the capacitor 110. The logic inversion circuit 120 and the logic output circuit 130 are provided.
The logic output circuit 130 includes a logic inversion circuit 140 as a first logic inversion circuit having a first logic inversion level with respect to the input, logic inversion level setting means 144, 146, 154, 156, A logic inversion circuit 150 as a second logic inversion circuit having a second logic inversion level and a logic output unit 135 are included.
The logic inversion circuit 140 determines the voltage at the other end of the capacitor 110 with reference to the first logic inversion level _VH , and outputs an output signal obtained by inverting the logic level of the voltage at the other end.
The logic inversion circuit 150 determines the voltage at the other end of the capacitor 110 with reference to the second logic inversion level _VL , and outputs an output signal obtained by inverting the logic level of the voltage at the other end.
The logic inversion level setting means 144, 146, 154, and 156 connect the logic inversion circuits 140 and 150 to the power source. Specifically, the logic inversion level setting unit 144 connects the logic inversion circuit 140 and the positive power source, and the logic inversion level setting unit 146 connects the logic inversion circuit 140 and the negative side power source. . Further, the logic inversion level setting means 154 connects the logic inversion circuit 150 and the positive power source, and the logic inversion level setting means 156 connects the logic inversion circuit 150 and the negative power source. Each of the logic inversion level setting means 144, 146, 154, and 156 is variable resistance means for changing the resistance of the connection. By changing the resistance of the connection, the first logic inversion level V _H and the second logic inversion level setting means 144, 146, 154, and 156 are changed. Set the inversion level _VL .
The logic output unit 135 inverts the logic output signal having the second logic amplitude when the output polarities of the logic inversion circuit 140 and the logic inversion circuit 150 match. The logic output unit 135 includes a NAND circuit 160, a NOR circuit 170, a logic inverting circuit 180, and a logic inverting circuit 190.
The logic inversion circuit 120 has a third logic inversion level lower than the first logic inversion level VH and higher than the second logic inversion level VL with respect to the input. Since the input and output of the logic inverting circuit 120 are connected in common to the node N110, the voltage of the output of the logic inverting circuit 120 becomes the third logic inversion level, and this third logic inversion level is the bias voltage V. _B.
Each element of the level shift circuit 100 is formed on the same substrate by the same semiconductor manufacturing process. Further, the TFTs as switching elements constituting the above-described circuits are formed so as to be arranged close to each other.

Here, the input terminal IN of the level shift circuit 100 is connected to one end of the capacitor 110, and the logic input signal from the input terminal IN is input to the capacitor 110 at this one end. On the other hand, the other end of the capacitor 110 is connected to the input and output of the logic inverting circuit 120, and further connected to the inputs of the logic inverting circuit 140 and the logic inverting circuit 150. The output of the logic inverting circuit 140 is connected to the input of the NAND circuit 160, and the output of the logic inverting circuit 150 is connected to the input of the NOR circuit 170.
The output of the NAND circuit 160 becomes the output terminal OUT of the level shift circuit 100 and is connected to the logic inverting circuit 180. The output of the logic inverting circuit 180 is connected to the input of the NOR circuit 170. The output of the NOR circuit 170 is connected to the input of the logic inverting circuit 190, and the output of the logic inverting circuit 190 is connected to the input of the NAND circuit 160.
The logic output unit 135 is a holding circuit that holds the determination result of the logic inversion circuit 140 and the determination result of the logic inversion circuit 150 by the NAND circuit 160, the NOR circuit 170, the logic inversion circuit 180, and the logic inversion circuit 190. Yes. This holding circuit is an RS flip-flop that is set by the L level signal of the logic inverting circuit 140 and is reset by the H level signal of the logic inverting circuit 150.

  Note that all the logic inverting circuits of the present embodiment are connected to the power supply. However, in the circuit diagram of FIG. 1, the logic inverting circuit 140 and the logic inverting circuits connected via the logic inverting level setting means 144, 146, 154, and 156 are used. Only the inverting circuit 150 is illustrated with the power supply omitted.

FIG. 2 is a circuit diagram showing the structure of the logic inversion circuit 140 and the logic inversion level setting means 144 and 146 of the level shift circuit 100. The logic inversion circuit 150, which is another logic inversion circuit, has the same configuration, and will not be described and illustrated.
The logic inversion circuit 140 is an inverter circuit including a complementary transistor circuit, and includes a P-channel TFT 141 and an N-channel TFT 142.
The input of the logic inverting circuit 140 is commonly connected to the gates of the P-channel TFT 141 and the N-channel TFT 142. The drains of the P-channel TFT 141 and the N-channel TFT 142 are also connected to each other and become the output of the logic inversion circuit 140.
The source of the P-channel TFT 141 which is the positive power supply terminal of the logic inverting circuit 140 is connected to the positive power supply at the V _DD level via the logic inverting level setting means 144. The source of the N-channel type TFT142 is a negative side of the power supply terminal of the logic inverting circuit 140 is connected to the negative side of the power supply is V _SS level through the logic inversion level setting means 146.

The logic inversion level setting means 144 includes a switch 144S1 as a circuit element selection means for selecting an effective resistance among the resistances 144R1 and 144R2, and the resistance 144R1 and the resistance 144R2 as a plurality of circuit elements having resistance values, and a switch 144S2. The resistors 144R1 and 144R2 are connected in parallel to the switches 144S1 and 144S2, respectively, and constitute a circuit in which a set of resistors and switches connected in parallel is connected in series. The logic inversion level setting means 144 connects the logic inversion circuit 140 to the positive power supply at the V _DD level, and makes the connection resistance variable depending on the state of the switches 144S1 and 144S2. For example, when the switch 144S1 is opened and the switch 144S2 is closed, the resistor 144R1 connected in parallel to each other is enabled and the resistor 144R2 is disabled. Therefore, the connection resistance of the logic inversion level setting unit 144 as a whole is the resistance value of the resistor 144R1.
The logic inversion level setting unit 146 is configured similarly to the logic inversion level setting unit 144.

Here, the first logic inversion level V _H that the logic inversion circuit 140 has is the characteristics of the P-channel TFT 141 and the N-channel TFT 142 constituting the logic inversion circuit 140 and the connection of the logic inversion level setting means 144 and 146. Set by resistance. The voltage setting will be described below.

FIG. 3 is a circuit diagram showing a configuration of connection resistors by the logic inversion circuit 140 and the logic inversion level setting means 144 and 146 of the level shift circuit 100. In the example of FIG. 3, the logic inversion level setting unit 144 uses Rp as the resistance value that connects the logic inversion circuit 140 and the positive power supply that is VDD, and the logic inversion level setting unit 146 has the logic inversion circuit 140 and VSS. The resistance value for connecting the negative power source, which is the level, is Rn.
Here, if, when connecting the inputs and outputs of the logic inversion circuit 140, equal to the voltage Vi of the input voltage Vo of the output, the value of the first logic inversion level V _H. At this time, the P-channel TFT 141 and the N-channel TFT 142 are in a saturation operation. (The relationship of Vds> Vgs−Vtp is established among the drain-source voltage Vds, the gate-source voltage Vgs, and the threshold voltage Vtp of each TFT.)
Here, the positive power source that is V _DD passes through the logic inversion level setting means 144, the P-channel TFT 141, the N-channel TFT 142, and the logic inversion level setting means 146, and becomes the negative power source that is Vss. Let the flowing current be Ids. With reference to the Vss level, the voltage at the connection point between the logic inversion level setting unit 144 and the logic inversion circuit 140 is Vd, and the voltage at the connection point between the logic inversion circuit 140 and the logic inversion level setting unit 146 is Vs. The following approximate expression is established for Ids of the P-channel TFT 141.

  Here, the coefficient β is determined by the following equation based on the gate length Lp, the gate width Wp, the gate capacitance Co depending on the manufacturing process, and the mobility μp of the P-channel TFT 141.

Further, the following approximate expression is established for Ids of the N-channel TFT 142.

  Here, the apparent threshold values Vtp ′ and Vtn ′ considering the voltage drop due to the connection resistance of the logic inversion level setting means 144 and 146 are set as Vtp ′ = Ttp + (Vdd−Vd), Vtn ′ = Vtn + Vs, Replace the above expression.

Then, the output voltage Vo at the logic inversion level V _H of the logic inversion circuit 140 is obtained by the following equation.

この一方で、論理反転レベル設定手段１４４、１４６について次の式が成立している。 Here, the coefficient α is as shown in the following equation.

On the other hand, the following formula is established for the logic inversion level setting means 144 and 146.

Therefore, as Rp increases, the apparent threshold voltage Vtp ′ of the P-channel TFT 141 increases. Further, as Rn increases, the apparent threshold voltage Vtn ′ of the N-channel TFT 142 increases. Therefore, when Rp increases, Vo decreases, and when Rn increases, Vo increases.
In this way, the logic inversion level setting means 144 and 146 change the connection resistances Rp and Rn between the logic inversion circuit 140 and the power supply at the V _DD level or the _VSS level, and thereby the first logic inversion circuit 140 has the first. setting the first logic inversion level V _H to a predetermined value.

The logic inversion circuit 140 and the logic inversion level setting means 144 and 146 have been described above. The same applies to the logic inversion circuit 150 and the logic inversion level setting means 154 and 156. The logic inversion level V _L can be obtained by the following equation.

ここで、α’は、論理反転回路１４０のαと同様であるが、ＴＦＴのゲート長および幅が論理反転回路１４０のＴＦＴと異なるため、αとは異なる。
さらに、論理反転回路１２０のバイアス電圧Ｖ_Ｂについても同様に求めることができる。本実施形態の論理反転回路１２０は、論理反転レベル設定手段を介さず、電源に直接に接続されるため、ＴＦＴのしきい値として、Ｖｔｐ’、Ｖｔｎ’ではなく、Ｖｔｐ、Ｖｔｎを用い以下の式で求めることができる。

Here, α ′ is the same as α of the logic inversion circuit 140, but is different from α because the gate length and width of the TFT are different from those of the TFT of the logic inversion circuit 140.
Further, the bias voltage V _B of the logic inverting circuit 120 can be similarly obtained. Since the logic inversion circuit 120 of this embodiment is directly connected to the power supply without going through the logic inversion level setting means, Vtp and Vtn are used as threshold values of TFTs instead of Vtp ′ and Vtn ′. It can be obtained by an expression.

ここで、α’’は、論理反転回路１４０のαと同様であるが、ＴＦＴのゲート長および幅が論理反転回路１４０のＴＦＴと異なるため、異なるものとしている。

Here, α ″ is the same as α of the logic inversion circuit 140, but is different because the gate length and width of the TFT are different from those of the TFT of the logic inversion circuit 140.

In the level shift circuit 100 of the present embodiment, the logic inversion circuits 120, 140, and 150 have a ratio between the gate width Wp and the gate length Lp of the TFTs that constitute each of them, or a ratio between the gate width Wn and the gate length Ln. Are different from each other, different coefficients α, α ′ and α ″ are set.
Specifically, for example, in the P-channel TFTs 141, 121, and 151 of the logic inversion circuits 140, 120, and 150, by increasing the gate length in this order and making the other dimensions the same, the coefficient is expressed by the following relationship: Set to.

In this case, even if the resistances Rp and Rn of the connection of the logic inversion level setting means 144, 146, 154 and 156 are all 0, the bias voltage V _B , the first logic inversion level V _H and the second logic inversion Specifically, the level V _L is set to have the relationship of the following equation.

That is, the bias voltage V _B of the logic inverting circuit 120 is set such that the first logic inverting level V _H of the logic inverting circuit 140 is set lower and the second logic inverting level _VL of the logic inverting circuit 150 is set higher. Yes.

  FIG. 4 is a graph showing input / output characteristics of the logic inversion circuits 120, 140, and 150.

Since the output and the input of the logic inverting circuit 120 are connected, in FIG. 4, the bias voltage V _{B is determined} by the intersection of the input / output characteristic curve of the logic inverting circuit 120 alone and the line VIN = VOUT. Is shown.
For the logic inversion circuit 140, if the logic inversion circuit 140 and the logic inversion level setting means 144 and 146 are taken out independently and input / output is connected, the input / output characteristic curve of the logic inversion circuit 140 and VIN = The first logic inversion level V _H is indicated by the intersection with the straight line of VOUT. As for the logic inversion circuit 140, the input / output characteristics when the connection resistances Rp and Rn of the logic inversion level setting means 144 and 146 are 0 are indicated by solid lines. Here, when the connection resistance Rp of the logic inversion level setting means 144 is increased, the input / output characteristic becomes, for example, the broken line on the left side of the solid line, and therefore, the first logic that is the intersection with the straight line of VIN = VOUT. The inversion level _VH becomes smaller. On the other hand, when the connection resistance Rn of the logic inversion level setting means 146 is increased, the input / output characteristic becomes, for example, a broken line on the right side of the solid line, and therefore, the first intersection that is the intersection with the straight line of VIN = VOUT. The logic inversion level V _H increases. Thus, by changing the connection resistance of the logic inversion level setting means 144 and 146, the first logic inversion level _VH can be changed and set to a value suitable for the state of the input signal.
Similarly, for the logic inversion circuit 150, the second logic inversion level _VL is indicated by the intersection of the input / output characteristic curve of the logic inversion circuit 150 in FIG. 4 and the straight line VIN = VOUT. Here, with respect to the input / output characteristics of the logic inversion circuit 150 and the second logic inversion level _VL as well as the logic inversion circuit 140, the connection resistance of the logic inversion level setting means 154 and 156 is changed to change the second The logic inversion level V _L can be changed and set to a value suitable for the state of the input signal. The changed curve of the input / output characteristics changes in the same manner as the logic inversion circuit 140, and is not shown.
In the graph of FIG. 4, a relationship of V _L <V _B <V _H is shown.

<1-2: Operation>
Next, the operation of the level shift circuit 100 will be described.
FIG. 5 is a diagram for explaining this operation, and shows voltage waveforms in each part of the level shift circuit 100.

First, when a low-amplitude logic input signal VIN is supplied to the input terminal IN, the voltage waveform V _B out appearing at the node N110, that is, the other end of the capacitor 110, is converted into a differential waveform of the logic input signal VIN and the bias voltage V _B Is added (offset). Note that the logic input signal VIN in FIG. 5 has noise.

Here, when the voltage at node N110 is higher than the first logic inversion level V _H, the logic inversion circuit 140 level of the input signal is determined to be H, the output signal V _H out to L level. Here, since the logic inversion circuit 150 maintains the output signal V _L out at the L level, the output polarities of the logic inversion circuit 140 and the logic inversion circuit 150 match. At this time, the output signal of the NAND circuit 160 connected to the output terminal OUT becomes H level, and the output signal of the logic inversion circuit 180 becomes L level. As a result, the output signal of the NOR circuit 170 becomes H level, and the output signal of the logic inversion circuit 190 becomes L level. As a result, the input of the NAND circuit 160 becomes L level, and this state is maintained. As described above, the logic output unit 135 including the NAND circuit 160, the NOR circuit 170, the logic inversion circuit 180, and the logic inversion circuit 190 has the same output polarity as the logic inversion circuit 140 and the logic inversion circuit 150. The logic output signal output from the output terminal OUT is inverted. Here, the logical output unit 135, the voltage of the node N110 is a determination result of the logic inversion circuit 140 to beyond the first logic inversion level _{V H,} the voltage of the node N110 falls below a first logic inversion level _{V H} Hold it after.
On the other hand, when the voltage at the node N110 falls below the second logic inversion level V _L , the logic inversion circuit 150 assumes that the level of the input signal is L and sets the output signal V _L out to the H level. Here, since the logic inverting circuit 140 has the output signal V _H out at the H level, the output polarities of the logic inverting circuit 140 and the logic inverting circuit 150 match. Further, the output signal of the NOR circuit 170 becomes L level, and the output signal of the logic inverting circuit 190 connected to the input of the NAND circuit 160 becomes H level. At this time, since the other input of the NAND circuit 160 is H, the output signal of the NAND circuit 160 connected to the output terminal OUT becomes L level. As a result, the output of the logic inverting circuit 180 becomes H level. State is maintained. In this manner, the logic output unit 135 inverts the logic output signal output from the output terminal OUT again when the output polarities of the logic inversion circuit 140 and the logic inversion circuit 150 match. Here, the logic output unit 135 indicates that the logic inversion circuit 150 has determined that the voltage at the node N110 has fallen below the second logic inversion level V _L , and the voltage at the node N110 has exceeded the second logic inversion level V _L. Hold it after.

When the low-amplitude logic input signal VIN supplied to the input terminal IN of the level shift circuit 100 becomes H level, the high-amplitude logic output signal VOUT output from the output terminal OUT becomes H level. On the other hand, when the logic input signal VIN becomes L level, the high amplitude logic output signal VOUT output from the output terminal OUT becomes L level. Therefore, a high-amplitude logic output signal corresponding to the low-amplitude logic input signal supplied to the input terminal IN of the level shift circuit 100 is output from the output terminal OUT. Note that when the logic output signal VOUT is at the H level, it is held until the logic input signal VIN is at the L level, and when the logic output signal VOUT is at the L level, it is held until the logic input signal VIN is at the H level. Is done.
The logic output unit 135 inverts the logic output signal output from the output terminal OUT when the output polarity of the logic inversion circuit 140 and that of the logic inversion circuit 150 coincide with each other. At the same time, by returning to the vicinity of the bias voltage V _B , the output of the logic output signal does not change even if it falls below the first logic inversion level V _H or conversely exceeds the second logic inversion level V _L. Therefore, it is possible to appropriately follow the output of the logic output signal even for an input signal having a long change cycle.

<1-3: Effect>
In the level shift circuit 100, the difference between the first logic inversion level V _H and the bias voltage V _B and the difference between the second logic inversion level V _L and the bias voltage V _B become input sensitivity. The input sensitivity needs to be increased to such an extent that the rise and fall of the input signal can be detected. That is, the difference between the first logic inversion level V _H and the bias voltage V _B and the difference between the second logic inversion level V _L and the bias voltage V _B are sufficient including a margin with respect to the amplitude of the input signal. Needs to be set small. On the other hand, since the input signal VIN includes noise as shown in FIG. 5, if the input sensitivity is too high, the input signal VIN malfunctions due to the noise. According to the present embodiment, the logic inversion level setting means 144, 146, 154, and 156 that connect the logic inversion circuit 140 and the logic inversion circuit 150 to the power source having the VDD level and the VSS level are connected to the resistance values Rp, By changing Rn, the logic inversion levels V _H and / or V _L can be changed. Therefore, the input sensitivity of the level shift circuit 100 can be changed, and the input sensitivity suitable for the logic input signal and the noise level can be set.

  Further, the logic inversion level setting means 144, 146, 154, and 156 include a plurality of resistors 144R1, 144R2, 146R1, and 146R2, and switches 144S1, 144S2, 146S1, and 146S2 that select effective resistors among the plurality of resistors. Therefore, the input sensitivity of the level shift circuit 100 can be reliably and easily adjusted by selecting the effective resistor by the switch.

In the level shift circuit 100, the difference between the first logic inversion level V _H and the bias voltage V _B and the difference between the second logic inversion level V _L and the bias voltage V _B are input sensitivities. That is, the change of the logical input signal supplied to the input terminal IN is normally judged by the logic inversion circuit 140 and the logic inversion circuit 150 because the first logic inversion level V _H is higher than the bias voltage V _B. second logic inversion level V _L is set to be lower than the bias voltage V _B, furthermore, it is when the logic inversion level V _H and V _L, the difference between the bias voltage V _B is maintained in good balance.

However, conventionally, when a level shift circuit is integrated and formed on a substrate, a switching element such as a P-channel TFT and an N-channel TFT is connected to the other end of the capacitive element, and the threshold voltage of the TFT is used as a reference. In the configuration in which the voltage of the logic input signal is determined, it is difficult to form the characteristics of both channel TFTs and the characteristics of the bias circuit so that they are ideally balanced with each other due to manufacturing variations. It was. The TFT is formed on a glass substrate, unlike a MOS transistor formed on a silicon substrate. Since the glass substrate is an insulator, the threshold voltage of the TFT formed on the glass substrate fluctuates during operation due to the charge accumulated each time the gate is turned on and off, and therefore the input sensitivity is also reduced. It will fluctuate.
On the other hand, according to the present embodiment, it is possible to reduce relative variations among the bias voltage V _B , the first logic inversion level V _H , and the second logic inversion level V _L. Hereinafter, this operation will be described.

  Assuming that the connection resistance of the logic inversion level setting means 144, 146, 154, and 156 is 0, the sensitivity to the rising edge of the input signal of the level shift circuit 100, that is, the input sensitivity on the high potential side is as follows: become.

  As shown in the above equation, the input sensitivity depends on the difference between α and α ″. Here, the coefficient α of the logic inverting circuit 140 is set as shown in the following equation.

Here, Wn / Ln and Wp / Lp are the ratios of the gate geometry of the TFT.
On the other hand, α ″ is set for the logic inversion circuit 120.
In the level shift circuit 100, the input sensitivity is adjusted not only by the logic inversion level setting means but also by making α and α ″ different.

Here, α / α ″ depends on the ratio of the shape dimensions of the TFTs included in the logic inversion circuit 140 and the logic inversion circuit 120. Therefore, the input sensitivity of the level shift circuit 100 is adjusted by designing the shape ratio of the TFTs. can do.
Further, since the P-channel TFT included in the logic inverting circuit 120 and the P-channel TFT 141 included in the logic inverting circuit 140 are formed on the same substrate, the threshold voltages Vtp and Vtn out of the characteristics of both are formed. The variation due to the manufacturing process variation between the substrates is large. However, between the TFTs included in the logic inversion circuits 120 and 140 arranged close to each other on the same substrate, the difference in Vtp and the difference in Vtn are extremely small. For this reason, when δ << 1, the dependence of V _H −V _B on Vtp and Vtn is extremely small.
Therefore, the difference between α and α ″ depends on the shape dimension ratio of the TFT gate and is less affected by variations in the manufacturing process. As a result, the level shift circuit 100 depends on the difference between α and α ″. The input sensitivity is also less affected by variations in the manufacturing process.

  As described above, the logic inversion circuits 140 and 150 that determine the voltages are complementary transistors, respectively, like the logic inversion circuit 120 that supplies the bias voltage, and the logic inversion circuits 140 and 150 and the logic inversion circuit 120 are formed on the same substrate. Since it is formed by the same manufacturing process, the deviation of the supply bias voltage of the logic inversion circuit 120 which is a complementary transistor circuit due to the variation in the manufacturing process between substrates, and the logic inversion which is also a complementary transistor circuit The shift of the logic inversion level in the circuit 140 and the logic inversion circuit 150 is canceled out. As a result, the influence of manufacturing process variations on the input sensitivity of the level shift circuit 100 can be reduced, and the input sensitivity can be stabilized.

  In addition, each of the logic inversion circuits 120, 140, and 150 is configured by a TFT formed on an insulator. However, since these circuits each include a complementary TFT, it is accumulated in the TFT as it is repeatedly turned on and off. The amount of charge to be generated also has the same tendency for each complementary TFT. Therefore, the deviation of the bias voltage due to the fluctuation of the threshold voltage of the TFT included in the logic inversion circuit 120 and the deviation of the logic inversion level due to the fluctuation of the threshold voltage of the TFT included in the logic inversion circuit 140 and the logic inversion circuit 150. It is canceled out and fluctuations in the input sensitivity of the level shift circuit 100 can be reduced.

  Further, in the level shift circuit 100, since the logic inverting circuit 140 and the logic inverting circuit 150 are both logic inverting circuits, voltage fluctuations due to manufacturing process variations and the like are easily offset. Therefore, it is possible to reduce the influence on the input sensitivity due to variations in the manufacturing process.

<2. Second Embodiment>
<2-1: Configuration>
FIG. 6 is a circuit diagram showing a configuration of the level shift circuit 200 according to the second embodiment of the present invention.
The level shift circuit 200 of the present embodiment differs from the configuration of the level shift circuit 100 (see FIG. 1) of the first embodiment in that it includes two capacitive elements to which a low-amplitude logic input signal is input. .
Specifically, the level shift circuit 200 receives a common logic input signal at one end, a capacitor 210 as a first capacitor element, a capacitor 211 as a second capacitor element, and the other end of the capacitor 210. , a logic inversion circuit 220 as a third logic inversion circuit as a first bias circuit for supplying a first bias voltage V _B1, the other end of the capacitor 211, the difference from the first bias voltage V _B1 2 A logic inversion circuit 222 as a fourth logic inversion circuit serving as a second bias circuit for supplying a bias voltage V _B2, and a logic inversion circuit as a first logic inversion circuit having a first logic inversion level V _H and 240, a logic inversion circuit 250 as a second logic inversion circuit having a second logic inversion level V _L, the logical anti connecting the the power supply logic inversion circuit 240 A level setting means 244 and 246, and a logic inversion level setting means 254, 256 for connecting the the power supply logic inversion circuit 250. Here, the logic inversion circuits 220, 240, 222, and 250 are complementary transistor circuits, respectively.
Other configurations are the same as those in the first embodiment, and a description thereof will be omitted.

In the level shift circuit 200, the bias voltage V _B1 supplied from the logic inverting circuit 220 is set lower than the first logic inverting level VH of the logic inverting circuit 240, and the fourth voltage supplied from the logic inverting circuit 222 of the logic inverting circuit 250. The bias voltage V _B2, which is the logic inversion level, is set higher than the second logic inversion level VL. This setting is performed by adjusting the ratio of the shape dimension or the number of series-parallel stages of the transistor elements constituting the logic inverting circuit 240 to the transistor elements constituting the logic inverting circuit 220, and the logic inverting circuit 222 of the transistor elements constituting the logic inverting circuit 250. This can be done by adjusting the ratio of the geometry or the number of series-parallel stages with respect to the transistor elements constituting the circuit. For adjustment, for example, the gate lengths of the P-channel TFTs included in the logic inversion circuits 240, 220, 222, and 250 are increased in the order of the logic inversion circuits 240, 220, 222, and 250, and other specifications are made the same. Do.

  The configuration of the logic inversion circuit 240 of the level shift circuit 200 and the logic inversion level setting means 244 and 246 for connecting the logic inversion circuit 240 and the power source are the logic inversion circuit 140 in the level shift circuit 100 of the first embodiment, and The same as the logic inversion level setting means 144 and 146. The same applies to the logic inversion circuit 250 of the level shift circuit 200 and the logic inversion level setting means 254 and 256 for connecting the logic inversion circuit 250 and the power source.

FIG. 7 is a graph showing input / output characteristics of the logic inversion circuits 220, 240, 222, and 250.
Since the outputs of the logic inverting circuits 220 and 222 are connected to the respective inputs, the bias voltage V _{B1 is determined} by the voltage at the intersection of the input / output characteristic curve of the logic inverting circuits 220 and 222 and the straight line VIN = VOUT. , V _B2 is shown. As for the first logic inversion level V _H and the second logic inversion level V _L of the logic inversion circuits 240 and 250, assuming that they are taken out separately and connected to the input / output, similarly to the logic inversion circuit 220, This is indicated by the intersection of the input / output characteristic curve and the straight line VIN = VOUT. Here, regarding the logic inversion circuit 240, the input / output characteristics when the connection resistances Rp and Rn of the logic inversion level setting means 244 and 246 are 0 are shown. Here, when the connection resistance Rp of the logic inversion level setting means 244 is increased, the curve of the input / output characteristics moves toward the left side of the figure, and therefore, the first logic that is the intersection with the straight line of VIN = VOUT. The inversion level _VH becomes smaller. On the other hand, when the connection resistance Rn of the logic inversion level setting means 246 is increased, the curve of the input / output characteristic moves toward the right side of the figure, and therefore, the first intersection which is the intersection with the straight line of VIN = VOUT. The logic inversion level V _H increases. Thus, by changing the connection resistance of the logic inversion level setting means 244 and 246, the first logic inversion level _VH can be changed and set to a value suitable for the state of the input signal.
Similarly, for the logic inversion circuit 250, the second logic inversion level V _L is indicated by the intersection of the input / output characteristic curve of the logic inversion circuit 250 in FIG. 7 and the straight line VIN = VOUT. Here, the input / output characteristics of the logic inversion circuit 250 and the second logic inversion level V _L are also changed by changing the connection resistance of the logic inversion level setting means 254 and 256 in the same manner as in the logic inversion circuit 240. The second logic inversion level V _L can be changed and set to a value suitable for the state of the input signal.
In the graph of FIG. 7, the relationship of V _L <V _B1 and V _B2 <V _H is shown.

<2-2: Operation>
Next, the operation of the level shift circuit 200 will be described.
FIG. 8 is a diagram for explaining this operation, and shows voltage waveforms in each part of the level shift circuit 200.
When one end of the capacitor 210 is supplied with a low-amplitude logic input signal from the input end IN and the voltage at the node N210 at the other end exceeds the first logic inversion level V _H , the signal output from the logic inversion circuit 240 is L level. Therefore, the output signal of the NAND circuit 260 becomes H level, and the output signal of the NOR circuit 270 also becomes H level.
On the other hand, when the voltage at the node N211 falls below the second logic inversion level _VL , the signal output from the logic inversion circuit 250 becomes H level. Therefore, the output signal of the NOR circuit 270 becomes L level, and the output signal of the NAND circuit 260 also becomes L level.
As a result, a high-amplitude logic output signal corresponding to the low-amplitude logic input signal supplied to the input terminal IN of the level shift circuit 200 is output from the output terminal OUT.

<2-3: Effect>
The level shift circuit 200 includes a plurality of capacitors 210 and 211 to which a common logic input signal is input, and each of the capacitors 210 and 211 is associated with a combination of a bias voltage and a logic inversion level that are independent of each other. That is, the capacitor 210 can be associated with the combination of the bias voltage V _B1 and the first logic inversion level V _H , and the capacitor 211 can be associated with the combination of the bias voltage V _B2 and the second logic inversion level _VL . Therefore, the characteristics of the elements constituting the logic inversion circuits 220 and 222 and the logic inversion circuits 240 and 250 can be adjusted independently for each of the capacitors 210 and 211 to set an optimum logic inversion level. For example, by adjusting the bias voltages V _B1 and V _B2 independently and setting them near the first logic inversion levels V _H and V _L , the input sensitivity can be increased.
Furthermore, according to the present embodiment, the logic inversion level setting means 244, 246, 254, and 256 that connect the logic inversion circuit 240 and the logic inversion circuit 250 to the power source at the VDD level and the VSS level are connected to the resistance value of the connection. By changing Rp and Rn, the logic inversion levels V _H and / or V _L can be changed. Therefore, the input sensitivity of the level shift circuit 100 suitable for the logic input signal and noise level can be set independently for the different capacitors 210 and 211.
Further, for example, when the logic inversion circuit 240 has a circuit configuration different from that of the logic inversion circuit 250, the same circuit configuration as the logic inversion circuit 240 is used for the logic inversion circuit 220. The variation in input sensitivity can be compensated for by offsetting the variation and the change with time. Further, the input sensitivity can be adjusted independently for each of the different capacitors 210 and 211.

<3. Third Embodiment>
<3-1: Configuration>
FIG. 9 is a circuit diagram showing a configuration of a level shift circuit 300 according to the third embodiment of the present invention.
The level shift circuit 300 of this embodiment is different from the configuration of the level shift circuit 200 (see FIG. 6) of the second embodiment in that the logic inversion level setting means 324 and 326 are logic inversion circuits as first logic inversion circuits. The difference is that the power supply is connected to the logic inversion circuit 320 as a third logic inversion circuit instead of 340. Furthermore, the logic inversion level setting means 358 and 359 connect the power supply to the logic inversion circuit 322 as the fourth logic inversion circuit, not the logic inversion circuit 350 as the second logic inversion circuit. Is different.
About this other structure, it is the same as 2nd Embodiment, and abbreviate | omits description.

In the level shift circuit 300, the bias voltage V _B1 supplied from the logic inverting circuit 320 is set lower than the first logic inverting level VH of the logic inverting circuit 340, and the fourth voltage supplied from the logic inverting circuit 322 of the logic inverting circuit 350. The bias voltage V _B2, which is the logic inversion level, is set higher than the second logic inversion level VL. This setting is performed by adjusting the ratio of the shape dimension or the number of series-parallel stages of the transistor elements constituting the logic inversion circuit 340 to the transistor elements constituting the logic inversion circuit 320, and the logic inversion circuit 322 of the transistor elements constituting the logic inversion circuit 350. This can be done by adjusting the ratio of the geometry or the number of series-parallel stages with respect to the transistor elements constituting the circuit.

  The configuration of the logic inversion circuit 320 of the level shift circuit 300 and the logic inversion level setting means 324 and 326 for connecting the logic inversion circuit 320 and the power source are the logic inversion circuit 140 in the level shift circuit 100 of the first embodiment, and The same as the logic inversion level setting means 144 and 146. The same applies to the logic inversion circuit 322 of the level shift circuit 300 and the logic inversion level setting means 258 and 359 for connecting the logic inversion circuit 322 and the power source.

The input / output characteristics of the logic inversion circuits 320, 340, 322, and 350 in this embodiment are the same as those shown in the graph of FIG. 7 for the second embodiment. However, in the present embodiment, when the connection resistance Rp of the logic inversion level setting means 324 is increased, the curve of the input / output characteristics that determines the bias voltage V _B1 that is the third logic inversion level moves toward the left side of the figure. Therefore, the bias voltage V _B1 , which is the intersection with the straight line of VIN = VOUT, is reduced. On the other hand, when the connection resistance Rn of the logic inversion level setting means 326 is increased, the curve of the input / output characteristic that determines the bias voltage VB1 moves toward the right side of the figure, and therefore, the intersection with the straight line VIN = VOUT. The bias voltage V _B1 increases. As described above, by changing the connection resistance of the logic inversion level setting means 324 and 326, the third logic inversion level V _B1 can be changed and set to a value suitable for the state of the input signal.
Similarly to the logic inversion circuit 320, the logic inversion circuit 322 also changes the bias voltage V _B2 by changing the connection resistance of the logic inversion level setting means 358 and 359 to a value suitable for the state of the input signal. Can be set.

<3-2: Operation and effect>
The operation of the level shift circuit 300 is the same as that of the level shift circuit 200 of the second embodiment.
According to the present embodiment, the logic inversion level setting means 324, 326, 358, 359 for connecting the logic inversion circuit 320 and the logic inversion circuit 322 to the power source at the VDD level and the VSS level are connected to the resistance values Rp, By changing Rn, the bias voltage V _B1 and / or V _B2 can be changed. Therefore, the input sensitivity of the level shift circuit 300 suitable for the logic input signal and the noise level can be set independently for the different capacitors 210 and 211. Other effects are the same as those of the second embodiment.

<4. Fourth Embodiment>
<4-1: Configuration>
FIG. 10 is a circuit diagram showing configurations of the logic inversion circuit 440 and the logic inversion level setting means 444 and 446 of the level shift circuit according to the fourth embodiment of the present invention.
The level shift circuit of this embodiment is different from the configuration of the level shift circuit 100 (see FIGS. 1 and 2) of the first embodiment in that the elements that generate the resistance values of the logic inversion level setting means 444 and 446 are resistance elements. Instead, it is a TFT.
Other configurations are the same as those in the first embodiment, and a description thereof will be omitted.
<4-2: Operation and effect>
According to the present embodiment, a TFT can be used as an element for generating the resistance value of the logic inversion level setting means 444, 446.
Further, the level shift circuit 400, the logic inversion circuit 440 which includes a logic inversion level setting means 444 and 446 is similar to the logic inverting circuit 420 supplies a bias voltage _{V B,} since the circuit according TFT, variation in manufacturing process or the like The tendency of voltage fluctuation due to is more approximate. Therefore, it is possible to reduce the influence on the input sensitivity due to variations in the manufacturing process.
Here, if the TFT 444R1 constituting the logic inversion level setting unit 444 is selected as valid, the TFT 444R1 is in an unsaturated operation. At this time, the connection resistance Rp of the logic inversion level setting unit 444 is as shown in the following equation. Desired.

  The connection resistance Rp is inversely proportional to βp. Here, the coefficient βp is as follows.

  Therefore, according to the present embodiment, since the TFT is used, the connection resistance Rp can be made variable by changing the shape dimension ratio of the TFT. For example, when the W / L value of the TFT 444R1 is increased, Rp is decreased, and conversely, when the W / L value is decreased, Rp is increased. The logic inversion level setting means 446 using complementary transistors can be considered similarly.

<5. Fifth Embodiment>
<5-1: Configuration>
FIG. 11 is a circuit diagram showing configurations of the logic inversion circuit 540 and the logic inversion level setting means 544 and 546 of the level shift circuit according to the fifth embodiment of the present invention.
The level shift circuit of the present embodiment is different from the configuration of the level shift circuit 100 (see FIGS. 1 and 2) of the first embodiment in that elements that generate resistance values of the logic inversion level setting means 544 and 546 are resistance elements. The difference is that it is a diode instead of.
Other configurations are the same as those in the first embodiment, and a description thereof will be omitted.
<5-2: Effect>
According to this embodiment, a diode can be used as an element for generating a resistance value of the logic inversion level setting means.

<10: Modifications and improvements>
It should be noted that the present invention is not limited to the above-described embodiment, and modifications, improvements, etc. within a scope that can achieve the object of the present invention are included in the present invention.

  For example, the present invention is not limited to each of the above embodiments, and embodiments in which the feature points of the above embodiments are combined are also included in the present invention.

  In the above-described embodiment, the connection resistances of the logic inversion level setting means are all 0 by changing the ratio of the gate geometry of the TFTs included in each logic inversion circuit or the number of TFT connection stages (ie, all of the connection resistances of the logic inversion level setting means). Even when the circuit element is not effective), the logic inversion levels of the respective logic inversion circuits have been described as being different from each other. However, the present invention is not limited to this. For example, when the connection resistances of the logic inversion level setting means are all 0, the logic inversion levels of the respective logic inversion circuits are assumed to be equal, and the logic inversion level setting means changes the resistance value of the connection resistance, thereby The logic inversion level of the inverting circuit may be set to be different.

  In the above embodiment, the logic inversion level setting means is described as being connected to the power supply terminals on both the positive side and the negative side of the logic inversion circuit. However, the present invention is not limited to this, and the logic inversion level is not limited thereto. The setting means may connect either the positive side or the negative side of the logic inverting circuit and the power source. However, since the logic inversion level setting means is connected to the power supply terminals on both the positive side and the negative side of the logic inversion circuit, the logic inversion level can be changed in both directions of increasing and decreasing the logic inversion level. Easy to set.

  In the above embodiment, the logic inversion level setting means is described as being connected to two logic inversion circuits. However, the present invention is not limited to this, and is connected to, for example, one logic inversion circuit. Or may be connected to three logic inversion circuits.

  Moreover, in the said embodiment, although the circuit element selection means was used as the switch, this invention is not limited to this. The circuit element selection means may be any means as long as it selects an effective circuit element. For example, the circuit element selection unit is a fuse that is blown by flowing current from an external terminal. Is turned off by supplying and burning. Thereby, in the stage after manufacture of a board | substrate, the setting of the input sensitivity according to a use and use environment can be performed. When the circuit element selection means is an analog switch, selection can be performed based on a selection control signal input from the outside.

  In the embodiment, for example, the plurality of resistors 144R2 and 144R1 of the logic inversion level setting unit 144 are connected in parallel to the switches 144S1 and 144S2, respectively, and a set of resistors and switches connected in parallel is connected in series. However, the present invention is not limited to this connection configuration. The logic inversion level setting means of the present invention may have a configuration in which, for example, each of a plurality of resistors is connected in series with a corresponding switch, and these connected sets are connected in parallel.

  In the above embodiment, the number of circuit elements included in the logic inversion level setting means has been described with two resistors, TFTs or diodes. However, the number of circuit elements of the present invention is not limited to this, and one or three circuit elements are provided. It may be a number greater than one.

  In the above embodiment, the switching element is described as a P-channel TFT and an N-channel TFT. However, the present invention is not limited to this, and any switching element that constitutes a complementary transistor may be used. For example, it may be a P channel type MOS transistor or an N channel type MOS transistor, and may be a PNP type transistor or an NPN type transistor.

  In the above embodiment, the main logic inversion circuit has been described as an inverter circuit. However, the present invention is not limited to this, and any circuit that inverts and outputs the logic level of an input signal may be used. For example, a NAND circuit, It may be a circuit such as a NOR circuit or an exclusive OR circuit.

  In the embodiment, the logic output unit included in the logic output circuit is a holding circuit such as a flip-flop that holds the determination result of the first logic inversion circuit and the determination result of the second logic inversion circuit. Although described, the present invention is not limited to this, and includes a configuration that is not a holding circuit. For example, the determination result of the first logic inversion circuit and the determination result of the second logic inversion circuit may be input to the P-type and N-type switching elements of the complementary transistors constituting the current buffer. However, a holding circuit is preferable from the viewpoint of appropriately following a signal having a long interval between adjacent change points.

  In the above embodiment, the complementary circuit driving signal is described as being output to the built-in output buffer.However, the present invention is not limited thereto, and may be supplied to an output buffer provided outside the level shift circuit. In this case, the complementary circuit drive signal is a logic output signal of the level shift circuit itself.

<11. Example of LCD panel configuration>
Next, the overall configuration of the electro-optical device 1 according to the above-described electrical configuration will be described with reference to FIGS. 12 and 13. Here, FIG. 12 is a perspective view showing the configuration of the electro-optical device 1, and FIG. 13 is a cross-sectional view taken along line AA in FIG. The liquid crystal panel includes an element substrate 1151 such as glass or a semiconductor on which pixel electrodes are formed, and a transparent counter substrate 1152 such as glass on which a common electrode 1158 is formed. Liquid crystal 1155 is sealed in the gap.

  A seal member 1154 that seals the gap between the element substrate 1151 and the counter substrate 1152 is provided on the outer periphery of the counter substrate 1152. The seal member 1154 forms a space in which the liquid crystal 1155 is sealed together with the element substrate 1151 and the counter substrate 1152. A spacer 1153 is mixed in the seal member 1154 in order to maintain a distance between the element substrate 1151 and the counter substrate 1152. Note that an opening for sealing the liquid crystal 1155 is formed in the seal member 1154, and the opening is sealed with a sealing material 1156 after the liquid crystal 1155 is sealed.

  Here, on the opposite surface of the element substrate 1151 and on the outer side of the seal member 1154, a data line driving circuit 1200 is formed to drive a data line extending in the Y direction. Further, a plurality of connection electrodes 1157 are formed on this side, and various signals and image signals from the timing generation circuit are input. A scanning line driving circuit 1500 is formed on one side adjacent to the one side, and the scanning line extending in the X direction is driven from both sides. On the other hand, the common electrode 1158 of the counter substrate 1152 is electrically connected to the element substrate 1151 by a conductive material provided in at least one of the four corners of the bonding portion with the element substrate 1151. In addition, the counter substrate 1152 is provided with, for example, a color filter arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal panel AA. A black matrix such as resin black in which a metal material such as nickel or nickel, carbon or titanium is dispersed in a photoresist is provided, and thirdly, a backlight for irradiating light to a liquid crystal panel is provided. In this case, a black matrix is provided on the counter substrate 1152 without forming a color filter.

  In addition, the opposing surfaces of the element substrate 1151 and the counter substrate 1152 are each provided with an alignment film or the like that has been rubbed in a predetermined direction, and a polarizing plate corresponding to the alignment direction is provided on each back side thereof. . However, if a polymer-dispersed liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 1155, the above-described alignment film, polarizing plate, and the like are not necessary. This is advantageous in terms of reducing power consumption. Instead of forming part or all of the peripheral circuits such as the data line driving circuit 1200 and the scanning line driving circuit 1500 on the element substrate 1151, for example, they are mounted on a film using a TAB (Tape Automated Bonding) technique. The driving IC chip may be electrically and mechanically connected through an anisotropic conductive film provided at a predetermined position of the element substrate 1151, or the driving IC chip itself may be COG (Chip On Grass). A technique may be used to electrically and mechanically connect to a predetermined position of the element substrate 1151 via an anisotropic conductive film.

<12. Application example>
In the above-described embodiments, the electro-optical device including the liquid crystal is illustrated, but the present invention is also applied to an electro-optical device using an electro-optical material other than the liquid crystal. An electro-optical material is a material whose optical characteristics such as transmittance and luminance change when an electric signal (current signal or voltage signal) is supplied. For example, a display panel using an OLED element such as an organic EL (Electro Luminescent) or a light emitting polymer as an electro-optical material, or a microcapsule containing a colored liquid and white particles dispersed in the liquid is used as an electro-optical material. The electrophoretic display panel used, the twist ball display panel using a twist ball painted differently for each region of different polarity as an electro-optical material, the toner display panel using black toner as an electro-optical material, or helium The present invention can be applied to various electro-optical devices such as a plasma display panel using a high-pressure gas such as or neon as an electro-optical material.

<13. Electronic equipment>
Next, an electronic apparatus to which the electro-optical device 1 according to the above-described embodiments and application examples is applied will be described. FIG. 14 shows a configuration of a mobile personal computer to which the electro-optical device 1 is applied. The personal computer 2000 includes the electro-optical device 1 as a display unit and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. Since the electro-optical device 1 includes a level shift circuit that can appropriately cope with a logic input signal and a noise level, it is possible to display a high-quality image with little influence of noise.

  FIG. 15 shows a configuration of a mobile phone to which the electro-optical device 1 is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 1 as a display unit. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled. FIG. 16 shows a configuration of a portable information terminal (PDA: Personal Digital Assistants) to which the electro-optical device 1 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 1 as a display unit. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 1.

  The electronic apparatus to which the electro-optical device 1 is applied includes, in addition to those shown in FIGS. 14 to 16, a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, Examples include electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, and devices equipped with touch panels. The electro-optical device 1 described above can be applied as a display unit of these various electronic devices.

2 is a circuit diagram showing a configuration of a level shift circuit 100. FIG. 3 is a circuit diagram showing the configuration of a logic inversion circuit 140 and logic inversion level setting means 144 and 146 of the level shift circuit 100. FIG. 4 is a circuit diagram showing a configuration of connection resistances by a logic inversion circuit 140 and logic inversion level setting means 144 and 146 of the level shift circuit 100. FIG. 3 is a graph showing input / output characteristics of logic inversion circuits 120, 140, and 150. 3 is a diagram showing voltage waveforms in each part of the level shift circuit 100. FIG. It is a circuit diagram which shows the structure of the level shift circuit 200 of 2nd Embodiment of this invention. 3 is a graph showing input / output characteristics of a logic inversion circuit 220, a logic inversion circuit 240, a logic inversion circuit 222, and a logic inversion circuit 250. FIG. 4 is a diagram showing voltage waveforms in each part of the level shift circuit 200. It is a circuit diagram which shows the structure of the level shift circuit 300 of 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the logic inversion circuit 440 and the logic inversion level setting means 444, 446 of the level shift circuit of 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the logic inversion circuit 540 of the level shift circuit of 5th Embodiment of this invention, and the logic inversion level setting means 544,546. It is a perspective view for demonstrating the structure of the electro-optical apparatus to which the said level shift circuit was applied. FIG. 3 is a cross-sectional view taken along line AA for explaining the structure of the electro-optical device. It is a perspective view showing the configuration of a mobile personal computer to which the above electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone to which the above-mentioned electro-optical apparatus is applied. It is a perspective view which shows the structure of the portable information terminal to which the above-described electro-optical device is applied.

Explanation of symbols

100, 200, 300 ... level shift circuit, 110, 210, 211, 310, 311 ... capacitor (capacitance element), 130, 230, 330 ... logic output circuit, 120, 220, 320 ... logic inversion circuit (third logic) Inverting circuit), 222, 322 ... logic inverting circuit (fourth logic inverting circuit), 140, 240, 340, 440, 540 ... logic inverting circuit (first logic inverting circuit), 150, 250, 350 ... logic inverting Circuit (second logic inversion circuit), 144, 146, 154, 156, 244, 246, 254, 256, 324, 326, 358, 359 ... logic inversion level setting means, 135, 235, 335 ... logic output section ( Holding circuit), 1 ... electro-optical device, 2000 ... personal computer, 3000 ... mobile phone

Claims (6)

A capacitive element to which a logic input signal having a first logic amplitude is input at one end;
A first logic inversion circuit having a first logic inversion level with respect to an input connected to the other end of the capacitor; and a second logic inversion with respect to an input connected to the other end of the capacitor A logic output that includes a second logic inversion circuit having a level and inverts a logic output signal having a second logic amplitude when the output polarities of the first logic inversion circuit and the second logic inversion circuit coincide with each other Circuit,
One end and an output of an input are connected to the other end of the capacitive element, and are lower than the first logical inversion level and lower than the second logical inversion level with respect to an input connected to the other end of the capacitive element. A third logic inversion circuit having a high third logic inversion level;
At least one of the first logic inversion circuit and the second logic inversion circuit is connected to a power supply corresponding to the second logic amplitude, and the first logic inversion level and the second logic inversion are connected. Logical inversion level setting means for setting at least one of the levels;
Level shift circuit with A first capacitive element to which a logic input signal having a first logic amplitude is input at one end;
A second capacitive element to which the logic input signal is input at one end;
A first logic inversion circuit having a first logic inversion level with respect to an input connected to the other end of the first capacitor, and an input connected to the other end of the second capacitor A second logic inversion circuit having a second logic inversion level, and a logic output having a second logic amplitude by matching the output polarities of the first logic inversion circuit and the second logic inversion circuit A logic output circuit for inverting the signal;
A third logic lower than the first logic inversion level with respect to the input connected to the other end of the first capacitive element, one end of the input and the output connected to the other end of the first capacitive element. A third logic inversion circuit having an inversion level;
A fourth logic higher than a second logic inversion level with respect to an input connected to the other end of the second capacitive element and having an input connected to the other end of the second capacitive element and connected to the other end of the second capacitive element. A fourth logic inversion circuit having an inversion level;
Connecting at least one of the first logic inversion circuit, the second logic inversion circuit, the third logic inversion circuit, and the fourth logic inversion circuit and a power supply corresponding to the second logic amplitude. Logic inversion level setting means for setting at least one of the first logic inversion level, the second logic inversion level, the third logic inversion level, and the fourth logic inversion level;
Level shift circuit with The level shift circuit according to claim 1 or 2,
The logic inversion level setting means includes a plurality of circuit elements having resistance values;
Circuit element selecting means for selecting an effective circuit element from among the plurality of circuit elements;
Level shift circuit with The level shift circuit according to claim 3, wherein
A level shift circuit, wherein the circuit element is a transistor.   An electro-optical device comprising the level shift circuit according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 5.

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