JP4433784B2 - LCD panel drive - Google Patents

Description

  The present invention relates to a drive device for a liquid crystal panel, and more particularly to a liquid crystal panel drive device in which EMI (Electro Magnetic Interface) generated when a liquid crystal panel is driven at high speed by overdrive is reduced.

First, a general configuration of a conventional liquid crystal panel will be briefly described with reference to FIG. 4 which is a schematic equivalent circuit diagram of one pixel portion. Each liquid crystal pixel LP is provided at the intersection of the gate line Xn and the signal line Ym on the liquid crystal panel, and this liquid crystal pixel LP is equivalently represented by a liquid crystal capacitance _CLC . Usually, an auxiliary capacitor C _S is connected to the liquid crystal capacitor C _LC in parallel. One end of the liquid crystal capacitance C _LC, together with being connected to the driving pixel transistor Tr, and the other end is connected to the counter electrode a predetermined reference voltage Vcom is applied.

The pixel transistor Tr becomes a thin film transistor TFT of the insulated gate field effect, its drain electrode D is supplied with image signal Vsig is connected to a signal line Ym, The source electrode S is one of the liquid crystal capacitance C _LC, i.e. pixel Connected to the electrode. Further, the gate electrode G of the pixel transistor Tr is connected to the gate line Xn so that a gate pulse _GP having a predetermined gate voltage Vgate is applied thereto. A coupling capacitor C _GS is formed between the liquid crystal capacitor C _LC and the gate electrode G.

When the gate pulse _GP of the voltage Vgate is applied to the gate electrode G during this pixel selection period, the pixel transistor Tr is turned on. At this time, the image signal Vsig supplied from the signal line Ym is written into the liquid crystal pixel via the pixel transistor Tr, and so-called sampling is performed. Next, when this pixel enters the non-selection period, the application of the gate pulse _GP is stopped and the low level gate voltage is applied, and the pixel transistor Tr is turned off, but the written image signal is held in the liquid crystal capacitor _CLC . Then, a voltage held in the liquid crystal capacitor _CLC is applied to the liquid crystal pixel, and the liquid crystal pixel transmits light with a transmittance corresponding to the voltage. In the following, the period from this selection period to the next selection period is referred to as one frame.

However, since the liquid crystal has an anisotropic dielectric constant, the dielectric constant varies depending on the direction of the liquid crystal molecules. In other words, when the direction of the liquid crystal molecules changes as the voltage is applied, the dielectric constant also changes accordingly, thereby changing the value of the liquid crystal capacitance _CLC . Once the TFT is turned on during the selection period and the charge is supplied to the liquid crystal capacitor _CLC , the TFT is turned off. However, the relationship between the charge Q, the capacitor C, and the voltage V is Q = CV. since holds, the pixel voltage V _P is actually applied to the liquid crystal when the value changes of the liquid crystal capacitance C _LC also comes to change.

Therefore, when the image signal Vsig applied to an arbitrary pixel changes from a low gradation to a high gradation (or from a high gradation to a low gradation), as shown in FIG. V _P, immediately can not reach the pixel voltage Vsig of the target, some frames is to reach the first target pixel voltage Vsig after the lapse. Similarly, since the transmittance of pixels in the current frame is affected by the transmittance of pixels in the previous frame, it is possible to obtain a desired transmittance after several frames have passed as shown in FIG. This is one of the causes of the slow display speed of the liquid crystal display panel.

  In order to increase the display speed of such a liquid crystal panel, as shown in FIG. 7, by applying so-called overdrive driving that applies a voltage Vod higher than a normal applied voltage, a pixel voltage that is actually applied is applied. A method has been proposed in which Vp reaches the target pixel voltage Vsig in a short time, and the transmittance of the liquid crystal panel reaches the target transmittance in a short time (see FIG. 6) to improve the moving image display. (Patent Document 1).

  For example, as shown in FIG. 8, the overdrive driving unit 10 includes an overdrive data calculation unit 13 including frame memories SDRAM (Synchronous Dynamic Random Access Memory) 1 to 4 and a lookup table 12. In this lookup table 12, overdrive (gradation correction) data obtained in advance by experiments based on all combinations of previous input data and current input data (target data) is set, and overdrive data calculation is performed. The means 13 can generate data that accurately overdrives the input data input from the video card by referring to the lookup table 12. In addition to such an overdrive data calculation means 13 that uses a look-up table, it is also possible to generate data that directly becomes overdrive by a digital circuit.

  Since such overdrive drive means 10 require large-capacity frame memories SDRAM1 to SDRAM4, components other than this frame memory are currently made ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable). Gate array), and an external SDRAM is generally used as a frame memory.

  The operation of the overdrive driving means will be described in more detail. The RGB 8-bit RGB signals from a video card (not shown) are combined into 48 bits by adding 2 dots for high-speed processing. An LVDS (Low Voltage Differential Signal) signal is input to the overdrive data calculation means 13 having the look-up table 12 via 48 transmission lines 11, where 24 bits of odd frame data. ODD data (odd number data) passes through 24 transmission lines 14 to SDRAM1, and 24 bit EVEN data (even number data) passes through 24 transmission lines 16 to SDRAM 3 and 24 of the even frame data. The bit of ODD data passes through 24 transmission lines 15 to the SDRAM 2 and 24 bits. EVEN data for a set is distributed to the SDRAM 4 through 24 transmission lines 17, and the above-described overdrive is performed by referring to the lookup table 12 from the current gradation signal and the previous gradation signal. Data generation occurs. The overdrive data obtained in this way is combined with 48-bit data in the same manner as the input signal, and is supplied to the liquid crystal module separately as an LVDS signal output via 48 transmission lines 18. ing.

  On the other hand, conventionally, a bus line for transferring the output from the video card to the data driver for driving the liquid crystal via the interface in the liquid crystal module has a large number of bus lines, for example, a total of 24 or 8 in the case of 8-bit RGB gradation. Forty-eight bus lines are used for two dots, and these bus lines are typically formed by ribbon cables or flexible wiring boards, so that the wiring is long and the wiring is not shielded. In combination with this, it was known that large EMI was generated.

  As a method for reducing the EMI from the bus line, the amount of change in data on the bus line is detected, and when the amount of change in data exceeds a majority, the polarity of all data is reversed to change the data. It has been known to transfer the inverted data using a so-called data translation reduction circuit (hereinafter referred to as “DTR”) that reduces the amount to a majority or less (see Patent Documents 2 to 4). .

However, at the same time, this DTR circuit has a large number of bus lines and a long length, and is used as an EMI countermeasure in the case where the bus lines are exposed without being shielded. In the case where is short, no DTR circuit was used. This is probably because the DTR circuit did not contribute as much as expected to the decrease in EMI when the distance was short, and EMI itself did not occur so much in places where the distance was short.
JP 2001-265298 A (paragraphs [0019] to [0034], [0078] to [0086], FIGS. 1 to 3, 9, and 14) JP 2000-207077 A (paragraphs [0003] to [0007], [0019] to [0023], FIG. 3) JP 2003-005729 A (claims, paragraphs [0042] to [0056], FIGS. 3 to 7) JP 2000-148605 A (claims, paragraphs [0002] to [0023], [0025] to [0027], FIGS. 5 and 8)

  In the liquid crystal panel driving apparatus using the overdrive driving means 10 as described above, when an image having a large number of data inversions such as a checkered pattern display is displayed, an adverse effect due to EMI has been observed.

  Therefore, the present inventor has examined various causes of the EMI deterioration in the overdrive driving means 10 described above, and the EMI deterioration occurs from the transmission lines 14 to 17 connecting the overdrive data calculating means 13 and the SDRAMs 1 to 4. I found out. This is coupled with the increase in the number of transmission lines in recent years and the fact that the operating frequency has become very high, and it has been found that this part also led to the occurrence of EMI.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a liquid crystal driving device that reduces EMI from a bus line connected to a frame memory in a liquid crystal driving device including an overdrive driving means for a liquid crystal panel using a frame memory.

The above object of the present invention can be achieved by the following constitution. That is, the invention of the liquid crystal panel control device according to claim 1 of the present application is a liquid crystal panel drive device including a frame memory and overdrive data calculation means, wherein the overdrive data calculation means includes:
Count the number of data transitions of all data transmitted to the frame memory every clock cycle,
(1) When the number of data transitions is more than a majority, all data is inverted and transmitted to the frame memory, and a toggle-controlled control signal is also transmitted to the frame memory.
(2) When the number of data transitions is less than a majority, all the data is transmitted to the frame memory as it is, and a control signal without toggle control is also transmitted to the frame memory.
A data transition reduction circuit having a function of reproducing the original data based on the control signal when reading the data of the frame memory is provided.

  The invention according to claim 2 of the present application is the liquid crystal panel driving device according to claim 1, wherein the frame memory includes an odd-numbered frame memory and an even-numbered frame memory, and the control signal also corresponds. It is configured to be stored in a frame memory and an even frame memory.

  The invention according to claim 3 of the present application is the invention of the liquid crystal panel control device according to claim 2, wherein the odd frame memory and the even frame memory are respectively an odd data memory and an even data memory. And the control signal is also stored in the corresponding odd data memory and even data memory.

  According to a fourth aspect of the present invention, in the liquid crystal panel driving device according to any one of the first to third aspects, the frame memory is an SDRAM provided outside the overdrive data calculating means. It is characterized by being.

  Further, the invention according to claim 5 of the present application is characterized in that, in the liquid crystal panel driving device according to claim 1, the overdrive data calculation means includes a lookup table.

  The present invention has the following excellent effects by having the above-described configuration. That is, according to the liquid crystal panel driving device according to claim 1 of the present application, since the number of data transitions through the transmission line connecting the frame memory and the overdrive data calculating means is reduced, EMI due to this transmission line is reduced. At the same time, there is an effect that power consumption is reduced. Therefore, overdrive driving can be performed on the high-resolution liquid crystal module without deteriorating EMI.

  Further, according to the liquid crystal panel driving device according to claim 2 of the present application, although the operating frequency is the same as the operating frequency of the input image data when processing one dot at a time, the frame memory is for odd frames and even numbers. Since only two frames are required, an inexpensive liquid crystal panel driving device can be obtained.

  Further, according to the liquid crystal panel driving apparatus according to claim 3 of the present application, since the frame data to be processed is processed two dots at a time to generate overdrive data, the processing speed is substantially doubled. As a result, the operating frequency can be lowered, and a high-resolution liquid crystal module having a high operating frequency can be stably driven.

  In addition, according to the liquid crystal panel driving device according to claim 4 of the present application, since a high-speed, large-capacity and inexpensive commercially available SDRAM can be used as a frame memory, the obtained liquid crystal driving device can be manufactured at low cost.

  Furthermore, according to the liquid crystal panel driving device of claim 5 of the present application, the configuration of the overdrive data calculation means becomes simpler than that of directly generating overdrive data by a digital circuit. It becomes easy.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to FIGS. However, the embodiment described below exemplifies a liquid crystal drive device for embodying the technical idea of the present invention, and is not intended to specify the present invention as this liquid crystal drive device. Other embodiments within the scope of the claims are equally applicable.

  FIG. 1 is a block diagram of overdrive driving means used in the liquid crystal driving device of the present invention, FIG. 2 is a block diagram of a DTR circuit, and FIG. 2 (a) is an overdrive data calculation means to SDRAM. FIG. 2B is a block diagram of a processing circuit for a signal received from the SDRAM, and FIG. 3 is a timing diagram for explaining inversion of data in the DTR circuit. FIG. 3A shows a signal before passing through the DTR circuit, and FIG. 3B shows a signal after passing through the DTR circuit.

  8 is different from the conventional overdrive drive unit 10 shown in FIG. 8 in that the DTR circuit 21 is incorporated in the overdrive data calculation unit 13 and each of the SDRAMs 1 to 4 and the overdrive data calculation unit 13. Are different from each other in that control signal lines (DEXR lines) 22 to 25 are provided, but the other configurations are substantially the same. A detailed description of the provision of the reference numerals will be omitted.

  In this overdrive drive means 20, an LVDS signal, which is composed of 48 bits of a total of 24 bits of RGB each from a video card (not shown) and combined for 2 dots for high speed processing, is combined into a transmission line. 11 is input to the overdrive data calculation means 13 having the look-up table 12, where 24-bit ODD data (odd data) out of the odd frame data passes through 24 transmission lines 14. Also, 24 bits of EVEN data (even data) passes through 24 transmission lines 16 to SDRAM 3, and 24 bits of ODD data out of even frame data passes through 24 transmission lines 15. In addition, 24 bits of EVEN data passes through 24 transmission lines 17. The data is allocated to the DRAM 4, and the generation of the data that causes overdrive as described above is generated by referring to the lookup table 12 from the gradation signal in the current frame and the gradation signal in the previous frame. However, before the data is distributed to the SDRAMs 1 to 4 and when the data stored in the SDRAMs 1 to 4 is read, the DTR circuit 21 performs signal processing, and the SDRAMs 1 to 4 pass through the control signal lines 22 to 25. 4, a control signal (DEXR signal) is also stored and read out. The overdrive data calculation means 13 is manufactured by ASIC or FPGA.

In the DTR circuit 21, before distributing the data to the SDRAMs 1 to 4, the following processes (1) to (6) are performed in synchronization with the clock pulse as shown in FIG.
(1) The data comparator 31 compares each of the 48 data lines with the previous data to determine whether the data has changed, and outputs an H level if the data has changed. If there is no change, L level is output.
(2) In the adder 32, the number of H levels output from the data comparator is obtained.
(3) The comparator 33 determines whether or not the number of H levels is 25 or more, which is a majority of 48. If it is 25 or more, it outputs an H level, and otherwise outputs an L level. .
(4) The toggle circuit 34 inverts the output every time H level data is input from the comparator 33.
(5) In the AND circuit 35, only when the enable signal EL is input, the signal from the toggle circuit 35 is output as it is to generate the DEXR signal.
(6) The XOR circuit 36 obtains a predetermined DTR signal by taking an exclusive OR between the DEXR signal and the input data signal, and transmits and stores it in the corresponding SDRAMs 1 to 4.

  The timing of the DTR signal thus obtained will be described in detail with reference to FIG. FIG. 3A shows a signal for 6 clocks before passing through the DTR circuit. The levels of DATA0 to DATA46 change every time in synchronization with the fall of the clock signal CLK, and only DATA47 rises at the first clock. Data falling at the time of 5 clocks is shown. In this case, the DEXR signal is at the L level. Then, the number of inverted signals only during the first clock and the sixth clock is 48 including the DEXR signal, and the number of inverted signals is 47 during the second to fifth clocks.

  Then, since the number of inverted signals in all of the first clock to the sixth clock is 25 or more, as shown in FIG. 3B, the DEXR signal is obtained as a signal obtained through the DTR circuit. The signal is inverted every time from the first clock to the sixth clock, and from DATA0 to DATA46 is not changed to an L level, and only DATA47 is a signal inverted every time from the second clock to the fifth clock. After all, including the DEXR signal, the number of inverted signals at the first clock and the sixth clock is 1, and the number of inverted signals from the second clock to the fifth clock is 2. Therefore, in the above case, the number of signals to be inverted can be greatly reduced by passing through the DTR circuit, and as a result, generation of EMI can be reduced.

  In addition, if the comparator 33 outputs an L level in the step (3), the number of lines in which data has changed is 24 or less, so the DEXR signal does not change and the input data is The data is transmitted to and stored in the SDRAMs 1 to 4 as they are.

  When reading the data stored in the frame memory, as shown in FIG. 2B, the XOR circuit 47 performs exclusive OR between the signals from the SDRAMs 1 to 4 and the DEXR signal, thereby obtaining the original signal. The overdrive data computing means 13 generates overdrive data based on the reproduced signal and supplies it to the liquid crystal module.

In this specific example, in accordance with the above-described prior art, the RGB LVDS signal synthesized by 48 bits by combining 2 dots for each of RGB 8 bits total 24 bits for high speed processing is processed. Although an example has been shown, the present invention is not limited to such a case. For example, a signal of 1 dot composed of 24 bits of 8 bits for each RGB, for example, can be processed by simultaneously inputting more than 2 dots. It is also possible to do so. In the former case, the operating frequency is the same as the operating frequency of the input data, but the required frame memory capacity can be halved compared to the above-mentioned specific example, so that the liquid crystal drive can be driven at a lower cost. The device can be manufactured. In the case of processing one dot at a time, only one frame memory is technically necessary. However, since the drive frequency becomes higher, the EMI deteriorates and the stability becomes inferior, so two are used. Is preferred.
In the latter case, since the operating frequency can be lowered as the number of simultaneously processed dots increases, the EMI can be reduced even in a high-resolution liquid crystal panel having a high operating frequency. The overdrive drive can be stably performed without deteriorating.

It is a block diagram of the overdrive drive means used with the liquid crystal drive device of this invention. FIG. 2A is a block diagram of a DTR circuit, FIG. 2A is a block diagram of a processing circuit for signals transmitted from the ASIC to the SDRAM, and FIG. 2B is a block diagram of a processing circuit for signals received from the SDRAM. FIGS. 3A and 3B are timing diagrams for explaining inversion of data in the DTR circuit. FIG. 3A shows a signal before passing through the DTR circuit, and FIG. 3B shows a signal after passing through the DTR circuit. . It is a typical equivalent circuit diagram of one pixel part of a liquid crystal panel. It is a figure which shows the relationship between the voltage applied to one pixel of the conventional liquid crystal panel, and an actual pixel voltage. It is a figure which shows the relationship between the target transmittance | permeability of one pixel of a liquid crystal, and actual transmittance | permeability. It is a figure which shows the relationship between the voltage applied to one pixel of a liquid crystal at the time of overdrive drive, and an actual pixel voltage. It is a block diagram of the overdrive drive means using the conventional look-up table.

Explanation of symbols

10, 20 Overdrive drive means 11, 18 Bus line 12 Look-up table 13 Overdrive data calculation means 14-17 Transmission line 21 DTR circuit 22, 23 DEXR line

Claims (3)

In a liquid crystal panel driving device provided with a frame memory and overdrive data calculation means,
The overdrive data calculation means counts the number of data transitions of all data transmitted to the frame memory every clock cycle,
(1) When the number of data transitions is more than a majority, the entire data is inverted and transmitted to the frame memory, and a toggle-controlled control signal is also transmitted to the frame memory.
(2) When the number of data transitions is less than a majority, all the data is transmitted to the frame memory as it is, and a control signal without toggle control is also transmitted to the frame memory.
A data transition reduction circuit having a function of reproducing the original data based on the control signal when reading the data of the frame memory;
The liquid crystal panel driving device according to claim 1, wherein the frame memory includes an odd data memory and an even data memory for odd frames, and an odd data memory and even data memories for even frames . 2. The liquid crystal panel driving device according to claim 1, wherein the frame memory is an SDRAM provided outside an overdrive data calculating means. The liquid crystal panel driving apparatus according to claim 1, wherein the overdrive data calculation means includes a lookup table.

Images