CN100461257C - Time sequence controller and liquid crystal display device including the same time sequence controller - Google Patents
Time sequence controller and liquid crystal display device including the same time sequence controller Download PDFInfo
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- CN100461257C CN100461257C CNB2006101622163A CN200610162216A CN100461257C CN 100461257 C CN100461257 C CN 100461257C CN B2006101622163 A CNB2006101622163 A CN B2006101622163A CN 200610162216 A CN200610162216 A CN 200610162216A CN 100461257 C CN100461257 C CN 100461257C
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Abstract
A liquid crystal display consists of a sequential controller including a data pin port with multiple pin, a control pin and a selector; a face plate and a driving chip. It is featured as using said control pin to receive a control signal, deciding pin sequence to transmit or receive signal by said selector according to control signal, driving said face plate to display by driving chip according to signal when signal is received by sequential controller.
Description
Technical field
The present invention relates to a kind of time schedule controller and comprise the LCD of this time schedule controller, especially relate to a kind of time schedule controller that is used for LCD.
Background technology
Along with scientific-technical progress, various electronic products have become people's indispensable part of living.Wherein, display is the significant components of electronic multimedia product.Because LCD (liquid crystal display, LCD) have that power saving, the no width of cloth are penetrated, volume is little, low power consumption, do not take up space, advantage such as flat square, high definition, image quality are stable, replace traditional cathode-ray tube display (cathode ray tubedisplay gradually, CRT display), be widely used on the display panel of electronic products such as mobile phone, screen, Digital Television, mobile computer.
Generally speaking, LCD has a panel and one drive circuit, the a plurality of chip for driving, a printed circuit board (PCB) and the glass substrate that comprise time schedule controller, a processor, serial connection in the driving circuit, after time schedule controller receives the pixel data signal of treated device processing, according to a sequential and output pixel data signal, control signal, frequency signal, wherein pixel data signal and frequency signal are generally differential wave (differential signal), and wherein pixel data signal can be divided into three kinds of pixel data signals of RGB.Time schedule controller sends pixel data signal to be positioned on the glass substrate a plurality of chip for driving by printed circuit board (PCB), and chip for driving produces voltage signal to drive the liquid crystal on the panel according to pixel data signal again.
When designing the driving circuit of LCD, need consider that at first the assembly that printed circuit board (PCB) uses is (being that assembly faces up) or positive (face-down) (being that assembly faces down) towards the back side of panel of LCD (face-up), it is respectively as Fig. 1 and shown in Figure 2.Because time schedule controller chip input Low Voltage Differential Signal and output Reduced Swing Differential Signal are reverse polarity in pairs and each other, therefore the assembly on the printed circuit board (PCB) is towards the front or the back side of panel, determined whether the pin position of time schedule controller chip can mate with the input end of panel, for example when chip faces up, as shown in Figure 1, leftmost pin position, time schedule controller 1 below is the LV0-signal, then be the LV0+ signal, and when chip faces down, as shown in Figure 2, leftmost pin position, time schedule controller 1 below becomes the LV3+ signal, then is the LV3-signal.Therefore often need to use two internal control circuits identical, but its input and the different time schedule controller chip of output pin position order, with the demand on realistic.The time schedule controller chip that has otherness like this needs assembling respectively and transportation to store, and causes cost to increase.
Therefore, this field is needed a kind of being applicable to simultaneously badly and is faced up or ventricumbent time schedule controller.
Summary of the invention
A purpose of the present invention is to provide a kind of time schedule controller, and it comprises a data pin port, a control pin and a selector switch.Data pin port has a plurality of pins.The control pin is in order to receive a control signal.Selector switch transmits or receives the order of the pin of a signal according to control signal determination data pin port.
Another object of the present invention is to provide a kind of LCD, it comprises aforesaid time schedule controller and a panel and a chip for driving, and chip for driving drives panel to show according to signal.This LCD has the runners that is suitable for time schedule controller, and have two kinds of runners received signals order one of them, change the signal sequence that control signal just can the control timing controller be sent to or be received from runners.
The present invention is applicable to the LCD of different circuit forms, and control method is easy, has not only avoided numerous and diverse manufacturing process and assembling, has also reduced the design and the manufacturing cost of different time schedule controllers.
Reach following description to embodiment in conjunction with the accompanying drawings, the ordinary technical staff in the technical field of the invention can understand other purpose of the present invention, and technological means of the present invention and embodiment.
Description of drawings
Fig. 1 is an assembly synoptic diagram up in the prior art;
Fig. 2 is an assembly synoptic diagram down in the prior art;
Fig. 3 is 1 synoptic diagram for the time schedule controller logic according to preferred embodiment of the present invention;
Fig. 4 is 0 synoptic diagram for the time schedule controller logic according to preferred embodiment of the present invention;
Fig. 5 is the synoptic diagram according to the Thin Film Transistor-LCD of preferred embodiment of the present invention; And
Fig. 6 is the synoptic diagram according to multiplexer of the present invention.
Wherein, Reference numeral:
1: time schedule controller
3: time schedule controller
31: data pin port
32: control signal
33: the control pin
351: phase inverter
353: with door
355: or door
357: the first multiplexers
359: the second multiplexers
371,373,375: pin
5: LCD
51: processor
53: chip for driving
55: printed circuit board (PCB)
57: glass substrate
59: panel
Embodiment
A preferred embodiment of the present invention is a kind of time schedule controller 3, as shown in Figures 3 and 4.Its mode with a chip is used for LCD, and (thin film transistor is TFT) in the LCD 5, as shown in Figure 5 in particular for thin film transistor (TFT).Thin Film Transistor-LCD 5 comprises outside the time schedule controller 3, also comprises a processor 51, a plurality of serial connection chip for driving 53, a printed circuit board (PCB) 55, a glass substrate 57 and a panel 59.Processor 51 produces a control signal 32 and a plurality of signal, and is sent to this time schedule controller 3.These signals comprise Reduced Swing Differential Signal (reduced swingdifferential signal, RSDS), output frequency signal, Low Voltage Differential Signal (low voltagedifferential signal, LVDS) and input frequency signal.
Selector switch transmits or receives the order of the pin of these signals according to control signal 32 determination data pin ports 31, after being positioned at chip for driving 53 on the glass substrate 57 and receiving these signals, thereby drives panel 59 to show.In this embodiment, selector switch is a multiplexer (multiplexer), as shown in Figure 6.The multiplexer that present embodiment uses have a phase inverter 351, two with door 353 and one or 355.When control signal 32 was 0, the output of multiplexer then was first input signal 352; When control signal 32 was 1, the output of multiplexer then was second input signal 354.
When control signal 32 was the state of logical one, as shown in Figure 3, the time schedule controller 3 of this moment was applied to the ventricumbent state of chip.The input of Low Voltage Differential Signal is counterclockwise to see, be followed successively by LV3+, LV3-, LCK+, LCK-, LV2+, LV2-, LV1+, LV1-, (LV means LVDS for LV0+, LV0-, the order of digitized representation signal correspondence), wherein LCK+/-for input low voltage differential frequency signal right, LV3+/-to LV0+/-then right for the input Low Voltage Differential Signal; This moment, the output of Reduced Swing Differential Signal was sorted with counter clockwise direction, then be RSR2+, RSR2-, RSR1+, RSR1-, RSR0+, RSR0-, RSG2+, RSG2-, RSG1+, RSG1-, RSG0+, RSG0-, RSCK+, RSCK-, RSB2+, RSB2-, RSB1+, RSB1-, RSB0+, RSB0-(RS means RSDS), wherein RSCK+/-to swing the differential frequency signal by a small margin right for output, RSR2+/-, RSR1+/-and RSR0+/-for the red Reduced Swing Differential Signal of output right, RSG2+/-, RSG1+/-and RSG0+/-for the green Reduced Swing Differential Signal of output right, RSB2+/-, RSB1+/-and RSB0+/-for the blue Reduced Swing Differential Signal of output right.
When control signal 32 was the state of logical zero, as shown in Figure 4, this moment, time schedule controller 3 was applied to the supine state of chip.The input of Low Voltage Differential Signal is counterclockwise to see, be followed successively by LV0-, LV0+, LV1-, LV1+, LV2-, LV2+, LCK-, LCK+, LV3-, LV3+, wherein LCK-/+for input low voltage differential frequency signal right, LV0-/+～LV3-/+then right for the input Low Voltage Differential Signal; Output as for Reduced Swing Differential Signal is sorted with counter clockwise direction, then be RSR0-, RSR0+, RSR1-, RSR1+, RSR2-, RSR2+, RSCK-, RSCK+, RSG0-, RSG0+, RSG1-, RSG1+, RSG2-, RSG2+, RSB0-, RSB0+, RSB1-, RSB1+, RSB2-, RSB2+, wherein RSCK-/+to swing the differential frequency signal by a small margin right for output, RSR0-/+, RSR1-/+and RSR2-/+for the red Reduced Swing Differential Signal of output right, RSG0-/+, RSG1-/+and RSG2-/+for the green Reduced Swing Differential Signal of output right, RSB0-/+, RSB1-/+and RSB2-/+for the blue Reduced Swing Differential Signal of output right.
In fact, the signal of two different definition may be exported or import to each pin in the data pin port 31, is example with pin 371, and it is in order to receive Low Voltage Differential Signal.When control signal 32 was the state of logical one, the voltage differential signal of its reception was LV3+; When control signal 32 was the state of logical one, the voltage differential signal of its reception was LV0-.
In the sequencing selection of Low Voltage Differential Signal and input frequency signal, the signal LV0-that handles with the need input is an example, as shown in Figure 3 and Figure 4.One of them is LV0-the signal that pin 371 and pin 373 are received, and therefore the signal of this two pins input is imported in one first multiplexer 357, utilizes control signal 32 as selection.When the logic level of control signal 32 was 0, selecting the signal of pin 371 inputs was LV0-; When the logic level of control signal 32 was 1, selecting the signal of pin 373 inputs was LV0-.
Reduced Swing Differential Signal and output frequency signal then are described, signal with 375 outputs of selection pin is that RSR0-or RSR2+ are example, the signal that pin 375 is exported be RSR0-and RSR2+ one of them, depend on and face up or face down and decide, therefore before with this two output signals output, in input one second multiplexer 359, utilize control signal 32 earlier as selecting.When the logic level of control signal 32 was 0, selecting the signal with output was RSR0-; Otherwise when the logic level of control signal 32 was 1, selecting the signal with output was RSR2+.
Except above-mentioned various pins, time schedule controller of the present invention also comprises the pin of some basic functions, the pin etc. that the power pin, ground connection pin of time schedule controller power supply for example is provided and transmits the required chip for driving control signal of control LCD.In addition, time schedule controller also can comprise the pin of other function, to increase the practicality of time schedule controller.
Time schedule controller of the present invention is also extendible to be the input and output of dual-port, is about to the output connecting pin of Reduced Swing Differential Signal and the input pin of Low Voltage Differential Signal and doubles, to increase the processing of data volume.
The present invention only need change the input signal of a certain specific pin, just can make time schedule controller be suitable for the LCD of two kinds of patterns that assembly faces upward or downward.Prior art can be because the difference that faces upward or downward of assembly, and causes the ordering of differential wave of input and output inappropriate, its line design will be gone up problem to avoid circuit to overlap at different layers (layer) when making designing printed circuit board; Therefore but can make that the impedance matching of differential wave is relatively poor, therefore need the different time schedule controller of two differential wave definition of pin position traditionally for use.The present invention then can overcome the problem of this overlapping development, not only need not to transport respectively to store or assemble and simplification manufacturing process, also reduces component design and manufacturing cost.
The above only is preferred embodiment of the present invention, and obviously under the situation that does not break away from the spirit and scope of the present invention, those of ordinary skill in the art can make various improvement and variation to the present invention.Therefore, the invention is intended to cover improvement and variation within all scopes that fall into appended claims and equivalent thereof.
Claims (12)
1. a time schedule controller is characterized in that, comprises:
One data pin port has a plurality of pins;
One control pin is in order to receive a control signal; And
One selector switch determines this data pin port to transmit or receive the order of a signal according to this control signal;
Wherein, this time schedule controller is a chip, and the level of this control signal is faced up by chip or ventricumbent circuit assembling morphology and determining.
2. time schedule controller according to claim 1 is characterized in that, this signal is a Low Voltage Differential Signal.
3. time schedule controller according to claim 1 is characterized in that, this signal is a Reduced Swing Differential Signal.
4. time schedule controller according to claim 1 is characterized in that this signal comprises frequency signal.
5. time schedule controller according to claim 1 is characterized in that, this selector switch is a multiplexer.
6. time schedule controller according to claim 1 is characterized in that this time schedule controller is used for a Thin Film Transistor-LCD.
7. a LCD is characterized in that, comprises:
Time schedule controller, it comprises:
One data pin port has a plurality of pins;
One control pin is in order to receive a control signal; And
One selector switch determines this data pin port to transmit or receive the order of a signal according to this control signal;
One panel; And
One chip for driving drives this panel according to this signal and shows;
Wherein, this time schedule controller is a chip, and the level of this control signal is faced up by chip or ventricumbent circuit assembling morphology and determining.
8. LCD according to claim 7 is characterized in that, this signal is a Low Voltage Differential Signal.
9. LCD according to claim 7 is characterized in that, this signal is a Reduced Swing Differential Signal.
10. LCD according to claim 7 is characterized in that this signal comprises frequency signal.
11. LCD according to claim 7 is characterized in that, this selector switch is a multiplexer.
12. LCD according to claim 7 is characterized in that, this LCD is a Thin Film Transistor-LCD.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006101622163A CN100461257C (en) | 2006-12-06 | 2006-12-06 | Time sequence controller and liquid crystal display device including the same time sequence controller |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101622163A CN100461257C (en) | 2006-12-06 | 2006-12-06 | Time sequence controller and liquid crystal display device including the same time sequence controller |
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| CN1975853A CN1975853A (en) | 2007-06-06 |
| CN100461257C true CN100461257C (en) | 2009-02-11 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109979405B (en) * | 2019-03-27 | 2021-08-06 | 昆山龙腾光电股份有限公司 | Time sequence control circuit and display device |
| CN111540314B (en) * | 2020-05-13 | 2021-07-06 | 芯颖科技有限公司 | Display control method, control circuit, chip and electronic equipment |
Citations (7)
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| JPH10268836A (en) * | 1997-03-21 | 1998-10-09 | Asahi Glass Co Ltd | Method for driving liquid crystal display device |
| JP2000089732A (en) * | 1998-09-11 | 2000-03-31 | Mitsubishi Electric Corp | One-chip microcomputer |
| CN1588527A (en) * | 2004-09-14 | 2005-03-02 | 友达光电股份有限公司 | Time sequence controller with external transmission interface and electronic product using said controller |
| CN1624746A (en) * | 2003-12-01 | 2005-06-08 | Lg电子株式会社 | Apparatus and method for driving plasma display panel |
| JP2005181669A (en) * | 2003-12-19 | 2005-07-07 | Sanyo Electric Co Ltd | Liquid crystal panel driving device |
| CN1797530A (en) * | 2004-12-29 | 2006-07-05 | 苏柏宪 | LCD module and control method |
| CN1870115A (en) * | 2005-05-26 | 2006-11-29 | 凌阳科技股份有限公司 | Time sequence controller and source driver of liquid crystal panel and control method and circuit |
-
2006
- 2006-12-06 CN CNB2006101622163A patent/CN100461257C/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10268836A (en) * | 1997-03-21 | 1998-10-09 | Asahi Glass Co Ltd | Method for driving liquid crystal display device |
| JP2000089732A (en) * | 1998-09-11 | 2000-03-31 | Mitsubishi Electric Corp | One-chip microcomputer |
| CN1624746A (en) * | 2003-12-01 | 2005-06-08 | Lg电子株式会社 | Apparatus and method for driving plasma display panel |
| JP2005181669A (en) * | 2003-12-19 | 2005-07-07 | Sanyo Electric Co Ltd | Liquid crystal panel driving device |
| CN1588527A (en) * | 2004-09-14 | 2005-03-02 | 友达光电股份有限公司 | Time sequence controller with external transmission interface and electronic product using said controller |
| CN1797530A (en) * | 2004-12-29 | 2006-07-05 | 苏柏宪 | LCD module and control method |
| CN1870115A (en) * | 2005-05-26 | 2006-11-29 | 凌阳科技股份有限公司 | Time sequence controller and source driver of liquid crystal panel and control method and circuit |
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| CN1975853A (en) | 2007-06-06 |
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