CN1870115A - Time sequence controller and source driver of liquid crystal panel and control method and circuit - Google Patents
Time sequence controller and source driver of liquid crystal panel and control method and circuit Download PDFInfo
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- CN1870115A CN1870115A CN 200510072099 CN200510072099A CN1870115A CN 1870115 A CN1870115 A CN 1870115A CN 200510072099 CN200510072099 CN 200510072099 CN 200510072099 A CN200510072099 A CN 200510072099A CN 1870115 A CN1870115 A CN 1870115A
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Abstract
A method for controlling sequential controller and source electrode actuator of liquid crystal front plate includes using sequential controller to convert control signal and data to be sequence-format first, then transmitting them to chip of each source electrode actuator, only setting three signal lines and two control lines on sequential controller and on each source electrode actuator since data is converted to be sequence-format in advance.
Description
Technical field
The present invention relates to the time schedule controller and the source electrode driver of liquid crystal panel, particularly about control circuit and control method with time schedule controller and the source electrode driver and the liquid crystal panel of sequence transmission mode.
Background technology
How increasing the battery service time of mobile computer (notebook) and reduce system cost, is the direction that manufacturer and system designer are made joint efforts and studied.Motherboard display system and Thin Film Transistor-LCD (Thin-Film Transistor Liquid Crystal Display between mobile computer, TFT-LCD) transmission of the signal between the panel (panel), Low Voltage Differential Signal (Low-VoltageDifferential Signal, LVDS) be the signal transmission standard of standard, therefore there is no and promote improved space.
And for the transmission between time schedule controller (timing controller) chip and source electrode driver (sourcedriver) chip, (Electromagnetic Interference, requirement EMI) is special the attention to low electromagnetic interference (EMI).So most design is all selected to reduce EMI with differential transmission (differentialtransmission), similarly be low wave differential wave (reduced swing differentialsignal, RSDS).The product of main flow is to be that the transmission architecture person is in the majority with RSDS at present.But with regard to RSDS, similarly be that the operating voltage that is lower than 2.3V is difficult to reach for the demand of low-work voltage.The RSDS transmission interface was the differential to (differential pair) transmission mode of current-mode (current mode) in the past, so its power consumption is not little.
Fig. 1 is the connection diagram between known time schedule controller and a plurality of source driving chip.As shown in Figure 1, time schedule controller 11 output control signals and data bus are to each source driver chip 120～129.Control signal between every source driver chip and data bus are and are connected in parallel.23 lines be must be connected between every source driver chip and the time schedule controller chip, 18 data lines and 5 control lines comprised.Therefore be to bother very much and must use 4 layers with regard to panel layout (layout).It is unsatisfactory with power saving just to reduce cost.
Summary of the invention
The objective of the invention is to propose a kind of time schedule controller that outputs signal to source driver chip in the sequence mode.
Another object of the present invention is the source electrode driver that proposes a kind of receiving sequence signal.
Another object of the present invention is control circuit and the control method that proposes a kind of liquid crystal panel.
For reaching above-mentioned purpose, time schedule controller of the present invention is to use in display panels, after this time schedule controller receives pixel data, transfers to the multiple source driver after control signal and pixel data changed into Format Series Lines, this sequential control comprises: a signal receiver receives pixel data; One data-reading unit is from the signal receiver reading of data; One steering logic unit after the reception data that data-reading unit read, produces pixel data; One Date Conversion Unit receives the pixel data of steering logic unit, and exports after converting pixel data to many group sequence signals.
The source electrode driver of liquid crystal panel of the present invention, this source electrode driver receives at least one data sequence signal, and produces the source drive signal of liquid crystal panel, and the source electrode driver of this liquid crystal panel comprises:
One control signal code translator and data buffer, receive a described data sequence signal and a mode control signal, and come the encoded control instruction or receive pixel data, and follow according to steering order output displacement control signal, Loading Control signal, polarity control signal, preparation control signal and data according to the state of this mode control signal;
One offset buffer receives the data of described control signal code translator and data buffer, and carries out shift motion according to control signal;
One data latching unit receives the data and the described Loading Control signal of described offset buffer, and according to this Loading Control signal with the data load that is received;
One D/A conversion unit receives data and described polarity control signal that described data latching unit is exported, and controls according to this polarity control signal; And
One output buffer receives the data and the described preparation control signal of described D/A conversion unit, and according to this preparation control signal data is exported.
The control circuit of liquid crystal panel of the present invention, this liquid crystal panel comprise time schedule controller and at least one source electrode driver, after this time schedule controller receives transmission signals, transfer to source electrode driver after control signal and data are changed into Format Series Lines.
A kind of control method of liquid crystal panel is sent to source electrode driver with pixel data from time schedule controller in the sequence transmission mode, it is characterized in that, this control method comprises the following step:
Wait for drawing frame data;
Judge whether to begin the transmission diagram frame data, if do not begin transmission as yet, then drawing frame data is waited in rebound, then skips to next step if will begin transmission;
Wait for data line;
Judge whether to begin to transmit data line, if do not begin transmission as yet, then the data line step is waited in rebound, then skips to next step if will begin transmission;
Output displacement steering order transmits the displacement steering order to source electrode driver by described time schedule controller;
Transmit pixel data, by time schedule controller each pixel data is changed into Format Series Lines after, be sent to each source driving chip in the sequence mode again;
Judge whether described data line end of transmission, if end of transmission not as yet, then rebound transmits the pixel data step, if end of transmission then skips to next step;
The instruction of output polarity control/Loading Control is instructed to each source electrode driver by described time schedule controller output polarity control/Loading Control;
Judge whether described picture frame end of transmission, if end of transmission not as yet, then the data line step is waited in rebound, if end of transmission, then the drawing frame data step is waited in rebound.
The present invention is because data change into Format Series Lines earlier, therefore the chip of time schedule controller and each source electrode driver only needs 3 signal line and two control lines to get final product, can reduce the degree of difficulty of the layout of liquid crystal circuit board, and also the flaggy number of circuit board is kept to 2 layers by 4 layers.
Description of drawings
Fig. 1 is the connection diagram between known time schedule controller and a plurality of source driving chip.
Fig. 2 is the time schedule controller of sequence transmission of the present invention and the connection diagram between a plurality of source driving chip.
Fig. 3 is the Organization Chart of time schedule controller of the present invention.
Fig. 4 is the Organization Chart of the Date Conversion Unit of Fig. 3.
Fig. 5 is the Organization Chart of source electrode driver of the present invention.
Fig. 6 is the control signal code translator of Fig. 5 and the Organization Chart of data buffer.
Fig. 7 A and Fig. 7 B represent the transfer process of whole line data, and wherein the steering order of Fig. 7 A is the STH instruction, and the steering order of Fig. 7 B is the POL/LOAD instruction.
Fig. 8 is the process flow diagram of the data control method of liquid crystal panel of the present invention.
11,21 time schedule controllers
120～129,220～229 source electrode drivers
31 LVDS receivers
32 data-reading unit
33 FRC logical blocks
34 Date Conversion Units
341 data processing units
342 data buffers
343 change sequence units side by side
344 control signal scramblers
41 first multiplexers
42 internal memories
421 first memory blocks
422 second memory blocks
43 second multiplexers
44 impact dampers
441 first buffer zones
442 second buffer zones
45 separate multiplexer
51 control signal code translator and data buffers
511 control signal code translators
512 sequences are changeed and column unit
513 data buffers
52 offset buffers
53 data latching devices
54 D/A conversion units
55 output buffers
Embodiment
Fig. 2 is the time schedule controller of sequence transmission of the present invention and the connection diagram between a plurality of source driving chip.As shown in Figure 2, time schedule controller 21 of the present invention changes into sequence (serial) with data bus signal from (parallel) arranged side by side, therefore 21 of time schedule controllers of the present invention need 2 control signal wires of output to each source driver chip 220～229, and only export 3 signal wires respectively to each source driver chip 220～229.So the connecting line between time schedule controller chip of the present invention and each source driver chip greatly reduces, can reduce the degree of difficulty of printed circuit board (PCB) (PCB) layout, and also the flaggy number of printed circuit board (PCB) is kept to 2 layers by 4 layers.Not only lowered manufacturing cost, also lowered power consumption and lower EMI.And this framework also is applicable to glass substrate chip (Chip on glass, COG) packing on the large size panel.With this embodiment, time schedule controller chip signal output to 10 source driver chip, though the total output signal line of this time schedule controller 21 increases to 32, but the signal wire that is connected to indivedual source driver chip 220～229 only needs 5, significantly reduces the degree of difficulty of printed circuit board layout.Certainly, the channel (channel) that the quantity of source driver chip is looked source electrode driver to be provided is adjusted with panel resolution, can be one or more.
Fig. 3 is the Organization Chart of time schedule controller of the present invention.As shown in the drawing, time schedule controller 21 of the present invention comprises a Low Voltage Differential Signal (LVDS) receiver 31, a data-reading unit 32, frame rate control (Framerate control, FRC) logical block 33 and a Date Conversion Unit 34.In the sequence controller 21, the framework of LVDS receiver 31, data-reading unit 32, FRC logical block 33 is identical with known time schedule controller with function, no longer repeat specification at this moment.Time schedule controller 21 of the present invention is to use Date Conversion Unit 34 to convert pixel data and control signal to sequence signal with the main difference of known time schedule controller, and is sent to each source driver chip 220～229 respectively.
The signal that time schedule controller 21 exports each source driver chip 220～229 to comprises mode control signal DINT, clock signal SCLK and R, G, three data lines of B.Mode control signal DINT is that what to be used for showing present R, G, three of B data line transmitted is general pixel data (data pattern) or steering order (instruction mode).For example mode control signal DINT is the instruction mode of transfer control instruction when first state (state is 1), and is the data pattern that transmits pixel data when second state (state is 0).Mode control signal DINT is the control signal of switch data pattern and instruction pattern.
Because instruction mode and data pattern are mutual exclusions, so do not influencing under the normal data transmission, the initial and line data that is used in line data usually finishes the back to be carried out.Certainly, also can be used in the Elementary Function setting of source electrode driver and the change function setting in the data transmission.The mode that produces as for mode control signal DINT is to use the sequential that open beginning and each line data transmission of internal state machine (figure does not show) according to each picture frame (frame), according to the transmission and the control method of known source electrode driver, on state machine, trigger the transfer mode that appropriate control signals is switched DINT.And clock signal SCLK is used for synchronous output data and the multiple source driver that is connected.
Because known time schedule controller is to export pixel data to each source driver chip in regular turn in data mode arranged side by side.Therefore, the data output sequence of FRC logical block 33 is data of exporting second source driver chip after the data output of first source driver chip finishes again.But 21 of time schedule controllers of the present invention are to utilize different signal wire while output datas to each source driver chip, could export after therefore the data of FRC logical block 33 must being changed.
Below will further specify the framework of Date Conversion Unit 34.Fig. 4 is the Organization Chart of the Date Conversion Unit of Fig. 3.As shown in the drawing, Date Conversion Unit 34 comprises one first multiplexer 41, an internal memory 42, one second multiplexer 43, an impact damper 44, is separated multiplexer 45, changes a sequence units 343 and a control signal scrambler 344 side by side.Internal memory 42 comprises two zones, is respectively first memory block 421 and second memory block 422.Impact damper 44 also comprises first buffer zone 441 and second buffer zone 442.The data that Date Conversion Unit 34 is transmitted FRC logical block 33 (comprising R, G, B) are stored to first memory block 421 or second memory block 422 via the control of first multiplexer 41.This first multiplexer 41 is to be controlled by a line switching signal LT.Afterwards, Date Conversion Unit 34 is stored to first buffer zone 441 or second buffer zone 442 with the data of first memory block 421 or second memory block 422 via the control of second multiplexer 43.And this second multiplexer 43 is to be controlled by line switching signal LT and some switching signal PT.Line switching signal LT controls from first memory block 421 or second memory block, 422 reading of data, and some switching signal PT control writes first buffer zone 441 or second buffer zone 442.Then, Date Conversion Unit 34 will be sent to commentaries on classics sequence units 343 arranged side by side via separating multiplexer 45 controls after first buffer zone 441 or second buffer zone, 442 reading of data.And this to separate multiplexer 45 be by some switching signal PT control.
Therefore, according to the state variation of line switching signal LT with some switching signal PT, the data of Date Conversion Unit 34 transmit four kinds of paths.
First path: when line switching signal LT is that first state (for example be 1 state) and some switching signal PT are when also being first state (for example be 0 state), the data (comprising R, G, B) that this Date Conversion Unit 34 is transmitted FRC logical block 33 are stored to second memory block 422 via first multiplexer 41, and this Date Conversion Unit 34 is stored to second buffer zone 442 with the data of first memory block 421 via second multiplexer 43 simultaneously.And this Date Conversion Unit 34 is sent to commentaries on classics sequence units 343 arranged side by side with the data of first buffer zone 441 via separating multiplexer 45.Shown in the dotted line arrow of Fig. 4.
Second path: when line switching signal LT is that first state (for example be 1 state) and some switching signal PT are also during second state (for example be 1 state), the data (comprising R, G, B) that this Date Conversion Unit 34 is transmitted FRC logical block 33 are stored to second memory block 422 via first multiplexer 41, and this Date Conversion Unit 34 is stored to first buffer zone 441 with the data of first memory block 421 via second multiplexer 43 simultaneously.And this Date Conversion Unit 34 is sent to commentaries on classics sequence units 343 arranged side by side with the data of second buffer zone 442 via separating multiplexer 45.
Third Road footpath: when line switching signal LT is that second state (for example be 0 state) and some switching signal PT are when also being first state (for example be 0 state), the data (comprising R, G, B) that this Date Conversion Unit 34 is transmitted FRC logical block 33 are stored to first memory block 421 via first multiplexer 41, and this Date Conversion Unit 34 is stored to the second slow middle district 442 with the data of second memory block 422 via second multiplexer 43 simultaneously.And this Date Conversion Unit 34 is sent to commentaries on classics sequence units 343 arranged side by side with the data of first buffer zone 441 via separating multiplexer 45.
The 4th path: when line switching signal LT is that second state (for example be 0 state) and some switching signal PT are when also being second state (for example be 1 state), the data (comprising R, G, B) that this Date Conversion Unit 34 is transmitted FRC logical block 33 are stored to first memory block 421 via first multiplexer 41, and this Date Conversion Unit 34 is stored to first buffer zone 441 with the data of second memory block 422 via second multiplexer 43 simultaneously.And this Date Conversion Unit 34 is sent to commentaries on classics sequence units 343 arranged side by side with the data of second buffer zone 442 via separating multiplexer 45.
Fig. 5 is the Organization Chart of source electrode driver of the present invention.As shown in the drawing, source electrode driver 50 comprises a control signal code translator and data buffer 51, an offset buffer (Shift Register) 52, one data latching device (Data Latches) 53, one D/A conversion unit (R-DAC) 54 and an output buffer (Output Buffer) 55.The function of offset buffer 52, data latching device 53, R-DAC 54 and output buffer 55 is identical with known source electrode driver with framework, no longer repeat specification.And control signal code translator and data buffer 51 are receiving mode control signal DINT, clock signal SCLK and R, G, three data lines of B, and produce required control signal or receive pixel data according to the state of mode control signal DINT.General known control signal has displacement control signal STH, Loading Control signal LOAD, polarity control signal POL and preparation control signal STBY.These control signals are used for controlling the action of offset buffer 52, data latching device 53, D/A conversion unit 54 and output buffer 55 respectively, and its control mode is identical with known source electrode driver with opportunity, no longer repeat specification.
Fig. 6 is the control signal code translator of Fig. 5 and the Organization Chart of data buffer.As shown in Figure 6, control signal code translator and data buffer 51 comprise a control signal code translator 511, a sequence is changeed and a column unit 512 and a data buffer 513.Control signal code translator 511 receiving mode control signal DINT and data line R, and the data according to data line R produce required displacement control signal STH, Loading Control signal LOAD, polarity control signal POL and preparation control signal STBY when mode control signal DINT is control model.Sequence is changeed and column unit 512 receiving mode control signal DINT and data line R, G, B, and is temporary in data buffer 513 after data are changed into parallel data.Sequence is changeed and column unit 512 is to come signal on sampled data line R, G, the B according to clock signal SCLK as the sampling clock pulse, and in the data bus mode data is sent to data buffer 513.It is identical with known technology with the framework and the technology of data latching device 53 as for data buffer 513 data to be reached offset buffer 52, no longer repeat specification.
Fig. 7 A and Fig. 7 B represent the transfer process of whole line data.As shown in the drawing, when time schedule controller 21 wants transfer control instruction to give source electrode driver, time schedule controller 21 can be set at mode control signal DINT instruction mode (being high levels at this embodiment) earlier, and after utilizing control signal scrambler 344 with steering order (at this embodiment for transmitting control signal STH) coding, the data after will encoding via commentaries on classics sequence units 343 arranged side by side are sent to each source electrode driver.Afterwards, time schedule controller 21 can be set at mode control signal DINT data pattern (being low level at this embodiment) again, and transmits the pairing pixel data of each source electrode driver in regular turn to each source electrode driver.Therefore, when instruction mode, the data of R0～R9 can be identical, also can be inequality, and conveniently to do control out of the ordinary.But when data pattern, the data of R0～R9 are the sequence data that is sent to each source driving chip.After sequence data transmits end, time schedule controller 21 can be according to the characteristic of source electrode driver, in appropriate time, mode control signal DINT is set at instruction mode, and after utilizing control signal scrambler 344 with steering order (being transmission control signal LOAD and POL) coding at this embodiment, data after will encoding via commentaries on classics sequence units 343 arranged side by side are sent to each source electrode driver, finish the transfer process of whole line data.In addition, the data line that can only use R0～R9 when instruction mode transmits data, also can use other data line to do transmission, decides on bilateral agreement.Fig. 7 A is that institute's control signals transmitted is different with the difference of Fig. 7 B.In addition, the data in Fig. 7 A and Fig. 7 B are 6, but also can be 8 or other figure place, adjust according to panel resolution fully.
In addition, if all be used for the sequence signal of taking a sample and being transmitted at the positive edge of the clock pulse SCLK of system and negative edge, shown in Fig. 7 A and Fig. 7 B, then the frequency of system's clock pulse SCLK can be reduced to half of frequency of known system clock pulse SCLK.So, because the reduction of the frequency of the clock pulse SCLK of system is therefore little a lot of than the system of known use RSDS with regard to the relative meeting of the consumption of power.And, more provide more high transmission speed and usefulness because of reducing by half of operating frequency for the bottleneck of transmission speed that high resolution image faces.
Fig. 8 is the process flow diagram of the data control method of liquid crystal panel of the present invention.This data control method is in the sequence transmission mode pixel data to be sent to source driving chip from time schedule controller.The data control method of liquid crystal panel of the present invention is described below with reference to Fig. 8.
Step S802: beginning.
Step S804: wait for drawing frame data.That is time schedule controller is in the state that receives drawing frame data of waiting for.
Step S806: judge whether to begin the transmission diagram frame data? if do not begin transmission as yet, then rebound step S804; Then skip to step S808 if will begin transmission.
Step S808: wait for data line.That is system is in the state that receives data line of waiting for.
Step S810: judge whether to begin to transmit data line? if do not begin transmission as yet, then rebound step S808; Then skip to step S812 if will begin transmission.
Step S812: output displacement control (STH) instruction.That is by time schedule controller output displacement steering order to each source driving chip.After this displacement steering order is converted into sequence signal in advance, transmit in the sequence mode again.
Step S814: transmit pixel data in the sequence mode.That is after by time schedule controller each pixel data being changed into Format Series Lines, be sent to each source driving chip in the sequence mode again.
Step S816: judge whether this data line end of transmission? if end of transmission not as yet, then rebound step S814; If end of transmission then skips to step S818.
Step S818: output polarity control (POL)/Loading Control (LOAD) instruction.That is by time schedule controller output polarity control/Loading Control instruction to each source driving chip.After this Polarity Control/the Loading Control instruction is converted into sequence signal in advance, transmit in the sequence mode again.
Step S820: judge whether this picture frame end of transmission? if end of transmission not as yet, then rebound step S808; If end of transmission then skips to step S822.
Step S822: finish the transmission of this drawing frame data, and rebound step S804.
Control method of the present invention mainly is in transmission during data, by time schedule controller each pixel data or steering order are changed into Format Series Lines after, be sent to each source driving chip in the sequence mode again.Because data have been converted into sequence signal in advance, thus only need R, G between time schedule controller and each source driving chip, three data lines of B, a clock pulse SCLK of system and a mode control signal get final product.
Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, the sector person can carry out various distortion or change.
Claims (15)
1. the time schedule controller of a liquid crystal panel after this time schedule controller receives transmission signals, transfers to the multiple source driver after control signal and pixel data changed into Format Series Lines, it is characterized in that the sequential control of this liquid crystal panel comprises:
One signal receiver receives described transmission signals;
One data-reading unit is from described signal receiver reading of data;
One steering logic unit, receive the data that described data-reading unit reads after, produce described pixel data;
One Date Conversion Unit receives the pixel data of described steering logic unit, and exports after converting described pixel data to many group sequence signals.
2. the time schedule controller of liquid crystal panel as claimed in claim 1 is characterized in that, described Date Conversion Unit comprises:
One internal memory comprises one first section internal memory and one second section internal memory;
One first multiplexer receives described pixel data, and selects signal to export the pixel data that is received to the described first section internal memory or the second section internal memory according to one first;
One impact damper comprises one first buffer location and one second buffer location;
One second multiplexer receives data from the described first section internal memory and the second section internal memory, and selects signal and one second to select signal to export the data that received to described first buffer location or second buffer location according to described first;
One separates multiplexer, receives the data of described first buffer location and second buffer location, and selects signal to select the data of first buffer location or second buffer location to export according to described second; And
One changes sequence units side by side, receives data from the described multiplexer of separating, and these data are converted to sequence signal output.
3. the time schedule controller of liquid crystal panel as claimed in claim 2 is characterized in that, described Date Conversion Unit comprises:
One control signal scrambler, the control signal that described source electrode driver is delivered in the tendency to develop generation coded signal of encoding;
Wherein, described commentaries on classics sequence units arranged side by side also receives described coded signal, and this coded signal is converted to sequence signal output.
4. the time schedule controller of liquid crystal panel as claimed in claim 3 is characterized in that, described Date Conversion Unit is also exported a mode control signal, and it is control signal or pixel data that this mode control signal is used to refer to the signal that is transmitted.
5. the time schedule controller of liquid crystal panel as claimed in claim 3 is characterized in that, described Date Conversion Unit is also exported a clock pulse signal, and this clock signal is used for synchronous output data and the multiple source driver that is connected.
6. the source electrode driver of a liquid crystal panel, this source electrode driver receives at least one data sequence signal, and produces the source drive signal of liquid crystal panel, it is characterized in that the source electrode driver of this liquid crystal panel comprises:
One control signal code translator and data buffer, receive a described data sequence signal and a mode control signal, and come the encoded control instruction or receive pixel data, and follow according to steering order output displacement control signal, Loading Control signal, polarity control signal, preparation control signal and data according to the state of this mode control signal;
One offset buffer receives the data of described control signal code translator and data buffer, and carries out shift motion according to control signal;
One data latching unit receives the data and the described Loading Control signal of described offset buffer, and according to this Loading Control signal with the data load that is received;
One D/A conversion unit receives data and described polarity control signal that described data latching unit is exported, and controls according to this polarity control signal; And
One output buffer receives the data and the described preparation control signal of described D/A conversion unit, and according to this preparation control signal data is exported.
7. the source electrode driver of liquid crystal panel as claimed in claim 6 is characterized in that, described control signal code translator and data buffer comprise:
One control signal code translator, receive described mode control signal and at least one described data sequence signal, and when this mode control signal is first state, decipher this data sequence signal, and produce described displacement control signal, Loading Control signal, polarity control signal, preparation control signal;
One sequence is changeed and column unit, receives the described data sequence signal of described mode control signal and bar, and the data sequence signal of when this mode control signal is second state interlocking being received converts to and column signal, and exports parallel data; And
One data buffer receives the parallel data that described sequence is changeed and column unit is exported.
8. the source electrode driver of liquid crystal panel as claimed in claim 7 is characterized in that, described sequence is changeed and column unit also receives a clock pulse signal as the reference clock signal.
9. the control circuit of a liquid crystal panel, it is characterized in that this liquid crystal panel comprises time schedule controller and at least one source electrode driver, after this time schedule controller receives transmission signals, transfer to source electrode driver after control signal and data are changed into Format Series Lines, this time schedule controller comprises:
One signal receiver receives described transmission signals;
One data-reading unit is from described signal receiver reading of data;
One steering logic unit, receive the data that described data-reading unit reads after, produce pixel data; And
One Date Conversion Unit receives the pixel data of described steering logic unit, and exports after converting described pixel data to many group sequence signals;
Wherein said each source electrode driver comprises:
One control signal code translator and data buffer, receive a described data sequence signal and a mode control signal, and come the encoded control instruction or receive pixel data, and follow according to steering order output displacement control signal, Loading Control signal, polarity control signal, preparation control signal and data according to the state of this mode control signal;
One offset buffer receives the data of described control signal code translator and data buffer, and carries out shift motion according to control signal;
One data latching unit receives the data and the described Loading Control signal of described offset buffer, and according to this Loading Control signal with the data load that is received;
One D/A conversion unit receives data and described polarity control signal that described data latching unit is exported, and controls according to this polarity control signal; And
One output buffer receives the data and the described preparation control signal of described D/A conversion unit, and according to this preparation control signal data is exported.
10. the control circuit of liquid crystal panel as claimed in claim 9 is characterized in that, described time schedule controller is to connect many signal line respectively to described each source electrode driver, to utilize the described many group sequence signals of described many signal line transmission.
11. the control circuit of liquid crystal panel as claimed in claim 10 is characterized in that, after described time schedule controller also changes into sequence signal with steering order, utilizes at least one described signal wire to come transfer control instruction.
12. the control circuit of liquid crystal panel as claimed in claim 10, it is characterized in that, described time schedule controller is also exported a mode control signal to described each source electrode driver, serves as instruction or pixel data with the sequence signal that utilizes this mode control signal to set to be transmitted.
13. the control method of a liquid crystal panel is sent to source electrode driver with pixel data from time schedule controller in the sequence transmission mode, it is characterized in that, this control method comprises the following step:
Wait for drawing frame data;
Judge whether to begin the transmission diagram frame data, if do not begin transmission as yet, then drawing frame data is waited in rebound, then skips to next step if will begin transmission;
Wait for data line;
Judge whether to begin to transmit data line, if do not begin transmission as yet, then the data line step is waited in rebound, then skips to next step if will begin transmission;
Output displacement steering order transmits the displacement steering order to source electrode driver by described time schedule controller;
Transmit pixel data, by time schedule controller each pixel data is changed into Format Series Lines after, be sent to each source driving chip in the sequence mode again;
Judge whether described data line end of transmission, if end of transmission not as yet, then rebound transmits the pixel data step, if end of transmission then skips to next step;
The instruction of output polarity control/Loading Control is instructed to each source electrode driver by described time schedule controller output polarity control/Loading Control;
Judge whether described picture frame end of transmission, if end of transmission not as yet, then the data line step is waited in rebound, if end of transmission, then the drawing frame data step is waited in rebound.
14. the control method of liquid crystal panel as claimed in claim 13, it is characterized in that, the step of described output displacement steering order is will be shifted after steering order changes into Format Series Lines by described time schedule controller, is sent to each source driving chip in the sequence mode again.
15. the control method of liquid crystal panel as claimed in claim 13, it is characterized in that, the step of described output polarity control/Loading Control instruction be by described time schedule controller with after Polarity Control/Loading Control instruction changes into Format Series Lines, be sent to each source driving chip in the sequence mode again.
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| CNB2005100720997A CN100446075C (en) | 2005-05-26 | 2005-05-26 | Time sequence controller and source driver of liquid crystal panel and control method and circuit |
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| CNB2005100720997A CN100446075C (en) | 2005-05-26 | 2005-05-26 | Time sequence controller and source driver of liquid crystal panel and control method and circuit |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461257C (en) * | 2006-12-06 | 2009-02-11 | 友达光电股份有限公司 | Time sequence controller and liquid crystal display device including the same time sequence controller |
| CN101246670B (en) * | 2007-02-17 | 2010-06-16 | 联詠科技股份有限公司 | Serial data transmission method and correlated device used for display device |
| CN101572047B (en) * | 2008-05-04 | 2011-05-18 | 联咏科技股份有限公司 | Data synchronization method for display and correlative device |
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| JP3830663B2 (en) * | 1998-07-14 | 2006-10-04 | 三菱電機株式会社 | Liquid crystal display |
| JP3777884B2 (en) * | 1999-07-23 | 2006-05-24 | セイコーエプソン株式会社 | Display driver IC and electronic device using the same |
| JP4118072B2 (en) * | 2001-03-29 | 2008-07-16 | 東芝松下ディスプレイテクノロジー株式会社 | Display device |
| KR100435114B1 (en) * | 2001-12-20 | 2004-06-09 | 삼성전자주식회사 | liquid display apparatus |
| CN1294552C (en) * | 2004-07-27 | 2007-01-10 | 友达光电股份有限公司 | Liquid crystal display and its method |
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2005
- 2005-05-26 CN CNB2005100720997A patent/CN100446075C/en not_active Expired - Fee Related
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| CN101246670B (en) * | 2007-02-17 | 2010-06-16 | 联詠科技股份有限公司 | Serial data transmission method and correlated device used for display device |
| CN101572047B (en) * | 2008-05-04 | 2011-05-18 | 联咏科技股份有限公司 | Data synchronization method for display and correlative device |
| CN102890919A (en) * | 2011-07-20 | 2013-01-23 | 联咏科技股份有限公司 | Source driver array and drive method of source driver array as well as liquid crystal drive device |
| CN105609068A (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Time schedule controller, source drive IC, and source driving method |
| WO2017118043A1 (en) * | 2016-01-04 | 2017-07-13 | 京东方科技集团股份有限公司 | Timing controller, source drive ic and source drive method |
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