JP4430719B2 - Electric field communication device - Google Patents

Description

  The present invention relates to an electric field communication device for performing communication by inducing an electric field in an electric field transmission medium.

  Conventionally, there has been proposed an electric field communication system in which an electric field is induced in an electric field transmission medium such as a human body and various information communication is performed via the induced electric field. This electric field communication system has electric field communication devices equipped with transmission means and / or reception means, and is similar to other people and facilities (PCs, station ticket gates, vending machines, doors, gates, etc.) Owns or installs the electric field communication device, and performs information communication according to the purpose. This information communication makes it possible to collect data such as security authentication, billing, and location (see Patent Document 1).

  The operation of a communication circuit, a drive circuit, a control circuit, and the like for such an electric field communication device to perform electric field communication is controlled by an execution sequence by the CPU. In addition, a clock signal necessary for the operation of the electric field communication apparatus is generally generated by a clock signal generation circuit using a crystal resonator or the like.

FIG. 5 shows an example of a clock signal generation circuit conventionally used. In the circuit of FIG. 5, an oscillation circuit is configured by the crystal unit 102, inverters 100 and 101, resistors 105 and 106, and capacitors 103 and 104.

FIG. 6 shows signal waveforms at points A and B in the figure. When a resonator (oscillator) oscillation request signal is input to the clock signal generation circuit (resonator), the clock signal generation circuit shown in FIG. 5 is activated to start oscillation of the clock signal.

In the prior art as described above, when observing the waveform of the signal at point A, it occurs resonator unstable period oscillation frequency in a period of time from the start of oscillation as shown in FIG. Along with the signal at point A, the clock signal output to point B has a state where the frequency is not stable for a certain period from the start of oscillation , as shown in FIG.

  The present invention has been made in view of the above, and an object of the present invention is to prevent an unstable clock signal from being output immediately after activation of the clock signal generation circuit, and to stop the CPU until the clock signal becomes stable. It is to reduce power consumption.

In order to achieve the above object, the present invention according to claim 1 is directed to an operation of a drive circuit for inducing an electric field in an electric field communication device for inducing communication in an electric field transmission medium. An original signal oscillation circuit for generating and outputting an original signal for generating a necessary clock signal, and the clock to the drive circuit until the amplitude of the original signal input from the original signal oscillation circuit exceeds a threshold value A Schmitt circuit for waiting without outputting a signal , wherein the Schmitt circuit sets the threshold on each of a high voltage side and a low voltage side with respect to the center of the amplitude of the original signal, and the high voltage A first transistor for setting the side as logic Vth high, a second transistor for setting the low voltage side as logic Vth low, and the original signal from the original signal oscillator circuit Wherein comprising first and NAND circuit for input to the transistor, and a NOR circuit for the signal input to the source signal to the second transistor from the source signal oscillating circuit.

  According to the present invention, it is possible to prevent an unstable clock signal from being output immediately after activation of the clock signal generation circuit, and to reduce power consumption by stopping the CPU until the clock signal becomes stable.

  FIG. 1 shows a circuit diagram of a clock signal generation circuit according to an embodiment of the electric field communication apparatus of the present invention. FIG. 1 shows a Schmitt circuit 1 having hysteresis characteristics, a crystal resonator 2, an inverter 3, resistors 4 and 5, and capacitors 6 and 7. Also, points A and C in FIG. 1 indicate waveform observation points.

  In the configuration of FIG. 1, the crystal resonator 2 determines the oscillation frequency, resonates with the capacitors 6 and 7 and oscillates at a predetermined frequency to generate a sine wave original signal. The inverter 3 can be a general CMOS-IC inverter circuit. The inverter 3 functions as an amplifier circuit in the circuit of FIG. 1, and the amplification degree (gain) is determined by the capacitance ratio of the capacitors 6 and 7. The resistor 4 is inserted to lower the gain of the amplifier circuit, and negative feedback is performed to the inverter 3 by the resistor 4. The resistor 5 is inserted to prevent overtone (a resonance frequency component that is an integral multiple of the intended oscillation frequency) from occurring in the oscillation circuit. The configuration up to this point constitutes an original signal oscillation circuit for oscillating a sine wave that is the source of the clock signal.

  The original signal oscillating with a sine wave is input to the Schmitt circuit 1 from the point A, and the threshold is set on each of the high voltage side and the low voltage side with respect to the center of the amplitude of the original signal. The threshold on the voltage side is set to logic Vth high, and the threshold on the low voltage side is set to logic Vth low.

  Next, FIG. 2 shows a configuration example of the Schmitt circuit 1.

  FIG. 2 shows a NAND circuit 10, a NOR circuit 11, inverters 12 and 16, TR (1) 13 composed of Pch transistors, and TR (2) 14 composed of Nch transistors. , Resistor 15.

  Next, referring to FIG. 3, when the amplitude of the original signal input to point A of Schmitt circuit 1 is small, the amplitude does not reach the logic Vth high of NAND circuit 10 and the logic Vth low of NOR circuit 11 and output. Does not change. However, when the amplitude at the point A exceeds the logic Vth high of the NAND circuit 10 and the logic Vth low of the NOR circuit 11, TR (1) 13 and TR (2) 14 are turned on and clocks at the F and C points. A signal appears.

  In actual circuit design, for example, the logic Vth high of the NAND circuit 10 is set closer to VDD / 2 than the logic Vth low of the NOR circuit 11. As a result, TR (1) 13 begins to turn on before TR (2) 14 and turns off later. As a result, the point F is fixed to VDD in a period in which the amplitude at the point A does not fall below the logic Vth low of the NOR circuit 11. The resistor 15 connected to the point F is a pull-up resistor for preventing floating when not operating for a long time.

  In this way, unstable oscillation immediately after the start of oscillation of the clock signal generation circuit is not output, so that an unstable clock signal is not input to a CPU or the like using this clock signal. During the period when the clock signal is not input, the CPU is in a stopped state, and the power consumed during this period can be reduced.

Next, FIG. 4 shows a configuration diagram of a modification of the embodiment of the present invention.

4 differs from the clock signal generation circuit already shown in FIG. 1 in that an AND circuit 20 and a counter 21 are added. An output from the Schmitt circuit 1 is input to the counter 21, and a resonator oscillation completion signal is output from the counter 21. This resonator oscillation completion signal is output in a state where the clock signal generation circuit is stably oscillating, and this output is transmitted to, for example, a CPU. The CPU is in a standby state until the resonator oscillation completion signal is input, and the power consumed during a period when the clock signal is unstable can be reduced. The clock signal is output from point C of the AND circuit 20.

  According to the embodiment of the present invention described above, an unstable clock signal is prevented from being output immediately after the clock signal generation circuit is started, and the CPU is stopped until the clock signal becomes stable, thereby reducing power consumption. can do.

The circuit diagram of the clock signal generation circuit based on embodiment of the electric field communication apparatus of this invention is shown. The structural example of the Schmitt circuit based on embodiment of this invention is shown. The wave form diagram for demonstrating operation | movement of a Schmitt circuit is shown . The modification of embodiment of this invention is shown. An example of the clock signal generation circuit by a prior art is shown. An example of the output waveform of the clock signal generation circuit by a prior art is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Schmitt circuit 2 ... Crystal oscillator 3, 12, 16 ... Inverter 4, 5, 15 ... Resistor 6, 7 ... Capacitor 10 ... NAND circuit 11 ... NOR circuit 13 ... TR (1)
14 ... TR (2)

Claims (1)

In an electric field communication apparatus for inducing communication in an electric field transmission medium and performing communication,
An original signal oscillation circuit for oscillating and outputting an original signal for generating a clock signal necessary for operation of the drive circuit for inducing the electric field;
A Schmitt circuit for waiting without outputting the clock signal to the drive circuit until the amplitude of the original signal input from the original signal oscillation circuit exceeds a threshold ,
The Schmitt circuit sets the threshold value on each of the high voltage side and the low voltage side with respect to the center of the amplitude of the original signal,
A first transistor for setting the high voltage side as a logic Vth high;
A second transistor for setting the low voltage side as a logic Vth low;
A NAND circuit for inputting the original signal from the original signal oscillation circuit to the first transistor;
A NOR circuit for inputting the original signal from the original signal oscillation circuit to the second transistor;
An electric field communication device comprising: