JP2006340133A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can start outputting of a clock signal quickly without starting a frequency division fault in a frequency dividing circuit when an output shut down is canceled by an output control signal. <P>SOLUTION: This semiconductor integrated circuit includes an oscillation circuit 10 which performs an oscillation performance and forms an oscillation signal by connecting a vibrator, a frequency dividing circuit 30 which frequency divides the oscillation signal generated by the oscillation circuit, an output circuit 40 which outputs the oscillation signal frequency divided by the frequency dividing circuit as a buffer, and a logic circuit 70 which stops the signal output from the output circuit if needed by activating or deactivating the output circuit according to at least an output control signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit incorporating an oscillation circuit that performs an oscillation operation using a vibrator such as a crystal vibrator, a frequency divider circuit that divides an oscillation signal, and the like.

  In order to supply a clock signal to the CPU in a personal computer, printer, mobile phone, etc., an oscillation circuit that performs an oscillation operation, a frequency dividing circuit that divides the oscillation signal, or a frequency-divided oscillation signal is output as a clock signal. A semiconductor integrated circuit incorporating an output circuit or the like is used. In such a semiconductor integrated circuit, by providing a switch means such as a NAND circuit at the subsequent stage of the oscillation circuit, the supply of the oscillation signal to the frequency divider circuit is stopped according to the output control signal, and the output of the clock signal is stopped. It was.

  However, since the divider circuit holds the previous data due to the stray capacitance, if the supply of the oscillation signal to the divider circuit is stopped, it is included in the oscillation signal when the output stop is canceled by the output control signal. A poor frequency division may occur for the first few pulses. Also, when the output stop is released, the oscillation signal output from the oscillation circuit propagates to the clock signal output terminal via the frequency divider and output circuit, so there is a delay until the clock signal is output. When a frequency division failure occurs, it takes time for the clock signal to stabilize.

As a related technique, the following Patent Document 1 discloses a semiconductor integrated circuit that eliminates the disadvantage that power line noise generated by the operation of an output buffer obstructs the start of oscillation in an oscillation unit. In this semiconductor integrated circuit, it is possible to accurately determine whether the oscillation is in a stable state or an unstable state by using two inverters having different logic levels at the input part of the oscillation start detection circuit. By using such an oscillation start detection circuit, in the initial state where oscillation is not stable, the operation of the frequency divider and output buffer is stopped, and after it is determined that the oscillation is stable, the frequency divider and output Operate the buffer unit. However, if the operation of the frequency dividing unit is stopped in the initial state, it takes time until the frequency dividing operation is stabilized after the frequency dividing unit starts operating after it is determined that the oscillation is stable.
Japanese Patent Application Laid-Open No. 5-48441 (Pages 1, 2 and 1)

  Therefore, in view of the above points, the present invention provides a semiconductor integrated circuit capable of quickly starting output of a clock signal without causing a frequency division failure in a frequency divider circuit when output stop is canceled by an output control signal. The purpose is to provide.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention oscillates when a vibrator is connected to generate an oscillation signal, and divides the oscillation signal generated by the oscillation circuit. A frequency divider circuit, an output circuit that buffers and outputs the oscillation signal divided by the frequency divider circuit, and activates or deactivates the output circuit in accordance with at least the output control signal, thereby enabling the output circuit to And a logic circuit for stopping the signal output.

  The semiconductor integrated circuit includes a voltage detection circuit that detects a rise of the power supply voltage, a power-on reset circuit that activates the second control signal when the voltage detection circuit detects the rise of the power supply voltage, and an oscillation circuit. A second logic circuit that inputs the generated oscillation signal and outputs the oscillation signal to the frequency divider circuit when the second control signal is activated may be further provided.

  In that case, the logic circuit may stop signal output from the output circuit by deactivating the output circuit when the output control signal or the second control signal is deactivated. good. Specifically, the logic circuit may include an AND circuit that obtains a logical product of the output control signal and the second control signal and activates or deactivates the output circuit based on the result.

  According to the present invention, when the output stop is released by the output control signal, the output circuit is activated or deactivated according to at least the output control signal and the signal output from the output circuit is stopped as necessary. The output of the clock signal can be started quickly without causing a frequency division failure in the frequency divider circuit.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. As shown in FIG. 1, this semiconductor integrated circuit receives an oscillation circuit 10 that generates an oscillation signal by performing an oscillation operation by connecting an oscillator, and an oscillation signal generated by the oscillation circuit 10. A logic circuit (using a NAND circuit in this embodiment) 20 that outputs an oscillation signal when the on-control signal DOUT is activated, and an oscillation signal supplied from the oscillation circuit 10 via the NAND circuit 20 A frequency dividing circuit 30 that divides the frequency of the signal and an output buffer 40 that buffers the oscillation signal divided by the frequency dividing circuit 30 and outputs it as a clock signal are incorporated.

In addition, the semiconductor integrated circuit includes a voltage detection circuit 50 that detects the rising of the power supply voltage between the power supply potential V _DD and the power supply potential V _SS (in this embodiment, the ground potential), and the voltage detection circuit 50 includes A power-on reset circuit 60 that activates the power-on control signal DOUT when the rising of the power supply voltage is detected, and a clock signal as necessary by activating or deactivating the output buffer 40 according to the output control signal OE And a logic circuit 70 (in this embodiment, an AND circuit is used) for stopping the output of the. The oscillation circuit 10, the frequency dividing circuit 30, and the voltage detection circuit 50 can be controlled by a test mode setting signal TEST that sets a test mode for measuring a quiescent current.

  FIG. 2 is a circuit diagram showing a configuration of an oscillation circuit built in the semiconductor integrated circuit shown in FIG. In the present embodiment, a crystal resonator XL is used as the resonator. In addition to the crystal resonator, a resonator such as a ceramic resonator or a SAW (Surface Acoustic Wave) resonator may be used.

The oscillation circuit 10 inverts the signal applied from the first terminal of the crystal resonator XL to the resonator input terminal _PIN , and outputs the inverted signal from the resonator output terminal P _OUT to the first crystal resonator XL. an inverter 11 for supplying a second terminal, the series resistor Rd connected between the output and the oscillator output terminal P _OUT of the inverter 11, and an input terminal P _iN output terminal P _OUT and vibrator vibrator a capacitor connected between the feedback resistor Rf connected, a capacitor Cg connected between the input terminal P _iN and the ground potential vibrators, and the output terminal P _OUT and the ground potential for transducer between Cd. Signal output from the output terminal P _OUT for transducer is fed back to a predetermined given the phase rotation vibrator input terminal P _IN by a crystal oscillator XL, etc., thereby oscillating operation is performed. One or more of the series resistor Rd, the feedback resistor Rf, the capacitor Cg, and the capacitor Cd may be external components of the semiconductor integrated circuit.

  FIG. 3 is a circuit diagram showing a configuration of a frequency dividing circuit built in the semiconductor integrated circuit shown in FIG. In the present embodiment, a flip-flop is used as the frequency dividing circuit 30. Frequency dividing circuit 30 is formed of P channel MOS transistors QP31 to QP38 and N channel MOS transistors QN31 to QN39.

  As shown in FIG. 3, the frequency dividing circuit 30 holds the data applied to the data input terminal D in synchronization with the rising edge of the oscillation signal applied to the clock signal input terminal C and holds the held data. Inverted data having the opposite phase to the inverted data output terminal Q is output from the inverted data output terminal Q, and data having the same phase as the stored data is output from the data output terminal Q. The inverted data output from the inverted data output terminal Q bar is fed back to the data input terminal D, whereby the oscillation signal is divided by 2, and the obtained divided signal is output from the data output terminal Q.

  FIG. 4 is a circuit diagram showing a configuration of an output buffer built in the semiconductor integrated circuit shown in FIG. Output buffer 40 includes P channel MOS transistors QP41 to QP56 and N channel MOS transistors QN41 to QN56.

  In FIG. 4, transistors QP41 and QN41 constitute a first inverter that inverts the frequency-divided signal input to the signal input terminal IN, and the transistors QP42 and QN42 output control input to the control input terminal CONT. A second inverter that inverts the signal OED is configured, and the transistors QP43 and QN43 configure a third inverter that further inverts the inverted output control signal output from the second inverter.

  Further, a fourth inverter constituted by transistors QP44 and QN44 and a transistor QN45 for activating or deactivating the fourth inverter according to the output control signal are connected in series. Transistors QP46 and QN46 constitute a fifth inverter that inverts the output signal of the fourth inverter. A transistor QP45 is provided to fix the gates of the transistors QP46 and QN46 to a high level according to the output control signal. Transistors QP47 to QP49 and QN47 to QN49 constitute sixth to eighth inverters, respectively.

  Similarly, a ninth inverter constituted by transistors QP50 and QN50 and a transistor QP51 for activating or deactivating the ninth inverter according to the output control signal are connected in series. Transistors QP52 and QN52 constitute a tenth inverter that inverts the output signal of the ninth inverter. A transistor QN51 is provided to fix the gates of the transistors QP52 and QN52 to a low level in accordance with the output control signal. Transistors QP53 to QP55 and QN53 to QN55 constitute the 11th to 13th inverters, respectively.

  When the output control signal is at a high level, the transistor QN45 is turned on and the transistor QP45 is turned off, so that the output signal of the fourth inverter is input to the gates of the transistors QP46 and QN46 constituting the fifth inverter. The output signal of the fifth inverter is supplied to the gate of the transistor QP56 via the sixth to eighth inverters. Since the transistor QP51 is turned on and the transistor QN51 is turned off, the output signal of the ninth inverter is input to the gates of the transistors QP52 and QN52 constituting the tenth inverter, and the output signal of the tenth inverter. Is supplied to the gate of the transistor QN56 through the 11th to 13th inverters. Therefore, the buffered frequency-divided signal is output from the drains of the transistors QP56 and QN56 to the output terminal OUT.

  On the other hand, when the output control signal becomes low level, the transistor QN45 is turned off and the transistor QP45 is turned on, so that the fourth inverter is deactivated and the transistors QP46 and QN46 constituting the fifth inverter are turned on. The gate is fixed at a high level. Further, since the transistor QP51 is turned off and the transistor QN51 is turned on, the ninth inverter is deactivated and the gates of the transistors QP52 and QN52 constituting the tenth inverter are fixed at a low level. Accordingly, the gate of the transistor QP56 is fixed at a high level, the gate of the transistor QN56 is fixed at a low level, and these transistors are cut off, so that the output terminal OUT is in a high impedance state.

  Referring to FIG. 1 again, conventionally, when the output control signal OE becomes low level, one input of the NAND circuit 20 is set to low level to stop the supply of the oscillation signal to the frequency dividing circuit 30. It was. However, since the frequency dividing circuit 30 holds data by stray capacitance (or parasitic capacitance), if the supply of the oscillation signal to the frequency dividing circuit 30 is stopped, the output control signal OE is shown in FIG. When the signal becomes high level again and the oscillation signal is supplied to the frequency dividing circuit 30, a frequency division failure may occur for the first few pulses included in the oscillation signal.

  Further, when the output control signal OE becomes high level again, the oscillation signal output from the oscillation circuit 10 is divided by the frequency dividing circuit 30, and the divided signal is output to the clock signal via the output buffer 40. Since the signal propagates to the terminal, there is a delay until the clock signal is output, and it takes time for the clock signal to stabilize when a frequency division failure occurs.

  Therefore, in the present embodiment, even when the output stop mode is set by the output control signal OE, only the output buffer 40 is deactivated without stopping the supply of the oscillation signal to the frequency divider circuit 30. Yes. The operation of the semiconductor integrated circuit according to this embodiment will be described below.

  When the voltage detection circuit 50 detects the rise of the power supply voltage, the power-on reset circuit 60 activates the power-on control signal DOUT to a high level, so that the NAND circuit 20 separates the oscillation signal generated by the oscillation circuit 10. This is supplied to the peripheral circuit 30. The frequency divider circuit 30 divides the supplied oscillation signal to generate a frequency-divided signal and supplies it to the output buffer 40.

  The AND circuit 70 obtains a logical product of the power-on control signal DOUT and the output control signal OE, and outputs the result as the output control signal OED. Therefore, when both the power-on control signal DOUT and the output control signal OE are at a high level, the output control signal OED is at a high level. When the output control signal OED becomes high level, the output buffer 40 buffers the divided signal and outputs it as a clock signal.

  On the other hand, when the output control signal OE becomes low level, the output control signal OED also becomes low level. When the output control signal OED becomes low level, the output buffer 40 enters a high impedance state, and the output of the clock signal is stopped. However, since the oscillation circuit 10 and the frequency dividing circuit 30 are operating even in this state, when the output control signal OE becomes high level again as shown in FIG. 6, the frequency dividing circuit 30 performs frequency division. The output buffer 40 can quickly output a clock signal without causing a failure.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of an oscillation circuit built in the semiconductor integrated circuit shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a frequency divider circuit built in the semiconductor integrated circuit shown in FIG. 1. FIG. 2 is a circuit diagram showing an output buffer built in the semiconductor integrated circuit shown in FIG. 1. 9 is a timing chart showing an operation in a conventional semiconductor integrated circuit. 2 is a timing chart showing an operation in the semiconductor integrated circuit shown in FIG.

Explanation of symbols

  10 oscillator circuit, 11 inverter, 20 logic circuit (NAND circuit), 30 frequency divider circuit, 40 output buffer, 50 voltage detection circuit, 60 power-on reset circuit, 70 logic circuit (AND circuit), XL crystal resonator, Rd series Resistor, Rf feedback resistor, Cg, Cd capacitor, QP31-QP38, QP41-QP56 P channel MOS transistor, QN31-QN39, QN41-QN56 N channel MOS transistor

Claims (4)

An oscillation circuit that generates an oscillation signal by performing an oscillation operation by connecting a vibrator;
A frequency dividing circuit for frequency-dividing the oscillation signal generated by the oscillation circuit;
An output circuit for buffering and outputting the oscillation signal divided by the divider circuit;
A logic circuit for activating or deactivating the output circuit according to at least an output control signal to stop signal output from the output circuit as necessary;
A semiconductor integrated circuit comprising: A voltage detection circuit for detecting the rise of the power supply voltage;
A power-on reset circuit that activates a second control signal when the voltage detection circuit detects a rising edge of a power supply voltage;
A second logic circuit that inputs an oscillation signal generated by the oscillation circuit and outputs an oscillation signal to the frequency divider circuit when a second control signal is activated;
The semiconductor integrated circuit according to claim 1, further comprising:   3. The logic circuit stops signal output from the output circuit by deactivating the output circuit when the output control signal or the second control signal is deactivated. Semiconductor integrated circuit.   4. The semiconductor integrated circuit according to claim 3, wherein the logic circuit includes an AND circuit that obtains a logical product of the output control signal and the second control signal and activates or deactivates the output circuit based on the result. .

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