JP4430126B2 - Thin film transistor substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a thin film transistor (TFT) substrate and a manufacturing method thereof, and more particularly to a TFT substrate used for a liquid crystal panel of a liquid crystal display device and a manufacturing method thereof.

  In general, a liquid crystal panel mounted on a liquid crystal display device uses a TFT substrate in which a pixel electrode and a TFT for driving the pixel electrode are formed on a transparent insulating substrate such as a glass substrate. Similarly, a liquid crystal layer is sandwiched between a counter substrate in which a common electrode, a color filter (CF), and the like are formed on a glass substrate or the like, thereby forming a liquid crystal panel. Various types of TFT substrates, such as an active matrix type, have been proposed so far for TFT substrates used in such liquid crystal panels.

  6 is a schematic plan view of an essential part of an example of a conventional TFT substrate, FIG. 7 is a schematic cross-sectional view taken along the line CC in FIG. 6, and FIG. 8 is a schematic cross-sectional view taken along the line DD in FIG.

  The TFT substrate shown in FIGS. 6 to 8 is an active matrix type, and only one of the TFTs arranged in a matrix is shown. In FIG. 6, among the components of the TFT substrate, the insulating substrate, the insulating film layer, the active layer, the etching stopper layer, and the protective film layer are not shown for convenience.

  In the case of an active matrix TFT substrate, a plurality of gate bus lines (scan bus lines) 101 and drain bus lines (signal application lines) 102 are formed on the insulating substrate 100 so as to be orthogonal to each other. The TFT 103 is disposed on the substrate.

  The TFT 103 has a gate electrode 101 a formed of the same material as the gate bus line 101 on the insulating substrate 100, and an operation layer 105 is formed on the gate electrode 101 a via an insulating film layer 104. A drain electrode 102 a and a source electrode 102 b are formed of the same material as the active layer 106 and the drain bus line 102. Note that the operation layer 105 functions as a channel of the TFT 103, and the etching stopper layer 107 formed thereon serves to protect the operation layer 105 during the etching for forming the active layer 106.

  A protective film layer 108 is formed on almost the entire surface of such a transistor structure, and a pixel electrode 109 made of a transparent conductive film is connected to the source electrode 102b through a contact hole 108a provided there. ing.

  Here, a TFT substrate having a configuration in which the formation region of the gate electrode and the pixel electrode does not overlap, that is, the pixel electrode is not disposed immediately above the gate electrode has been illustrated. There has also been proposed a TFT substrate or the like in which the formation regions are stacked with an insulating film layer interposed therebetween.

  Furthermore, conventionally, when the formation region of the gate electrode and the pixel electrode overlaps with the insulating film layer interposed therebetween, the gate electrode is provided on the insulating substrate for the purpose of reducing the parasitic capacitance generated there. There has also been a proposal of extending the distance from the gate electrode to the pixel electrode by forming it in the groove (see Patent Document 1).

JP 2001-83550 A

  However, the parasitic capacitance generated between the electrodes in the TFT substrate is not limited to between the gate electrode and the pixel electrode as described above, but is similarly generated between the other electrodes in the TFT substrate depending on the configuration of the TFT substrate. obtain.

  For example, in the case of the TFT substrate configured as shown in FIGS. 6 to 8, the source electrode 102b is disposed immediately above the gate electrode 101a although the formation regions of the gate electrode 101a and the pixel electrode 109 do not overlap each other. As a result, a parasitic capacitance Cgs is generated there. The value of the parasitic capacitance Cgs is proportional to the size of the overlapping area between the gate electrode 101a and the source electrode 102b and inversely proportional to the distance between the gate electrode 101a and the source electrode 102b.

  The parasitic capacitance Cgs is largely related to a phenomenon in which the data voltage held in the pixel is lowered by the fall of the gate scan pulse, so-called feedthrough. The feedthrough voltage V can be expressed as V = (Cgs / (Cgs + Cs + Clc)) × ΔVg, where Cs is a holding capacitor, Clc is a liquid crystal capacitor, and ΔVg is a gate pulse amplitude voltage. Thus, the feedthrough voltage V increases as the parasitic capacitance Cgs increases.

  By the way, the plurality of TFTs arranged in a matrix on the TFT substrate are formed as a repeated pattern on the insulating substrate using a photolithography technique in manufacturing. However, in the photolithography process, exposure light is shot in a predetermined area so that adjacent pixel patterns are connected at the time of exposure, that is, no extra space is formed between the pixels. For this reason, when a deviation occurs in the exposure pattern, a display unevenness called a so-called shot unevenness eventually occurs.

  Further, when such an exposure pattern misalignment occurs during the formation of a TFT substrate configured such that the gate electrode 101a and the source electrode 102b overlap with the insulating film layer 104 interposed therebetween as shown in FIGS. In some cases, a difference occurs in the parasitic capacitance Cgs depending on the pixel. In this case, display unevenness is more likely to appear, which is a cause of lowering the display quality of the liquid crystal panel.

  In recent years, liquid crystal panels have been increased in size and definition. However, along with this, there is a possibility that the falling of the gate scan pulse becomes dull due to the circuit delay of the gate bus line, the feedthrough voltage V is distributed, and the luminance unevenness occurs in the liquid crystal panel surface. Therefore, when a TFT substrate having a configuration in which the gate electrode 101a and the source electrode 102b overlap with the insulating film layer 104 interposed therebetween as shown in FIGS. 6 to 8 is used, if the parasitic capacitance Cgs is reduced, the feed It is also possible to suppress the distribution by reducing the through voltage V.

  As described above, the parasitic capacitance Cgs generated between the gate electrode and the source electrode in the TFT substrate has a considerable influence on the display characteristics when the TFT substrate is used in a liquid crystal panel. The same applies to the TFT substrate having a configuration in which the source and the drain are interchanged with the TFT substrate exemplified here.

  The present invention has been made in view of such a point, and an object thereof is to provide a TFT substrate capable of obtaining high display quality and a method for manufacturing the same.

  In the present invention, in order to solve the above-described problem, in a TFT substrate in which a TFT having a drain electrode disposed immediately above a gate electrode is formed on an insulating substrate, an insulating substrate in which a recess is formed, and the insulating substrate A gate electrode formed in a region including the concave portion, an insulating film layer formed on the insulating substrate so as to fill the concave portion in which the gate electrode is formed, and the insulating film layer embedded in the insulating film layer There is provided a TFT substrate having a drain electrode formed in a region including a region immediately above the recess.

  According to such a TFT substrate, a concave portion is formed in the insulating substrate, a TFT gate electrode is formed in a region including the concave portion, and the concave portion in which the gate electrode is formed is embedded in the insulating film layer. A drain electrode is formed in a region including a region immediately above the recess. As a result, the distance between the gate electrode and the drain electrode sandwiching the insulating film layer is widened compared to the case where the concave portion is not provided in the insulating substrate, so that the parasitic capacitance therebetween can be suppressed to be small.

  According to the present invention, in a method for manufacturing a TFT substrate in which a TFT having a drain electrode disposed immediately above a gate electrode is formed on an insulating substrate, a step of forming a recess in the insulating substrate; Forming a gate electrode in a region including a recess, forming an insulating film layer on the insulating substrate so as to fill the recess in which the gate electrode is formed, and filling the insulating film layer with the insulating film layer And a step of forming a drain electrode in a region including a region directly above the recess. A method for manufacturing a TFT substrate is provided.

  According to such a method for manufacturing a TFT substrate, a recess is formed in an insulating substrate, a TFT gate electrode is formed in a region including the recess, and the recess in which the gate electrode is formed is embedded with an insulating film layer, A drain electrode is formed in a region including the region immediately above the recess. Thereby, a TFT substrate in which the parasitic capacitance between the gate electrode and the drain electrode is suppressed to be small is formed.

  In the present invention, a TFT gate electrode is formed in a region including a recess formed in an insulating substrate, an insulating film layer is formed thereon, and a drain electrode is disposed immediately above the recess. It was configured as follows. As a result, the parasitic capacitance between the gate electrode and the drain electrode formed with the insulating film layer interposed therebetween can be suppressed to be smaller than that in the case where the concave portion is not provided in the insulating substrate.

  Therefore, even when the exposure pattern of each pixel region is shifted during the formation of the TFT substrate, the difference in parasitic capacitance between the pixels can be suppressed, and the degree of shot unevenness can be reduced. It becomes possible.

  Furthermore, since the feedthrough voltage can be reduced by keeping the parasitic capacitance between the gate electrode and the drain electrode small, it is caused by the circuit delay of the gate bus line even in a large and high-definition liquid crystal panel. It is possible to suppress the generation of the feedthrough voltage distribution and make the luminance distribution in the liquid crystal panel surface inconspicuous.

It is a principal part schematic diagram of an example of a TFT substrate. It is an AA cross-sectional schematic diagram of FIG. It is a BB cross-sectional schematic diagram of FIG. It is a principal part perspective schematic diagram of the formation process of a gate electrode. It is a principal part cross-sectional schematic diagram of the formation process of an insulating film layer. It is a principal part plane schematic diagram of an example of the conventional TFT substrate. It is CC sectional schematic diagram of FIG. FIG. 7 is a DD cross-sectional schematic diagram of FIG. 6.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Here, a reference example to which the present invention is referred will be described first.

[Reference example]
1 is a schematic plan view of an essential part of an example of a TFT substrate, FIG. 2 is a schematic cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a schematic cross-sectional view taken along line BB in FIG.

  The TFT substrate shown in FIGS. 1 to 3 is an active matrix type, and only one of the TFTs arranged in a matrix, that is, only one pixel is illustrated. In FIG. 1, among the components of the TFT substrate, the insulating substrate, the insulating film layer, the active layer, the etching stopper layer, and the protective film layer are not shown for convenience.

  The TFT substrate shown in FIGS. 1 to 3 has a gate bus line 2 and a drain bus line 3 orthogonal to each other on a transparent insulating substrate 1 such as a glass substrate using a metal such as aluminum (Al) or molybdenum (Mo). The TFT 4 for driving the pixel electrode 10 to be described later is disposed at each of the intersections.

  The insulating substrate 1 has a recess 1a having a predetermined dimension in a region where the TFT 4 is formed, and a gate electrode 2a is formed on the insulating substrate 1 using the same material as the gate bus line 2. Has been. The gate bus line 2 is formed outside the recess 1a on the insulating substrate 1, while the gate electrode 2a is formed continuously from the gate bus line 2 to the recess 1a.

  On the insulating substrate 1 on which the gate bus line 2 and the gate electrode 2a are formed, an insulating film layer 5 is formed on the entire surface using a silicon nitride (SiN) film or the like, and functions as a channel of the TFT 4 thereon. The operating layer 6 is formed using amorphous silicon (a-Si) or the like.

  Further, an active layer 7 is formed on the operation layer 6 using a-Si doped with a predetermined impurity, and the same material as the drain bus line 3 is used on the active layer 7. A drain electrode 3a and a source electrode 3b are formed. Among these, the drain electrode 3 a is formed continuously with the drain bus line 3.

  The etching stopper layer 8 formed on the operation layer 6 is formed using a SiN film or the like, and will be described later when there is no etching selectivity between the operation layer 6 and the active layer 7. As described above, the channel region of the operation layer 6 is protected during the etching for forming the active layer 7 under the drain electrode 3a and the source electrode 3b.

  On such a transistor structure, a protective film layer 9 is formed almost entirely using a SiN film or the like, and transparent, such as ITO (Indium Tin Oxide), through a contact hole 9a provided there. The pixel electrode 10 made of a conductive film is formed in a state of being connected to the source electrode 3b.

  Such a structure is arranged in a matrix on the insulating substrate 1 to constitute a TFT substrate. The TFT substrate having the above configuration can be formed by the following procedure, for example. A method for forming a TFT substrate will be described with reference to FIGS. 1 to 3 and FIGS. 4 and 5 are explanatory views of a method for forming a TFT substrate. FIG. 4 is a schematic perspective view of the main part of the gate electrode forming process, and FIG. 5 is a schematic cross-sectional view of the main part of the insulating film layer forming process. FIG.

  When the TFT substrate is formed, first, as shown in FIG. 4, for each pixel region, a predetermined region is formed in a region directly below the source electrode 3b to be formed later in the region on the insulating substrate 1 on which the TFT 4 is formed. A recess 1a having a size is formed. After that, a metal layer such as Al or Mo is formed with a film thickness of about 150 nm to 200 nm on the entire surface including all the pixel areas, and each pixel area is exposed using a photolithography technique, and each pixel area is gated. The bus line 2 and the gate electrode 2a are formed simultaneously.

  The recess 1a formed in the insulating substrate 1 is a region other than the recess 1a of the insulating film layer 5 formed on the gate bus line 2 and the gate electrode 2a by using a plasma CVD (Chemical Vapor Deposition) method or the like. The film is formed with a depth greater than or equal to the film thickness. By forming the recess 1a at such a depth, the thickness of the insulating film layer 5 existing between the gate electrode 2a and the source electrode 3b is secured, and the parasitic capacitance Cgs is compared with the case where the recess 1a is not provided. Can be made sufficiently small.

  Further, the recess 1a is formed with a width equal to or greater than the film thickness in a region other than the recess 1a of the insulating film layer 5. By forming the recess 1a with such a width, when the insulating film layer 5 is formed on the gate bus line 2 and the gate electrode 2a using the plasma CVD method or the like, the insulating film is formed in the recess 1a. It is possible to reliably fill the layer 5 and prevent the formation of unnecessary voids in the recess 1 a filled with the insulating film layer 5. As a result, it is possible to prevent variation in capacitance due to the gap between the gate electrode 2a and the source electrode 3b, and to form the TFTs 4 uniformly on the insulating substrate 1.

  Furthermore, as shown in FIG. 4, the recess 1a is formed so that its cross section has a forward tapered shape from the surface of the insulating substrate 1 toward the inside. At that time, the taper angle θ of the side wall of the recess 1a is preferably in a range from vertical to 45 °. By forming the recess 1a in such a shape, it is possible to prevent the formation of a gap in the recess 1a when the insulating film layer 5 is formed, and to make the TFT 4 uniform. If the cross section of the recess 1a has an inversely tapered shape, there is a high possibility that a void is formed when the insulating film layer 5 is formed, and it becomes difficult to form a uniform TFT 4. Further, when the taper angle is larger than 45 °, the formation area of the TFT 4 becomes larger than necessary.

  After the formation of the recess 1a, the gate bus line 2 and the gate electrode 2a, the insulating film layer 5 is formed of an insulating film such as SiN over the entire surface including all the pixel regions so as to cover the surfaces thereof. When the insulating film layer 5 is formed, the plasma CVD method or the like is used as described above, and as shown in FIG. 5, an insulating film is first deposited with a film thickness of about 400 nm, and then an insulating film is further formed thereon. Deposited with a thickness of about 400 nm. This deposition process is repeated to sequentially stack insulating films, and finally an insulating film layer 5 having a predetermined thickness is formed.

  In addition to the recess 1a having the dimensions or shape as described above, the insulating film layer 5 is formed by such a method, so that the recess 1a can be formed in comparison with the case where an insulating film is deposited to a predetermined thickness at a stretch. An insulating film is deposited without any gap on the bottom surface, side wall, or the surface of the gate electrode 2a formed in the recess 1a, and the variation of the parasitic capacitance Cgs between the pixels can be suppressed and the TFT 4 can be made more uniform. Become.

  After the formation of the insulating film layer 5, a-Si or the like is formed on the entire surface including all the pixel regions, each pixel region is exposed using a photolithography technique, and the operation layer 6 is formed in each pixel region. Form. Thereafter, an insulating film such as a SiN film is formed on the entire surface, and an etching stopper layer 8 is formed in each pixel region by using a photolithography technique.

  Next, an impurity-doped layer such as a-Si and a metal layer such as Al are sequentially stacked on the entire surface including all the pixel regions, and each pixel region is exposed using a photolithography technique. Thereby, the active layer 7 is formed in each pixel region, and the drain bus line 3, the drain electrode 3a, and the source electrode 3b are simultaneously formed.

  Finally, a protective film layer 9 is formed over the entire pixel region, contact holes 9a are formed in each pixel region, a transparent conductive film such as ITO is formed over the entire surface, and the photolithography technique is used. Each pixel region is exposed to form a pixel electrode 10 connected to the source electrode 3b of the TFT 4 via the contact hole 9a.

  As described above, in the TFT substrate having the above-described configuration, the gate electrode 2a is formed in the region including the recess 1a provided in the insulating substrate 1 for each TFT 4 arranged in a matrix on the insulating substrate 1, thereby insulating the TFT substrate. The source electrode 3b is formed immediately above the recess 1a embedded with the film layer 5. Therefore, as compared with the case where such a recess 1a is not provided (see FIGS. 6 to 8), the interval between the gate electrode 2a and the source electrode 3b facing it can be increased, and the parasitic capacitance Cgs is reduced. It becomes possible to do.

  By reducing the parasitic capacitance Cgs generated in the TFT substrate in this way, the difference in the parasitic capacitance Cgs between the pixels is small even when the exposure pattern in each pixel region is displaced when forming the TFT substrate. Therefore, the degree of shot unevenness can be reduced.

  Furthermore, the feedthrough voltage V can be reduced by reducing the parasitic capacitance Cgs generated in the TFT substrate. Therefore, when the TFT substrate having the above configuration is applied to, for example, a large and high-definition liquid crystal panel, it is possible to suppress the distribution of the feedthrough voltage V caused by the scan pulse dullness caused by the circuit delay of the gate bus line 2. It becomes possible. As a result, the luminance distribution in the liquid crystal panel surface can be made inconspicuous.

  In the above description of the reference example, the TFT in which the gate electrode and the source electrode are arranged so as to overlap each other with the insulating film layer interposed therebetween is described. However, the present invention has a configuration in which the source and the drain are interchanged, that is, The present invention relates to a TFT substrate having TFTs arranged so that drain electrodes overlap with an insulating film layer interposed therebetween.

  By using the TFT substrate as described above for the liquid crystal panel, the display quality can be improved. Further, by using such a liquid crystal panel, a liquid crystal display device with high display quality can be realized.

  The thin film transistor substrate and the manufacturing method thereof of the present invention can be used for a liquid crystal panel of a liquid crystal display device and a manufacturing method of the liquid crystal panel.

(Supplementary note 1) In a TFT substrate in which a TFT is formed on a substrate,
An insulating substrate having a recess formed thereon;
A gate electrode formed in a region including the recess on the insulating substrate;
An insulating film layer formed on the insulating substrate so as to embed the recess in which the gate electrode is formed;
Source / drain electrodes formed in a region including a region immediately above the recess embedded in the insulating film layer;
A TFT substrate characterized by comprising:

  (Supplementary note 2) The TFT substrate according to supplementary note 1, wherein the recess has a depth equal to or greater than a film thickness of the insulating film layer formed on a region other than the recess of the insulating substrate.

  (Additional remark 3) The said recessed part is the TFT substrate of Additional remark 1 characterized by being more than the film thickness of the said insulating film layer formed on the area | regions other than the said recessed part of the said insulating substrate.

  (Supplementary note 4) The TFT substrate according to Supplementary note 1, wherein the recess has a forward tapered shape in cross section from the surface of the insulating substrate toward the inside.

  (Supplementary Note 5) The TFT substrate according to Supplementary Note 4, wherein the concave portion has a side wall taper angle in a range from vertical to 45 °.

(Supplementary Note 6) In the manufacturing method of the TFT substrate in which the TFT is formed on the substrate,
Forming a recess in the insulating substrate;
Forming a gate electrode in a region including the recess on the insulating substrate;
Forming an insulating film layer on the insulating substrate so as to embed the recess in which the gate electrode is formed;
Forming source / drain electrodes in a region including a region immediately above the recess embedded in the insulating film layer;
A method for manufacturing a TFT substrate, comprising:

(Supplementary Note 7) In the step of forming the concave portion in the insulating substrate,
The manufacturing method of a TFT substrate according to appendix 6, wherein the recess is formed so that a depth is equal to or greater than a film thickness of the insulating film layer formed on a region other than the recess of the insulating substrate. .

(Supplementary Note 8) In the step of forming the concave portion in the insulating substrate,
The method for manufacturing a TFT substrate according to appendix 6, wherein the recess is formed so that a width is equal to or greater than a film thickness of the insulating film layer formed on a region other than the recess of the insulating substrate.

(Supplementary Note 9) In the step of forming the concave portion in the insulating substrate,
The manufacturing method of a TFT substrate according to appendix 6, wherein the recess is formed so that a cross section has a forward tapered shape from the surface of the insulating substrate toward the inside.

(Supplementary Note 10) When the recess is formed so that the cross section has a forward tapered shape from the surface of the insulating substrate toward the inside,
The method for manufacturing a TFT substrate according to appendix 9, wherein the recess is formed so that the taper angle of the side wall is in a range from vertical to 45 °.

(Supplementary Note 11) In a liquid crystal panel using a TFT substrate,
The TFT substrate includes an insulating substrate in which a recess is formed, a gate electrode formed in a region including the recess on the insulating substrate, and the recess in which the gate electrode is formed on the insulating substrate. A liquid crystal panel comprising: an insulating film layer formed so as to be embedded; and source / drain electrodes formed in a region including a region immediately above the concave portion embedded in the insulating film layer.

(Supplementary Note 12) In a liquid crystal display device using a TFT substrate,
The TFT substrate includes an insulating substrate in which a recess is formed, a gate electrode formed in a region including the recess on the insulating substrate, and the recess in which the gate electrode is formed on the insulating substrate. A liquid crystal display device comprising: an insulating film layer formed so as to be embedded; and a source / drain electrode formed in a region including a region immediately above the recess embedded in the insulating film layer.

DESCRIPTION OF SYMBOLS 1 Insulating substrate 1a Recess 2 Gate bus line 2a Gate electrode 3 Drain bus line 3a Drain electrode 3b Source electrode 4 TFT
5 Insulating film layer 6 Operating layer 7 Active layer 8 Etching stopper layer 9 Protective film layer 9a Contact hole 10 Pixel electrode

Claims (5)

In the thin film transistor substrate in which the thin film transistor in which the drain electrode is disposed immediately above the gate electrode is formed on the insulating substrate,
An insulating substrate having a recess formed thereon;
A gate electrode formed in a region including the recess on the insulating substrate;
An insulating film layer formed on the insulating substrate so as to embed the recess in which the gate electrode is formed;
A drain electrode formed in a region including a region immediately above the recess embedded in the insulating film layer;
A thin film transistor substrate comprising:   2. The thin film transistor substrate according to claim 1, wherein the recess has a depth equal to or greater than a thickness of the insulating film layer formed on a region other than the recess of the insulating substrate.   The thin film transistor substrate according to claim 1, wherein the recess has a width equal to or greater than a film thickness of the insulating film layer formed on a region other than the recess of the insulating substrate.   2. The thin film transistor substrate according to claim 1, wherein the recess has a forward tapered shape in cross section from the surface of the insulating substrate toward the inside. In the method of manufacturing a thin film transistor substrate in which a thin film transistor in which a drain electrode is disposed immediately above a gate electrode is formed on an insulating substrate,
Forming a recess in the insulating substrate;
Forming a gate electrode in a region including the recess on the insulating substrate;
Forming an insulating film layer on the insulating substrate so as to embed the recess in which the gate electrode is formed;
Forming a drain electrode in a region including a region directly above the recess embedded in the insulating film layer;
A method for producing a thin film transistor substrate, comprising:

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