JP2010156867A - Thin film transistor substrate precursor and method for manufacturing thin film transistor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct a defect of a thin film transistor by suppressing degradation in the display quality of a liquid crystal display. <P>SOLUTION: A thin film transistor substrate precursor is provided with: a plurality of gate lines 11a in which a gate electrode is defined for each pixel and which extend parallel to one another; a first semiconductor layer 13a provided in the form of an island so as to be superposed on the gate electrode of each pixel via an insulation film; a second semiconductor layer 13b provided in the form of an island so as to be superposed on each gate line 11a for each pixel via the insulation film; a plurality of source lines 14a in which a source electrode 14aa is defined so as to be superposed on one end of the gate electrode for each pixel via the first semiconductor layer 13a and which extend parallel to one another in a direction intersecting each gate line 11a; and a plurality of drain lines 14b each of which is connected to each pixel electrode and in each of which a drain electrode 14ba is defined so as to be superposed on the other end of the gate electrode for each pixel via the first semiconductor layer 13a, and so as to be opposite the source electrode 14aa. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor substrate precursor and a method for manufacturing a thin film transistor substrate, and more particularly to a technique for correcting a defect in a thin film transistor constituting the thin film transistor substrate.

  An active matrix driving type liquid crystal display device includes, for example, a thin film transistor (hereinafter referred to as “TFT”) substrate and a color filter (hereinafter referred to as “CF”) disposed opposite to the TFT substrate. A substrate) and a liquid crystal layer provided between the TFT substrate and the CF substrate.

  The TFT substrate includes a TFT as a switching element for each pixel which is the minimum unit of an image. In this TFT substrate, there is a possibility that a malfunction of the TFT may occur due to particles adhering to the substrate surface during the manufacturing process. Therefore, a method for correcting the TFT substrate has been proposed.

For example, Patent Document 1 discloses a connection portion in which a first TFT has a cut portion that can be electrically separated from a pixel electrode, and a second TFT can be electrically connected to the pixel electrode in a source electrode path. The second TFT uses the parasitic capacitance of the connection portion, and the capacitance between the scanning line and the pixel electrode in a state where the first TFT is electrically connected to the pixel electrode, and the first TFT Disclosed is a liquid crystal display device that reduces the difference between the capacitance between the scanning line and the pixel electrode in a state where the TFT is electrically disconnected from the pixel electrode and instead the second TFT is electrically connected to the pixel electrode. ing. According to this, a redundant structure in which a plurality of TFTs are arranged per pixel is adopted, and the difference between the scanning line / pixel electrode capacitance between the normal pixel and the repaired pixel is reduced by the configuration of the source side electrode path. Therefore, it is described that the difference in display characteristics between the normal pixel and the pixel after repair can be reduced without complicating the configuration.
Japanese Patent Laid-Open No. 7-104311

  FIG. 10 is a plan view of a conventional TFT substrate 120 in which each pixel includes a pair of sub-pixels and each sub-pixel includes a TFT.

  As shown in FIG. 10, the TFT substrate 120 includes a plurality of gate lines 111a provided so as to extend in parallel with each other, and a plurality of capacitance lines 111b provided so as to extend in parallel with each other between the gate lines 111a. A gate insulating film (not shown) provided so as to cover each gate line 111a and each capacitor line 111b, and provided on the gate insulating film so as to extend in parallel to each other in a direction perpendicular to each gate line 111a. A plurality of source lines 114a, a plurality of first TFTs 105a and a plurality of second TFTs 105b provided in pairs at the intersections of the gate lines 111a and the source lines 114a, and the first TFTs 105a, the second TFTs 105b, and the source lines 114a. An interlayer insulating film (not shown) provided so as to cover, and provided in a matrix on the interlayer insulating film And a plurality of pixel electrodes 117.

  As shown in FIG. 10, the first TFT 105a and the second TFT 105b are connected to a common gate line 111a for each pixel. Here, as shown in FIG. 10, the pixel electrode 117 connected to the first TFT 105a constitutes the first subpixel Pa, and the pixel electrode 117 connected to the second TFT 105b constitutes the second subpixel Pb. Yes. The first sub pixel Pa and the second sub pixel Pb are adjacent to each other across the gate line 111a along the direction in which the source line 114a extends to form one pixel.

  Here, as shown in FIG. 10, in the first TFT 105a of the first sub-pixel Pa on the upper left side in the drawing, for example, the film residue R is interposed as a particle between the source electrode 114aa and the drain electrode 114b, thereby the source electrode When a short-circuit defect occurs between 114aa and the drain electrode 114b and the short-circuit defect is corrected, the drain electrode 114b is cut at the X portion by irradiating the X portion with laser light. According to this, since the charge corresponding to the source signal is not written in the pixel electrode 117 constituting the first sub pixel Pa on the upper left side in FIG. 10, in normally black, it is easily recognized as a bright spot in FIG. The first sub-pixel Pa on the upper left side becomes a black spot, and short circuit defects can be made difficult to be recognized.

  However, in this defect correction, there is room for improvement because one sub-pixel of the corrected pixel becomes a black point and the display quality is degraded.

  The present invention has been made in view of the above points, and an object of the present invention is to correct a defect in a thin film transistor by suppressing deterioration in display quality.

  In order to achieve the above object, according to the present invention, a second semiconductor layer is provided in addition to the first semiconductor layer constituting the thin film transistor.

  Specifically, a thin film transistor substrate precursor according to the present invention includes a plurality of pixels provided in a matrix, a plurality of thin film transistors provided for each pixel, and a plurality of pixel electrodes respectively connected to the thin film transistors. A gate electrode for each pixel, a plurality of gate lines provided to extend in parallel with each other, and an insulating film interposed between the gate electrode of each pixel. A first semiconductor layer provided in an island shape so as to overlap each other, a second semiconductor layer provided in an island shape so as to overlap each gate line via an insulating film for each pixel, and for each pixel A source electrode is defined so as to overlap one end of the gate electrode via the first semiconductor layer, and provided so as to extend parallel to each other in a direction intersecting the gate lines. A drain electrode is defined so as to overlap a plurality of source lines and the other end portion of the gate electrode via the first semiconductor layer for each pixel, and to face the source electrode. And a plurality of drain lines provided to be connected.

  According to the above configuration, since the second semiconductor layer is formed in addition to the first semiconductor layer constituting the thin film transistor, for example, in the defective pixel in which the defect is detected in the portion to become the thin film transistor, the drain line is cut. Thus, a thin film transistor substrate on which a pixel electrode and the like are formed by separately forming a source electrode and a drain electrode so that a portion to be a thin film transistor is disabled and the second semiconductor layer functions as a thin film transistor In the pixel electrode of the defective pixel in which the defect is detected, when the ON gate signal is sent to the corresponding gate line, the source line, the separately formed source electrode, the second semiconductor layer, and the separately formed gate signal are formed. A source signal is sent through the drain electrode. Thereby, since the defective pixel in which the defect is detected is corrected as a normal pixel, it is possible to correct the defect of the thin film transistor while suppressing the deterioration of the display quality.

  The second semiconductor layer may not be connected to the source lines and the drain lines.

  According to the above configuration, since the second semiconductor layer for defect correction is not connected to each source line and each drain line, when the defect is not corrected, the second semiconductor layer does not specifically operate. Become.

  Each of the thin film transistors may be a bottom gate type.

  According to said structure, the precursor of the thin-film transistor substrate provided with the bottom gate type thin-film transistor is specifically comprised.

  Each of the pixels may constitute a plurality of subpixels adjacent to each other along a direction in which each of the source lines extends, and each of the thin film transistors and each pixel electrode may be arranged for each of the subpixels. .

  In addition, each pixel constitutes a pair of sub-pixels for each of a plurality adjacent to each other along the extending direction of each gate line, and each thin-film transistor and each pixel electrode are arranged for each sub-pixel. May be.

  Further, each pixel constitutes a pair of subpixels adjacent to each other along the extending direction of each gate line and each source line, and each thin film transistor and each pixel electrode is provided for each subpixel. You may be comprised so that it may arrange.

  According to the above configuration, each pixel has a plurality of sub-pixels, and each thin-film transistor and each pixel electrode are arranged for each sub-pixel. Therefore, in one of the plurality of sub-pixels, a portion that becomes a thin-film transistor has a defect. Even if it is detected, as described above, one subpixel in which a defect is detected is treated as another normal subpixel by using a separately formed source electrode, a second semiconductor layer, and a separately formed drain electrode. It becomes possible to correct it.

  The thin film transistor substrate manufacturing method according to the present invention includes a plurality of pixels provided in a matrix, a plurality of thin film transistors provided for each pixel, and a plurality of pixel electrodes respectively connected to the thin film transistors. A gate layer forming step in which a gate electrode is defined for each pixel and a plurality of gate lines are formed to extend in parallel with each other; and a gate electrode of each pixel Forming an island-shaped first semiconductor layer so as to overlap with an insulating film, and forming an island-shaped second semiconductor layer so as to overlap each gate line with an insulating film for each pixel A source electrode is defined so as to overlap with one end of the gate electrode via the first semiconductor layer for each pixel, and intersects with each gate line. A plurality of source lines extending in parallel with each other in a direction to be connected to each other, and a drain electrode defining each pixel so as to overlap the other end of the gate electrode through the first semiconductor layer and to face the source electrode By forming the plurality of drain lines formed, the thin film transistor forming portion that becomes each of the above thin film transistors is formed, and the defective pixel having the thin film transistor forming portion in which the defect is detected cannot use the thin film transistor forming portion in which the defect is detected. A source electrode forming portion that overlaps one end of the second semiconductor layer and each gate line and is connected to a source line connected to the thin film transistor forming portion in which the defect is detected, and the second semiconductor It is configured to overlap the other end of the layer and each gate line and to be connected to the pixel electrode of the defective pixel. A source layer forming step for forming the drain electrode forming portion, an interlayer insulating film forming step for forming an interlayer insulating film so as to cover each source line, each drain line, the source electrode forming portion and the drain electrode forming portion, and And a pixel electrode forming step of forming the plurality of pixel electrodes in a matrix on the interlayer insulating film.

  According to the above method, in the semiconductor layer forming step, the first semiconductor layer is formed so as to overlap each gate electrode constituting the thin film transistor via the insulating film, and the gate line is provided for each pixel via the insulating film. A second semiconductor layer is formed so as to overlap, and in the source layer forming step, a source electrode (source line) and a drain electrode (drain line) constituting the thin film transistor are formed, and a thin film transistor forming portion in which a defect is detected is provided In the defective pixel, for example, the drain electrode is cut to disable the thin film transistor formation portion, and the source electrode formation portion and the drain electrode formation portion are formed so that the second semiconductor layer functions as a thin film transistor. Thin film transistor substrate manufactured by performing interlayer insulating film forming step and pixel electrode forming step In the pixel electrode of the defective pixel in which the defect is detected in the source layer formation step, when an ON gate signal is sent to the corresponding gate line, the source line, the source electrode formation portion, the second semiconductor layer, and the drain A source signal is sent through the electrode forming portion. Thereby, since the defective pixel in which the defect is detected is corrected as a normal pixel, it is possible to correct the defect of the thin film transistor while suppressing the deterioration of the display quality.

  The semiconductor layer forming step may be performed after performing the gate insulating film step of forming the plurality of gate lines on the substrate in the gate layer forming step and forming the insulating film so as to cover the gate lines. Good.

  According to the above method, since the gate electrode is disposed on the substrate side with respect to the first semiconductor layer and the second semiconductor layer, the thin film transistor substrate including the bottom gate type thin film transistor is specifically manufactured.

  In the source layer formation step, the thin film transistor formation portion in which the defect is detected may be disabled by cutting the drain line formed in the defective pixel.

  According to the above method, by disconnecting the drain line formed in the defective pixel, the connection between the corresponding thin film transistor forming portion and the pixel electrode is released, so that the thin film transistor forming portion where the defect is detected is specifically Disabled.

  In the source / drain formation step, the upper layer portion of the first semiconductor layer exposed from the source electrode and the drain electrode and the upper layer portion of the second semiconductor layer exposed from the source electrode formation portion and the drain electrode formation portion are etched. By doing so, each channel region may be formed.

According to the above method, the upper layer portion (for example, the n ⁺ layer) of the first semiconductor layer and the second semiconductor layer is partially etched so that the source electrode formation portion and the source electrode formation portion For example, since an intrinsic amorphous silicon layer is exposed between the drain electrode formation portions, a thin film transistor using amorphous silicon is specifically configured.

  The width and length of the channel region of the second semiconductor layer may be set to be the same as the width and length of the channel region of the first semiconductor layer.

  According to the above method, since the width and length of the channel region of the second semiconductor layer are the same as the width and length of the channel region of the first semiconductor layer, the characteristics of the (regular) thin film transistor having the first semiconductor layer And the characteristics of the (preliminary) thin film transistor having the second semiconductor layer.

  In the source / drain formation step, the source electrode formation portion and the drain electrode formation portion may be formed by laser CVD.

  According to the above method, since the uniform conductive film is formed by drawing by laser CVD, the source electrode forming portion and the drain electrode forming portion are specifically formed.

  According to the present invention, since the second semiconductor layer is provided in addition to the first semiconductor layer constituting the thin film transistor, it is possible to suppress the deterioration of the display quality and to correct the defect of the thin film transistor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

Embodiment 1 of the Invention
1 to 5 show Embodiment 1 of a TFT substrate precursor and a method for manufacturing a TFT substrate according to the present invention. Specifically, FIG. 1 is a plan view of the TFT substrate 20a of the present embodiment, and FIG. 2 is a cross-sectional view of the TFT substrate 20a along the line II-II in FIG.

  As shown in FIGS. 1 and 2, the TFT substrate 20a is provided so as to extend in parallel with each other between a plurality of gate lines 11a provided on the insulating substrate 10 so as to extend in parallel with each other. A plurality of capacitance lines 11b, a gate insulating film 12 provided so as to cover each gate line 11a and each capacitance line 11b, and each gate line 11a on each gate P which will be described later on the gate insulating film 12 The second semiconductor layer 13b provided in this manner, a plurality of source lines 14a on the gate insulating film 12 so as to extend in parallel to each other in a direction orthogonal to the gate lines 11a, and the gate lines 11a and the source lines 14a. A plurality of first TFTs 5a and a plurality of second TFTs 5b provided in pairs at the intersections, each second semiconductor layer 13b, each first TFT 5a, each second TFT 5b, and each source 14a, an inorganic insulating film 15 provided so as to cover 14a, an organic insulating film 16 provided so as to cover the inorganic insulating film 15, and an interlayer insulating film 18 composed of the inorganic insulating film 15 and the organic insulating film 16 in a matrix form And a plurality of pixel electrodes 17 provided on the substrate. Here, as shown in FIG. 1, the pixel electrode 17 connected to the first TFT 5a constitutes the first sub-pixel Pa, and the pixel electrode 17 connected to the second TFT 5b constitutes the second sub-pixel Pb. Yes. As shown in FIG. 1, the first sub-pixel Pa and the second sub-pixel Pb are adjacent to each other across the gate line 11a along the direction in which the source line 14a extends, thereby forming one pixel P. is doing.

As shown in FIGS. 1 and 2, the first TFT 5a includes one gate electrode 11aa (downward in FIG. 1) protruding from both sides of each gate line 11a and a gate provided so as to cover the gate electrode 11aa. The insulating film 12, the first semiconductor layer 13c provided in an island shape at a position corresponding to the gate electrode 11aa on the gate insulating film 12, and the source electrode 14aa provided to face each other on the first semiconductor layer 13c And a drain electrode 14ba. Here, as shown in FIG. 2, the first semiconductor layer 13c includes a lower intrinsic amorphous silicon layer 13ca having a channel region C defined on the upper surface, and an n ⁺ layer 13cb provided on the upper layer. Further, as shown in FIG. 1, the source electrode 14aa is a portion protruding to the side of each source line 14a. Further, as shown in FIG. 1, the drain electrode 14ba extends as a drain line 14b to a region overlapping with the capacitor line 11b, thereby forming a part of the auxiliary capacitor (capacitance electrode) and on the capacitor line 11b. And connected to the pixel electrode 17 through a contact hole 16 a formed in the interlayer insulating film 18. As shown in FIG. 1, the drain line 14b is bifurcated before overlapping the capacitor line 11b, and is connected to the pixel electrode 17 via the contact hole 16a in the region overlapping the capacitor line 11b. It has a pair of capacitive electrodes.

  The second TFT 5b has a gate electrode 11aa on the other side (upper side in FIG. 1) protruding from both sides of each gate line 11a, and the other configuration is substantially the same as the first TFT 5a.

  The TFT substrate 20a having the above-described configuration constitutes a liquid crystal display device together with a CF substrate disposed oppositely and a liquid crystal layer sealed between the two substrates.

  Next, an example is given and demonstrated about the manufacturing method of TFT substrate 20a in which the short circuit defect between the TFT substrate 20a and the source electrode and the drain electrode was corrected. 3 is a plan view of the substrate 19a in which the short-circuit defect is detected, FIG. 4 is a plan view of the substrate 19b in which the short-circuit defect is corrected, and FIG. 5 is a TFT in which the short-circuit defect is corrected. It is a top view of the board | substrate 20r. Note that the manufacturing method of this embodiment includes a gate layer forming step, a gate insulating film forming step, a semiconductor layer forming step, a source layer forming step, an interlayer insulating film forming step, and a pixel electrode forming step.

<Gate layer formation process>
For example, a titanium film, an aluminum film, a titanium film, and the like are sequentially formed on the entire substrate of the insulating substrate 10 such as a glass substrate by a sputtering method, and then patterning and etching are performed by photolithography to obtain a gate line 11a and a gate electrode. 11aa and the capacitor line 11b are formed.

<Gate insulation film formation process>
For example, a silicon nitride film or the like is formed by plasma CVD (Chemical Vapor Deposition) method on the entire substrate on which the gate line 11a, the gate electrode 11aa, and the capacitor line 11b are formed in the gate layer forming step, and the gate insulating film 12 Form.

<Semiconductor layer formation process>
For example, an intrinsic amorphous silicon film and an n ⁺ amorphous silicon film doped with phosphorus are sequentially formed on the entire substrate on which the gate insulating film 12 has been formed in the gate insulating film forming step by a plasma CVD method. Patterning and etching are performed in an island shape on the gate electrode 11aa and the gate line 11a by photolithography to form the first semiconductor layer 13a and the second semiconductor layer 13b.

<Source layer forming process>
First, for example, an aluminum film and a titanium film are sequentially formed by sputtering on the entire substrate on which the first semiconductor layer 13a and the second semiconductor layer 13b are formed in the semiconductor layer forming step, and then by photolithography. Patterning and etching are performed to form the source line 14a, the source electrode 14aa, the drain electrode 14ba, and the drain line 14b. Thereby, the TFT formation part S is formed for each sub-pixel Pa and Pb, and the TFT substrate precursor 19a is produced (see FIG. 3).

  Subsequently, a pattern check of the source line 14a, the source electrode 14aa, the drain electrode 14ba, and the drain line 14b is performed, and for example, a film residue R or the like is provided between the source electrode 14aa and the drain electrode 14ba constituting the TFT forming unit S. It is confirmed whether a short-circuit defect has occurred due to the particles (see FIG. 3).

  Here, as shown in FIG. 3, when a short-circuit defect is detected between the source electrode 14aa and the drain electrode 14ba, as shown in FIG. The linear source electrode forming portion 14c and the lower end portion of the second semiconductor layer 13b and the gate are cut and overlapped with the upper end portion of the second semiconductor layer 13b and the gate line 11a and connected to the source line 14a. A TFT substrate precursor 19b is manufactured by forming an L-shaped drain electrode forming portion 14d by laser CVD so as to be connected to the lower side portion of the drain line 14b that is cut (divided) and overlaps the line 11a. To do. The source electrode forming portion 14c and the drain electrode forming portion 14d can be formed by drawing a tungsten film using, for example, an LCD laser repair device.

Further, the source electrode 14aa and the drain electrode ba (and the source electrode formation portion 14c and the drain electrode formation portion 14d when the source electrode formation portion 14c and the drain electrode formation portion 14d are formed to correct the short-circuit defect) are masked. As a result, the n ⁺ layer of the first semiconductor layer 13a (and the second semiconductor layer 13b) is etched to form the channel region C, thereby forming the first semiconductor layer 13c (and the second semiconductor layer 13d) ( (See FIG. 5). Thereby, the first TFT 5a and the second TFT 5b (and the spare TFT 5c) are formed. Here, the width and length of the channel region C of the first semiconductor layer 13c are substantially the same as the width and length of the channel region C of the second semiconductor layer 13d. In this embodiment, assuming a panel having a 46-inch FHD (Full High Definition) screen and a pixel size of 530.25 μm × 176.75 μm, for example, the size of the channel region C of the first TFT 5 a is 44 μm × The source electrode forming portion 14c and the drain electrode forming portion 14d are drawn by laser CVD so that the size of the channel region of the second TFT 5b is 44 μm × 4 μm.

<Interlayer insulating film formation process>
First, for example, a silicon nitride film or the like is formed by plasma CVD on the entire substrate on which the first TFT 5a and the second TFT 5b (and the spare TFT 5c) are formed in the source layer forming step, and the inorganic insulating film 15 is formed.

  Subsequently, for example, an acrylic photosensitive resin is applied to the entire substrate on which the inorganic insulating film 15 is formed by a spin coating method, and the applied photosensitive resin is exposed through a photomask and then developed. As a result, the organic insulating film 16 having the contact hole 16a is formed on the drain line 14b (capacitance electrode).

  Further, the inorganic insulating film 15 exposed from the contact hole 16 a of the organic insulating film 16 is etched to form an interlayer insulating film 18 composed of the inorganic insulating film 15 and the organic insulating film 16.

<Pixel electrode formation process>
For example, an ITO (Indium Tin Oxide) film is formed by sputtering on the entire substrate on which the interlayer insulating film 18 has been formed in the interlayer insulating film forming step, and then patterning and etching are performed by photolithography. As shown in FIG. 2, the pixel electrode 17 is formed.

  As described above, the TFT substrate 20a and the (TFT substrate 20r with the short-circuit defect corrected) can be manufactured.

  As described above, according to the manufacturing method of the TFT substrate 20a (20r) of the present embodiment, after the gate layer forming step and the gate insulating film forming step, the first TFT 5a and the second TFT 5b are formed in the semiconductor layer forming step. The first semiconductor layer 13a is formed so as to overlap each gate electrode 11aa to be formed, and the second semiconductor layer 13b is formed so as to overlap each gate line 11a for each pixel P. In the source layer forming step, the first TFT 5a is formed. In addition, the source electrode 14aa (source line 14a) and the drain electrode 14ba (drain line 14b) constituting the second TFT 5b are formed, and in the defective pixel having the TFT forming portion S in which the short-circuit defect is detected, the drain line 14b is cut. The source electrode forming portion 14c and the drain are formed so that the second semiconductor layer 13b functions as a TFT. Then, in the TFT substrate 20r manufactured by performing the interlayer insulating film forming step and the pixel electrode forming step, the pixel electrode of the defective pixel in which the short-circuit defect is detected in the source layer forming step is formed. 17, when an ON gate signal is sent to the corresponding gate line 11a, the source signal is sent via the source line 14a, the source electrode formation portion 14c, the second semiconductor layer 13d, and the drain electrode formation portion 14d. Will be. As a result, a defective pixel in which a short-circuit defect is detected between the source electrode 14aa and the drain electrode 14ba can be corrected as a normal sub-pixel, so that deterioration in display quality is suppressed and the source electrode 14aa and the drain electrode 14ba are suppressed. The short circuit defect between can be corrected.

  Further, according to the manufacturing method of the TFT substrate 20a (20r) of the present embodiment, the width and length of the channel region C of the second semiconductor layer 13d are substantially the same as the width and length of the channel region C of the first semiconductor layer 13c. Therefore, the characteristics of the regular first TFT 5a and the second TFT 5b having the first semiconductor layer 13c and the characteristics of the spare TFT 5c having the second semiconductor layer 13d can be made uniform.

  Further, according to the manufacturing method of the TFT substrate 20a (20r) of this embodiment, each pixel P has the first sub-pixel Pa and the second sub-pixel Pb, and the TFT 5a (5b) and the pixel electrode 17 have the first sub-pixel. Since it is provided for each pixel Pa and second sub-pixel Pb, even if a short-circuit defect is detected between the source electrode 14aa and the drain electrode 14ba in one of the first sub-pixel Pa and the second sub-pixel Pb, As described above, by using the second semiconductor layer 13b (13d), the source electrode formation portion 14c, and the drain electrode formation portion 14d, one subpixel in which a short-circuit defect is detected is corrected as a normal other subpixel. be able to.

  In the present embodiment, the interlayer insulating film 18 composed of the inorganic insulating film 15 and the organic insulating film 16 is illustrated. However, for example, the organic insulating film 16 may be omitted or a CF material may be used instead of the organic insulating film 16. .

  Further, in the present embodiment, the TFT substrate provided with two TFTs 5a and 5b in one pixel P composed of the first sub-pixel Pa and the second sub-pixel Pb is illustrated, but the present invention is one TFT per pixel. It is applicable also to the TFT substrate provided with.

  In the present embodiment, the TFT substrate 20a (20r) provided with one second semiconductor layer 13b in one pixel P including the first subpixel Pa and the second subpixel Pb is illustrated. For example, the present invention can also be applied to a TFT substrate in which one pixel P including the first subpixel Pa and the second subpixel Pb includes two second semiconductor layers. According to this, even if a short-circuit defect is detected in both the first TFT 5a of the first sub-pixel Pa and the second TFT 5b of the second sub-pixel Pb, the two second semiconductor layers are used to make both normal sub-pixels. As can be corrected.

  In this embodiment, a TFT using amorphous silicon is exemplified, but the present invention can also be applied to a TFT using polysilicon.

  In the present embodiment, the method of forming the source electrode forming portion 14c and the drain electrode forming portion 14d using laser CVD has been exemplified. However, the method is formed using inkjet, photolithography, sputtering using a mask, CVD, or the like. May be.

  In the present embodiment, a method of correcting a short-circuit defect caused by a film residue R between the source electrode 14aa and the drain electrode 14ba is exemplified as a TFT defect. However, the present invention provides a pinhole in a gate insulating film. The present invention can also be applied to correcting other TFT defects such as a short-circuit defect between the gate electrode 11aa and the first semiconductor layer 13a (the source electrode 14aa and the drain electrode 14ba) caused by the above. As for the short-circuit defect between the gate electrode 11aa and the source electrode 14aa, not only the corresponding drain line 14b but also the base of the gate electrode 11aa may be cut.

<< Embodiment 2 of the Invention >>
6 to 8 show Embodiment 2 of a TFT substrate precursor and a method for manufacturing a TFT substrate according to the present invention. Specifically, FIGS. 6, 7 and 8 are plan views showing the TFT substrates 20b, 20c and 20d of this embodiment, respectively. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same part as FIGS. 1-5, and the detailed description is abbreviate | omitted.

  In the first embodiment, a pair of sub-pixels adjacent to each other across the gate line 11a along the extending direction of each source line 14a constitutes one pixel P. However, in the present embodiment, each gate line A pair of subpixels defined every two adjacent to each other along the extending direction of 11a constitutes one pixel P.

  In the TFT substrate 20b, as shown in FIG. 6, each gate line 11a protrudes to one side (downward in the drawing) to form each gate electrode 11aa of the first TFT 5a and the second TFT 5b, and each pixel electrode 17 in the drawing. A gate line 11a is provided along the upper side and the lower side in the figure, and a source line 14a is provided along the left side and the right side in the figure of each pixel electrode 17.

  In the TFT substrate 20c, as shown in FIG. 7, each gate line 11a protrudes to one side (downward in the figure) to form each gate electrode 11aa of the first TFT 5a and the second TFT 5b, and the first subpixel Pa and the first subpixel Pa A gate line 11a is provided along the upper side and the lower side in the drawing of the pixel P having two sub-pixels Pb, and a pair of source lines 14a extending in parallel with each other along the left side and the right side in the drawing of each pixel P. And 14a are provided.

  In the TFT substrate 20d, as shown in FIG. 8, each gate line 11a protrudes to one side (downward in the figure) to form each gate electrode 11aa of the first TFT 5a and the second TFT 5b, and the first subpixel Pa and the first A gate line 11a is provided along the upper side and lower side in the figure of the pixel P having two sub-pixels Pb, and a source line 14a is provided along the left side and right side in the figure of each pixel P.

  The TFT substrates 20b, 20c, and 20d having the above-described configuration can be manufactured by changing the pattern shape of wiring, electrodes, etc. in the TFT substrate manufacturing method described in the first embodiment. This can be performed in the same manner as in the first embodiment.

  According to the manufacturing method of the TFT substrates 20b to 20d of the present embodiment, the second semiconductor layer 13b is provided in addition to the first semiconductor layer 13c (13a) constituting the first TFT 5a and the second TFT 5b, as in the first embodiment. Therefore, it is possible to correct the defects of the first TFT 5a and the second TFT 5b while suppressing the deterioration of display quality.

<< Embodiment 3 of the Invention >>
FIG. 9 is a plan view showing the TFT substrate 20e of this embodiment.

  In the first embodiment, a pair of sub-pixels adjacent to each other along the extending direction of each source line 14a constitutes one pixel P. In the second embodiment, adjacent to each other along the extending direction of each gate line 11a. A pair of sub-pixels defined for every two matched constitutes one pixel P. In this embodiment, every two adjacent sub-pixels along the extending direction of each gate line 11a and each source line 14a. The four sub-pixels defined in 1 constitute one pixel P.

  In the TFT substrate 20e, as shown in FIG. 9, the first TFT 5a, the second TFT 5b, the third TFT 5c, and the fourth TFT 5d are provided at the intersections of the gate lines 11a and the source lines 14a, respectively. That is, in the TFT substrate 20e, as shown in FIG. 9, each gate line 11a protrudes on both sides to form each gate electrode 11aa of the first TFT 5a, second TFT 5b, third TFT 5c, and fourth TFT 5d, and each source line 14a has both sides. The source electrodes 14aa of the first TFT 5a, the second TFT 5b, the third TFT 5c, and the fourth TFT 5d are configured to protrude in the direction. In the TFT substrate 20e, as shown in FIG. 9, the pixel electrode 17 connected to the first TFT 5a (or the third TFT 5c) and the region surrounded by each gate line 11a, each source line 14a, and each capacitance line 11b The pixel electrodes 17 connected to the second TFT 5b (or the fourth TFT 5d) are provided adjacent to each other. Here, as shown in FIG. 9, the pixel electrode 17 connected to the first TFT 5a constitutes the first sub-pixel Pa, the pixel electrode 17 connected to the second TFT 5b constitutes the second sub-pixel Pb, The pixel electrode 17 connected to the third TFT 5c constitutes a third subpixel Pc, and the pixel electrode 17 connected to the fourth TFT 5d constitutes a fourth subpixel Pa. As shown in FIG. 9, the first sub-pixel Pa, the second sub-pixel Pb, the third sub-pixel Pc, and the third sub-pixel Pd are connected to each other along the extending direction of each gate line 11a and each source line 14a. Adjacent to each other constitutes one pixel P.

  The TFT substrate 20e having the above-described configuration can be manufactured by changing the pattern shape of wiring, electrodes, and the like in the TFT substrate manufacturing method described in the first embodiment. 1 can be performed.

  According to the manufacturing method of the TFT substrate 20e of the present embodiment, the first TFT 5a, the second TFT 5b, the third TFT 5c, and the fourth TFT 5d are formed in addition to the first semiconductor layer 13c (13a) as in the first and second embodiments. Since the two semiconductor layers 13b are provided, it is possible to correct the defects of the first TFT 5a, the second TFT 5b, the third TFT 5c, and the fourth TFT 5d while suppressing the deterioration of display quality.

  In the present embodiment, the configuration in which one second semiconductor layer is provided for every four TFTs is exemplified, but the number of second semiconductor layers per TFT may be changed as appropriate.

  As described above, the present invention can correct defects in TFTs by suppressing deterioration in display quality, and thus, for example, liquid crystal display devices for use in liquid crystal televisions that require high display quality, TFTs This is useful for all display devices using the.

2 is a plan view of a TFT substrate 20a according to Embodiment 1. FIG. It is sectional drawing of the TFT substrate 20a along the II-II line | wire in FIG. It is a top view of TFT substrate precursor 19a by which the short circuit defect was detected. It is a top view of TFT substrate precursor 19b by which the short circuit defect was corrected. It is a top view of TFT substrate 20r by which the short circuit defect was corrected. 6 is a plan view of a TFT substrate 20b according to Embodiment 2. FIG. 6 is a plan view of a TFT substrate 20c according to Embodiment 2. FIG. 6 is a plan view of a TFT substrate 20d according to Embodiment 2. FIG. It is a top view of TFT substrate 20e concerning Embodiment 3. It is a top view of the conventional TFT substrate 120.

Explanation of symbols

C channel region P pixel Pa first sub-pixel Pb second sub-pixel Pc third sub-pixel Pd fourth sub-pixel ST TFT formation portion 5a first TFT
5b 2nd TFT
DESCRIPTION OF SYMBOLS 10 Insulating substrate 11a Gate line 11aa Gate electrode 12 Gate insulating film 13a, 13c 1st semiconductor layer 13b, 13d 2nd semiconductor layer 14a Source line 14aa Source electrode 14b Drain line 14ba Drain electrode 14c Source electrode formation part 14d Drain electrode formation part 17 Pixel electrode 18 Interlayer insulating film 19a, 19b TFT substrate precursor 20a-20e, 20r TFT substrate

Claims (12)

A precursor of a thin film transistor substrate comprising a plurality of pixels provided in a matrix, a plurality of thin film transistors provided for each of the pixels, and a plurality of pixel electrodes respectively connected to the thin film transistors,
A gate electrode is defined for each of the pixels, and a plurality of gate lines provided to extend in parallel to each other;
A first semiconductor layer provided in an island shape so as to overlap with the gate electrode of each pixel through an insulating film;
A second semiconductor layer provided in an island shape so as to overlap each gate line via an insulating film for each pixel;
A source electrode is defined for each pixel so as to overlap one end of the gate electrode via the first semiconductor layer, and a plurality of pixels are provided so as to extend in parallel to each other in a direction intersecting the gate lines. Source line,
A drain electrode is defined for each of the pixels so as to overlap the other end of the gate electrode through the first semiconductor layer and to face the source electrode, and is provided to be connected to the pixel electrode. A thin film transistor substrate precursor comprising a plurality of drain lines. The thin film transistor substrate precursor according to claim 1,
The thin film transistor substrate precursor, wherein the second semiconductor layer is not connected to the source lines and the drain lines. The thin film transistor substrate precursor according to claim 1,
Each thin film transistor is a bottom-gate type thin film transistor substrate precursor. The thin film transistor substrate precursor according to claim 1,
Each pixel constitutes a plurality of sub-pixels adjacent to each other along the extending direction of each source line,
The thin film transistor substrate precursor, wherein each of the thin film transistors and each pixel electrode is arranged for each of the sub pixels. The thin film transistor substrate precursor according to claim 1,
Each of the pixels constitutes a pair of sub-pixels for each of a plurality adjacent to each other along the extending direction of the gate lines,
The thin film transistor substrate precursor, wherein each of the thin film transistors and each pixel electrode is arranged for each of the sub pixels. The thin film transistor substrate precursor according to claim 1,
Each of the pixels constitutes a pair of sub-pixels for each of a plurality adjacent to each other along the extending direction of the gate lines and the source lines,
The thin film transistor substrate precursor, wherein each of the thin film transistors and each pixel electrode is arranged for each of the sub pixels. A method of manufacturing a thin film transistor substrate comprising a plurality of pixels provided in a matrix, a plurality of thin film transistors provided for each of the pixels, and a plurality of pixel electrodes respectively connected to the thin film transistors. ,
A gate layer forming step in which a gate electrode is defined for each pixel and a plurality of gate lines are formed to extend in parallel with each other;
An island-shaped first semiconductor layer is formed so as to overlap with the gate electrode of each pixel via an insulating film, and an island-shaped second semiconductor layer is overlapped with each gate line via the insulating film for each pixel. A semiconductor layer forming step of forming a semiconductor layer;
A source electrode is defined for each pixel so as to overlap one end of the gate electrode via the first semiconductor layer, and a plurality of source lines extend in parallel to each other in a direction intersecting the gate lines. And forming a plurality of drain lines having a drain electrode defined so as to overlap the other end portion of the gate electrode through the first semiconductor layer and to face the source electrode through the first semiconductor layer. In a defective pixel having a thin film transistor forming portion in which a thin film transistor forming portion that becomes each thin film transistor is detected and having a defect detected, the thin film transistor forming portion in which the defect is detected is disabled, and one end portion of the second semiconductor layer and A source electrode is connected to a source line that overlaps each gate line and is connected to a thin film transistor formation portion in which the defect is detected. Generating unit, and a source layer formation step of forming a drain electrode forming portion configured to connect to the pixel electrode of the defective pixel with overlap at the other end and the respective gate lines of the second semiconductor layer,
An interlayer insulating film forming step of forming an interlayer insulating film so as to cover each source line, each drain line, the source electrode forming portion and the drain electrode forming portion;
And a pixel electrode forming step of forming the plurality of pixel electrodes in a matrix on the interlayer insulating film. In the manufacturing method of the thin-film transistor substrate described in Claim 7,
The semiconductor layer forming step is performed after performing the gate insulating film step of forming the plurality of gate lines on the substrate in the gate layer forming step and forming the insulating film so as to cover the gate lines. A method of manufacturing a thin film transistor substrate. In the manufacturing method of the thin-film transistor substrate described in Claim 7,
In the source layer forming step, the drain line formed in the defective pixel is cut so that the thin film transistor forming portion where the defect is detected is made unusable. In the manufacturing method of the thin-film transistor substrate described in Claim 8,
In the source / drain formation step, the upper layer portion of the first semiconductor layer exposed from the source electrode and the drain electrode and the upper layer portion of the second semiconductor layer exposed from the source electrode formation portion and the drain electrode formation portion are etched. Thus, a channel region is formed, respectively, and a method for manufacturing a thin film transistor substrate, In the manufacturing method of the thin-film transistor substrate described in claim 10,
A method of manufacturing a thin film transistor substrate, wherein the width and length of the channel region of the second semiconductor layer are set to be the same as the width and length of the channel region of the first semiconductor layer. In the manufacturing method of the thin-film transistor substrate described in Claim 7,
In the source / drain forming step, the source electrode forming portion and the drain electrode forming portion are formed by laser CVD.

Images