JP4426413B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a manufacturing method of a semiconductor equipment comprising a MEMS device which is sealed with an integrated circuit.

  Various micromachines manufactured on a silicon substrate are widely used in various application fields (see Non-Patent Document 1). Silicon can be obtained in large quantities at low cost, and it can be easily miniaturized while maintaining extremely high dimensional accuracy and processing accuracy by micromachining technology based on LSI manufacturing technology. In addition, mass production is possible. Therefore, development of micromachines using silicon has been actively conducted. In recent years, a technical field called MEMS (MicroElectro Mechanical System) technology has been created, and in addition to the application fields described in Non-Patent Document 1, the present invention is also applied to various fields such as sensors, medical care, optical communication, and wireless communication. Applications are spreading.

  In particular, MEMS (called RFMEMS) that processes high-frequency signals such as radio signals has been extensively researched and developed. There are many types of RFMEMS elements such as inductors, switches, variable capacitors, resonators, filters, transmission lines, antennas, and the like. In the RF MEMS technology that has been widely studied in this manner, a complicated circuit function is realized by integrating a plurality of MEMS elements and a semiconductor integrated circuit is integrated, and sealing and packaging for mounting the MEMS elements are reduced. Cost reduction is desired.

  For example, a technique has been proposed in which a semiconductor integrated circuit and a plurality of MEMS elements are mounted on the same substrate to enable an integrated transceiver (one-chip transceiver) for wireless communication (see Non-Patent Document 2). According to this technology, it is possible to reduce the number of parts, the mounting cost, mass production by batch processing, and the like, and the radio transceiver can be reduced in size and cost. However, only the concept of integration is proposed in Non-Patent Document 2, and in a wireless communication application, a device in which a semiconductor integrated circuit and a plurality of MEMS elements are integrated on the same substrate is realized. It has not been.

  In addition, regarding mounting and packaging methods, conventionally, individual MEMS elements fabricated on a substrate are cut out from the substrate and then sealed for each element (see Patent Document 1). There is a method of cutting into individual MEMS elements after sealing with (see Non-Patent Documents 3, 4 and 5).

  In the method of Patent Document 1, the MEMS element is packaged by a method similar to a known hermetic seal (hermetic seal). In this technique, as shown in FIG. 8, a fixed substrate 501 in which signal lines and fixed electrodes are formed on a glass substrate, and a movable substrate in which movable electrodes, beams and anchors made from a silicon substrate are integrally formed. 502 forms a package. The movable substrate 502 operates as an electrostatic micro relay (switch).

  The movable substrate 502 is fixed to the fixed substrate 501 by anodic bonding, and a cap member 503 is fixed to the fixed substrate 501 by anodic bonding at the outer peripheral portion of the movable substrate 502, and from the fixed substrate 501 and the cap member 503. The movable substrate 502 is sealed in the configured container. In this case, after manufacturing the MEMS element on the substrate, in order to protect minute movable parts from damage in the process of cutting out the element for mounting and handling of the cut out element, handling with great care is required. In the inspection after mounting, it is necessary to guarantee the quality of each element.

  For these reasons, in the above-described MEMS element, the dimensions of the parts cannot be made very small, and application to mass production is not easy. Furthermore, in order to realize a circuit function by combining a plurality of MEMS elements having different functions, the individual MEMS elements are individually sealed and then mounted on a mounting substrate. In some cases, the overall dimensions are inevitably increased, and there is a limit to downsizing after mounting as a whole.

  On the other hand, as a technique for cutting into individual MEMS elements after sealing, in Non-Patent Document 3, a space is formed in a glass substrate, a SAW (Surface Acoustic Wave) element is built in the formed space, and a new glass is added thereto. After the substrates are bonded together, they are cut into individual chips to obtain a sealed SAW chip.

  In Non-Patent Document 4, after manufacturing a MEMS element on a wafer, another substrate (sealing chip) for sealing is prepared, and the periphery of the MEMS element is surrounded on the sealing chip. A shaped BCB (benzocyclobutene) film is formed as a frame pattern, a sealing chip on which the frame pattern is formed is attached to the wafer by flip-flops, and the MEMS element formed on the wafer is sealed After that, it is cut out into individual chips.

  In Non-Patent Document 5, after a MEMS element is fabricated on a wafer, the MEMS element is covered with a small cap that is slightly larger than the fabricated element, and a material called LCP (Liquid Crystal Polymer) is formed on the MEMS element. After deposition, a film is formed, solidified and sealed, and then cut into individual chips.

  However, these methods require a special dedicated process for sealing the MEMS element, and it is very difficult to reduce the manufacturing cost including the mounting of the chip provided with the MEMS element.

The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
JP 2000-311572 A KEPetersen, “Silicon as a mechanical materia1”, Proc. IEEE, Vol.70, No.5, pp.420-457, May 1982. Clark T.-C.Nguyen, LPBKatehi, and GMRebeiz, "Micromachined Devices for Wireless Communications", IEEE Proceeding, vol.86, No.8, pp.1756-1768, Aug. 1998. D. Ando, K. Oishi, T. Nakamura, and S. Umeda, "Glass direct bonding technology for hermetic seal package", IEEE 10th Int. Wiorkshop on Micro Electro Mechanical Systems, pp. 186-190, Jan. 1997. A. Jourdain, P. De Moor, S. Pamidighantam, and ACTilmans, "Investigation of the hermeticity of BCB-sealed cavities for housing (RF-) MEMS devices", 15th IEEE Int. Conf. Micro Electro Mechanical Systems, pp. 677 -680, Jan. 2002. FFFaheem, KCGupta, and Y.-C.Lee, "Flip-chip assembly and liquid crystal polymer encapsulation for variable MEMS capacitors", IEEE Trans. Microwave Theory and Tech., Vol.51, No.12, pp.2562-2567 , Dec. 2003. N.Sato, H.Ishii, S.Shigematu, H.Morimura, T.Kamei, K.Kudou, M.Yano, K.Machida, H.Kyuragi, "A sealing technique for stacking MEMS on LSI using spin-coating film transfer and hot pressing ", Jpn.J.App1.Phys., Vol.42, Part 1, No.4B, pp.2462-2467, Apr.2003.

  As described above, for example, in a wireless communication application, an apparatus in which a plurality of MEMS elements and a semiconductor integrated circuit are integrated and integrated has not been realized. In addition, there has been a problem that it is not easy with conventional technology to realize sealing and packaging for mounting such an integrated device at a low cost.

  The present invention has been made in order to solve the above-described problems, and the object of the present invention is to form an LSI or the like in a different form of an element composed of a fine structure such as a MEMS element. An object of the present invention is to provide a semiconductor device monolithically mounted on a semiconductor substrate.

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor integrated circuit having a circuit function including signal processing on a semiconductor substrate, and a step of connecting the semiconductor integrated circuit to the semiconductor integrated circuit on the semiconductor substrate. A state in which one passive element is formed, a side wall frame surrounding a predetermined region on the semiconductor substrate, and a second passive element disposed in the side wall frame and connected to the semiconductor integrated circuit A step in which a ceiling wall facing the surface of the semiconductor substrate is formed on the side wall frame, and the second passive element is placed in a container composed of the side wall frame and the ceiling wall, and the first passive A step of embedding the element and the second passive element to form a resin insulating layer having a flat upper surface over the entire area of the semiconductor substrate, and a state in which terminals for connection to the outside are formed on the upper surface of the resin insulating layer And at least the process of Those were Unishi.

  In the semiconductor device manufacturing method, after the semiconductor integrated circuit is formed on the semiconductor substrate, the interlayer insulating layer is formed on the semiconductor integrated circuit, and the interlayer insulating layer is formed on the interlayer insulating layer. After the second step in which the first seed layer is formed and the first metal pattern and the thicker second metal pattern are formed on the first seed layer by the plating method, A third step in which the seed layer is selectively removed by etching using the first metal pattern and the second metal pattern as a mask; and a state in which a portion of the second metal pattern is exposed between the second metal patterns. In the fourth step, the first sacrificial layer made of an organic resin is formed on the interlayer insulating layer in the state where the first metal pattern is covered, and the exposed second metal pattern portion is included. On one sacrificial layer After the fifth step in which the two seed layers are formed and the third metal pattern and the fourth metal pattern thicker than the fifth metal pattern are formed on the second seed layer by plating, the third step is performed. A sixth step in which the second seed layer is selectively removed by etching using the metal pattern and the fourth metal pattern as a mask, and a part of the fourth metal pattern is exposed between the fourth metal pattern and embedded. A seventh step of forming a second sacrificial layer made of an organic resin on the first sacrificial layer in a state where the third metal pattern is covered in a state, and an exposed portion of the fourth metal pattern After the eighth step in which the third seed layer is formed on the second sacrificial layer and the plating method, the metal layer having a plurality of openings and the fifth metal pattern are formed, Metal layer and fifth metal pattern A ninth step in which the third seed layer is selectively removed by etching using the mask; a tenth step in which the first sacrificial layer and the second sacrificial layer are removed; and An eleventh step in which a sealing insulating layer is formed so as to close the opening; a first metal pattern, a second metal pattern, a third metal pattern, a fourth metal pattern, a fifth metal pattern, a metal layer, and A twelfth step in which the resin insulating layer is formed in a state where the upper surface is flat across the entire area of the semiconductor substrate above the interlayer insulating layer so that the sealing insulating layer is embedded; At least a thirteenth step in which a terminal connected to the semiconductor integrated circuit is formed on the upper surface of the resin insulating layer, and the second metal pattern includes a frame-shaped portion surrounding a region where the first metal pattern is formed; Placed inside this frame-shaped part The fourth metal pattern includes a portion that is disposed on the frame-shaped portion of the second metal pattern and is formed in a frame shape, and the frame-shaped portion of the second metal pattern. And the third metal pattern is formed to be connected to the inner part of the second metal pattern, the metal layer is disposed on the side wall frame as a ceiling wall, and the first metal pattern and the third metal The pattern is arranged inside the container constituted by the side wall frame and the ceiling wall, and the first sacrificial layer and the second sacrificial layer arranged inside the container are removed by etching through the opening. May be.

  In the above-described method for manufacturing a semiconductor device, a first step in which an interlayer insulating layer is formed on a semiconductor integrated circuit after the semiconductor integrated circuit is formed on the semiconductor substrate, and the interlayer insulating layer The first metal layer and the second metal pattern thicker than this are formed on the first seed layer by the second step in which the first seed layer is formed on the surface and the plating method. Thereafter, a third step in which the seed layer is selectively removed by etching using the first metal pattern and the second metal pattern as a mask, and a part of the second metal pattern is embedded between the second metal patterns. A fourth step in which a first sacrificial layer made of an organic resin is formed on the interlayer insulating layer in a state where the first metal pattern is covered in an exposed state; and a first metal pattern of the first sacrificial layer First insulation on top of A fifth step in which a turn is formed, and a state in which a second seed layer is formed on the first sacrificial layer including the exposed portion of the second metal pattern, and then a third method is performed by plating. A sixth step in which the metal pattern is formed on the second seed layer, and the second seed layer is selectively removed by etching using the third metal pattern as a mask; and a first insulating pattern And a seventh step in which a second sacrificial layer made of an organic resin is formed on the first sacrificial layer with the space between the third metal pattern and the upper part exposed, and a part of the exposed portion An eighth step in which the second insulating pattern is formed on the third metal pattern; and a state in which the third seed layer is formed on the second sacrificial layer including the exposed portion of the third metal pattern. After that, the fourth metal pattern is formed by plating. A ninth step in which the first seed layer is formed on the third metal pattern and the first insulating pattern, and the third seed layer is selectively removed by etching using the fourth metal pattern as a mask; A tenth step in which a third sacrificial layer made of an organic resin is formed on the second sacrificial layer, with the upper surface exposed between the second insulating pattern and the fourth metal pattern, and exposure; After the fourth seed layer is formed on the third sacrificial layer including the portion of the second insulating pattern and the fourth metal pattern, the fifth metal pattern is formed in a part of the fourth metal pattern by plating. An eleventh step in which the fourth seed layer is selectively removed by etching using the fifth metal pattern as a mask, and the upper surface is buried between the fifth metal pattern and formed on the metal pattern. Dew In a state where the fourth sacrificial layer made of an organic resin is formed on the third sacrificial layer, and the fifth step on the fourth sacrificial layer including the fifth metal pattern portion. After the seed layer is formed, the metal layer having a plurality of openings and the sixth metal pattern are formed by plating, and then the etching is performed using the metal layer and the sixth metal pattern as a mask. And a fifteenth step in which the fifth seed layer is selectively removed, and a fifteenth step in which the first sacrificial layer, the second sacrificial layer, the third sacrificial layer, and the fourth sacrificial layer are removed. A sixteenth step of forming a sealing insulating layer on the metal layer so as to close the opening, a first metal pattern, a second metal pattern, a third metal pattern, a fourth metal pattern, 5 metal pattern, 6th metal pattern, metal layer and sealing insulating layer A 17th step in which the resin insulating layer is formed in a state where the upper surface is flat across the entire area of the semiconductor substrate above the interlayer insulating layer so as to be embedded, and connected to the semiconductor integrated circuit via the resin insulating layer At least an eighteenth step in which the terminal is formed on the upper surface of the resin insulating layer, and the second metal pattern, the third metal pattern, and the fourth metal pattern have a region where the first metal pattern is formed. It is composed of an enclosing frame-like part and an internal part arranged inside the frame-like part, and the fifth metal pattern is arranged on the frame-like part of the fourth metal pattern and formed into a frame shape The second metal pattern, the third metal pattern, and the frame shape of the fourth metal pattern and the side wall frame are formed, and the metal layer is disposed on the side wall frame as a ceiling wall, Metal pattern, 3rd metal pattern And the internal part arrange | positioned inside the frame-shaped part of a 4th metal pattern, and the 1st metal pattern are arrange | positioned inside the container comprised by the side wall frame and the ceiling wall, and are arrange | positioned inside the container. The first sacrificial layer, the second sacrificial layer, the third sacrificial layer, and the fourth sacrificial layer may be removed by etching through the opening.

  As described above, according to the present invention, the interior of the container including the ceiling wall and the side wall includes the second passive element that includes the movable part and is connected to the semiconductor integrated circuit. Since the resin insulation layer is sealed and the upper surface side of the resin insulation layer provided with terminals is the mounting surface, different forms of elements composed of fine structures such as MEMS elements are monolithically integrated with the integrated circuit. The mounted semiconductor device can be handled in the same manner as a general semiconductor component and can be mounted in the same manner.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 3 are process diagrams showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1A, a semiconductor integrated circuit 102 having a circuit function including signal processing is formed on a semiconductor substrate 101 such as a silicon wafer by a known semiconductor integrated circuit manufacturing technique. The electrode pad 103 is formed around the periphery. The electrode pad 103 is a terminal for connection to the outside during mounting. In addition, a connection pad 104 for connecting to a MEMS element to be described later and a component pad 105 for connecting a surface mount component are formed in a predetermined region.

  The connection pad 104 is a terminal for connecting the MEMS element and the semiconductor integrated circuit 102, and may be formed to have a dimension that allows connection to the MEMS element. Further, the component pad 105 only needs to be formed to a size that allows connection with a surface-mounted component to be flip-mounted. 1 and 2 show one chip region, these are perspective views showing portions. The semiconductor substrate 101 extends to a region not shown, and a plurality of chips are simultaneously formed thereon.

  Next, as shown in FIG. 1B, the metal movable structures 106b and 106c surrounded by the metal side wall frame 106a and the fixed element 107 made of the fixed structure are integrated into the integrated circuit by the connection pads. It is assumed that it is formed on the semiconductor substrate 101 in a connected state. In FIG. 1B and subsequent figures, connection pads and integrated circuits are not shown. The movable structures 106b and 106c are, for example, switch elements, variable capacitance elements, resonators, mechanical filters, and the like. The fixed element 107 is, for example, an inductor element, a transmission line, an antenna element, an impedance matching element, or the like. In FIG. 1B, a spiral inductor element is shown as the fixed element 107. The side wall frame 106a may be made of a material such as silicon oxide or silicon nitride.

  Next, as shown in FIG. 2C, a metal ceiling wall 106d is formed on the side wall frame 106a, and the MEMS element 106 is formed. On the semiconductor substrate 101, the inside of the side wall frame 106a is sealed with a space provided by the formed ceiling wall 106d. In the sealed space, the movable structures 106b and 106c are in an operable state. For example, after the ceiling wall 106d is disposed on the side wall frame 106a, an organic resin film can be used to seal a container composed of the side wall frame 106a and the ceiling wall 106d.

  The container composed of the side wall frame 106a and the ceiling wall 106d enables the movable structure to be sealed in an inert gas atmosphere such as a rare gas or in a vacuum, and is electrically affected by external noise or the like. Unwanted radiation can be shielded. The ceiling wall 106d may be made of a material such as silicon oxide or silicon nitride. However, by configuring the side wall frame 106a and the ceiling wall 106d from a metal material, it is possible to more effectively shield the influence of electrical external noise and the like and unnecessary radiation to the outside.

  Next, as shown in FIG. 2D, a columnar metal post 109 is formed on the electrode pad 103, and the MEMS element 106 and the fixing element 107 are formed on the resin insulating layer 108 having a sufficient thickness. Covered. The upper surface of the resin insulating layer 108 is flat because the upper surface of the metal post 109 is exposed to facilitate mounting as a semiconductor component. Bumps may be provided on the upper surface of the metal post 109.

  After each element is covered with the resin insulating layer 108 as described above, each chip region is cut out from the semiconductor substrate 101 to obtain a chip component (semiconductor device) state. In the state of the chip component, the movable structures 106b and 106c that express the function of the MEMS element 106 are sealed by a container including the side wall frame 106a and the ceiling wall 106d. It is possible to handle. It should be noted that a plurality of movable structures may be arranged in one container constituted by the side wall frame 106a and the ceiling wall 106d.

  For example, as shown in FIG. 3E, the surface mounting component 110 may be mounted on the metal post 109 exposed on the upper surface of the chip component 112. The surface mounting component 110 is connected to the component pad via a metal post 109 disposed on the component pad (not shown). Further, the surface mounting component 110 can be fixed to the upper surface of the resin insulating layer 108 of the chip component 112 using, for example, an ultraviolet curable resin or a thermosetting resin. The surface mount component 110 is a passive component such as a SAW filter, a dielectric filter, a BAW filter, a crystal resonator, a chip inductor, a chip capacitor, or a chip resistor.

  FIG. 4 is a cross-sectional view schematically showing an example in which the chip component 112 is mounted on the mounting substrate 111. As shown in FIG. 4A, the chip component 112 is bonded and fixed to a predetermined portion of the mounting substrate 111 with a conductive adhesive or a resin material, and the pads 114 and the chip component 112 provided on the mounting substrate 111 are fixed. The upper surface of the metal post 109 is connected by a wire 113. As described above, the surface mounting component 110 is mounted on the chip component 112. An underfill resin 121 is filled between the surface mount component 110 and the chip component 112. Further, on the mounting substrate 111, the chip component 112 including the region of the pad 114 is covered with the potting resin 115.

  FIG. 4A shows a state in which the chip component 112 is mounted on the mounting substrate 111 by wire bonding technology. The mounting board 111 is a printed wiring board. The printed wiring board may be a flexible board, a ceramic board, a semiconductor board, or the like. Further, the mounting substrate 111 may be a part of a mold resin or a lead frame constituting the package.

  Further, the chip component 112 may be flip-chip mounted on the mounting substrate 111 as shown in FIG. The bump 116 provided on the metal post 109 of the chip component 112 can be flip-chip mounted on the mounting substrate 111. If necessary, an underfill resin may be filled between the chip component 112 and the mounting substrate 111, and a potting resin layer may be formed so as to cover the chip component 112.

  Further, when the surface mounting component 110 is mounted on the chip component 112, as shown in FIG. 4C, a space 117 is provided in the mounting substrate 111, and the surface mounting component 110 is disposed in the space 117. The chip component 112 may be flip-chip mounted. The mounting substrate 111 may be a film-like tape carrier used in a TAB (Tape Automated Bonding) method.

  According to the chip component described above, since a plurality of MEMS elements are integrated on the semiconductor substrate together with the integrated circuit in a state of being sealed in the space, the chip component can be handled in the same manner as a normal semiconductor chip. . Further, since the planarized resin insulating layer 108 is provided and the metal post 109 serving as a terminal for connection to the outside is disposed on the surface, mounting and the like are facilitated. In the same manner, it is easy to mount a surface mounting component having a function that cannot be realized by a sealed MEMS element on a chip component. According to the present invention, a higher-performance semiconductor device can be realized. become.

  Next, a method for manufacturing the above-described semiconductor device (chip component) will be described in more detail. First, as shown in FIG. 5A, a semiconductor integrated circuit 302 composed of a plurality of transistors, resistors, capacitors, wirings, and the like is formed on a semiconductor substrate 301 that is a silicon wafer by a known integrated circuit manufacturing process. It is assumed that it is formed. Further, an electrode portion 303 connected to a predetermined portion of a wiring layer (not shown) is formed on the semiconductor integrated circuit 302, and an interlayer insulating layer 304 made of, for example, silicon oxide or silicon nitride is formed thereon.

  Next, after a contact hole for connecting to a predetermined electrode portion 303 is formed in the interlayer insulating layer 304, a seed layer 305 is formed on the interlayer insulating layer 304 as shown in FIG. It is assumed that it is formed. The seed layer 305 may be formed, for example, by first depositing titanium and then depositing gold thereon by sputtering or vapor deposition. The thickness of titanium may be about 0.1 μm, and the thickness of gold may be about 0.1 μm.

  Next, a resist material is applied on the seed layer 305 and exposed using a mask having a desired pattern to form a resist pattern having an opening at a desired location, and exposed to the opening of the resist pattern. A gold pattern is formed on the seed layer 305 by plating, and then the resist pattern is removed, so that the first metal pattern 306 is formed as shown in FIG. Subsequently, by repeating the same process, the second metal pattern 307 is formed. The second metal pattern 307 is formed to be thicker than the first metal pattern 306.

  For example, when the first metal pattern 306 is formed, the resist pattern serving as a mask may be about 1 μm thick and the plating film may be formed to a thickness of about 0.3 μm. Further, when the second metal pattern 307 is formed, the resist pattern serving as a mask may have a thickness of about 1 μm and the plating film may be formed in a thickness of about 0.6 μm.

  Thereafter, the seed layer 305 is removed by etching using the first metal pattern 306 and the second metal pattern 307 as a mask, so that the first metal pattern 306 and the second metal pattern 307 are separated on the interlayer insulating layer 304. For example, gold over the seed layer 305 may be wet-etched with an etching solution made of iodine, ammonium iodide, water, and ethanol. The titanium under the seed layer 305 exposed by this etching can be wet-etched with a hydrogen fluoride aqueous solution.

  Next, as shown in FIG. 5D, a sacrificial layer 308 is formed on the interlayer insulating layer 304 with the first metal pattern 306 covered and the upper surface of the second metal pattern 307 exposed. State. For example, the sacrificial layer 308 can be formed by applying a photosensitive organic resin made of PBO (polybenzoxazole) to form a coating film, and patterning the formed coating film by a known lithography technique. In the patterning process for forming the sacrificial layer 308, pre-baking at 120 ° C. is performed for about 4 minutes as pre-processing, and heat processing at about 310 ° C. is performed after patterning, so that the organic resin film is thermally cured. As the organic resin, CRC8300 manufactured by Sumitomo Bakelite Co., Ltd. can be used.

  Next, in the same manner as the seed layer 305, a new seed layer is formed, and the same lithography process and plating method as the first metal pattern 306 and the second metal pattern 307 are performed. As shown in FIG. 5E, the third metal pattern 309 having a thickness of about 0.3 μm and the fourth metal pattern 310 having a thickness of about 0.6 μm are obtained by selective etching of the seed layer using the metal pattern as a mask. Is formed.

  The third metal pattern 309 is connected to a part of the second metal pattern 307 and becomes a part of the movable structure constituting the MEMS element. The 4th metal pattern 310 arrange | positioned around the 3rd metal pattern 309 comprises the 2nd metal pattern 307 arrange | positioned under this, and comprises a side wall frame. Further, the other fourth metal pattern 310 is connected and disposed on a part of the second metal pattern 307 and constitutes a fixed element. Next, in the same manner as described with reference to FIG. 5D, the third metal pattern 309 is covered and the upper surface of the fourth metal pattern 310 is exposed as shown in FIG. The sacrificial layer 311 is formed on the sacrificial layer 308.

  Next, in the same manner as the seed layer 305, a new seed layer is formed, and the same lithography process and plating method as the formation of each metal pattern and a seed using the formed metal pattern as a mask. As shown in FIG. 5G, a plurality of metal layers 312 and metal patterns 314 are formed by selective etching of the layers. The plating thickness may be about 1 μm. An opening 313 is formed in some of the metal layers 312, and the metal layer 312 having the openings 313 serves as a ceiling wall. For example, the plurality of openings 313 may be arranged in a lattice pattern.

  As described above, the movable structure made of the third metal pattern 309 connected to a part of the second metal pattern 307, the side wall frame made of the second metal pattern 307 and the fourth metal pattern 310 surrounding them, A state in which the MEMS element formed by the ceiling wall made of the metal layer 312 having the opening 313 formed on the semiconductor substrate 301 is obtained is obtained. A movable structure will be in the state arrange | positioned in the space in the container which consists of a side wall frame and a ceiling wall. In addition, a state in which a fixing element including a part of the second metal pattern 307, the fourth metal pattern 310, and the metal pattern 314 is formed on the semiconductor substrate 301 is obtained.

  Next, ozone is applied to the sacrificial layer 308 and the sacrificial layer 311 using, for example, an ozone asher device, and the sacrificial layer 308 and the sacrificial layer 311 are removed. Each sacrificial layer in the closed space surrounded by the side wall frame made of the second metal pattern 307 and the fourth metal pattern 310 below the metal layer 312 can be removed by applying ozone through the opening 313. After that, as shown in FIG. 6H, the sealing insulating layer 315 is attached to the metal layer 312 so that the MEMS element 106 connected to the semiconductor integrated circuit 302 by the electrode portion 303 and A state in which the fixed element 107 is formed on the interlayer insulating layer 304 is obtained. Each element functions as, for example, a passive element.

  In addition, since the opening 313 of the metal layer 312 is blocked by the sealing insulating layer 315, the space surrounded by the side wall frame including the second metal pattern 307 and the fourth metal pattern 310 under the metal layer 312 is It will be in the sealed state. Note that the sealing insulating layer 315 may be formed by patterning an insulating film attached by, for example, an STP (spin-coating film transfer and hot pressing: see Non-Patent Document 6) method. The insulating film to be attached may be a film made of an organic material having a thickness of about 5 μm, for example. Alternatively, the insulating film may be formed by applying a resin. Alternatively, the insulating film may be formed by chemical vapor deposition. Further, instead of the insulating film, a conductive film such as a metal may be used so as to close the opening 313 of the metal layer 312.

  Next, as illustrated in FIG. 6I, a resin insulating layer 316 having a thickness of about 20 μm is formed so as to cover the MEMS element 106 and the fixed element 107. The resin insulating layer 316 can be formed by applying a photosensitive organic resin made of PBO. Next, the resin insulating layer 316 is patterned by a known photolithography technique to form a through hole 316a that penetrates to a predetermined electrode portion 303 as shown in FIG. 6 (j). After the through-hole 316a is formed, a heat treatment at about 310 ° C. is performed so that the organic resin constituting the resin insulating layer 316 is in a thermoset state.

  Next, after forming a seed layer by plating on the surface of the resin insulating layer 316 including the bottom of the through hole 316a, a resist pattern having an opening is formed in the through hole 316a, and the resist pattern is selected as the opening. Thus, a plating film is formed. The plating film is formed to a thickness of about 20 μm, and the through hole 316a is filled with the formed plating film.

  Next, after removing the resist pattern, it is flattened by a known CMP (Chemical Mechanical Policing) method to form a metal post 317 as shown in FIG. After removing the resist pattern, the seed layer exposed in the region where the plating film is not formed may be removed by wet etching similar to that described above, and then planarized by CMP. Thereafter, as shown in FIG. 6L, a bump 318 made of, for example, gold or a solder material may be formed on the metal post 317. The bump 318 can be formed by, for example, a stud method or a plating method. Thereafter, each chip region is cut out from the semiconductor substrate 301 to obtain a chip component (semiconductor device) state.

  As described above, a chip component in which a plurality of MEMS elements are monolithically mounted together with an integrated circuit can be easily formed by a series of semiconductor manufacturing processes. Further, the MEMS element can be sealed and packaged by a consistent manufacturing process of the wafer state.

  Next, another example of the manufacturing method will be described. First, in the same manner as the above-described steps of FIGS. 5A to 5D, as shown in FIG. 7A, a semiconductor integrated circuit 402, an electrode portion 403, and an interlayer insulation are formed on a semiconductor substrate 401. After the layer 404, the first metal pattern 405, the second metal pattern 406, and the sacrificial layer 407 are formed, the insulating pattern 408 and the third metal pattern 409 are formed as shown in FIG. 7B. It is assumed that

  The formation of the insulating pattern 408 will be described. First, after a titanium film (film thickness: 0.1 μm) is formed on the sacrificial layer 407 by, for example, sputtering, a silicon oxide film (film thickness) is formed by, for example, sputtering. 0.3 μm) is formed. Next, the insulating pattern 408 can be formed by processing the silicon oxide film into a pattern by a known photolithography technique and a dry etching method, and etching the titanium layer using this pattern as a mask. The titanium layer can be processed by etching using an aqueous hydrogen fluoride solution as an etchant. The third metal pattern 409 is the same as the formation of each metal pattern described above. The third metal pattern 409 may be formed with a film thickness of about 0.4 μm, for example.

  Next, in the same manner as described with reference to FIG. 5D, the sacrificial layer 407 is formed in a state where the upper surfaces of the insulating pattern 408 and the third metal pattern 409 are exposed as shown in FIG. 7C. It is assumed that the sacrificial layer 410 is formed thereon. Next, in the same manner as the formation of the insulating pattern 408 and the third metal pattern 409, the insulating pattern 411 and the fourth metal pattern 412 are formed as shown in FIG. The sacrificial layer 413 is formed in the same manner as the sacrificial layer 410. Next, as shown in FIG. 7E, a fifth metal pattern 414 is formed and a sacrificial layer 415 is formed.

  Next, in the same manner as described with reference to FIG. 5G, a plurality of metal layers 416 and metal patterns 417 are formed as shown in FIG. A plurality of openings are formed in the metal layer 416 similarly to the metal layer 312. Thereafter, in the same manner as described with reference to FIG. 6, the movable structure including the third metal pattern 409 connected to a part of the second metal pattern 406, the second metal pattern 406, the third metal pattern 406 surrounding them, A MEMS element composed of a side wall frame made of the metal pattern 409, the fourth metal pattern 412 and the fifth metal pattern 414 and a ceiling wall made of the metal layer 416 formed thereon is formed on the semiconductor substrate 401. The obtained state is obtained. A movable structure will be in the state arrange | positioned in the space in the container which consists of a side wall frame and a ceiling wall, for example in the state provided with the insulating pattern 408 in the contact part. In addition, a fixing element including a part of the second metal pattern 406, the third metal pattern 409, the fourth metal pattern 412, the fifth metal pattern 414, and the metal pattern 417 is formed on the semiconductor substrate 401. Is obtained.

It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. 4 is a cross-sectional view schematically showing an example in which a chip component 112 is mounted on a mounting substrate 111. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. 10 is a perspective view showing a package state of a MEMS element disclosed in Patent Document 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate, 102 ... Integrated circuit, 103 ... Electrode pad, 104 ... Connection pad, 105 ... Component pad, 106 ... MEMS element, 106a ... Side wall frame, 106b, 106c ... Movable structure, 106d ... Ceiling wall, 107 ... fixing element, 108 ... resin insulating layer, 109 ... metal post.

Claims (3)

A step of forming a semiconductor integrated circuit having a circuit function including signal processing on a semiconductor substrate;
Forming a first passive element connected to the semiconductor integrated circuit on the semiconductor substrate; and
A step of forming a side wall frame surrounding a predetermined region on the semiconductor substrate and a second passive element disposed in the side wall frame and connected to the semiconductor integrated circuit;
Forming a ceiling wall facing the surface of the semiconductor substrate on the side wall frame, and placing the second passive element in a container composed of the side wall frame and the ceiling wall;
A step of embedding the first passive element and the second passive element to form a resin insulating layer having a flat top surface over the entire area of the semiconductor substrate;
And a step of forming a terminal for connection with the outside on the upper surface of the resin insulating layer. In the manufacturing method of the semiconductor device according to claim 1 ,
A first step of forming an interlayer insulating layer on the semiconductor integrated circuit after the semiconductor integrated circuit is formed on the semiconductor substrate;
A second step in which a first seed layer is formed on the interlayer insulating layer;
Etching using the first metal pattern and the second metal pattern as a mask after the first metal pattern and the second metal pattern thicker than the first metal pattern are formed on the first seed layer by plating. A third step of selectively removing the seed layer by:
A first sacrificial layer made of an organic resin is formed on the interlayer insulating layer in a state where the first metal pattern is covered with the second metal pattern being embedded with a part of the second metal pattern exposed. A fourth step of forming a state;
A fifth step in which a second seed layer is formed on the first sacrificial layer including the exposed portion of the second metal pattern;
Etching using the third metal pattern and the fourth metal pattern as a mask after the third metal pattern and the fourth metal pattern thicker than the third metal pattern are formed on the second seed layer by plating. A sixth step of selectively removing the second seed layer by:
A second sacrificial layer made of an organic resin on the first sacrificial layer in a state where the third metal pattern is covered with the fourth metal pattern being buried and a part of the fourth metal pattern is exposed. A seventh step in which is formed;
An eighth step in which a third seed layer is formed on the second sacrificial layer including the exposed portion of the fourth metal pattern;
After the metal layer having a plurality of openings and the fifth metal pattern are formed by plating, the third seed layer is selectively formed by etching using the metal layer and the fifth metal pattern as a mask. A ninth step of removing it;
A tenth step of removing the first sacrificial layer and the second sacrificial layer;
An eleventh step in which a sealing insulating layer is formed on the metal layer so as to close the opening;
The first metal pattern, the second metal pattern, the third metal pattern, the fourth metal pattern, the fifth metal pattern, the metal layer, and the sealing insulating layer are embedded on the interlayer insulating layer. A twelfth step in which the resin insulating layer is formed in a state where the upper surface is flat over the entire area of the semiconductor substrate;
And at least a thirteenth step in which a terminal connected to the semiconductor integrated circuit through the resin insulating layer is formed on an upper surface of the resin insulating layer.
The second metal pattern is composed of a frame-shaped portion that surrounds a region where the first metal pattern is formed, and an internal portion arranged inside the frame-shaped portion,
The fourth metal pattern includes a portion that is disposed on the frame-shaped portion of the second metal pattern and is formed in a frame shape, and constitutes a frame-shaped portion of the second metal pattern and a side wall frame,
The third metal pattern is formed connected to an inner part of the second metal pattern,
The metal layer is disposed on the side wall frame as a ceiling wall,
The first metal pattern and the third metal pattern are arranged inside a container constituted by the side wall frame and the ceiling wall,
The method of manufacturing a semiconductor device, wherein the first sacrificial layer and the second sacrificial layer disposed inside the container are removed by etching through the opening. In the manufacturing method of the semiconductor device according to claim 1 ,
A first step of forming an interlayer insulating layer on the semiconductor integrated circuit after the semiconductor integrated circuit is formed on the semiconductor substrate;
A second step in which a first seed layer is formed on the interlayer insulating layer;
Etching using the first metal pattern and the second metal pattern as a mask after the first metal pattern and the second metal pattern thicker than the first metal pattern are formed on the first seed layer by plating. A third step of selectively removing the seed layer by:
A first sacrificial layer made of an organic resin is formed on the interlayer insulating layer in a state where the first metal pattern is covered with the second metal pattern being embedded with a part of the second metal pattern exposed. A fourth step of forming a state;
A fifth step in which a first insulating pattern is formed on top of the first metal pattern of the first sacrificial layer;
After the second seed layer is formed on the first sacrificial layer including the exposed portion of the second metal pattern, the third metal pattern is formed on the second seed layer by plating. A sixth step in which the second seed layer is selectively removed by etching using the third metal pattern as a mask; and
A seventh step in which a second sacrificial layer made of an organic resin is formed on the first sacrificial layer in a state where the space between the first insulating pattern and the third metal pattern is buried and the upper surfaces thereof are exposed; ,
An eighth step in which the second insulating pattern is formed on the exposed part of the third metal pattern;
After the third seed layer is formed on the second sacrificial layer including the exposed portion of the third metal pattern, a fourth metal pattern is formed by plating using the third metal pattern and the second metal pattern. A ninth step in which the third seed layer is selectively removed by etching using the fourth metal pattern as a mask;
A tenth step in which a third sacrificial layer made of an organic resin is formed on the second sacrificial layer in a state where the space between the second insulating pattern and the fourth metal pattern is buried and the upper surfaces thereof are exposed; ,
After the fourth seed layer is formed on the third sacrificial layer including the exposed portions of the second insulating pattern and the fourth metal pattern, a part of the fifth metal pattern is formed by plating. An eleventh step in which the fourth seed layer is formed on the fourth metal pattern and the fourth seed layer is selectively removed by etching using the fifth metal pattern as a mask;
A twelfth step in which a fourth sacrificial layer made of an organic resin is formed on the third sacrificial layer in a state where the space between the fifth metal patterns is buried and the upper surface is exposed;
After the fifth seed layer is formed on the fourth sacrificial layer including the portion of the fifth metal pattern, a metal layer having a plurality of openings and a sixth metal pattern are formed by plating. A thirteenth step in which the fifth seed layer is selectively removed by etching using the metal layer and the sixth metal pattern as a mask,
A fifteenth step of removing the first sacrificial layer, the second sacrificial layer, the third sacrificial layer, and the fourth sacrificial layer;
A sixteenth step in which a sealing insulating layer is formed on the metal layer so as to close the opening;
The first metal pattern, the second metal pattern, the third metal pattern, the fourth metal pattern, the fifth metal pattern, the sixth metal pattern, the metal layer, and the sealing insulating layer are embedded. A seventeenth step in which the resin insulating layer is formed in a state where the upper surface is flat over the entire area of the semiconductor substrate above the interlayer insulating layer;
And at least an eighteenth step in which a terminal connected to the semiconductor integrated circuit through the resin insulating layer is formed on the upper surface of the resin insulating layer.
The second metal pattern, the third metal pattern, and the fourth metal pattern include a frame-shaped portion that surrounds an area where the first metal pattern is formed, and an internal portion that is disposed inside the frame-shaped portion. Consisting of
The fifth metal pattern includes a portion that is disposed on a frame-like portion of the fourth metal pattern and is formed in a frame shape, and includes a second metal pattern, a third metal pattern, and a fourth metal pattern. Configure the frame-shaped part and the side wall frame,
The metal layer is disposed on the side wall frame as a ceiling wall,
The second metal pattern, the third metal pattern, and the inner portion disposed inside the frame-shaped portion of the fourth metal pattern and the first metal pattern are configured by the side wall frame and the ceiling wall. Placed inside the container,
The first sacrificial layer, the second sacrificial layer, the third sacrificial layer, and the fourth sacrificial layer disposed inside the container are removed by etching through the opening. A method for manufacturing a semiconductor device.

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