JP4323435B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a MEMS element sealed together with an integrated circuit, and a manufacturing method thereof.

  Various micromachines manufactured on a silicon substrate are widely used in various application fields (see Non-Patent Document 1). Silicon can be obtained in large quantities at low cost, and it can be easily miniaturized while maintaining extremely high dimensional accuracy and processing accuracy by micromachining technology based on LSI manufacturing technology. In addition, mass production is possible. Therefore, development of micromachines using silicon has been actively conducted. In recent years, a technical field called MEMS (MicroElectro Mechanical System) technology has been created, and in addition to the application fields described in Non-Patent Document 1, the present invention is also applied to various fields such as sensors, medical care, optical communication, and wireless communication. Applications are spreading.

  In particular, MEMS (called RFMEMS) that processes high-frequency signals such as radio signals has been extensively researched and developed. There are many types of RFMEMS elements such as inductors, switches, variable capacitors, resonators, filters, transmission lines, antennas, and the like. In the RF MEMS technology that has been widely studied in this way, a plurality of MEMS elements are integrated and a semiconductor integrated circuit is integrated to realize a complicated circuit function, and the sealing and packaging for mounting the MEMS element are low. Cost reduction is desired.

  For example, a technique has been proposed in which a semiconductor integrated circuit and a plurality of MEMS elements are mounted on the same substrate to enable an integrated transceiver (one-chip transceiver) for wireless communication (see Non-Patent Document 2). According to this technology, it is possible to reduce the number of parts, the mounting cost, mass production by batch processing, and the like, and the radio transceiver can be reduced in size and cost. However, only the concept of integration is proposed in Non-Patent Document 2, and in a wireless communication application, a device in which a semiconductor integrated circuit and a plurality of MEMS elements are integrated on the same substrate is realized. It has not been.

  Regarding the sealing and packaging method, first, there is a CSP (chip size packaging) technique as a small packaging technique for semiconductor integrated circuits (see Patent Document 1, Patent Document 2, and Patent Document 3). ). As a MEMS element sealing technique, there is a method in which individual MEMS elements manufactured on a substrate are cut out from the substrate and then sealed for each element (see Patent Document 4). In addition, there is a method in which MEMS elements are collectively sealed in a substrate state and then cut into individual MEMS elements.

  Here, the above-described CSP technology will be described. This is one of the small packaging technologies for semiconductor integrated circuits, and is a generic name for technologies for packaging integrated circuits fabricated on a semiconductor wafer with approximately the same size as a chip. is there. Patent Document 1 discloses a CSP technology in which another substrate on which circuit wiring for packaging is manufactured is bonded to a wafer on which a semiconductor integrated circuit is manufactured, the bonded wafer and the substrate are ground, and then the wafer is cut into chips. It is shown. Patent Documents 2 and 3 describe CSP technology in which an insulating layer and a wiring layer having a desired pattern are stacked on a wafer on which a semiconductor integrated circuit is manufactured, and a packaging structure is formed in the wafer state. Has been.

  Hereinafter, the technique disclosed in Patent Document 2 will be described. As shown in FIG. 8, first, a circuit element formation region 502 made of an integrated circuit is provided on a silicon substrate 501, and connection pads 503 are provided outside these. Both are connected by wiring 503a. In addition, an insulating layer 504 and a protective film 505 are formed thereon, and a lead-out wiring 507 is formed from the opening 506 provided on the connection pad 503 to the upper surface of the protective film 505. A connection pad portion 507a is provided in part. In addition, a columnar electrode (metal post) 508 is formed on the connection pad portion 507a, and a sealing film 509 made of epoxy resin or the like is formed on the entire area of the silicon substrate 501 so that the upper surface of the electrode 508 is exposed. Is formed. After forming such a configuration, the silicon substrate 501 is cut into individual chips, and in Patent Document 2, a semiconductor component packaged in the same size as the chip is obtained.

  As described above, the conventional CSP manufacturing technology described above is a technology aimed at obtaining a smaller package at a lower cost with respect to a normal semiconductor device that is not integrated with a MEMS element. Technical requirements are not considered for integrating the MEMS element and the integrated circuit. In the techniques disclosed in Patent Documents 1, 2, and 3 described above, it is very difficult to integrate the MEMS element with an integrated circuit and to form a CSP having the same size as a semiconductor chip.

  Next, a description will be given of a conventional technique related to sealing of a MEMS element. As shown in Patent Document 4, the MEMS element is sealed by a technique similar to a well-known hermetic seal (hermetic seal). There is a technology for packaging and mounting. In this technique, as shown in FIG. 9, a fixed substrate 601 in which signal lines and fixed electrodes are formed on a glass substrate, and a movable substrate in which movable electrodes, beams and anchors made from a silicon substrate are integrally formed. 602 and the package. The movable substrate 602 operates as an electrostatic micro relay (switch).

  The movable substrate 602 is fixed to the fixed substrate 601 by anodic bonding, and a cap member 603 is fixed to the fixed substrate 601 by anodic bonding at the outer peripheral portion of the movable substrate 602, and from the fixed substrate 601 and the cap member 603. The movable substrate 602 is sealed in the configured container. In this case, after manufacturing the MEMS element on the substrate, in order to protect minute movable parts from damage in the process of cutting out the element for mounting and handling of the cut out element, handling with great care is required. In the inspection after mounting, it is necessary to guarantee the quality of each element.

  As a result, the technique disclosed in Patent Document 4 inevitably increases the size of components, and it is very difficult to apply a small package technique such as CSP. Furthermore, in order to realize a circuit function by combining a plurality of MEMS elements having different functions, the individual MEMS elements are individually sealed and then mounted on a mounting board. In some cases, the overall dimensions are inevitably increased, and there is a limit to downsizing after mounting as a whole.

  Next, a conventional technique for collectively sealing the MEMS elements in a wafer state will be described. For example, in Non-Patent Document 3, a space is formed in a glass substrate, a SAW (Surface Acoustic Wave) element is built in the formed space, a new glass substrate is bonded thereto, and then cut into individual chips and sealed. The SAW chip in a stopped state is obtained.

  In Non-Patent Document 4, after manufacturing a MEMS element on a wafer, another substrate (sealing chip) for sealing is prepared, and the periphery of the MEMS element is surrounded on the sealing chip. A shaped BCB (benzocyclobutene) film is formed as a frame pattern, a sealing chip on which the frame pattern is formed is affixed to the wafer with a flip chip, and a MEMS element formed on the wafer is sealed After that, it is cut out into individual chips.

  In Non-Patent Document 5, after a MEMS element is fabricated on a wafer, the MEMS element is covered with a small cap that is slightly larger than the fabricated element, and a material called LCP (Liquid Crystal Polymer) is formed thereon. A film is formed by deposition, solidified and sealed, and then cut into individual chips.

  However, these methods require a special dedicated process for sealing the MEMS element, and it is very difficult to reduce the manufacturing cost including the mounting of the chip provided with the MEMS element.

The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
Japanese Patent No. 29898898 Japanese Patent No. 3465617 Japanese Patent No. 3540729 JP 2000-311572 A KEPetersen, “Silicon as a mechanical materia1”, Proc. IEEE, Vol.70, No.5, pp.420-457, May 1982. Clark T.-C.Nguyen, LPBKatehi, and GMRebeiz, "Micromachined Devices for Wireless Communications", IEEE Proceeding, vol.86, No.8, pp.1756-1768, Aug. 1998. D. Ando, K. Oishi, T. Nakamura, and S. Umeda, "Glass direct bonding technology for hermetic seal package", IEEE 10th Int. Wiorkshop on Micro Electro Mechanical Systems, pp. 186-190, Jan. 1997. A. Jourdain, P. De Moor, S. Pamidighantam, and ACTilmans, "Investigation of the hermeticity of BCB-sealed cavities for housing (RF-) MEMS devices", 15th IEEE Int. Conf. Micro Electro Mechanical Systems, pp. 677 -680, Jan. 2002. FFFaheem, KCGupta, and Y.-C.Lee, "Flip-chip assembly and liquid crystal polymer encapsulation for variable MEMS capacitors", IEEE Trans. Microwave Theory and Tech., Vol.51, No.12, pp.2562-2567 , Dec. 2003. Saito, Kosugi, Yamaguchi, Kudo, Yano, Yagi, Ishii, Machida, Kuraki, “On-Chip Thick Film Wiring by Cu Damascene Process Using Photosensitive Resin”, IEICE Transactions C, Vol. J85-C , No.3, pp.187-195, March 2002. N.Sato, H.Ishii, S.Shigematu, H.Morimura, T.Kamei, K.Kudou, M.Yano, K.Machida, H.Kyuragi, "A sealing technique for stacking MEMS on LSI using spin-coating film transfer and hot pressing ", Jpn.J.App1.Phys., Vol.42, Part 1, No.4B, pp.2462-2467, Apr.2003.

  As described above, for example, in wireless communication applications, there is no technology that integrates and integrates a plurality of MEMS elements and a semiconductor integrated circuit and realizes a small package such as a CSP. Moreover, in order to mount these, there existed a problem that it was not easy with the prior art to implement | achieve sealing and packaging at low cost.

  The present invention has been made in order to solve the above-described problems, and the object of the present invention is to form an LSI or the like in a different form of an element composed of a fine structure such as a MEMS element. An object of the present invention is to provide a semiconductor device that is monolithically mounted on a semiconductor substrate and is in a smaller package state.

  A semiconductor device according to the present invention includes a semiconductor integrated circuit formed on a semiconductor substrate and having a circuit function including signal processing, a first passive element formed on the semiconductor substrate and connected to the semiconductor integrated circuit, A container having a ceiling wall formed on a semiconductor substrate and facing a surface of the semiconductor substrate, and a side wall for supporting the ceiling wall on the semiconductor substrate, and movable on the semiconductor substrate inside the container And a second passive element connected to the semiconductor integrated circuit, and connected to at least one of the semiconductor integrated circuit, the first passive element, and the second passive element on the semiconductor substrate, An electrode formed together with the passive element, a resin insulating layer formed in the entire area of the semiconductor substrate by embedding the first passive element and the container, and a through electrode penetrating through the resin insulating layer disposed on and connected to the electrode Shaped on top of the resin insulation layer Connected to the through electrode, a protective film formed so as to cover the reconnected wiring, and a part of the surface of the protective film exposed to be connected to the outside connected to the reconnected wiring And at least a terminal for performing the operation.

  According to the semiconductor device described above, the inside of the container is sealed with the resin insulating layer, and the upper surface side of the protective film provided with the terminals is the mounting surface. Further, the terminals can be arranged on the upper surface side of the protective film on the region where each passive element is arranged by using the reconnection wiring. A first terminal and a second terminal formed on the protective film and connected to the outside connected to the reconnection wiring, and a bump made of a conductive material formed on the first terminal. You may make it prepare.

  Further, the semiconductor device may include a third passive element configured from a part of the reconnection wiring, and the third passive element has a spiral shape configured as a part of the reconnection wiring. An inductor may be used, and a ground conductor formed of a part of the reconnection wiring may be provided.

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor integrated circuit having a circuit function including signal processing on a semiconductor substrate, and a semiconductor integrated circuit connected to the semiconductor integrated circuit on the semiconductor substrate. A step of forming a first passive element, a side wall frame surrounding a predetermined region on the semiconductor substrate, and a second passive element provided in the side wall frame and connected to the semiconductor integrated circuit and having a movable part And a step of forming a ceiling wall facing the surface of the semiconductor substrate on the side wall frame, and a state in which the element is disposed in a container composed of the side wall frame and the ceiling wall, and A state in which the resin insulating layer in which the first passive element and the second passive element are embedded is formed over the entire area of the semiconductor substrate, and a state in which a through electrode that is connected to the electrode and penetrates the resin insulating layer is formed And contact with the through electrode A step of forming a reconnection wiring on the resin insulating layer, a step of forming a protective film covering the reconnection wiring, and connecting the reconnection wiring to the outside The terminal includes at least a step of forming a state in which the terminal is partially exposed on the surface of the protective film.

In the semiconductor device manufacturing method, after the semiconductor integrated circuit is formed on the semiconductor substrate, the interlayer insulating layer is formed on the semiconductor integrated circuit, and the interlayer insulating layer is formed on the interlayer insulating layer. After the second step in which the first seed layer is formed and the first metal pattern and the thicker second metal pattern are formed on the first seed layer by the plating method, A third step in which the seed layer is selectively removed by etching using the first metal pattern and the second metal pattern as a mask; and a state in which a portion of the second metal pattern is exposed between the second metal patterns. In the fourth step, the first sacrificial layer made of an organic resin is formed on the interlayer insulating layer in the state where the first metal pattern is covered, and the exposed second metal pattern portion is included. On one sacrificial layer After the fifth step in which the two seed layers are formed and the third metal pattern and the fourth metal pattern thicker than the fifth metal pattern are formed on the second seed layer by plating, the third step is performed. A sixth step in which the second seed layer is selectively removed by etching using the metal pattern and the fourth metal pattern as a mask, and a part of the fourth metal pattern is exposed between the fourth metal pattern and embedded. A seventh step of forming a second sacrificial layer made of an organic resin on the first sacrificial layer in a state where the third metal pattern is covered in a state, and an exposed portion of the fourth metal pattern After the eighth step in which the third seed layer is formed on the second sacrificial layer and the plating method, the metal layer having a plurality of openings and the fifth metal pattern are formed, Metal layer and fifth metal pattern A ninth step in which the third seed layer is selectively removed by etching using the mask; a tenth step in which the first sacrificial layer and the second sacrificial layer are removed; and An eleventh step in which a sealing insulating layer is formed so as to close the opening; a first metal pattern, a second metal pattern, a third metal pattern, a fourth metal pattern, a fifth metal pattern, a metal layer, and A twelfth step in which the resin insulating layer is formed over the entire area of the semiconductor substrate above the interlayer insulating layer so that the sealing insulating layer is embedded; and the through electrode connected to the semiconductor integrated circuit is formed of the resin insulating layer A thirteenth step for forming a through-hole, a fourteenth step for forming a reconnection wiring connected to the through electrode on the resin insulating layer, and a resin so that the reconnection wiring is covered A protective film is formed on the insulating layer At least a fifteenth step and a sixteenth step in which a terminal connected to the reconnection wiring is formed in a state where a part of the terminal is exposed on the surface of the protective film. A frame-shaped portion surrounding a region where the first metal pattern is formed, an inner portion disposed inside the frame-shaped portion, and a portion serving as a first passive element . A frame-shaped portion disposed on the frame-shaped portion of the second metal pattern and a portion serving as a first passive element; and a frame-shaped portion of the fourth metal pattern and a frame of the second metal pattern The third metal pattern is formed by connecting to the inner part of the second metal pattern and becomes a part of the movable part constituting the second passive element, and the metal layer is formed on the ceiling. The first metal pattern and the third gold are arranged on the side wall frame as a wall. Pattern is located within the container made of the side wall frame and the ceiling wall, a portion serving as the first passive element of the second metal pattern, a portion to be the first passive element of the fourth metal pattern, fifth The first and second sacrificial layers constituting the first passive element and the metal pattern may be removed by etching through the opening.

  As described above, according to the present invention, the interior of the container including the ceiling wall and the side wall includes the second passive element that includes the movable part and is connected to the semiconductor integrated circuit. Since the upper surface side of the protective film provided with the terminals provided via the reconnection wiring is in a state of being sealed by the resin insulating layer, it is a mounting surface, so that different forms configured from fine structures such as MEMS elements A semiconductor device in which these elements are monolithically mounted together with an integrated circuit can be handled in the same manner as a general semiconductor component and can be mounted in the same manner.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 3 are process diagrams showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1A, a semiconductor integrated circuit 102 having a circuit function including signal processing is formed on a semiconductor substrate 101 such as a silicon wafer by a known semiconductor integrated circuit manufacturing technique. The electrode pad 103 is formed around the periphery. The electrode pad 103 is a terminal for connection to the outside during mounting. Further, a connection pad 104 for connecting to a MEMS element described later is formed in a predetermined region.

  The connection pad 104 is a terminal for connecting the MEMS element and the semiconductor integrated circuit 102, and may be formed to have a dimension that allows connection to the MEMS element. 1 and 2 show one chip region, these are perspective views showing portions. The semiconductor substrate 101 extends to a region not shown, and a plurality of chips are simultaneously formed thereon.

  Next, as shown in FIG. 1B, the metal movable structures 106b and 106c surrounded by the metal side wall frame 106a and the fixed element 107 made of the fixed structure are integrated into the integrated circuit by the connection pads. It is assumed that it is formed on the semiconductor substrate 101 in a connected state. In FIG. 1B and subsequent figures, connection pads and integrated circuits are not shown. The movable structures 106b and 106c are, for example, switch elements, variable capacitance elements, resonators, mechanical filters, and the like. The fixed element 107 is, for example, an inductor element, a transmission line, an antenna element, an impedance matching element, or the like. In FIG. 1B, a spiral inductor element is shown as the fixed element 107. The side wall frame 106a may be made of a material such as silicon oxide or silicon nitride.

  Next, as shown in FIG. 2C, a metal ceiling wall 106d is formed on the side wall frame 106a, and the MEMS element 106 is formed. On the semiconductor substrate 101, the inside of the side wall frame 106a is sealed with a space provided by the formed ceiling wall 106d. In the sealed space, the movable structures 106b and 106c are in an operable state. For example, after the ceiling wall 106d is disposed on the side wall frame 106a, an organic resin film can be used to seal a container composed of the side wall frame 106a and the ceiling wall 106d.

  The container composed of the side wall frame 106a and the ceiling wall 106d enables the movable structure to be sealed in an inert gas atmosphere such as a rare gas or in a vacuum, and is electrically affected by external noise or the like. Unwanted radiation can be shielded. The ceiling wall 106d may be made of a material such as silicon oxide or silicon nitride. However, by configuring the side wall frame 106a and the ceiling wall 106d from a metal material, it is possible to more effectively shield the influence of electrical external noise and the like and unnecessary radiation to the outside.

  Next, as shown in FIG. 2D, a columnar metal post (through electrode) 109 is formed on the electrode pad 103, and the MEMS element 106 and the fixing element 107 are made of a resin having a sufficient thickness. The state is covered with the insulating layer 108. The top surface of the resin insulating layer 108 is in a flat state with the top surface of the metal post 109 exposed. Next, as shown in FIG. 3E, the mounting pads 111 arranged on the inner side are reconnected by the reconnection wiring 110 connected to the metal post 109 in the portion exposed on the resin insulating layer 108. The metal post 109 (electrode pad 103) is connected via the wiring 110. The configuration shown in FIG. 3E shows an example in which the mounting pads 111 are arranged similar to a well-known BGA (ball grid array) package. After the mounting pad 111 is formed in this manner, as shown in FIG. 3F, the mounting pad 111 is exposed and the other film is covered and the protective film 112 is formed. And

  After each element is covered with the protective film 112 as described above, each chip region is cut out from the semiconductor substrate 101 by, for example, dicing, to obtain a chip component (semiconductor device) state. In the state of the chip component, the movable structures 106b and 106c that express the function of the MEMS element 106 are sealed by a container including the side wall frame 106a and the ceiling wall 106d. It is possible to handle. It should be noted that a plurality of movable structures may be arranged in one container constituted by the side wall frame 106a and the ceiling wall 106d.

  As described above, by rearranging the positions of the pads by the reconnection wiring 110, it becomes possible to arrange more mounting pads in a small chip size. Further, by changing the wiring pattern for rearrangement, the placement of the mounting pads in a state compatible with the existing package without changing the placement of the electrode pads 103 formed on the semiconductor substrate 101. Is feasible. In addition, as a pad arrangement, a test pad used for an operation test of a semiconductor device and a mounting pad used for mounting are prepared, and these pads and the pad 103 are connected by wiring for rearrangement. It is also possible to enter a state.

  For example, the test pads should be arranged to match the position of the probe used in the evaluation device for operation test, and the mounting pads should be arranged to be compatible with the BGA package. May be. If these pad arrangements are used, in the test evaluation, the test pads are used for inspection, and then bumps are formed on the mounting pads so that the BGA package can be mounted on a flip chip. It is easy to share. In flip chip mounting, a state in which the test pad is sealed is obtained by forming an underfill with a resin material in the gap between the chip and the mounting substrate. According to the pad arrangement exemplified above, it is possible to reduce the man-hours and required time until the package product is supplied.

  Next, a configuration example of another semiconductor device in this embodiment is described. FIG. 4 is a schematic cross-sectional view illustrating a configuration example of the semiconductor device according to the present embodiment. This semiconductor device includes, for example, a semiconductor integrated circuit 102 having a circuit function including signal processing on a semiconductor substrate 101 such as a silicon wafer by a known semiconductor integrated circuit manufacturing technique, and electrode pads 103 are provided around the semiconductor integrated circuit 102. I have. FIG. 4 is a perspective view showing a portion. The semiconductor substrate 101 extends to a region not shown, and a plurality of chips are simultaneously formed thereon. The electrode pad 103 is a terminal for connection to the outside during mounting. Further, a connection pad 104 for connecting to a MEMS element described later is formed in a predetermined region. The connection pad 104 is a terminal for connecting the MEMS element and the semiconductor integrated circuit 102, and is formed to a dimension that allows connection to the MEMS element.

  A region other than the electrode pad 103 and the connection pad 104 is covered with an insulating layer 205. On the insulating layer 205, the MEMS element 106 and the fixing element 107 shown in FIGS. Covered with a layer 108. A metal post 109 connected to the electrode pad 103 and the connection pad 104 is formed at a predetermined position of the resin insulating layer 108. The upper surface of the metal post 109 forms substantially the same plane as the upper surface of the resin insulating layer 108. A reconnection wiring 110 for connecting a predetermined metal post 109 is formed on the resin insulating layer 108 including the upper surface of the metal post 109, and a protective film is formed on the reconnection wiring 110 so as to cover them. 112 is formed. In addition, a mounting pad 111 is formed so as to connect to the reconnection wiring 110 and pass through the protective film 112 and exposed to the top. Although not shown, bumps may be formed on the mounting pads 111.

  According to the semiconductor device shown in FIG. 4, the semiconductor integrated circuit 102, the MEMS element 106, and the fixing element 107 are integrally formed and sealed on the semiconductor substrate 101. A state in which the wiring layer is formed on the substrate can be easily obtained. The semiconductor device having this configuration can be manufactured on the semiconductor substrate 101 by a manufacturing method described below as an example and in a consistent process while being in the wafer state.

  As shown in FIG. 4, by using the reconnection wiring 110, it becomes easy to form the pad structure 213 in which the mounting pads 111 are arranged at desired positions, and various types of reconnection wiring 110 are used. The circuit function can be realized. For example, the thick film inductor 214 can be realized by connecting the semiconductor integrated circuit 102 to the reconnection wiring 110 formed in a spiral shape via the metal post 109. According to the thick film inductor 214 formed in this way, an operation similar to that of the thick film inductor disclosed in Non-Patent Document 6 can be obtained, and a high performance inductor can be obtained.

  Further, when the reconnection wiring 110 is grounded via the mounting pad 111 and is connected to the semiconductor integrated circuit 102 by the metal post 109, the ground conductor 215 is formed. can do. With the configuration of the ground conductor 215, a good ground state can be obtained, and an external noise blocking state and a strong and stable ground potential can be obtained. Needless to say, the reconnection wiring 110 may be used as a normal wiring layer and a wiring may be formed on the MEMS element.

  Next, a method for manufacturing the above-described semiconductor device (chip component) will be described in more detail. First, as shown in FIG. 5A, a semiconductor integrated circuit 302 composed of a plurality of transistors, resistors, capacitors, wirings, and the like is formed on a semiconductor substrate 301 that is a silicon wafer by a known integrated circuit manufacturing process. It is assumed that it is formed. Further, an electrode portion 303 connected to a predetermined portion of a wiring layer (not shown) is formed on the semiconductor integrated circuit 302, and an interlayer insulating layer 304 made of, for example, silicon oxide or silicon nitride is formed thereon.

  Next, after a contact hole for connecting to a predetermined electrode portion 303 is formed in the interlayer insulating layer 304, a seed layer 305 is formed on the interlayer insulating layer 304 as shown in FIG. It is assumed that it is formed. The seed layer 305 may be formed, for example, by first depositing titanium and then depositing gold on the seed layer 305 by sputtering or vapor deposition. The thickness of titanium may be about 0.1 μm, and the thickness of gold may be about 0.1 μm.

  Next, a resist material is applied on the seed layer 305 and exposed using a mask having a desired pattern to form a resist pattern having an opening at a desired location, and exposed to the opening of the resist pattern. A gold pattern is formed on the seed layer 305 by plating, and then the resist pattern is removed, so that the first metal pattern 306 is formed as shown in FIG. Subsequently, by repeating the same process, the second metal pattern 307 is formed. The second metal pattern 307 is formed to be thicker than the first metal pattern 306.

  For example, when the first metal pattern 306 is formed, the resist pattern serving as a mask may be about 1 μm thick and the plating film may be formed to a thickness of about 0.3 μm. Further, when the second metal pattern 307 is formed, the resist pattern serving as a mask may have a thickness of about 1 μm and the plating film may be formed in a thickness of about 0.6 μm.

  Thereafter, the seed layer 305 is removed by etching using the first metal pattern 306 and the second metal pattern 307 as a mask, so that the first metal pattern 306 and the second metal pattern 307 are separated on the interlayer insulating layer 304. For example, gold over the seed layer 305 may be wet-etched with an etching solution made of iodine, ammonium iodide, water, and ethanol. The titanium under the seed layer 305 exposed by this etching can be wet-etched with a hydrogen fluoride aqueous solution.

  Next, as shown in FIG. 5D, a sacrificial layer 308 is formed on the interlayer insulating layer 304 with the first metal pattern 306 covered and the upper surface of the second metal pattern 307 exposed. State. For example, the sacrificial layer 308 can be formed by applying a photosensitive organic resin made of PBO (polybenzoxazole) to form a coating film, and patterning the formed coating film by a known lithography technique. In the patterning process for forming the sacrificial layer 308, pre-baking at 120 ° C. is performed for about 4 minutes as pre-processing, and heat processing at about 310 ° C. is performed after patterning, so that the organic resin film is thermally cured. As the organic resin, CRC8300 manufactured by Sumitomo Bakelite Co., Ltd. can be used.

  Next, in the same manner as the seed layer 305, a new seed layer is formed, and the same lithography process and plating method as the first metal pattern 306 and the second metal pattern 307 are performed. As shown in FIG. 5E, the third metal pattern 309 having a thickness of about 0.3 μm and the fourth metal pattern 310 having a thickness of about 0.6 μm are obtained by selective etching of the seed layer using the metal pattern as a mask. Is formed.

  The third metal pattern 309 is connected to a part of the second metal pattern 307 and becomes a part of the movable structure constituting the MEMS element. The 4th metal pattern 310 arrange | positioned around the 3rd metal pattern 309 comprises the 2nd metal pattern 307 arrange | positioned under this, and comprises a side wall frame. Further, the other fourth metal pattern 310 is connected and disposed on a part of the second metal pattern 307 and constitutes a fixed element. Next, in the same manner as described with reference to FIG. 5D, the third metal pattern 309 is covered and the upper surface of the fourth metal pattern 310 is exposed as shown in FIG. The sacrificial layer 311 is formed on the sacrificial layer 308.

  Next, in the same manner as the seed layer 305, a new seed layer is formed, and the same lithography process and plating method as the formation of each metal pattern and a seed using the formed metal pattern as a mask. As shown in FIG. 6G, a plurality of metal layers 312 and metal patterns 314 are formed by selective etching of the layers. The plating thickness may be about 1 μm. An opening 313 is formed in some of the metal layers 312, and the metal layer 312 having the openings 313 serves as a ceiling wall. For example, the plurality of openings 313 may be arranged in a lattice pattern.

  As described above, the movable structure made of the third metal pattern 309 connected to a part of the second metal pattern 307, the side wall frame made of the second metal pattern 307 and the fourth metal pattern 310 surrounding them, A state in which the MEMS element formed by the ceiling wall made of the metal layer 312 having the opening 313 formed on the semiconductor substrate 301 is obtained is obtained. A movable structure will be in the state arrange | positioned in the space in the container which consists of a side wall frame and a ceiling wall. In addition, a state in which a fixing element including a part of the second metal pattern 307, the fourth metal pattern 310, and the metal pattern 314 is formed on the semiconductor substrate 301 is obtained.

  Next, ozone is applied to the sacrificial layer 308 and the sacrificial layer 311 using, for example, an ozone asher device, and the sacrificial layer 308 and the sacrificial layer 311 are removed. Each sacrificial layer in the closed space surrounded by the side wall frame made of the second metal pattern 307 and the fourth metal pattern 310 below the metal layer 312 can be removed by applying ozone through the opening 313. After that, as shown in FIG. 6H, the sealing insulating layer 315 is attached to the metal layer 312 so that the MEMS element 106 connected to the semiconductor integrated circuit 302 by the electrode portion 303 and A state in which the fixed element 107 is formed on the interlayer insulating layer 304 is obtained. Each element functions as, for example, a passive element.

  In addition, since the opening 313 of the metal layer 312 is blocked by the sealing insulating layer 315, the space surrounded by the side wall frame including the second metal pattern 307 and the fourth metal pattern 310 under the metal layer 312 is It will be in the sealed state. Note that the sealing insulating layer 315 may be formed by patterning an insulating film attached by, for example, an STP (spin-coating film transfer and hot pressing: see Non-Patent Document 6) method. The insulating film to be attached may be a film made of an organic material having a thickness of about 5 μm, for example. Alternatively, the insulating film may be formed by applying a resin. Alternatively, the insulating film may be formed by chemical vapor deposition. Further, instead of the insulating film, a conductive film such as a metal may be used so as to close the opening 313 of the metal layer 312.

  Next, as illustrated in FIG. 6I, a resin insulating layer 316 having a thickness of about 20 μm is formed so as to cover the MEMS element 106 and the fixed element 107. The resin insulating layer 316 can be formed by applying a photosensitive organic resin made of PBO. Next, the resin insulating layer 316 is patterned by a known photolithography technique to form a through hole 316a that penetrates to a predetermined electrode portion 303 as shown in FIG. 6 (j). After the through-hole 316a is formed, a heat treatment at about 310 ° C. is performed so that the organic resin constituting the resin insulating layer 316 is in a thermoset state.

  Next, after forming a seed layer by plating on the surface of the resin insulating layer 316 including the bottom of the through hole 316a, a resist pattern having an opening is formed in the through hole 316a, and the resist pattern is selected as the opening. Thus, a plating film is formed. The plating film is formed to a thickness of about 20 μm, and the through hole 316a is filled with the formed plating film.

  Next, after removing the resist pattern, it is flattened by a known CMP (Chemical Mechanical Policing) method to form a metal post 317 as shown in FIG. After removing the resist pattern, the seed layer exposed in the region where the plating film is not formed may be removed by wet etching similar to that described above, and then planarized by CMP.

  As described above, a state where a plurality of MEMS elements are monolithically mounted together with an integrated circuit can be easily formed by a series of semiconductor manufacturing processes. Next, by forming the seed layer and the metal pattern by plating, the wiring 318 is formed on the resin insulating layer 316 as shown in FIG. Is assumed to have been removed. The film thickness of the metal pattern formed by the above-described plating may be about 2 μm. Next, the resin insulating layer 319 is formed so as to fill a region where the wiring 318 is not formed. The metal post 317 and the wiring 318 are formed by a well-known (see Non-Patent Document 6) dual damascene method after the resin insulating layer 316 and the resin insulating layer 319 having openings in these regions are formed. May be.

  Next, for example, a photosensitive organic resin made of PBO (polybenzoxazole) is applied to form a coating film, the formed coating film is patterned by a known lithography technique, and then heat-cured, whereby FIG. As shown in (m), the protective film 320 is formed. The protective film 320 should just be formed in the film thickness of about 5 micrometers. Next, the mounting pad 321 was formed by setting the metal film formed by plating on the opening of the protective film 320 and also by planarizing the metal film formed by CMP. State. In addition, bumps 322 may be formed on the mounting pads 321. The bump 322 can be formed by, for example, a stud method or a plating method. Moreover, the bump 322 should just be comprised from gold | metal | money and solder material, for example.

  Further, as shown in FIG. 7 (n), a test pad 321a connected to the wiring 318 may be formed. With the configuration shown in FIG. 7N, it is possible to perform flip-chip mounting with the bumps 322 after performing test evaluation using the test pads 321a.

It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is typical sectional drawing which shows the structural example of the semiconductor device in this Embodiment. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is process drawing which shows the example of the manufacturing method of the semiconductor device in embodiment of this invention. It is typical sectional drawing which shows the structural example of the conventionally sealed semiconductor device. It is a perspective view which shows the structural example of the conventionally sealed MEMS element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate, 102 ... Semiconductor integrated circuit, 103 ... Electrode pad, 104 ... Connection pad, 106 ... MEMS element, 106a ... Side wall frame, 106b, 106c ... Movable structure, 107 ... Fixed element, 108 ... Resin insulating layer, 109... Metal post, 110. Reconnection wiring, 111. Mounting pad, 112.

Claims (2)

A step of forming a semiconductor integrated circuit having a circuit function including signal processing on a semiconductor substrate;
Forming a first passive element connected to the semiconductor integrated circuit on the semiconductor substrate; and
A step of forming a side wall frame surrounding a predetermined region on the semiconductor substrate and a second passive element disposed in the side wall frame and connected to the semiconductor integrated circuit and including a movable part ;
Forming a ceiling wall facing the surface of the semiconductor substrate on the side wall frame, and placing the element in a container composed of the side wall frame and the ceiling wall;
A step of forming a resin insulating layer in which the first passive element and the second passive element are embedded in the entire region of the semiconductor substrate;
A step of forming a through electrode connected to the electrode and penetrating the resin insulating layer; and
A step of forming a reconnection wiring connected to the through electrode on the resin insulating layer;
A step of forming a protective film covering the reconnection wiring; and
A step of forming a terminal for connecting to the reconnection wiring and connecting to the outside in a state where a part of the terminal is exposed on the surface of the protective film. Method. In the manufacturing method of the semiconductor device according to claim 1 ,
A first step of forming an interlayer insulating layer on the semiconductor integrated circuit after the semiconductor integrated circuit is formed on a semiconductor substrate;
A second step in which a first seed layer is formed on the interlayer insulating layer;
Etching using the first metal pattern and the second metal pattern as a mask after the first metal pattern and the second metal pattern thicker than the first metal pattern are formed on the first seed layer by plating. A third step of selectively removing the seed layer by:
A first sacrificial layer made of an organic resin is formed on the interlayer insulating layer in a state where the first metal pattern is covered with the second metal pattern being embedded with a part of the second metal pattern exposed. A fourth step of forming a state;
A fifth step in which a second seed layer is formed on the first sacrificial layer including the exposed portion of the second metal pattern;
Etching using the third metal pattern and the fourth metal pattern as a mask after the third metal pattern and the fourth metal pattern thicker than the third metal pattern are formed on the second seed layer by plating. A sixth step of selectively removing the second seed layer by:
A second sacrificial layer made of an organic resin on the first sacrificial layer in a state where the third metal pattern is covered with the fourth metal pattern being buried and a part of the fourth metal pattern is exposed. A seventh step in which is formed;
An eighth step in which a third seed layer is formed on the second sacrificial layer including the exposed portion of the fourth metal pattern;
After the metal layer having a plurality of openings and the fifth metal pattern are formed by plating, the third seed layer is selectively formed by etching using the metal layer and the fifth metal pattern as a mask. A ninth step of removing it;
A tenth step of removing the first sacrificial layer and the second sacrificial layer;
An eleventh step in which a sealing insulating layer is formed on the metal layer so as to close the opening;
The first metal pattern, the second metal pattern, the third metal pattern, the fourth metal pattern, the fifth metal pattern, the metal layer, and the sealing insulating layer are embedded on the interlayer insulating layer. A twelfth step in which a resin insulating layer is formed over the entire area of the semiconductor substrate;
A thirteenth step in which a through electrode connected to the semiconductor integrated circuit is formed through the resin insulating layer;
A fourteenth step in which a reconnection wiring connected to the through electrode is formed on the resin insulating layer;
A fifteenth step in which a protective film is formed on the resin insulating layer so as to cover the reconnection wiring;
A terminal connected to the reconnection wiring is provided with at least a sixteenth step that is formed in a state where a part of the terminal is exposed on the surface of the protective film
The second metal pattern includes a frame-shaped part surrounding a region where the first metal pattern is formed, an internal part disposed inside the frame-shaped part, and a part serving as the first passive element. Configured,
The fourth metal pattern includes a portion disposed on the frame-shaped portion of the second metal pattern and formed in a frame shape, and a portion to be the first passive element ,
A side wall frame is constituted by the frame-shaped portion of the fourth metal pattern and the frame-shaped portion of the second metal pattern,
The third metal pattern is formed by being connected to an inner part of the second metal pattern, and becomes a part of the movable part constituting the second passive element,
The metal layer is disposed on the side wall frame as a ceiling wall,
The first metal pattern and the third metal pattern are arranged inside a container constituted by the side wall frame and the ceiling wall,
The portion that becomes the first passive element of the second metal pattern, the portion that becomes the first passive element of the fourth metal pattern, and the fifth metal pattern constitute the first passive element,
The method of manufacturing a semiconductor device, wherein the first sacrificial layer and the second sacrificial layer disposed inside the container are removed by etching through the opening.

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