JP4424476B2 - Noise suppression circuit - Google Patents

Description

  The present invention relates to a noise suppression circuit that suppresses noise propagating on a conductive wire.

  Power electronics devices such as switching power supplies, inverters, lighting circuits for lighting devices, and the like have a power conversion circuit that converts power. The power conversion circuit has a switching circuit that converts direct current into rectangular alternating current. For this reason, the power conversion circuit generates a ripple voltage having a frequency equal to the switching frequency of the switching circuit and noise associated with the switching operation of the switching circuit. This ripple voltage and noise adversely affect other devices. Therefore, it is necessary to provide a means for reducing ripple voltage and noise between the power conversion circuit and another device or line.

  As means for reducing ripple voltage and noise, a filter including an inductance element (inductor) and a capacitor, a so-called LC filter is often used. The LC filter includes a T-type filter and an n-type filter in addition to one having one inductance element and one capacitor. A general noise filter for electromagnetic interference (EMI) countermeasures is also a kind of LC filter. A general EMI filter is configured by combining discrete elements such as a common mode choke coil, a normal mode choke coil, an X capacitor, and a Y capacitor.

  Recently, power line communication has been considered promising as a communication technique used in building a communication network in the home, and its development is being promoted. In power line communication, communication is performed by superimposing a high-frequency signal on the power line. In this power line communication, noise is generated on the power line due to the operation of various electric / electronic devices connected to the power line, which causes a decrease in communication quality such as an increase in error rate. Therefore, a means for reducing noise on the power line is required. In power line communication, it is necessary to prevent a communication signal on the indoor power line from leaking to the outdoor power line. The LC filter is also used as means for reducing such noise on the power line or preventing a communication signal on the indoor power line from leaking to the outdoor power line.

  Noise that propagates through two conductive lines includes normal mode (differential mode) noise that causes a potential difference between the two conductive lines, and common mode noise that propagates through the two conductive lines in the same phase. There is.

  Patent Document 1 describes a line filter using a transformer. This line filter includes a transformer and a filter circuit. The secondary winding of the transformer is inserted into one of the two conductive wires that transport power supplied from the AC power source to the load. Two input ends of the filter circuit are connected to both ends of the AC power source, and two output ends of the filter circuit are connected to both ends of the primary winding of the transformer. In this line filter, a noise component is extracted from a power supply voltage by a filter circuit, and this noise component is supplied to the primary winding of the transformer, whereby the power supply voltage is applied on the conductive line in which the secondary winding of the transformer is inserted. The noise component is subtracted from. This line filter reduces noise in the normal mode.

  Patent Document 2 describes a low-pass filter composed of three impedance elements. This low-pass filter has two high impedance elements inserted in series on one of two conductive lines, one end connected between the two high impedance elements, and the other end of the two conductive lines. And a low impedance element connected to the other of the two. Each of the two high impedance elements is configured by a parallel connection circuit of a coil and a resistor, and the low impedance element is configured by a capacitor. This low-pass filter reduces normal mode noise.

Patent Document 3 describes a normal mode noise filter circuit for reducing normal mode noise and a common mode noise filter circuit for reducing common mode noise. The normal mode noise filter circuit is composed of two coils inserted in two conductive wires and a capacitor connecting the middle windings of the coils. The common mode noise filter circuit is composed of two coils inserted into two conductive wires, and two capacitors provided between the windings of each coil and the ground.
JP-A-9-102723 Japanese Patent Laid-Open No. 5-121988 (FIG. 1) Japanese Patent No. 2784833 (FIG. 6)

  Since the conventional LC filter has a specific resonance frequency determined by inductance and capacitance, there is a problem that a desired attenuation can be obtained only in a narrow frequency range.

  In addition, the filter inserted into the power transporting conductive wire is required to obtain desired characteristics in a state where a current for power transporting flows and to take measures against temperature rise. Therefore, a ferrite magnetic core with a gap is usually used as a magnetic core in an inductance element in a filter for a power conversion circuit. However, such an inductance element has a problem that the characteristic of the inductance element approaches that of an air-core inductance element, so that the inductance element is increased in size in order to realize a desired characteristic.

  Moreover, in the line filter described in Patent Document 1, if the impedance of the filter circuit is 0 and the coupling coefficient of the transformer is 1, theoretically, the noise component can be completely removed. However, in practice, the impedance of the filter circuit does not become zero, and further changes according to the frequency. In particular, when a filter circuit is constituted by a capacitor, a series resonance circuit is constituted by the capacitor and the primary winding of the transformer. Therefore, the impedance of the signal path including the capacitor and the primary winding of the transformer is reduced only in a narrow frequency range near the resonance frequency of the series resonance circuit. As a result, this line filter can remove noise components only in a narrow frequency range. For these reasons, the actually configured line filter has a problem that noise components cannot be effectively removed in a wide frequency range.

  Further, the low-pass filter described in Patent Document 2 and the filter circuit described in Patent Document 3 have the same problems as the conventional LC filter because the principle of noise reduction is the same as that of the conventional LC filter. is doing.

  By the way, in each country, various regulations are often provided for noise emitted from an electronic device to the outside via an AC power supply line, that is, a noise terminal voltage. For example, in the standard of CISPR (International Radio Interference Special Committee), the standard of the noise terminal voltage is set in the frequency range of 150 kHz to 30 MHz. When noise is reduced in such a wide frequency range, the following problems occur particularly with respect to noise reduction in a low frequency range of 1 MHz or less. That is, in the low frequency range of 1 MHz or less, the absolute value of the coil impedance is represented by 2πfL, where L is the coil inductance and f is the frequency. Therefore, in general, in order to reduce noise in a low frequency range of 1 MHz or less, a filter including a coil having a large inductance is required. As a result, the filter becomes large.

  The present invention has been made in view of such problems, and an object thereof is to provide a noise suppression circuit capable of suppressing noise in a wide frequency range with a relatively simple configuration.

  A noise suppression circuit according to a first aspect of the present invention is a circuit that suppresses normal mode noise that is transmitted through first and second conductive lines and causes a potential difference between these conductive lines. The first and second inductors inserted in series and electromagnetically coupled to the first conductive line, and the series circuit composed of the third inductor and the first capacitor connected in series are connected in parallel. And a parallel circuit portion having at least one stage of a parallel circuit including the fourth inductor and the second capacitor. One end of the parallel circuit portion is connected to the series circuit, one end of the circuit composed of the series circuit and the parallel circuit portion is connected between the first inductor and the second inductor, and the other end is the second. It is connected to the conductive wire.

  In the noise suppression circuit according to the first aspect of the present invention, the first and second inductors are electromagnetically coupled to each other. Each of the first and second inductors may be formed of separate windings, or may be formed of a single winding. When forming with a single winding, for example, a connection point is provided in the middle of a single winding, and the first inductor and the other end of the winding are connected from one end of the winding to the connection point. To the connection point may be the second inductor. One end of a circuit composed of a series circuit and a parallel circuit portion is connected to this connection point. In the noise suppression circuit according to the first aspect of the present invention, the inductances of the first and second inductors may be the same value. When the first and second inductors are formed with a single winding, for example, the inductance can be made equal by providing the connection point at the midpoint of the single winding.

  In the noise suppression circuit according to the first aspect of the present invention, the parallel circuit may include a resistance element connected in parallel to the fourth inductor and the second capacitor.

  Here, one end of the circuit composed of the series circuit and the parallel circuit portion is called a first end portion where the connection portion is connected to the first and second inductors, and the other end is connected to the second conductive line. The connecting portion is referred to as a second end portion. Also, the end of the first inductor opposite to the first end is called one end of the first inductor, and the end of the first inductor on the first end side is the first end. Called the other end of one inductor. The end of the second inductor on the first end side is called one end of the second inductor, and the end of the second inductor opposite to the first end is the second end. Called the other end of the two inductors.

In the noise suppression circuit according to the first aspect of the present invention, when a normal mode voltage is applied between one end of the first inductor and the second end of the second conductive line, This voltage is divided by the first inductor and the circuit composed of the series circuit and the parallel circuit portion, and a predetermined voltage is generated between both ends of the first inductor and both ends of the circuit composed of the series circuit and the parallel circuit portion. To do. Since the first inductor and the second inductor are electromagnetically coupled to each other, a predetermined voltage is generated between both ends of the second inductor in accordance with the voltage generated between both ends of the first inductor. As a result, the voltage between the other end of the second inductor and the second end is the voltage applied between the one end of the first inductor and the second end. Smaller than.
Further, by providing the parallel circuit portion including the inductor and the capacitor, the noise component is more effectively suppressed in the vicinity of the resonance point between the inductor and the capacitor than in the case of only the series circuit. Therefore, by setting the resonance point by the parallel circuit to, for example, the high frequency region, it is possible to more effectively suppress noise components particularly in the high frequency region.

  In the noise suppression circuit according to the first aspect of the present invention, a normal mode voltage is applied between the other end of the second inductor and the second end of the second conductive line. In the same manner as described above, the voltage between one end of the first inductor and the second end is equal to the other end of the second inductor and the second end. It becomes smaller than the voltage applied between.

  A noise suppression circuit according to a second aspect of the present invention is a circuit that suppresses normal mode noise that is transmitted through first and second conductive lines and causes a potential difference between the conductive lines. The first and second inductors inserted in series and electromagnetically coupled to the first conductive line, and the series circuit composed of the third inductor and the first capacitor connected in series are connected in parallel. A parallel circuit portion including at least one stage of a parallel circuit including the fourth inductor and the second capacitor, and a fifth circuit and a fifth circuit that are inserted in series in the second conductive line and electromagnetically coupled to each other. 6 inductors. One end of the parallel circuit portion is connected to the series circuit, one end of the circuit composed of the series circuit and the parallel circuit portion is connected between the first inductor and the second inductor, and the other end is the fifth. And the sixth inductor.

  In the noise suppression circuit according to the second aspect of the present invention, the first and second inductors are electromagnetically coupled to each other in the same manner as the noise suppression circuit according to the first aspect. It may be formed by separate windings or may be formed by a single winding. The fifth and sixth inductors can be similarly configured. When the fifth and sixth inductors are formed with a single winding, for example, a connection point is provided in the middle of the single winding, and the fifth inductor extends from one end of the winding to the connection point. The sixth inductor may be from the other end of the winding to the connection point. The other end of the circuit composed of the series circuit and the parallel circuit portion is connected to this connection point. In the noise suppression circuit according to the second aspect of the present invention, the inductances of the fifth and sixth inductors may be the same value. When the fifth and sixth inductors are formed by a single winding, for example, the inductance can be made equal by providing the connection point at the midpoint of the single winding.

  In the noise suppression circuit according to the second aspect of the present invention, the parallel circuit may include a resistance element connected in parallel to the fourth inductor and the second capacitor. Alternatively, the first and second inductors and the fifth and sixth inductors may be electromagnetically coupled.

  Here, one end of the circuit composed of the series circuit and the parallel circuit portion is called a first end portion, which is connected to the first and second inductors, and is connected to the fifth and sixth inductors. The connecting portion at the other end is referred to as a second end portion. Also, the end of the first inductor opposite to the first end is called one end of the first inductor, and the end of the first inductor on the first end side is the first end. Called the other end of one inductor. The end of the second inductor on the first end side is called one end of the second inductor, and the end of the second inductor opposite to the first end is the second end. Called the other end of the two inductors. The end of the fifth inductor opposite to the second end is called one end of the fifth inductor, and the end of the fifth inductor on the second end side is called the first end. 5 is called the other end of the inductor. The end of the sixth inductor on the second end side is called one end of the sixth inductor, and the end of the sixth inductor opposite to the second end is the first end. 6 is called the other end of the inductor.

In the noise suppression circuit according to the second aspect of the present invention, when a normal mode voltage is applied between one end of the first inductor and one end of the fifth inductor, the voltage is reduced. The first inductor is divided by the circuit including the series circuit and the parallel circuit portion and the fifth inductor, and is divided between the both ends of the first inductor, between the both ends of the circuit including the series circuit and the parallel circuit portion, and the fifth inductor. A predetermined voltage is generated between the both ends of each. Since the first inductor and the second inductor are electromagnetically coupled to each other, a predetermined voltage is generated between both ends of the second inductor in accordance with the voltage generated between both ends of the first inductor. Similarly, since the fifth inductor and the sixth inductor are electromagnetically coupled to each other, a predetermined voltage is generated between both ends of the sixth inductor according to the voltage generated between both ends of the fifth inductor. appear. As a result, the voltage between the other end of the second inductor and the other end of the sixth inductor is between one end of the first inductor and one end of the fifth inductor. It becomes smaller than the voltage applied between them.
Further, by providing the parallel circuit portion including the inductor and the capacitor, the noise component is more effectively suppressed in the vicinity of the resonance point between the inductor and the capacitor than in the case of only the series circuit. Therefore, by setting the resonance point by the parallel circuit to, for example, the high frequency region, it is possible to more effectively suppress noise components particularly in the high frequency region.

  In the noise suppression circuit according to the second aspect of the present invention, when a normal mode voltage is applied between the other end of the second inductor and the other end of the sixth inductor, In the same manner as described above, the voltage between one end of the first inductor and one end of the fifth inductor is the other end of the second inductor and the other end of the sixth inductor. It becomes smaller than the voltage applied between the ends of the.

  A noise suppression circuit according to a third aspect of the present invention is a circuit that suppresses common mode noise propagating through the first and second conductive lines in the same phase, and is inserted in series with the first conductive line. And the first and second inductors coupled electromagnetically and the third and fourth inductors inserted in series in the second conductive line and coupled electromagnetically. A first series circuit composed of a fifth inductor and a first capacitor; a second series circuit composed of a sixth inductor and a second capacitor connected in series; and a seventh series connected in parallel. At least one stage of a parallel circuit including an eighth inductor and a fourth capacitor connected in parallel with a first parallel circuit portion having at least one stage of a parallel circuit including the inductor and the third capacitor. Second parallel time In which and a part. One end of the first parallel circuit portion is connected to the first series circuit, and one end of the first circuit composed of the first series circuit and the first parallel circuit portion is connected to the first inductor and the first series circuit. And the other end of the inductor is grounded. One end of the second parallel circuit portion is connected to the second series circuit, and one end of the second circuit composed of the second series circuit and the second parallel circuit portion is connected to the third inductor and the second series circuit. 4 is connected to the other inductor, and the other end is grounded.

  In the noise suppression circuit according to the third aspect of the present invention, the first and second inductors are electromagnetically coupled to each other. Each of the first and second inductors may be formed of separate windings, or may be formed of a single winding. When forming with a single winding, for example, a connection point is provided in the middle of a single winding, and the first inductor and the other end of the winding are connected from one end of the winding to the connection point. To the connection point may be the second inductor. One end of a circuit composed of the first series circuit and the first parallel circuit portion is connected to this connection point. In the noise suppression circuit according to the third aspect of the present invention, the inductances of the first and second inductors may be the same value. When the first and second inductors are formed with a single winding, for example, the inductance can be made equal by providing the connection point at the midpoint of the single winding. The third and fourth inductors can be configured similarly to the first and second inductors.

  In the noise suppression circuit according to the third aspect of the present invention, the parallel circuit in the first parallel circuit portion may further include a resistance element connected in parallel to the seventh inductor and the third capacitor. . The parallel circuit in the second parallel circuit portion may further include a resistance element connected in parallel to the eighth inductor and the fourth capacitor.

  Here, one end of the circuit composed of the first series circuit and the first parallel circuit portion is referred to as a first end portion where the connection portion connected to the first and second inductors, and the other end is grounded. The connecting portion is referred to as a second end portion. In addition, one end of the circuit composed of the second series circuit and the second parallel circuit portion is called a third end portion where the connection portion connected to the third and fourth inductors is connected to the other end grounded. The connecting portion is called a fourth end. Also, the end of the first inductor opposite to the first end is called one end of the first inductor, and the end of the first inductor on the first end side is the first end. Called the other end of the inductor. The end on the first end side of the second inductor is referred to as one end of the second inductor, and the end opposite to the first end of the second inductor is the second end. Called the other end of the inductor. In addition, the end of the third inductor opposite to the third end is called one end of the third inductor, and the end of the third inductor on the third end side is the third end. Called the other end of the inductor. In addition, the end on the third end side of the fourth inductor is referred to as one end of the fourth inductor, and the end of the fourth inductor opposite to the third end P3 is the fourth end. Called the other end of the inductor.

  In the noise suppression circuit according to the third aspect of the present invention, when a common mode voltage is applied to one end of the first inductor and one end of the third inductor, An equal voltage is generated between one end and ground and between one end of the third inductor and ground. The voltage generated between one end of the first inductor and the ground is divided by the first inductor and the first circuit, and is divided between both ends of the first inductor and both ends of the first circuit. A predetermined voltage is generated. Similarly, a voltage generated between one end of the third inductor and the ground is divided by the third inductor and the second circuit, so that the voltage between both ends of the third inductor and the both ends of the second circuit is divided. A predetermined voltage is generated between them.

Since the first inductor and the second inductor are electromagnetically coupled to each other, a predetermined voltage is generated between both ends of the second inductor in accordance with the voltage generated between both ends of the first inductor. Similarly, since the third inductor and the fourth inductor are electromagnetically coupled to each other, a predetermined voltage is generated between both ends of the fourth inductor according to the voltage generated between both ends of the third inductor. appear. As a result, the common mode voltage generated between the other end of the second inductor and the ground is smaller than the common mode voltage generated between the one end of the first inductor and the ground.
Further, by providing the first and second parallel circuit portions including the inductor and the capacitor, the common mode noise component is more effective near the resonance point between the inductor and the capacitor than in the case of only the series circuit. Is suppressed. Therefore, by setting the resonance point by the parallel circuit to, for example, the high frequency region, it is possible to more effectively suppress noise components particularly in the high frequency region.

  In addition, in the noise suppression circuit according to the third aspect of the present invention, when a common mode voltage is applied to the other end of the second inductor and the other end of the fourth inductor, Similarly to the description, the common mode voltage generated at one end of the first inductor and one end of the third inductor is the same as that of the other end of the second inductor and the fourth inductor. It becomes smaller than the voltage of the common mode applied to the other end.

  In addition, in the noise suppression circuit according to each aspect, examples of the first conductive line and the second conductive line include each conductive line in the single-phase two-wire power line, and are currently widely used for power supply. There are two of the three wires in the single-phase three-wire power line being used.

  The noise suppression circuit according to each aspect of the present invention can suppress noise in a wide frequency range with a relatively simple configuration.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
First, the noise suppression circuit according to the first embodiment of the present invention will be described. The noise suppression circuit according to the present embodiment is a circuit that suppresses normal mode noise that is transmitted through two conductive lines and causes a potential difference between the conductive lines.

  1A and 1B show first and second configuration examples of a noise suppression circuit according to the present embodiment. The noise suppression circuit includes a pair of terminals 1a and 1b, another pair of terminals 2a and 2b, a first conductive line 3 connecting the terminals 1a and 2a, and a second connecting the terminals 1b and 2b. The conductive wire 4 is provided. The noise suppression circuit further includes first and second inductors L1 and L2 inserted in series with the first conductive line 3. The noise suppression circuit also includes a series circuit 15 including a third inductor L3 and a first capacitor C1 connected in series. The noise suppression circuit also includes a parallel circuit 16 including a fourth inductor L4 and a second capacitor C2 connected in parallel.

  Note that the parallel circuit 16 is not limited to one stage, and may be connected in multiple stages as in the configuration example shown in FIG. FIG. 3 shows a first parallel circuit (inductor L4-1, capacitor C2-1) and a second parallel circuit (inductor L4-2, capacitor C2) as a parallel circuit 16 with respect to the configuration example of FIG. -2) are connected in two stages in series. Thus, the noise suppression circuit according to the present embodiment includes a parallel circuit portion having at least one parallel circuit. One end of the parallel circuit portion is connected to the series circuit 15, and one end of the circuit composed of the series circuit 15 and the parallel circuit portion is connected between the first inductor L1 and the second inductor L2. Is connected to the second conductive wire 4.

  Here, a connection portion where one end of the circuit composed of the series circuit 15 and the parallel circuit portion is connected to the first and second inductors L1 and L2 is referred to as a first end portion P1, and the second conductive line 4 The connecting portion at the other end connected to is referred to as a second end portion P2. Further, the end of the first inductor L1 opposite to the first end P1 is called one end of the first inductor L1, and the first end P1 side of the first inductor L1 is the first end. This is called the other end of one inductor L1. In addition, the first end P1 side of the second inductor L2 is referred to as one end of the second inductor L2, and the end of the second inductor L2 opposite to the first end P1 is the first end. The other end of the second inductor L2.

  In FIG. 1A, of the series circuit 15 and the parallel circuit 16, the series circuit 15 is connected to the first end P1, and the parallel circuit 16 is connected to the second end P2. It is a structural example. 1B, conversely, of the series circuit 15 and the parallel circuit 16, the parallel circuit 16 is connected to the first end P1, and the series circuit 15 is connected to the second end P2. This is a configuration example.

  In the series circuit 15, the third inductor L3 has a winding 13a wound around the magnetic core 13b. In the series circuit 15, the first capacitor C1 functions as a high-pass filter that passes a normal mode signal having a frequency equal to or higher than a predetermined value. Note that the positional relationship between the third inductor L3 and the first capacitor C1 in the series circuit 15 may be opposite to that illustrated. For example, in FIG. 1A, the third inductor L3 is disposed closer to the first end P1, but the first capacitor C1 is disposed closer to the first end P1. May be.

  In the parallel circuit 16, the fourth inductor L4 has a winding 17a wound around the magnetic core 17b. The parallel circuit 16 includes, in addition to the fourth inductor L4 and the second capacitor C2, a resistance element R1 connected in parallel thereto, as in the other configuration examples shown in FIGS. May further be included. FIG. 2A is a configuration example including a parallel circuit 16A to which a resistance element R1 is added in the noise suppression circuit of FIG. FIG. 2B is a configuration example including a parallel circuit 16A to which a resistance element R1 is added in the noise suppression circuit of FIG.

  The first and second inductors L1 and L2 are electromagnetically coupled to each other. The first inductor L1 has a winding 11a wound around the first portion 12a of the magnetic core 12. The second inductor L2 has a winding 11b wound around the second portion 12b of the magnetic core 12. The first and second inductors L1 and L2 may be formed by separate windings 11a and 11b as described above, but may be formed by a single winding 11 as shown in FIG. It is. The winding 11 is wound around the magnetic core 12. In FIG. 4, circuits other than the first and second inductors L1 and L2 are not shown.

  When the first and second inductors L1 and L2 are formed by a single winding, as shown in FIG. 4, for example, a connection point (first end portion P1) is provided in the middle of the single winding 11. The first inductor L1 may be provided as a winding 11a from one end of the winding 11 to the connection point. Similarly, what is necessary is just to let it be the 2nd inductor L2 by making into the coil | winding 11b from the other edge part of the coil | winding 11 to a connection point. One end of a circuit composed of the series circuit 15 and the parallel circuit portion is connected to this connection point.

  The inductances of the first and second inductors L1, L2 are preferably the same value. When the first and second inductors L1 and L2 are formed by a single winding 11, by providing the connection point at the midpoint of the single winding 11, for example, the inductances can be made equal.

  Next, the operation of the noise suppression circuit according to the present embodiment will be described. Here, description will be made based on the configuration example of FIG. First, a case where a normal mode voltage Vi is applied between the terminals 1a and 1b as shown in FIG. 1A will be described. In this case, the voltage Vi is applied between one end of the first inductor L1 and the second end P2. This voltage Vi is divided by the first inductor L1 and the circuit composed of the series circuit 15 and the parallel circuit 16, and is divided between both ends of the first inductor L1 and the circuit composed of the series circuit 15 and the parallel circuit 16. A predetermined voltage is generated for each. Note that the arrow in the figure indicates that the potential ahead is higher. Since the first inductor L1 and the second inductor L2 are electromagnetically coupled to each other, a predetermined voltage is generated between both ends of the second inductor L2 according to the voltage generated between both ends of the first inductor L1. Occurs. As a result, the voltage between the other end of the second inductor L2 and the second end P2, that is, the voltage Vo between the terminals 2a and 2b is equal to the second end of the first inductor L1 and the second end P2. The voltage Vi is smaller than the voltage Vi applied to the end P2.

  In the present embodiment, even when a normal mode voltage is applied between the terminals 2a and 2b, the voltage between the terminals 1a and 1b is applied between the terminals 2a and 2b in the same manner as described above. It becomes smaller than the voltage. As described above, according to the noise suppression circuit according to the present embodiment, the normal mode noise is applied to the terminals 1a and 1b and the normal mode noise is applied to the terminals 2a and 2b. Also, normal mode noise can be suppressed.

  In particular, in the noise suppression circuit according to the present embodiment, by providing the parallel circuit 16 including the fourth inductor L4 and the second capacitor C2, the noise suppression circuit includes the fourth inductor L4 and the second capacitor C2. In the vicinity of the resonance point, the noise component is more effectively suppressed as compared with the case of only the series circuit 15. Therefore, by setting the resonance point by the parallel circuit 16 in, for example, a high frequency region, it is possible to more effectively suppress noise components particularly in the high frequency region.

  Next, the effect of the noise suppression circuit according to the present embodiment will be specifically shown by the following simulation results.

  5A to 5C show an equivalent circuit of the noise suppression circuit used in the first simulation. FIG. 5A is a circuit serving as a comparative example of the noise suppression circuit according to this embodiment. The circuit of this comparative example has a circuit configuration in which the parallel circuit portion is omitted from the noise suppression circuit according to the present embodiment. FIG. 5B corresponds to the noise suppression circuit of FIG. 1A, and has a configuration in which only one stage of the parallel circuit 16 is provided as a parallel circuit portion. FIG. 5C corresponds to the noise suppression circuit of FIG. 3, and has a configuration having a two-stage parallel circuit as a parallel circuit portion. In each circuit of FIGS. 5A to 5C, Ra and Rb are set as input / output impedances. For example, Ra corresponds to the input / output impedance on the power supply system side, and Rb corresponds to the input / output impedance on the device side. In this simulation, the Rb side is set as the measuring device side. In the circuit of FIG. 5C, Rc is a parasitic resistance.

  5A to 5C, the element values of the circuit elements used in the simulation are described in the vicinity of the circuit symbols. As illustrated, the inductances of the first and second inductors L1 and L2 are both set to the same value (560 μH). In addition, the coupling coefficient k1 of the first and second inductors L1 and L2 was set to 0.998.

  FIG. 6 shows a simulation result by each circuit of FIGS. This is a graph showing the frequency characteristics of the attenuation amount of normal mode noise in the noise suppression circuit. In FIG. 6, the horizontal axis represents frequency (Hz) and the vertical axis represents attenuation (gain) (dB). The smaller the gain, that is, the larger the absolute value of the negative gain, the greater the amount of noise attenuation. In FIG. 6, the line denoted by reference numeral 61 indicates the simulation result by the circuit of FIG. 5A, and the line denoted by reference numeral 62 indicates the simulation result by the circuit of FIG. The solid line shows the simulation result by the circuit of FIG.

  5A and 6C having the parallel circuit portion, the attenuation poles 64 and 65 are generated on the high frequency side, but in the circuit of FIG. 5A in which the parallel circuit portion is omitted. It can be seen that no attenuation pole occurs. Here, in the circuit of FIG. 5B, only one attenuation pole 64 is generated at the resonance point by having only one parallel circuit. In the circuit of FIG. 5C, two stages of parallel circuits are provided, so that two attenuation poles 64 and 65 are generated due to the resonance points of each parallel circuit. Thus, by having a parallel circuit part, a noise component can be suppressed more effectively partially.

  FIGS. 7A and 7B show an equivalent circuit of the noise suppression circuit used as the second simulation. FIG. 7A corresponds to the noise suppression circuit of FIG. 1A, and has a configuration in which only one stage of the parallel circuit 16 is provided as a parallel circuit portion. FIG. 7B corresponds to the noise suppression circuit of FIG. 2A, and has a configuration in which only one stage of the parallel circuit 16A including the resistance element R1 is provided as a parallel circuit portion. The difference between the circuits in FIGS. 7A and 7B is only the presence or absence of the resistance element R1. 7A and 7B, the same parts as those in FIGS. 5A to 5C are denoted by the same reference numerals.

  FIG. 8 shows a simulation result by each circuit of FIGS. 7 (A) and 7 (B). This is a graph showing the frequency characteristics of the attenuation amount of the normal mode noise in the noise suppression circuit, as in FIG. In FIG. 8, a line denoted by reference numeral 71 indicates a simulation result by the circuit of FIG. 7A, and a line denoted by reference numeral 72 indicates a simulation result by the circuit of FIG. 7B.

  From FIG. 8, it can be seen that in each of the circuits of FIGS. 7A and 7B, an attenuation pole due to the parallel circuit is generated on the high frequency side. In addition, it can be seen that a sharp attenuation pole 73 is generated in the circuit of FIG. 7A in which the parallel circuit does not include the resistance element R1.

  As described above, according to the noise suppression circuit according to the present embodiment, normal mode noise is effectively suppressed in a wide frequency range with a relatively simple configuration and without using a coil having a large inductance. It becomes possible.

[Second Embodiment]
FIGS. 9A and 9B show first and second configuration examples of the noise suppression circuit according to the second embodiment of the present invention. The noise suppression circuit of FIGS. 9A and 9B is obtained by adding fifth and sixth inductors L5 and L6 to the configuration of the noise suppression circuit of FIGS. In other respects, the configuration is the same as that of the noise suppression circuit of FIGS. The fifth and sixth inductors L5 and L6 are inserted in series with the second conductive line 4.

  Here, in the noise suppression circuit according to the present embodiment, one end of the circuit including the series circuit 15 and the parallel circuit portion is connected to the first and second inductors L1 and L2 as the first end. The portion P1 is referred to as the second end portion P2, and the other end connected to the fifth and sixth inductors L5 and L6 is referred to as the second end portion P2. In addition, the end of the first inductor L1 opposite to the first end P1 is called one end of the first inductor L1, and the end of the first inductor L1 on the first end P1 side. This part is called the other end of the first inductor L1. In addition, the first end P1 side of the second inductor L2 is referred to as one end of the second inductor L2, and the end of the second inductor L2 opposite to the first end P1 is the first end. The other end of the second inductor L2. The end of the fifth inductor L5 opposite to the second end P2 is referred to as one end of the fifth inductor L5, and the end of the fifth inductor L5 on the second end P2 side. This part is referred to as the other end of the fifth inductor L5. The end of the sixth inductor L6 on the second end P2 side is referred to as one end of the sixth inductor L6, and is the end opposite to the second end P2 of the sixth inductor L6. This portion is called the other end portion of the sixth inductor L6.

  In FIG. 9A, of the series circuit 15 and the parallel circuit 16, the series circuit 15 is connected to the first end P1, and the parallel circuit 16 is connected to the second end P2. It is a structural example. 9B, conversely, of the series circuit 15 and the parallel circuit 16, the parallel circuit 16 is connected to the first end P1, and the series circuit 15 is connected to the second end P2. This is a configuration example.

  In the noise suppression circuit according to the present embodiment, the parallel circuit 16 is not limited to one stage, and may be connected in a plurality of stages. The parallel circuit 16 includes a resistor connected in parallel to the fourth inductor L4 and the second capacitor C2 as in the other configuration examples shown in FIGS. An element R1 may be further included. FIG. 10A is a configuration example including a parallel circuit 16A to which a resistance element R1 is added in the noise suppression circuit of FIG. 9A. FIG. 10B is a configuration example including a parallel circuit 16A to which a resistance element R1 is added in the noise suppression circuit of FIG. 9B.

  The fifth and sixth inductors L5 and L6 are electromagnetically coupled to each other like the first and second inductors L1 and L2. The fifth inductor L5 has a winding 21a wound around the first portion 22a of the magnetic core 22. The sixth inductor L6 has a winding 21b wound around the second portion 22b of the magnetic core 22. Similarly to the first and second inductors L1 and L2, the fifth and sixth inductors L5 and L6 may be formed by separate windings 21a and 21b. However, as shown in FIG. It is also possible to form the winding 21. The winding 21 is wound around the magnetic core 22. In FIG. 11, the circuits other than the first and second inductors L1 and L2 and the fifth and sixth inductors L5 and L6 are not shown.

  When the fifth and sixth inductors L5 and L6 are formed by a single winding, as shown in FIG. 11, for example, a connection point (second end portion P2) is provided in the middle of the single winding 21. The fifth inductor L5 may be provided as a winding 21a from one end of the winding 21 to the connection point. Similarly, what is necessary is just to make it the 6th inductor L6 by making into the coil | winding 21b from the other edge part of the coil | winding 21 to a connection point. The other end of the circuit composed of the series circuit 15 and the parallel circuit portion is connected to this connection point.

  The inductances of the fifth and sixth inductors L5 and L6 are preferably the same value as the inductances of the first and second inductors L1 and L2. More preferably, all the inductances of the first and second inductors L1 and L2 and the fifth and sixth inductors L5 and L6 are set to the same value. When the fifth and sixth inductors L5 and L6 are formed by a single winding 21, for example, the fifth and sixth inductors L5 and L5 are provided by providing the connection point at the midpoint of the single winding 21. Each inductance of L6 can be made equal.

  Alternatively, the first and second inductors L1 and L2 and the fifth and sixth inductors L5 and L6 may be electromagnetically coupled. In this case, it is configured to be coupled so as to increase the magnetic field generated in the first and second inductors L1 and L2 when a normal mode signal is passed. In this case, the impedance of normal mode noise can be increased and noise can be suppressed more effectively. Furthermore, the magnetic cores 12 of the first and second inductors L1 and L2 and the magnetic cores 22 of the fifth and sixth inductors L5 and L6 can be made common, contributing to downsizing, A coil having a small inductance can be used as the second inductors L1 and L2, the fifth and sixth inductors L5 and L6, and the third inductor L3.

  Next, the operation of the noise suppression circuit according to the present embodiment will be described. Here, description will be made based on the configuration example of FIG. First, a case where a normal mode voltage Vi is applied between the terminals 1a and 1b as shown in FIG. 1A will be described. In this case, the voltage Vi is applied between one end of the first inductor L1 and one end of the fifth inductor L5. This voltage Vi is divided by the circuit including the first inductor L1, the series circuit 15 and the parallel circuit 16, and the fifth inductor L5, and between the both ends of the first inductor L1 and from the series circuit 15 and the parallel circuit 16. A predetermined voltage is generated between both ends of the circuit and between both ends of the fifth inductor L5. Note that the arrow in the figure indicates that the potential ahead is higher.

  Since the first inductor L1 and the second inductor L2 are electromagnetically coupled to each other, a predetermined voltage is generated between both ends of the second inductor L2 according to the voltage generated between both ends of the first inductor L1. Occurs. Similarly, since the fifth inductor L5 and the sixth inductor L6 are electromagnetically coupled to each other, according to the voltage generated between both ends of the fifth inductor L5, between the both ends of the sixth inductor L6. A predetermined voltage is generated. As a result, the voltage between the other end of the second inductor L2 and the other end of the sixth inductor L6, that is, the voltage Vo between the terminals 2a and 2b is equal to one end of the first inductor L1. And a voltage Vi applied between the first inductor and one end of the fifth inductor L5.

  In the present embodiment, even when a normal mode voltage is applied between the terminals 2a and 2b, the voltage between the terminals 1a and 1b is applied between the terminals 2a and 2b in the same manner as described above. It becomes smaller than the voltage. As described above, according to the noise suppression circuit according to the present embodiment, the normal mode noise is applied to the terminals 1a and 1b and the normal mode noise is applied to the terminals 2a and 2b. Also, normal mode noise can be suppressed.

  Next, the effect of the noise suppression circuit according to the present embodiment will be specifically shown by the following simulation results.

  12A to 12C show an equivalent circuit of the noise suppression circuit used in the simulation. FIG. 12A is a circuit serving as a comparative example of the noise suppression circuit according to this embodiment. The circuit of this comparative example corresponds to the noise suppression circuit of FIG. 1A, and is a circuit in which the fifth and sixth inductors L5 and L6 are omitted from the noise suppression circuit according to the present embodiment. It has a configuration. FIG. 12B corresponds to the noise suppression circuit of FIG. 9A, and fifth and sixth inductors L5 and L6 are added to the circuit of the comparative example of FIG. Circuit configuration. FIG. 12C corresponds to the noise suppression circuit of FIG. 10A, and includes a parallel circuit 16A in which a resistance element R1 is added to the circuit of FIG. 12B. ing. 12A to 12C, Ra and Rb are set as input / output impedances. For example, Ra corresponds to the input / output impedance on the power supply system side, and Rb corresponds to the input / output impedance on the device side. In this simulation, the Rb side is set as the measuring device side.

  12A to 12C, the element values of the circuit elements used in the simulation are described near each circuit symbol. As illustrated, in the circuit of the comparative example in FIG. 12A, the inductances of the first and second inductors L1 and L2 are both set to the same value (560 μH). In addition, the coupling coefficient k1 of the first and second inductors L1 and L2 was set to 0.998. The inductance of the third inductor L3 was set to 672 μH. In the circuits of FIGS. 12B and 12C, all the inductances of the first and second inductors L1 and L2 and the fifth and sixth inductors L5 and L6 are set to the same value (280 μH). . In the circuits of FIGS. 12B and 12C, the inductance of the third inductor L3 is set to 600 μH. Further, the coupling coefficient k1 of the first and second inductors L1 and L2 was set to 0.998, as in the comparative example circuit of FIG. Similarly, the coupling coefficient k2 of the fifth and sixth inductors L5 and L6 is set to 0.998.

  FIG. 13 shows simulation results by the circuits of FIGS. 12 (A) to 12 (C). This is a graph showing the frequency characteristics of the attenuation amount of the normal mode noise in the noise suppression circuit, as in FIG. In FIG. 13, the line denoted by reference numeral 81 indicates the simulation result by the circuit of FIG. 12A, and the line denoted by reference numeral 82 indicates the simulation result by the circuit of FIG. The solid line shows the simulation result by the circuit of FIG.

  From FIG. 13, it can be seen that the attenuation poles 81A, 82A, and 83A are generated on the high frequency side in all the circuits of FIGS. 12A to 12C by having the parallel circuit portion. That is, similar to the noise suppression circuit according to the first embodiment, the noise suppression circuit according to the present embodiment can also suppress the noise component partially and more effectively by including the parallel circuit portion. You can see that it is made. In addition, it can be seen that a sharp attenuation pole 82A is generated in the circuit of FIG. 12B in which the parallel circuit does not include the resistance element R1.

  As described above, according to the noise suppression circuit according to the present embodiment, an inductor is inserted into each of the first and second conductive lines 3 and 4, and the first and second conductive lines 3 and 4 are inserted. Since it is comprised so that an impedance characteristic may become equilibrium, the increase in the radiation electric field strength from the 1st and 2nd conductive wires 3 and 4 can be suppressed, and generation | occurrence | production of radiation noise can be suppressed. Other configurations, operations, and effects in the present embodiment are the same as those in the first embodiment.

[Third Embodiment]
Next, a noise suppression circuit according to the third embodiment of the present invention will be described. The noise suppression circuit according to the present embodiment is a circuit that suppresses common mode noise that propagates through two conductive wires in the same phase.

  FIG. 14 shows a configuration example of the noise suppression circuit according to the present embodiment. The noise suppression circuit includes a pair of terminals 1a and 1b, another pair of terminals 2a and 2b, a first conductive line 3 connecting the terminals 1a and 2a, and a second connecting the terminals 1b and 2b. Conductive line 4, ground terminal 5, and ground line 6 connected to ground terminal 5.

  The noise suppression circuit is further inserted in series with the first and second inductors L11 and L12 inserted in series in the first conductive line 3 and the second conductive line 4, and the first and second The third and fourth inductors L13 and L14 that suppress common mode noise in cooperation with the inductors L11 and L12. The noise suppression circuit further includes a first series circuit including a fifth inductor L15 and a first capacitor C11 connected in series, a sixth inductor L16 and a second capacitor C12 connected in series, And a second series circuit. The fifth and sixth inductors L15 and L16 have a winding 37a wound around the magnetic core 37b.

  Here, in the configuration example of FIG. 14, one end of the first capacitor C11 of the first series circuit is connected between the first inductor L11 and the second inductor L12, and the second of the second series circuit. One end of the capacitor C12 is connected between the third inductor L13 and the fourth inductor L14, whereby the fifth inductor L15 in the first series circuit and the sixth inductor L16 in the second series circuit. And are common. When the fifth inductor L15 and the sixth inductor L16 are not shared, the positional relationship between the fifth inductor L15 and the first capacitor C11 in each of the first series circuit and the second series circuit, In addition, the positional relationship between the sixth inductor L16 and the second capacitor C12 may be opposite to that illustrated. For example, in the first series circuit, instead of the first capacitor C11, the fifth inductor L15 may be connected between the first inductor L11 and the second inductor L12.

  The noise suppression circuit further includes a parallel circuit 41 including a seventh inductor L17 and a third capacitor C13 connected in parallel. The seventh inductor L17 has a winding 38a wound around the magnetic core 38b. The parallel circuit 41 may further include a resistance element. That is, as in the other configuration example shown in FIG. 15, in addition to the seventh inductor L17 and the third capacitor C13, a parallel circuit 16A further including a resistance element R11 connected in parallel thereto is provided. It may be a configuration.

  Further, the parallel circuit 41 is not limited to one stage, and may be connected in a plurality of stages as in the configuration example shown in FIG. FIG. 16 shows a first parallel circuit (inductor L17-1, capacitor C13-1) and a second parallel circuit (inductor L17-2, capacitor C13-2) as a parallel circuit 41 with respect to the configuration example of FIG. Are connected in two stages in series.

  Thus, the noise suppression circuit according to the present embodiment includes a parallel circuit portion having at least one parallel circuit. One end of the parallel circuit portion is connected to the first and second series circuits. In the first and second series circuits, when the fifth inductor L15 and the sixth inductor L16 are not shared, two parallel circuit portions are provided, and each of the first and second series circuits is provided with A configuration in which separate parallel circuit portions are connected is also possible. That is, the parallel circuit 41 including the seventh inductor L17 and the third capacitor C13 is connected to the first series circuit as a first parallel circuit portion, and includes an eighth inductor and a fourth capacitor not shown. It is also possible to employ a configuration in which the parallel circuit is connected to the second series circuit as the second parallel circuit portion. In this case, one end of the first parallel circuit portion is connected to the first series circuit, and one end of the first circuit composed of the first series circuit and the first parallel circuit portion is the first inductor L11. And the second inductor L12, and the other end is grounded. One end of the second parallel circuit portion is connected to the second series circuit, and one end of the second circuit composed of the second series circuit and the second parallel circuit portion is connected to the third inductor L13. It is connected between the fourth inductor L14 and the other end is grounded.

  In the configuration example of FIG. 14, the first parallel circuit portion and the second parallel circuit portion are shared, and one end of the shared parallel circuit portion is a common inductor of the first and second series circuits. L15 (L16) is connected and the other end is grounded.

  Note that the first parallel circuit portion and the second parallel circuit portion are not provided between the first and second inductors L11 and L12, and the third and second series circuits, respectively, instead of the first and second series circuits. It is also possible to connect between the fourth inductors L13 and L14. FIG. 17 shows an example of the configuration. In this configuration example, one end of the common inductor L15 (L16) of the first and second series circuits is connected to the capacitors C11 and C12 of the first and second series circuits, and the other end is grounded. ing. One end of the first parallel circuit 41-1 is connected to one end of the first capacitor C11 of the first series circuit, and the other end is connected between the first and second inductors L11 and L12. Yes. One end of the second parallel circuit 41-2 is connected to one end of the second capacitor C12 of the second series circuit, and the other end is connected between the third and fourth inductors L13 and L14. Yes. The first parallel circuit 41-1 includes a seventh inductor L17 and a third capacitor C13 connected in parallel to each other, and the second parallel circuit 41-2 includes an eighth inductor connected in parallel to each other. L18 and the fourth capacitor C14.

Here, in the noise suppression circuit according to the present embodiment, one end of a circuit composed of the first series circuit and the first parallel circuit portion is connected to the first and second inductors L11 and L12. Is called the first end P1, and the connecting portion at the other end grounded is called the second end P2. Also, a connection portion where one end of the circuit composed of the second series circuit and the second parallel circuit portion is connected to the third and fourth inductors L13 and L14 is called a third end portion P3 and is grounded. The connection portion at the other end is called a fourth end portion P4. In FIG. 14, since the first parallel circuit portion and the second parallel circuit portion are shared, the second end portion P2 and the fourth end portion P4 are shared.
The end of the first inductor L11 opposite to the first end P1 is referred to as one end of the first inductor L11, and the end of the first inductor L11 on the first end P1 side. This part is referred to as the other end of the first inductor L11. The end of the second inductor L12 on the first end P1 side is referred to as one end of the second inductor L12, and the end of the second inductor L12 opposite to the first end P1. This portion is referred to as the other end portion of the second inductor L12. Further, the end of the third inductor L13 opposite to the third end P3 is called one end of the third inductor L13, and the end of the third inductor L13 on the third end P3 side is called the end of the third inductor L13. This portion is called the other end portion of the third inductor L13. The end of the fourth inductor L14 on the third end P3 side is referred to as one end of the fourth inductor L14, and the end of the fourth inductor L14 opposite to the third end P3. This part is called the other end of the fourth inductor L14.

  The first and second inductors L11 and L12 are electromagnetically coupled to each other. The third and fourth inductors L13 and L14 are similarly electromagnetically coupled to each other. The first and second inductors L11 and L12 may be formed by separate windings or may be formed by a single winding. The same applies to the third and fourth inductors L13 and L14. FIG. 14 shows a configuration example in which the first and second inductors L 11 and L 12 are formed by a single winding 31, and the third and fourth inductors L 13 and L 14 are formed by a single winding 32. Thus, when forming the 1st and 2nd inductors L11 and L12 by the single coil | winding 31, a connection point (1st edge part P1) is provided in the middle of the single coil | winding 31, and the coil | winding From the one end of 31 to the connection point, the winding 31a is used as the first inductor L11. Similarly, from the other end of the winding 31 to the connection point, the winding 31b is used as the second inductor L12. Can do. One end of a circuit composed of the first series circuit and the first parallel circuit portion is connected to this connection point. Similarly, for the third and fourth inductors L13 and L14, a connection point (third end portion P3) is provided in the middle of the single winding 32, and from one end of the winding 32 to the connection point. Can be the third inductor L13 as the winding 32a, and the fourth inductor L14 can be the winding 32b from the other end of the winding 32 to the connection point. One end of a circuit composed of the second series circuit and the second parallel circuit portion is connected to this connection point.

  The inductances of the first and second inductors L11 and L12 are preferably the same value. When the first and second inductors L11 and L12 are formed by a single winding 31, for example, by providing the connection point at the midpoint of the single winding 31, each inductance can be made equal. Similarly, the inductances of the third and fourth inductors L13 and L14 are preferably set to the same value. More preferably, all the inductances of the first and second inductors L11 and L12 and the third and fourth inductors L13 and L14 are set to the same value.

  The winding 31 and the winding 32 are wound around a common magnetic core 33 and are coupled to each other so as to suppress common mode noise in cooperation. That is, the windings 31 and 32 are aligned with the magnetic core 33 in such a direction that the magnetic fluxes induced in the magnetic core 33 by the currents flowing through the windings 31 and 32 when the normal mode currents flow through them are mutually offset. It is rolled up. As described above, the windings 31 and 32 and the magnetic core 33 constitute a common mode choke coil that suppresses common mode noise and allows a normal mode signal to pass.

  However, it is also possible to adopt a configuration in which the winding 31 and the winding 32 are not coupled, but are wound around different magnetic cores. In this case, the normal mode noise can be suppressed as compared with the case where the winding 31 and the winding 32 are combined.

  Next, the operation of the noise suppression circuit according to the present embodiment will be described. Here, the configuration example of FIG. 14 will be basically described. First, the case where the common mode voltage Vi is applied to the terminals 1a and 1b will be described. In this case, an equal voltage Vi is generated between one end of the first inductor L11 and the ground, and between one end of the third inductor L13 and the ground. The voltage Vi generated between one end of the first inductor L11 and the ground is divided by the first inductor L11 and the first circuit (the first series circuit and the parallel circuit 41), and the first A predetermined voltage is generated between both ends of the inductor L11 and between both ends of the first circuit. Note that the arrow in the figure indicates that the potential ahead is higher. Similarly, the voltage Vi generated between one end of the third inductor L13 and the ground is divided by the third inductor L13 and the second circuit (the second series circuit and the parallel circuit 41), Predetermined voltages are generated between both ends of the third inductor L13 and between both ends of the second circuit. Since the first inductor L11 and the second inductor L12 are electromagnetically coupled to each other, a predetermined voltage is generated between both ends of the second inductor L12 according to the voltage generated between both ends of the first inductor L11. Occurs. As a result, the voltage between the other end of the second inductor L12 and the ground, that is, the voltage Vo between the terminal 2a and the ground is the voltage generated between the one end of the first inductor L11 and the ground, that is, the terminal. It becomes smaller than the voltage Vi generated between 1a and ground.

  Similarly, since the third inductor L13 and the fourth inductor L14 are electromagnetically coupled to each other, according to the voltage generated between the both ends of the third inductor L13, between the both ends of the fourth inductor L14. A predetermined voltage is generated. As a result, the voltage between the other end of the fourth inductor L14 and the ground, that is, the voltage Vo between the terminal 2b and the ground is the voltage generated between the one end of the third inductor L13 and the ground, that is, the terminal. It becomes smaller than the voltage Vi generated between 1b and ground. Thus, when a common mode voltage is applied to the terminals 1a and 1b, the common mode voltage generated at the terminals 2a and 2b is smaller than the common mode voltage applied to the terminals 1a and 1b. Become.

  In the present embodiment, when a common mode voltage is applied to the terminals 2a and 2b, the common mode voltage generated at the terminals 1a and 1b is applied to the terminals 2a and 2b in the same manner as described above. It becomes smaller than the applied common mode voltage. As described above, according to the noise suppression circuit according to the present embodiment, the common mode noise is applied to the terminals 1a and 1b and the common mode noise is applied to the terminals 2a and 2b. In addition, common mode noise can be suppressed.

  In particular, in the noise suppression circuit according to the present embodiment, by providing the parallel circuit 41 including the seventh inductor L17 and the third capacitor C13, the fourth inductor L17 and the third capacitor C13 are used. In the vicinity of the resonance point, the common mode noise component is more effectively suppressed as compared with the case of only the series circuit. Therefore, by setting the resonance point by the parallel circuit 41 in, for example, a high frequency region, it is possible to more effectively suppress noise components particularly in the high frequency region.

  Next, the effect of the noise suppression circuit according to the present embodiment is specifically shown by the following measurement results based on actual experiments.

  FIG. 18 shows an equivalent circuit of the noise suppression circuit used for the measurement. This circuit corresponds to the noise suppression circuit shown in FIG. 15, and includes a parallel circuit 41A including a seventh inductor L17, a third capacitor C13, and a resistance element R11. In the equivalent circuit of FIG. 18, Ca and Cb are capacitors for suppressing normal mode noise, and Rd is a resistor for impedance adjustment in the first and second series circuits.

  In FIG. 18, the element value of each circuit element used for the measurement is described near each circuit symbol. In this measurement, all the inductances of the first and second inductors L11 and L12 and the third and fourth inductors L13 and L14 were set to the same value (580 μH). Regarding the elements in the parallel circuit portion, the seventh inductor L17 = 22 μH, the third capacitor C13 = 1 pF, and the resistance element R11 = 1.1 kΩ.

  FIG. 19 shows the measurement results. 3 is a graph showing the frequency characteristics of the attenuation amount of common mode noise in the noise suppression circuit. The horizontal axis represents frequency (Hz), and the vertical axis represents attenuation (gain) (dB). In FIG. 19, a line denoted by reference numeral 93 indicates an actual measurement result using the circuit of FIG. 18. A line denoted by reference numeral 91 is set as a target value of attenuation. A line denoted by reference numeral 92 indicates an actual measurement result of a circuit prepared as a comparative example this time. The circuit of this comparative example is obtained by omitting the seventh inductor L17, the third capacitor C13, and the resistance element R11, which are parallel circuit portions, from the circuit of FIG.

  From the measurement result of FIG. 19, it can be seen that the noise suppression circuit according to the present embodiment has the parallel circuit portion, and thus the attenuation pole 93A is generated on the high frequency side. Thereby, compared with the circuit of the comparative example which does not have a parallel circuit part, especially in the high frequency side, the noise component can be suppressed more effectively.

  The characteristics of the noise suppression circuit according to the present embodiment are the same as those of the noise suppression circuit according to the first embodiment except for the difference between the normal mode and the common mode. Therefore, the noise suppression circuit according to the present embodiment has a relatively simple configuration in which two series circuits composed of an inductor and a capacitor are added to the common mode choke coil, and a parallel circuit is further added. Common mode noise can be effectively suppressed in a wide frequency range without using a coil having a large inductance.

  Note that the noise suppression circuit according to each embodiment includes means for reducing ripple voltage and noise generated by the power conversion circuit, noise on the power line in power line communication, and communication signals on the indoor power line are transmitted to the outdoor power line. It can be used as a means for preventing leakage.

  In addition, this invention is not limited to said each embodiment, A various change is possible. For example, the noise suppression circuit of the present invention may include the normal mode noise suppression circuit according to the first or second embodiment and the common mode noise suppression circuit according to the third embodiment. Good.

It is a circuit diagram which shows the 1st and 2nd structural example of the noise suppression circuit which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows the other structural example of the noise suppression circuit which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows the further another structural example of the noise suppression circuit which concerns on the 1st Embodiment of this invention. It is a figure which shows the actual structural example of a 1st and 2nd inductor. It is a figure which shows the circuit structure used for the 1st simulation for calculating | requiring the characteristic of the noise suppression circuit which concerns on the 1st Embodiment of this invention. It is a characteristic view which shows a 1st simulation result. It is a figure which shows the circuit structure used for the 2nd simulation for calculating | requiring the characteristic of the noise suppression circuit which concerns on the 1st Embodiment of this invention. It is a characteristic view which shows a 2nd simulation result. It is a circuit diagram which shows one structure of the noise suppression circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the other structural example of the noise suppression circuit which concerns on the 2nd Embodiment of this invention. It is a figure which shows the actual structural example of a 1st and 2nd inductor, and a 5th and 6th inductor. It is a figure which shows the circuit structure used for the simulation for calculating | requiring the characteristic of the noise suppression circuit which concerns on the 2nd Embodiment of this invention. It is a characteristic view which shows the simulation result of the noise suppression circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows one structural example of the noise suppression circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the 2nd structural example of the noise suppression circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the 3rd structural example of the noise suppression circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the 4th structural example of the noise suppression circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows the circuit structure used for the measurement for calculating | requiring the characteristic of the noise suppression circuit which concerns on the 3rd Embodiment of this invention. It is a characteristic view which shows the measurement result of the characteristic of the noise suppression circuit which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

  C1, C11 ... first capacitor, C2, C12 ... second capacitor, C3, C13 ... third capacitor, Ca, Cb ... parasitic capacitance, L1, L11 ... first inductor, L2, L12 ... second Inductor, L3, L13 ... Third inductor, L4, L14 ... Fourth inductor, L5, L15 ... Fifth inductor, L6, L16 ... Sixth inductor, L17 ... Seventh inductor, R1, R11 ... Resistance Element, Rd ... parasitic resistance, 3 ... first conductive wire, 4 ... second conductive wire, 11, 11a, 11b, 21, 21a, 21b ... winding, 12, 22 ... magnetic core, 15 ... series circuit, 16, 16A, 16B, 41, 41A, 41B ... parallel circuit.

Claims (10)

A circuit that suppresses normal mode noise that is transmitted by first and second conductive lines and causes a potential difference between the conductive lines,
First and second inductors inserted in series and electromagnetically coupled to the first conductive line;
A series circuit composed of a third inductor and a first capacitor connected in series;
A parallel circuit portion having at least one stage of a parallel circuit including a fourth inductor and a second capacitor connected in parallel;
One end of the parallel circuit portion is connected to the series circuit, one end of a circuit composed of the series circuit and the parallel circuit portion is connected between the first inductor and the second inductor, and the other end is connected A noise suppression circuit, wherein the noise suppression circuit is connected to the second conductive line. The noise suppression circuit according to claim 1, wherein inductances of the first and second inductors have the same value. The noise suppression circuit according to claim 1, wherein the parallel circuit further includes a resistance element connected in parallel to the fourth inductor and the second capacitor. A circuit that suppresses normal mode noise that is transmitted by first and second conductive lines and causes a potential difference between the conductive lines,
First and second inductors inserted in series and electromagnetically coupled to the first conductive line;
A series circuit composed of a third inductor and a first capacitor connected in series;
A parallel circuit portion having at least one stage of a parallel circuit including a fourth inductor and a second capacitor connected in parallel;
And fifth and sixth inductors inserted in series in the second conductive line and electromagnetically coupled,
One end of the parallel circuit portion is connected to the series circuit, one end of a circuit composed of the series circuit and the parallel circuit portion is connected between the first inductor and the second inductor, and the other end is connected The noise suppression circuit is connected between the fifth inductor and the sixth inductor. The noise suppression circuit according to claim 4, wherein inductances of the first and second inductors have the same value, and inductances of the fifth and sixth inductors have the same value. 6. The noise suppression circuit according to claim 4, wherein the parallel circuit further includes a resistance element connected in parallel to the fourth inductor and the second capacitor. The noise suppression circuit according to any one of claims 4 to 6, wherein the first and second inductors and the fifth and sixth inductors are electromagnetically coupled. A circuit for suppressing common mode noise propagating in the same phase through the first and second conductive lines,
First and second inductors inserted in series and electromagnetically coupled to the first conductive line;
Third and fourth inductors inserted in series and electromagnetically coupled to the second conductive line;
A first series circuit comprising a fifth inductor and a first capacitor connected in series;
A second series circuit comprising a sixth inductor and a second capacitor connected in series;
A parallel circuit including an eighth inductor and a fourth capacitor connected in parallel with a first parallel circuit portion having at least one stage of a parallel circuit including a seventh inductor and a third capacitor connected in parallel A second parallel circuit portion having at least one stage of circuit,
One end of the first parallel circuit portion is connected to the first series circuit, and one end of the first circuit composed of the first series circuit and the first parallel circuit portion is connected to the first inductor. Connected to the second inductor, and the other end is grounded;
One end of the second parallel circuit portion is connected to the second series circuit, and one end of a second circuit composed of the second series circuit and the second parallel circuit portion is connected to the third inductor. A noise suppression circuit, wherein the noise suppression circuit is connected to the fourth inductor and the other end is grounded. The noise suppression circuit according to claim 8, wherein the inductances of the first and second inductors have the same value, and the inductances of the third and fourth inductors have the same value. The parallel circuit in the first parallel circuit portion further includes a resistance element connected in parallel to the seventh inductor and the third capacitor,
10. The noise suppression according to claim 8, wherein the parallel circuit in the second parallel circuit portion further includes a resistance element connected in parallel to the eighth inductor and the fourth capacitor. circuit.

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