JP4414520B2 - Control device for pachinko machines - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device for a pachinko gaming machine, and in particular, controls a pachinko gaming machine having a function of controlling a gaming machine represented by a pachinko gaming machine, a slot machine, etc. and returning a malfunction to a normal operation. Relates to the device.
[0002]
[Prior art]
In general, pachinko machines have special advantages for players when a predetermined condition is established according to a signal input to the game operation of the pachinko machine, and a predetermined condition is established for paying the pachinko balls to the player. The control is performed by the CPU, such as a game control for converting to a different state and a ball payout control for paying out a ball and lending a ball instead of money.
[0003]
The CPU that controls the pachinko gaming machine may not operate normally due to noise or the like and may run away. Therefore, as a method of preventing runaway of the CPU, Japanese Patent Laid-Open No. 9-253312, a function with a security check function, detects a malfunction (runaway) due to causes such as noise or a decrease in power supply voltage and returns it to a normal state. A CPU with a built-in watchdog function has been proposed. This is because a predetermined signal is periodically output from the CPU to the monitoring means (so-called watch dog circuit), and when the program runs out of control and the predetermined signal is not output, the watch dog circuit makes a determination. Is. When no signal is input from the CPU during the monitoring time set by the watchdog circuit, it is determined that the CPU is out of control and a reset signal for initializing the CPU is output from the watchdog circuit to execute the program to the initial address of the program. It is a method to prevent runaway by returning.
[0004]
Japanese Patent Application Laid-Open No. 10-15201 proposes a reset method in which a periodic pulse signal is input from the outside of the CPU to the reset terminal of the CPU in the gaming machine, and the program is executed from the first address for each reset. Yes.
[0005]
[Problems to be solved by the invention]
However, in the technique described in Japanese Patent Application Laid-Open No. 9-253312, since the CPU has a built-in watch dog circuit, there is a possibility that the watch dog circuit may not operate normally when a factor causing the CPU to run away occurs. .
[0006]
Further, in a CPU having a security check function, when the CPU is operating normally, a program that periodically outputs a signal to the watchdog circuit is executed. However, this program is not executed until it is determined that the program is appropriate after the security check, and a signal cannot be output to the watchdog circuit. If the watchdog circuit monitoring time is shorter than the security check time, the reset pulse signal is input from the watchdog circuit to the CPU before the security check is completed. Cannot transition to. On the other hand, if the watchdog circuit monitoring time is longer than the security check time, there is a problem that the CPU cannot be promptly restored when the CPU runs out of control after shifting to the user mode.
[0007]
Further, the technique described in Japanese Patent Laid-Open No. 10-15201 has a drawback that fraud is easily performed because the program processing is executed in synchronization with a pulse signal generated by hardware. Further, since all the program processing must be completed within the reset interval, there is a problem that the hardware must be changed depending on the amount of processing to be programmed.
[0008]
The present invention has been made to solve the above-mentioned problem. The monitoring time of the monitoring means can be set to the most efficient time, and the monitoring means can be normally operated even when a factor causing the control means to run away occurs. An object of the present invention is to provide a control device for a pachinko gaming machine that can be operated.
[0009]
[Means for Solving the Problems]
In order to achieve the above-mentioned object, the invention according to claim 1 is configured to sequentially execute predetermined control procedures for pachinko gaming machines and to perform security check for determining whether or not the program for performing the control is appropriate. A control means for executing a predetermined time from the input, a periodic signal output from the control means, and a monitoring means for resetting the control means when the periodic signal is interrupted; and During the security check period, By outputting to the monitoring means a pseudo signal representing the periodic signal different from the periodic signal, Said monitoring means Regulating surveillance And a monitoring and regulating means.
[0010]
According to the first aspect of the present invention, the control means executes various controls of the pachinko gaming machine by sequentially executing predetermined control procedures of the pachinko gaming machine. For example, a prize ball control for paying out a pachinko ball to the player in accordance with a signal input to the game operation of the pachinko gaming machine, a game that is converted into a special advantageous state for the player when a predetermined condition is satisfied Arithmetic processing for performing various controls such as control and ball payout control for paying out pachinko balls and lending pachinko balls instead of money is performed. Further, the control means executes a security check for diagnosing whether or not the program for performing the various controls described above is normally performed for a predetermined time from the time of power-on.
[0011]
The monitoring unit monitors a periodic signal output from the control unit (a signal output when performing the above control, a basic clock signal, etc.), and when the periodic signal is interrupted, the control unit The control means is reset because it is not operating normally. Therefore, when the control means is not operating normally due to runaway or the like, the control means can be reset.
[0012]
And the monitoring and regulating means during the security check period of the controlling means, By outputting to the monitoring means a pseudo signal representing a periodic signal, which is different from the periodic signal, Monitoring of control means by monitoring means Regulation By doing so, monitoring of the control means by the monitoring means can be restricted only during the security check period. Further, when the security check is completed, the invalidation of the monitoring unit by the monitoring restriction unit is canceled, and the control unit can be monitored by the monitoring unit.
[0013]
That is, since monitoring of the control means by the monitoring means is restricted only during the security check period, the monitoring time of the control means by the monitoring means can be set to the most efficient time, and after the security check period ends, Even when a factor that causes the control means to run away occurs, the monitoring means can be operated normally.
[0014]
According to a second aspect of the present invention, in the first aspect of the invention, the monitoring and regulating means is A signal from the mode terminal of the control means for generating a predetermined clock is output to the monitoring means as the pseudo signal. It is characterized by that.
[0015]
According to the invention of claim 2, in the invention of claim 1, the monitoring and regulating means is As a pseudo signal, the signal from the mode terminal of the control means for generating a predetermined clock Monitoring means What By outputting, monitoring of the control means of the monitoring means can be restricted only during the security check period. When the security check is completed, a periodic signal is output from the control unit instead of the pseudo signal output from the pseudo signal output unit, so that the control unit can be monitored by the monitoring unit.
[0016]
That is, since monitoring of the control means by the monitoring means is restricted only during the security check period, the monitoring time of the control means by the monitoring means can be set to the most efficient time, and after the security check period ends, Even when a factor that causes the control means to run away occurs, the monitoring means can be operated normally.
[0017]
According to a third aspect of the present invention, in the first aspect of the present invention, the monitoring and regulating means includes: A signal adjusted by dividing the signal from the mode terminal of the control means for generating a predetermined clock is output to the monitoring means as the pseudo signal. It is characterized by that.
[0018]
According to the invention of claim 3, in the invention of claim 1, A signal adjusted by dividing the signal from the control mode terminal that generates a predetermined clock is output to the monitoring means. As a result, the operation of the monitoring means during the security check can be restricted. When the security check is completed, the monitoring function of the monitoring unit is executed, so that the control unit can be monitored by the monitoring unit.
[0019]
That is, since monitoring of the control means by the monitoring means is restricted only during the security check period, the monitoring time of the control means by the monitoring means can be set to the most efficient time, and after the security check period ends, Even when a factor that causes the control means to run away occurs, the monitoring means can be operated normally.
[0020]
According to a fourth aspect of the invention, in the invention according to any one of the first to third aspects, the control means and the monitoring means are provided at different positions.
[0021]
According to the invention described in claim 4, in the invention described in any one of claims 1 to 3, each means is provided by providing the control means and the monitoring means at different positions. Since the difference due to the environment can be ensured, the monitoring means can be operated normally even if a factor causing inconvenience occurs in the control means. Further, it is possible to provide an effective noise countermeasure circuit or the like according to each environment, and it is possible to improve the reliability of the control means.
[0022]
Accordingly, there is provided a control device for a pachinko machine in which the monitoring time of the monitoring means can be set to the most efficient time, and the monitoring means can be operated normally even when a factor causing the control means to run away occurs. be able to.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a control device 10 for a pachinko gaming machine according to the present embodiment.
[0024]
The control device 10 of the pachinko gaming machine, for example, a prize ball control for paying out a pachinko ball to the player in accordance with a signal input to the gaming operation of the pachinko gaming machine, a player that satisfies a predetermined condition CPU chip 12 called V2 (hereinafter referred to as CPU), which is a main part of control of pachinko gaming machines such as game control to be converted to a state advantageous to the user, and has a function of performing a security check at power-on, The CPU monitoring means 14, the power-on reset circuit 16, the clock generating means 18 for generating the reference clock, and the monitoring restricting means 20 for restricting the operation of the CPU monitoring means 14 are the main components. 10 and the interface 22 for matching the pachinko gaming machine, the ROM 24 storing the program for operating the control device 10 and various data, and the like. Les decoder 26 is connected via a data bus 28 and address bus 30, clock generator 18 is connected to the clock terminal CL. The clock generator 18 generates a basic clock for the CPU 12.
[0025]
In the present embodiment, what is constituted by the control means including the CPU 12 and part of the ROM 24 and the address decoder 26 is referred to as so-called V2. In the V2, security information indicating that the program suitability is determined to have passed as a result of a test by a third-party organization is stored in the ROM 24 in advance. Based on the security information, the security information is stored as a security check function when the power is turned on. Verification is performed. Here, when a program stored in the ROM 24 is falsified or an illegally created ROM is mounted, it is possible to determine that the security information is inconsistent and the program has been illegally modified. It is configured.
[0026]
The CPU 12 sequentially executes predetermined control procedures for pachinko gaming machines, and has a security function for determining whether a program is appropriate when the power is turned on as described above. Further, the CPU 12 and the pachinko gaming machine are connected so as to be able to communicate with each other.
[0027]
A coder 26 is connected to the address terminal A of the CPU 12 by an address via an address bus 30, and when the address decoder 26 outputs certain address data from the address terminal A, the corresponding input / output port 32 has a corresponding input / output. Has the function to enable the port. If the program is executed and proceeds normally, a periodic clock is output from the CPU 12 to the data bus at time intervals determined in advance by the program. Address data for enabling the input / output port connected to the CPU monitoring means 14 is output from the CPU 12 to the address decoder 26 in accordance with the timing at which this clock is output, so that the CPU 12 periodically sends it to the CPU monitoring means 14. The CPU monitoring means 14 clearing clock is input. The CPU monitoring means 14 clearing clock may be directly output from the data bus of the CPU 12.
[0028]
The CPU monitoring means 14 is a so-called watch dog circuit, and a reset signal for initializing the CPU 12 is applied to the reset terminal RES of the CPU 12 only when the CPU monitoring means 14 clearing clock is not input for a time longer than a predetermined time. input.
[0029]
The monitoring restricting means 20 corresponds to the pseudo signal output means and the monitoring function stop means of the present invention, and restricts the operation of the CPU monitoring means 14, and the CPU 12 of the CPU monitoring means 14 monitors the CPU 12 during the security check period. To regulate.
[0030]
Next, the operation of the control device 10 for the pachinko gaming machine according to the embodiment of the present invention will be described.
[0031]
First, when the control device 10 and the pachinko gaming machine are powered on, the power-on reset circuit 16 operates to output a reset signal to the reset terminal RES of the CPU 12. As a result, the CPU 12 is initialized, and at the same time, the basic clock is input to the CPU 12 from the basic clock generating means. Then, the above-described security check function is activated by the CPU 12. At this time, the monitoring restricting means 20 controls the CPU monitoring means 14 to input a signal equivalent to the above-described CPU monitoring means 14 clearing clock. In addition, you may make it control so that operation | movement of the CPU monitoring means 14 stops.
[0032]
When the security check is completed, the CPU 12 periodically executes a program for outputting a CPU monitoring means 14 clearing clock to the CPU monitoring means 14. Then, simultaneously with the execution of the program, the normal operation of the CPU monitoring unit 14 is controlled by the monitoring restriction unit.
[0033]
That is, the CPU monitoring means 14 determines that the CPU 12 is out of control and outputs a reset signal to the CPU 12 because the CPU monitoring means 14 clear clock is not input from the CPU 12 to the CPU monitoring means 14 before the security check is completed. Since it is possible to prevent the user mode from being shifted to the user mode for executing the user program, the CPU monitoring means 14 starts its operation at the same time as the CPU monitoring means 14 clearing clock is input to the user monitor. After the transition to the mode, if the CPU 12 runs away, the CPU 12 can be quickly returned.
[0034]
Further, by providing the CPU 12 and the CPU monitoring means 14 separately, it is possible to ensure the difference in noise environment due to the difference in the position where they are arranged, so even when a factor causing the CPU 12 to run away occurs. The CPU monitoring means 14 can be operated normally. Further, by providing the CPU 12 and the CPU monitoring unit 14 separately, it is possible to provide an effective noise countermeasure circuit corresponding to each environment, and the reliability of the CPU 12 itself can be improved.
[0035]
【Example】
Hereinafter, with reference to the drawings, a reference example and embodiments of the CPU monitoring means 14 and the monitoring restriction means 20 of the present invention will be described in detail. In the embodiment, the CPU 12, the ROM 24, and the address decoder 26 are described as separate configurations. However, in the following embodiments, the CPU 12 is described as V2 including the CPU 12, the ROM 24, and the address decoder 26 as described above. .
[First reference Example]
As shown in FIG. 2, the VD1 terminal and the VD2 terminal of the CPU 12 called V2 having a function of performing a security check when the power is turned on are connected to the power supply voltage V, and the VSS1 terminal and the VSS2 terminal of the CPU 12 are grounded.
[0036]
A mode (MODE) terminal of the CPU 12 generates a predetermined clock and is connected to an input terminal of an Ex-OR circuit (exclusive OR circuit) 34. The other input terminal of the Ex-OR circuit 34 is grounded, the output terminal is connected to the cathode side terminal of the diode D1, the resistor R1 is connected in series to the anode side terminal of the diode D1, and the resistor R1. Is connected to the input terminal of the inverter circuit 36.
[0037]
A resistor R2 is connected in parallel with the diode D1 and the resistor R1 between the output terminal of the Ex-OR circuit 34 and the input terminal of the inverter circuit 36. The input terminal of the inverter circuit 36 further includes a capacitor C1. Is grounded.
[0038]
The output terminal of the inverter circuit 36 is connected to the input terminal of a switching circuit 38 mainly composed of resistors and transistors. The output terminal of the switching circuit 38 comprises an emitter terminal and a collector terminal of a transistor Tr as shown in FIG. 2, the emitter terminal is grounded, and the collector terminal receives the high impedance of the watchdog circuit (CPU monitoring means) 20. It is connected to the RCT terminal that functions while being stopped and stops functioning when it goes low.
[0039]
The watchdog circuit 14 has an H level or an L level of the clock input to the CT terminal and the CK terminal for defining the time from when the clock is input to the CK (clock) terminal to when the reset signal is output from the RESET_ terminal. The VS terminal for setting the boundary voltage is grounded via capacitors C3 and C4, and the GRD terminal is grounded. The VCC terminal is connected to the power supply voltage V and grounded via the capacitor C2.
[0040]
Further, a RESET_ (reset) terminal that outputs a low level as a reset signal of the watchdog circuit 14 is connected to an input terminal of the Ex-OR circuit 40, and the other input terminal of the Ex-OR circuit 40 is grounded. The output terminal is connected to the reset terminal of the CPU 12 via a resistor R3 and an inverting circuit.
[0041]
The reset terminal of the CPU 12 is connected to the above-described resistor R3 through an inverting circuit and grounded through a capacitor C5.
[0042]
Next, the first reference The operation of the example will be described.
[0043]
During the security check period of the CPU 12, the output terminal of the Ex-OR circuit 34 outputs a signal similar to the signal output from the mode terminal of the CPU 12. That is, after the power is turned on, the mode terminal in the security check period generates a clock having a predetermined width. If the security check is normal, the ROM fetch wait for the period of three clocks output by the mode terminal in the security check period After a while, shift to user mode. At this time, the mode terminal becomes high level (H level). When the H level is output from the mode terminal here, the capacitor C1 is charged through the resistor R2.
[0044]
As the battery is charged, the voltage applied to the capacitor C1 gradually increases. However, before reaching the threshold voltage of the inverter circuit 36, the output terminal of the Ex-OR circuit 34 becomes a low level (L level) so that discharging starts. Are set to the values of the resistor R2 and the capacitor C1, and the electric charge at the time of discharging is discharged via the Ex-OR circuit 34.
[0045]
As described above, the H level signal output from the mode terminal is input to the inverter circuit 36 through the integrating circuit including the resistor R2 and the capacitor C1. By selecting the values of the resistor R2 and the capacitor C1 to be larger than the clock width of the clock signal output from the mode terminal, the potential at the point A shown in FIG. it can. After that, the width of the signal output from the mode terminal when shifting to the user mode is sufficiently larger than the clock width output from the mode terminal during the security check period, so the potential at point A shifts from the mode terminal to the user mode. After the signal is output, it becomes H level after a certain time. The predetermined time is determined by the values of the resistor R2 and the capacitor C1. Therefore, the potential at the point B shifts to the user mode from when the power is turned on and remains at the H level until a certain time later, but then changes to the L level. In this way, the function of the watchdog circuit 14 can be limited for a certain period from the time of power-on.
[Second reference Example]
As shown in FIG. 3, the VD01 terminal and the VD02 terminal of the CPU 12 are connected to the power supply voltage V, and the VSS1 terminal and the VSS2 terminal of the CPU 12 are grounded.
[0046]
The RES_ terminal of the CPU 12 is connected to the RESET_ terminal of the watchdog circuit 14, and the OUT terminal of the CPU 12 is connected to a CK terminal for inputting a periodic clock for judging the runaway of the CPU 12 of the watchdog circuit 14.
[0047]
The GRD terminal of the watchdog circuit 14 is grounded, and the CT terminal is grounded via a capacitor C10. The VCC terminal is connected to the power supply voltage V, the RCT terminal is connected to the collector terminal of the transistor Tr1, the emitter terminal of the transistor Tr1 is grounded, and the base terminal is connected to the output terminal of the inverter circuit 42 via the resistor R10. ing.
[0048]
An input terminal of the inverter circuit 42 is grounded via a capacitor C11 and is connected to a parallel circuit of a resistor R11 and a diode D2. The other end of the parallel circuit is connected to a power supply voltage V.
[0049]
Then, the second reference The operation of the example will be described.
[0050]
Immediately after the power supply voltage is turned on, no electric charge is accumulated in the capacitor C11, so that the potential at the point C is at the ground level. Thereafter, a current flows from the power supply voltage V to the capacitor C11 through the resistor R11, and electric charge is accumulated in the capacitor C11. In this process, the threshold voltage of the inverter circuit 42 connected to the point C is always reached, so that the potential at the point D becomes H level immediately after the power is turned on and shifts to L level after a predetermined time. While the point D is at the H level, the subsequent transistor Tr1 is turned on, so that the RCT terminal of the watchdog circuit 14 is at the L level. When the point D becomes L level after a predetermined time, the transistor Tr1 is turned off and the RCT terminal is in the oven state. Accordingly, the function of the watch dog circuit 14 can be stopped only for a predetermined time after the power is turned on, and the output from the watch dog circuit 14 to the CPU 12 can be regulated.
[0051]
If a periodic clock is not output from the CPU 12 even after the monitoring time set by the capacitor C10 has elapsed after a predetermined time has elapsed, a reset signal is output from the watchdog circuit 14 to the CPU 12 and the CPU 12 is reset. Is done. This predetermined time can be set by setting values of the resistor R11 and the capacitor C11. The diode D2 is for quickly discharging the charge of the capacitor C11 when the power is turned off to prepare for the next power-on.
[Third reference Example]
As shown in FIG. 4, the VD01 terminal and the VD02 terminal of the CPU 12 are connected to the power supply voltage V, and the VSS1 terminal and the VSS2 terminal of the CPU 12 are grounded.
[0052]
The RES_ terminal of the CPU 12 is connected to the RESET_ terminal of the watch dog circuit 14, and the OUT terminal of the CPU 12 is connected to the CK terminal of the watch dog circuit 14.
[0053]
The GRD terminal of the watchdog circuit 14 is grounded, and the CT terminal is grounded via a capacitor C21. The VCC terminal is connected to the power supply voltage V, the RCT terminal is connected to the collector terminal of the transistor Tr2, the emitter terminal of the transistor Tr2 is grounded, and the base terminal is connected to the output terminal of the inverter circuit 44 via the resistor R21. ing.
[0054]
The input terminal of the inverter circuit 44 is grounded via the capacitor C22 and is connected to the resistor R22. The other end of the resistor R22 is connected to the mode terminal of the CPU 12.
[0055]
Then, the third reference The operation of the example will be described.
[0056]
In the security check period after power-on, the mode terminal generates a clock. The clock width is four times the basic clock width input to the CPU 12. When the security check is normal, the system shifts to the user mode after a ROM fetch waiting period corresponding to three clocks output from the mode terminal during the security check period. At this time, the mode terminal becomes H level. A signal output from the mode terminal is input to the inverter circuit 44 through an integrating circuit including a resistor R22 and a capacitor C22. If the values of the resistor R22 and the capacitor C22 are set to be larger than the clock width of the clock signal output from the mode terminal, the potential at the point E can be maintained at the L level during power-on and the security check period. After that, the width of the signal output from the mode terminal when the mode is shifted to the user mode is sufficiently larger than the width of the clock output from the mode terminal during the security check period. After the shifted signal is output, the signal shifts to the H level after a predetermined time. The predetermined time is determined by the values of the resistor R22 and the capacitor C22. Therefore, the potential at the point F shifts to the user mode from the time of power-on and shifts to the H level until a predetermined time later, but then shifts to the L level. In this way, the function of the watchdog circuit 14 can be limited for a predetermined time from when the power is turned on.
[0057]
[4th reference Example]
As shown in FIG. 5, the VD01 terminal and the VD02 terminal of the CPU 12 are connected to the power supply voltage V, and the VSS1 terminal and the VSS2 terminal of the CPU 12 are grounded.
[0058]
The RES_ terminal of the CPU 12 is connected to the RESET_ terminal of the watch dog circuit 14, and the OUT terminal of the CPU 12 is connected to the CK terminal of the watch dog circuit 14.
[0059]
The GRD terminal of the watch dog circuit 14 is grounded, and the CT terminal is grounded via a capacitor C31. The VCC terminal is connected to the power supply voltage V, the RCT terminal is connected to the collector terminal of the transistor Tr3, the emitter terminal of the transistor Tr3 is grounded, and the base terminal is 1Q_ of the IC circuit 46 having a latch circuit via the resistor R31. Connected to the terminal. The IC circuit 46 can use a general-purpose IC 74HC73.
[0060]
The 1J terminal and the VCC terminal of the IC circuit 46 are connected to the power supply voltage V, and the 1K terminal and the GRD terminal are grounded. The 1CK terminal of the IC circuit 46 is connected to the LIR terminal of the CPU 12 and is connected to the power supply voltage V via the resistor R32. Further, the 1CLR terminal of the IC circuit 46 is grounded via a capacitor C32, and is connected to the power supply voltage V via a parallel circuit including a resistor R33 and a diode D3.
[0061]
Then, the fourth reference The operation of the example will be described.
[0062]
The LIR terminal of the CPU 12 outputs a signal indicating that the CPU 12 has started fetching instructions. The LIR terminal is in a high impedance state during system reset and security check, and this signal is connected to the power supply voltage V through the resistor R32. Therefore, while the LIR terminal is in the high impedance state, the 1CK terminal of the IC circuit 46 is Becomes H level.
[0063]
Immediately after the power is turned on, the IC circuit 46 is initialized by the reset circuit constituted by the resistor R33, the capacitor C32, and the diode D3, and the 1Q_ terminal shifts to the H level. The LIR terminal of the CPU 12 shifts to the user mode after the security check period, and shifts to the L level when the first instruction is fetched. That is, during the security check period after the power is turned on, the 1CK terminal is at the H level. When the mode is shifted to the user mode and the first instruction is fetched, the level is shifted to the L level and the falling edge of the signal at the 1CK terminal is input. At that time, since it is input to the 1K terminal, the L level is output to the 1Q_ terminal. After that, since the L level is latched at the 1Q_ terminal unless the power is turned off, the function of the watch dog circuit 14 can be stopped only during the period from the time when the power is turned on to the time when the mode is shifted to the user mode and the first instruction is fetched. it can.
[No. 1 Example]
As shown in FIG. 6, the VD01 terminal and the VD02 terminal of the CPU 12 are connected to the power supply voltage V, and the VSS1 terminal and the VSS2 terminal of the CPU 12 are grounded.
[0064]
The RES_ terminal of the CPU 12 is connected to the RESET_ terminal of the watch dog circuit 14, and the OUT terminal of the CPU 12 is grounded via the resistor R 41 and is connected to the input terminal of the OR circuit 48. The other input terminal of the OR circuit 48 is connected to the mode terminal of the CPU 12 via an inverter circuit 50 including an inverting circuit.
[0065]
The output terminal of the OR circuit 48 is connected to the CK terminal of the watch dog circuit 14, the GRD terminal of the watch dog circuit 14 is grounded, and the CT terminal is grounded via a capacitor C41. The VCC terminal of the watch dog circuit 14 is connected to the power supply voltage V.
[0066]
Followed by 1 The operation of the embodiment will be described.
[0067]
The output of the OUT terminal of the CPU 12 cannot be controlled by the program during the period from when the power is turned on until the mode is changed to the user mode. Since this signal is connected to the GRD terminal via the resistor R41, the input terminal of the subsequent OR circuit 48 is at the L level during this period. Since the mode terminal of the CPU 12 outputs a clock during this period, this clock is input to the CK terminal of the watch dog circuit 14 as it is. Since the clock can be periodically input to the watchdog circuit 14 during this period, the reset signal cannot be output from the watchdog circuit 14 to the CPU 12.
[0068]
After shifting to the user mode, the mode terminal of the CPU 12 shifts to the H level and is inverted by the inverter circuit 50 and input to the OR circuit 48. Therefore, the input terminal of the OR circuit 48 to which the inverter circuit 50 is connected is L Move to level. During this period, if a clock is output from the OUT terminal of the CPU 12 in accordance with the program, this clock becomes a clear signal for the watchdog circuit 14.
[0069]
Therefore, during the security check period, the function of the watchdog circuit 14 can be restricted, and the watchdog circuit 14 can be operated along with the transition to the user mode.
[No. 2 Example]
As shown in FIG. 7, the VD01 terminal and the VD02 terminal of the CPU 12 are connected to the power supply voltage V, and the VSS1 terminal and the VSS2 terminal of the CPU 12 are grounded.
[0070]
The RES_ terminal of the CPU 12 is connected to the RESET_ terminal of the watch dog circuit 14, the OUT terminal is connected to the 1 Clear terminal of the IC circuit 52 having a frequency dividing function, and is connected to the input terminal of the OR circuit 54. The 1Clear terminal of the circuit 52 is grounded through a resistor R51. The IC circuit 52 can use a general-purpose IC 74HC393.
[0071]
The other input terminal of the OR circuit 54 is connected to the QD terminal of the IC circuit 52, and the output terminal is connected to the CK terminal of the watchdog circuit 14.
[0072]
The GRD terminal of the watchdog circuit 14 is grounded, the CT terminal is grounded via a capacitor C51, and the VCC terminal is connected to the power supply voltage V.
[0073]
Further, the 1A terminal of the IC circuit 52 and the mode terminal of the CPU 12 are connected, the GRD terminal of the IC circuit 52 is grounded, and the VCC terminal is connected to the power supply voltage V.
[0074]
Followed by 2 The operation of the embodiment will be described.
[0075]
First 2 In the embodiment, the clock signal output from the mode terminal of the CPU 12 and the clock signal to be input to the watchdog circuit 14 are adjusted by frequency division when there is a gap in the period or clock width.
[0076]
During the period from when the power is turned on to the transition to the user mode, the OUT terminal of the CPU 12 is at L level, and the IC circuit 52 changes the outputs of QA to QD at the fall of the signal input to the 1A terminal. The output of the QD terminal is a clock having a width of 16 clocks input to the 1A terminal, and this is input to one of the OR circuits 54. Since the other input of the OR circuit 54 during this period is at the L level, the reset signal cannot be output from the watchdog circuit 14 to the CPU 12 by the clock of the QD terminal.
[0077]
When the mode is shifted to the user mode and the clock is output from the OUT terminal of the CPU 12, the IC circuit 52 is cleared and the output of the QD terminal of the IC circuit 52 becomes L level. Therefore, the clock output from the OUT terminal of the CPU 12 becomes a clear signal for the watchdog circuit 14.
[0078]
Accordingly, the function of the watchdog circuit 14 can be restricted during the security check period, and the watchdog circuit 14 can be operated along with the shift to the user mode.
[0079]
the above Reference examples and As shown in the embodiment, the monitoring time of the watch dog circuit 14 can be set to the most efficient time. Also, above Reference examples and In each of the embodiments, the CPU 12 and the watch dog circuit 14 are separately provided. Therefore, even if a factor causing the CPU 12 to run away occurs, the difference in environment is ensured. Therefore, the watch dog circuit 14 can be operated normally. it can.
[0080]
【The invention's effect】
As described above, according to the present invention, the monitoring time of the monitoring means can be set to the most efficient time, and the monitoring means can be operated normally even when a factor that causes the control means to run away occurs. There is an effect that a control device for a pachinko gaming machine can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a control device for a pachinko gaming machine according to an embodiment of the present invention.
FIG. 2 reference It is a figure which shows the control apparatus of an example.
FIG. 3 reference It is a figure which shows the control apparatus of an example.
FIG. 4 reference It is a figure which shows the control apparatus of an example.
FIG. 5 reference It is a figure which shows the control apparatus of an example.
FIG. 6 1 It is a figure which shows the control apparatus of an Example.
FIG. 7 2 It is a figure which shows the control apparatus of an Example.
[Explanation of symbols]
10 Pachinko machine control device
12 CPU (control means)
14 Watchdog circuit (monitoring means)
20 Monitoring restriction means (pseudo signal output means and monitoring function stop means)

Claims (4)

Control means for sequentially executing a predetermined pachinko gaming machine control procedure and executing a security check for determining whether or not the program for performing the control is appropriate for a predetermined time from power-on;
Monitoring means for monitoring a periodic signal output from the control means, and resetting the control means when the periodic signal is interrupted;
A monitoring regulation unit that regulates monitoring of the monitoring unit by outputting a pseudo signal representing the periodic signal, which is different from the periodic signal, to the monitoring unit during a security check period of the control unit. When,
A control device for a pachinko gaming machine, comprising: 2. The control device for a pachinko gaming machine according to claim 1, wherein the monitoring restricting means outputs a signal from a mode terminal of the control means for generating a predetermined clock to the monitoring means as the pseudo signal . 2. The monitoring restriction unit outputs a signal adjusted by dividing a signal from a mode terminal of the control unit that generates a predetermined clock to the monitoring unit as the pseudo signal. Control device for pachinko machines.   4. The control device for a pachinko gaming machine according to claim 1, wherein the control unit and the monitoring unit are provided at different positions.

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