JP2011104072A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which avoids malfunction when applying the power source of a game machine, and in which each part of the game machine can appropriately perform an initial setting operation. <P>SOLUTION: A main control part 21 for centrally and integrally controlling a game operation is provided with a backup function of conserving the memory content of a RAM after the power source is shut down, and a watchdog timer circuit for compulsorily resetting a CPU unless clear pulses are received periodically. The CPU of the main control part 21 operates by performing a control program having: a system reset processing started upon the supply of dc voltage; and a timer interruption processing started at every fixed time. By repeatedly outputting clear pulses to the watchdog timer circuit until the initial processing performed in a subcontrol part 23 upon the start of dc voltage supply is terminated, a standby processing ST5 which does not shift to subsequent processing is provided in the system reset processing in the main control part. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a gaming machine such as a ball game machine or a slot machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that suppresses the possibility of a CPU reset due to a malfunction.

  A ball game machine such as a pachinko machine is configured by being divided into a game board on which game parts such as an electric tulip and a symbol start port are arranged, and a main body frame having a central opening. And a game machine will be in a completion state by making a game board fit in a center opening.

  The game board is provided with a symbol display section for displaying a series of symbol variation modes by a plurality of display symbols, a grand prize opening for opening and closing the opening and closing plate, and the like. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player.

  In this type of pachinko machine, generally, a main control board that centrally controls game operations, a payout control board that pays out game media based on control commands for payout operations output from the main control board, And an effect control board that executes the effect operation based on the control command for the effect operation output from the control board. The effect control board is generally equipped with a one-tick microcomputer that receives a control command from the main control unit and a VDP (Video Display Processor) that controls display of the liquid crystal display.

  By the way, in the gaming machine having such a configuration, even if the main control unit transmits a control command during the initial setting operation of the liquid crystal control board or the payout control board, the control command is not received by the downstream control board. Or, even if it is received, the control operation based on the control command cannot be started.

  Therefore, generally, a configuration is adopted in which the power reset timing of the CPU mounted on the main control board is delayed from the power reset timing of the CPU of the effect control board and the payout control board. Specifically, the power reset operation is delayed by providing a delay circuit in the power reset circuit of the main control board.

JP 2000-237435 A JP 2002-253822 A JP 2009-078036 A

  However, in order to further increase the image quality of the liquid crystal display and achieve a powerful effect, it takes a considerable amount of time (for example, about 2 seconds) for the initial setting of the effect control board when the power is turned on. Therefore, there is a problem that the time until the initial setting is completed cannot be ensured only by the delay circuit of the main control board.

  In such a case, the standby time can be ensured by software processing. However, if such a configuration is adopted, the watchdog timer is activated during the standby time, the CPU is forcibly reset, and thereafter the CPU is forcibly reset. By repeating the above, the gaming operation is not started.

  Here, as in the configuration described in Patent Document 1, a dedicated control terminal for stopping the charge / discharge operation of the watchdog timer is provided, and the operation of the watchdog timer is performed by maintaining the control terminal at the L level for a predetermined time. Prohibition is also possible. However, in the configuration of Patent Document 1, another dedicated circuit is required for maintaining the control terminal at the L level for a predetermined time. Furthermore, if this dedicated circuit fails, there is a problem that the watchdog timer does not operate permanently, and the failure cannot be detected at all in practice.

  In addition, the configurations of Patent Document 2 and Patent Document 3 are also known, but none of them can wait for the operation of the main control board until the initial setting operation on the downstream control board is completed.

  The present invention has been made in view of the above-described problems, and provides a gaming machine that avoids a malfunction when a gaming machine is turned on and that each part of the gaming machine can appropriately execute an initial setting operation. The purpose is to do.

  In order to achieve the above object, the present invention executes a lottery process based on a detection signal indicating the occurrence of a predetermined gaming operation, and determines whether or not to generate a gaming state advantageous to the player The main control unit that centrally controls the gaming operation, the sub control unit that executes the control operation based on the control command output from the main control unit, and the DC voltage generated from the AC voltage A power supply unit that supplies power to each control unit, and the main control unit includes a backup function that retains the stored contents of the RAM even after the power is shut off, and a CPU unless it receives a clear pulse periodically. A watchdog timer circuit for forcibly resetting, and the CPU of the main control unit performs a system reset process activated based on the supply of the DC voltage and a timer interrupt process activated at regular intervals. The watchdog is executed until the initial process executed in the system reset process and executed in the sub-control unit based on the start of supply of the DC voltage is completed. A standby process that does not proceed to the subsequent process by repeatedly outputting the clear pulse to the timer circuit is provided.

  The standby process is preferably executed in a state where interruption of the timer interrupt process is prohibited. Further, the clear pulse output in the standby process is preferably set to a duty ratio of about 50% for the purpose of suppressing high frequency noise. When such a clear pulse is generated by software processing, In practice, it is preferably set within the range of 40 to 60%.

  Preferably, the main control unit is provided with a reset circuit that detects an abnormal level of the DC voltage supplied from the power supply unit and resets the CPU, and the reset circuit includes the watchdog timer circuit. It is preferable that it is comprised.

  Further, the power supply unit is configured to detect that the AC voltage is cut off and output a power supply abnormality signal having an abnormal level, and the main control unit determines the level of the power supply abnormality signal, which is normal. Unless it is a level, it is preferable that a determination process for repeatedly determining the level of the power supply abnormality signal without shifting to the subsequent process is provided after the standby process.

  If the power supply abnormality signal is an abnormal level, the main control unit obtains the power supply abnormality signal a plurality of times in the execution period of the timer interrupt process, on condition that this is an abnormal level continuously. It is preferable that a power supply monitoring process for waiting for the DC voltage to become an abnormal level after storing predetermined management data in the RAM is provided. In this case, it is preferable that after passing through the standby process, whether or not the management data is appropriate is determined, and the stored contents of the RAM held by the backup power supply are used on condition that this is a predetermined value. .

  In the timer interrupt process, the present invention supplies a clear pulse to the watchdog timer circuit, and the power supply monitoring process sets the CPU to a timer interrupt disabled state after completing all the processes. Thus, it is preferable that the infinite loop process is repeated, and the maximum time from the start of the power monitoring process to the start of the infinite loop process is set shorter than the timer interrupt cycle.

  The standby time of the standby process is preferably set longer than the operation time of the initial setting process executed by the image control unit that controls the display device.

  According to the above-described present invention, it is possible to avoid an erroneous operation at the time of turning on the power of the gaming machine and to appropriately perform the initial setting operation of each part of the gaming machine.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit diagram which shows the circuit structure of a power supply board. It is a circuit diagram of the reset circuit of a main control part and a payout control part. It is a time chart which shows operation | movement of a power supply monitoring part and a reset circuit. It is a flowchart explaining the system reset process of a main control part. It is a flowchart explaining the timer interruption process of a main control part. It is a flowchart which shows a part of system reset process of a main control part in detail.

  Examples of the present invention will be described in detail below. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display is provided at the approximate center of the game area 5a inside. A display device DISP is arranged. In addition, at a suitable place in the game area 5a, a symbol start opening 15, a big winning opening 16, a plurality of normal winning openings 17 (four on the right and left of the large winning opening 16), and a gate 18 serving as a passing opening are arranged. Yes. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The display device DISP variably displays a specific symbol related to the big hit state and also displays a background image, various characters, and the like in an animated manner. This display device DISP has a special symbol display part Da to Dc in the center and a normal symbol display part 19 in the upper right part. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, the symbol start port 15 is opened and closed. The claw 15a is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM mainly receives a 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DISP, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is the main board relay board. It is transmitted to the payout control board 24 via 28.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Thus, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the image control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 is a sub-control unit.

  In addition to the one-chip microcomputer, the image control unit 23 is equipped with a dedicated VDP (Video Display Processor) for controlling the display of the liquid crystal display, thereby enabling complex and advanced image effects. The one-chip microcomputer mounted on the main control board 21 and the payout control board 24 incorporates a CPU core equivalent to Z80 CPU.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display device DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the power supply abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V received from the power supply board 20 to the main control unit 21 as they are. On the other hand, the power relay board 30 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the image control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been turned on to the power supply board 20. The power is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The effect control unit 22 and the image control unit 23 execute the effect operation in a dependent manner based on the control command from the main control unit 21, so that the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS output from is used.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  The power supply abnormality signals ABN1 and ABN2 received from the power supply board 20 by the main control unit 21 and the payout control unit 24 are signals indicating that the AC input power supply AC24V starts to drop, and receive the power supply abnormality signals ABN1 and ABN2. Thus, the control units 21 and 24 start necessary termination processing prior to a power failure or business termination. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 25 via the main board relay board 28, while the payout control unit 25 indicates a game ball payout operation. A prize ball counting signal and a status signal CON related to an abnormality in the payout operation are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with a power supply voltage VB (12 V) supplied from the main control unit 21. Each switch signal indicating a winning state to the symbol starting port 15 is converted to a TTL level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). Then, the data is transmitted to the main control unit 21.

  FIG. 4 is a circuit diagram showing a power supply circuit of the power supply board 20. This power supply circuit includes a second power supply unit SD that generates a DC voltage supplied to the production interface board 27, and a first power supply unit FR that generates a DC voltage supplied to the main control unit 21 and the payout control unit 24. A power monitoring unit MNT that monitors power-on and power-off, and a power-cut-off unit CUT that cuts off the ground line when an excessive AC voltage is received. Note that illustration of other DC voltages (DC 32 V) supplied to the payout control unit 24 and other DC voltages (DC 32 V, DC 15 V) supplied to the production interface board 27 is omitted.

<Second power supply unit SD>
The second power supply unit SD includes a full-wave rectifier circuit including diodes D1 to D4, a smoothing capacitor C1, a DC-DC converter that generates a DC voltage VB (12V), and a DC-DC that generates a DC voltage Vcc (5V). The converter includes smoothing capacitors C2 and C3. Each of the two DC-DC converters is a chopper type, and operates in common with the smoothing capacitor C1. The direct-current voltage generated by the second power supply unit SD is transmitted to the effect interface board 27 and then stepped down as appropriate to be used by the effect interface board 27, the effect control board 22, and the image control board 23. Is done.

<First power supply FR>
The first power supply unit FR generates a full-wave rectifier circuit using diodes D1, D2, D5, and D6, a smoothing capacitor C4, a DC-DC converter that generates a DC voltage VB (12V), and a DC voltage Vcc (5V). The power storage unit BK is configured by a DC-DC converter, smoothing capacitors C5 and C6, a diode D7, and a capacitor Cb. These two DC-DC converters are also of a chopper type and operate in common with the smoothing capacitor C4. The DC voltage generated by the power storage unit BK serves as a backup power supply BAK that holds data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24.

  The DC voltage VB and the DC voltage Vcc generated by the first power supply unit FR are supplied only to the main control unit 21 and the payout control unit 24, and the DC voltage transmitted to the effect interface board 27 is on the wiring. It is distinguished. Therefore, the main control unit 21 and the payout control unit 24 are not connected to the other sub-control units 22 and 23 via the power line, and transmission of high-frequency noise and the like is prevented.

  The total current in the main control unit 21 and the payout control unit 24 does not exceed 600 mA on the power supply voltage VB line and does not exceed 300 mA on the power supply voltage Vcc line. The voltage drop of the VB and Vcc power supply lines is not a problem at all.

<Power cutoff unit CUT>
The power cut-off unit CUT corresponds to the rectifying unit 51 that generates a DC voltage of a predetermined level from the AC voltage AC24V, the AC monitoring unit 52 that is turned on when the AC power supply lines LN1 and LN2 are overvoltage, and the AC monitoring unit 52 that is turned on. And a switch circuit 53 that performs an OFF operation.

  The rectifier 51 includes a diode D12 that receives an AC voltage from the AC power supply line LN2, a current limiting resistor R1, and a parallel circuit of a capacitor C8 and a Zener diode ZD2, which are connected in series. During normal operation, the voltage across the capacitor C8 is constant at the breakdown voltage of the Zener diode ZD2.

  The switch circuit 53 includes a MOS transistor Q2 having a large current capacity and a bias resistor R5 connected in parallel to the capacitor C8. Here, the transistor Q2 is in an ON state as long as the voltage across the capacitor C8 is at a predetermined level, and connects the ground line of all the circuits of the gaming machine and the frame ground FG.

  The AC monitoring unit 52 includes two diodes D8 and D9 connected to the AC power supply lines LN1 and LN2, a Zener diode ZD1 connected to the connection point of the diodes D8 and D9, a bias resistor R2 and R3, and a capacitor C7 in parallel. The circuit includes a transistor Q1 that is turned on when the voltage across the bias resistor R3 increases, and a current limiting resistor R4 of the transistor Q1.

  Zener diode ZD1 is normally in an OFF state, but when an excessive AC voltage (for example, AC 100V) is applied to AC power supply lines LN1 and LN2, it enters a breakdown state. In this breakdown state, the voltage at both ends of the bias resistor R3 increases and the transistor Q1 is turned on, so that the voltage at both ends of the capacitor C8 decreases.

  Then, the transistor Q2 that has been in the ON state until then is turned OFF, whereby the circuit ground and the frame ground FG are disconnected, and all the power supply voltages of all the gaming machines are cut off. The operation content of the power cut-off unit CUT is as described above. When the voltage across the AC power supply lines LN1 and LN2 exceeds the limit value, the power cut-off unit CUT functions to cut off all the power supply voltages of all the gaming machines at once.

<Power supply monitoring unit MNT>
Next, the power supply monitoring unit MNT will be described. The power supply monitoring unit MNT includes a power supply monitoring unit 54 that monitors the voltage levels of the AC power supply lines LN1 and LN2, a comparison voltage unit 55 that receives the power supply voltage Vcc and outputs a comparison reference voltage Vo, and a power supply monitoring unit 54. An abnormality detection unit 56 that detects a power supply abnormality by comparing output voltages of the unit 55 and a power supply reset unit 57 that generates a system reset signal SYS are configured.

[Power supply monitoring unit 54]
The power supply monitoring unit 54 includes two diodes D10 and D11 connected to the AC power supply lines LN1 and LN2, a series circuit of a resistor R6 and a Zener diode ZD3 connected to a connection point of the diodes D10 and D11, and a Zener diode ZD3. A series circuit of a diode D13 and a smoothing capacitor C9 connected in parallel, a series circuit of resistors R7 and R8 connected in parallel to the smoothing capacitor C9, and a comparator A3 that short-circuits the resistor R8 are configured.

  In this embodiment, the breakdown voltage of the Zener diode ZD3 is about 5.1V, and the Zener diode ZD3 receives the AC voltage AC24V through the current limiting resistor R6. For this reason, when the AC input power supply is in a power supply state, the voltage across the smoothing capacitor C9 is a constant value of about 4.5V. Since the resistance values of the two resistors R7 and R8 are set to R8 >> R7, the both-ends voltage Vs of the resistor R8 is about 4.5V corresponding to the normal level AC voltage AC24V. However, if the output of the comparator A3 is at L level, the voltage Vs across the resistor R8 is substantially 0V correspondingly. The resistor R7 functions as a current limiting resistor for the comparator A3 when the L level is output.

  The comparator A3 is composed of a QUAD comparator (NJM2901) together with other comparators A1 to A4. This QUAD comparator includes four comparators A1 to A4, but each of the comparators A1 to A4 is an open collector type (see FIG. 6 (i)).

  The output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminal of the comparator A3, and the comparison voltage V1 of about 2.8V is supplied to the plus terminal in the steady state. The comparison voltage V1 is generated by dividing the two types of power supply voltages Vcc and VB generated by the first power supply unit FR with resistors.

  As will be described later, when the power is turned on, the output voltage Vo of the comparison voltage unit 55 becomes a level corresponding to the power supply voltage Vcc whose level is rising (Vo = Vcc−Vf−Δ). Vf and Δ are voltage drops in the diodes D14 and D15 and the resistor R9.

  On the other hand, since the comparison voltage V1 is generated by dividing the power supply voltages Vcc and VB, immediately after the power is turned on, it is lower than the output voltage Vo of the comparison voltage unit 55. Therefore, in a transient state immediately after the power is turned on, the output of the comparator A3 becomes L level to short-circuit the resistor R8. As a result, the output voltage Vs of the power supply monitoring unit 54 becomes almost 0V.

  On the other hand, in a steady state in which the power supply voltages Vcc and VB have reached a predetermined level, the comparison voltage V1 is about 2.8V, while the output voltage Vo of the comparison voltage unit 55 is kept constant at about 2.5V. That is, the comparator A3 has a magnitude relationship of [input voltage to the plus input]> [input voltage to the minus terminal], but the output part of the comparator A3 is an open collector (see FIG. 6 (i)). As shown in FIG. 4, since the output terminal is not pulled up, the output section of the comparator A3 is opened and does not affect other circuits.

The operation of the power supply monitoring unit 54 described above is organized as follows.
(1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the resistor R8 is short-circuited by the output part of the comparator A3, so that the voltage Vs across the resistor R8 becomes approximately 0V.
(2) Thereafter, when the power supply voltage Vcc increases to near the normal level, the output part of the comparator A3 is opened, so that the voltage Vs across the resistor R8 is approximately 4.5 V corresponding to the voltage across the Zener diode ZD3. It becomes.
(3) When the AC voltage AC24V is cut off, the voltage Vs across the resistor R8 quickly drops to 0V. However, even if the AC voltage AC24V is cut off, the power supply voltages Vcc and VB maintain a predetermined level for a while, so that the output unit of the comparator A3 maintains the open state as it is.

[Comparison voltage unit 55]
The comparison voltage unit 55 includes diodes D14 and D15 that receive two power supply voltages Vcc and Vcc generated separately by the first power supply unit FR and the second power supply unit SD at respective anode terminals, and cathodes of the diodes D14 and D15. A current limiting resistor R9 connected to the terminal and the voltage generator GN are connected in series. In this embodiment, a shunt regulator (HA17431: RENESAS) is used as the voltage generator GN.

  This shunt regulator has an anode terminal A, a cathode terminal K, and a comparison terminal REF. In the state shown in the figure, in which the anode terminal A and the cathode terminal K are connected, the shunt regulator functions in the same manner as a Zener diode. A constant reference voltage Vo (2.5 V) is output between the anode and cathode terminals (see FIG. 6H). On the other hand, during the non-breakdown operation, the internal circuit is turned OFF, and the anode and cathode terminals are opened.

  Therefore, when the power is turned on, until the power supply voltage Vcc reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 (voltage generation unit GN) corresponds to the power supply voltage Vcc whose level is rising, Vo = Vcc−Vf. −Δ. On the other hand, when the power supply voltage Vcc reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 becomes a constant comparison reference voltage (2.5 V).

[Abnormality detection unit 56]
The abnormality detection unit 56 includes a comparator A1 that generates a power supply abnormality signal ABN1 to the main control unit 21, a comparator A2 that generates a power supply abnormality signal ABN2 to the payout control unit 24, and pull-up resistors R10 of the comparators A1 and A2. , R11 and a capacitor Cs connected between the input terminals of the comparators A1, A2. The output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminals of the comparators A1 and A2, and the voltage Vs across the resistor R8 is supplied to the plus terminal. The comparators A1 and A2 are built in the QUAD comparator (NJM2901) described above.

  Although not shown, power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 are supplied to input ports of the main control unit 21 and the payout control unit 24. An appropriate capacitor is connected between the input terminal of each input port and the ground, and each input port receives a power supply abnormality signal via an appropriate resistor to ensure noise resistance. . Further, the influence of spike noise is eliminated by appropriate software processing (ST34 to ST35 in FIG. 8).

  Since the power supply monitoring unit 54 operates as described above in (1) to (3), the abnormality detection unit 56 operates as follows in response to this.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the voltage Vs across the resistor R8 is almost 0V, while the output voltage Vo of the comparison voltage unit 55 corresponds to the power supply voltage Vcc whose level is rising. Vcc−Vf−Δ. Therefore, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 stably maintain the L level without changing the level. Timings T0 to T1 in FIG. 6C show a stable L level state when the power is turned on.

  (2) Thereafter, after the power supply voltage Vcc whose level is rising exceeds a predetermined level, the output voltage Vo of the comparison voltage unit 55 is maintained at 2.5V. Further, when the power supply voltage Vcc increases to near the normal level, the output part of the comparator A3 is opened, so that the voltage Vs across the resistor R8 becomes approximately 4.5V corresponding to the voltage across the Zener diode ZD3.

  Therefore, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 transition to the H level, and thereafter the H level indicating the normal state is constantly maintained. After timing T1 in FIG. 6C, normal level power supply abnormality signals ABN1, ABN2 are shown.

  (3) Thereafter, when the AC voltage AC24V is cut off for some reason, the voltage Vs across the resistor R8 quickly drops to 0V. However, since the power supply voltages Vcc and VB are maintained at a predetermined level for a while, the comparator A3 and the comparison voltage unit 55 maintain the operation so far.

  Therefore, when the AC voltage AC24V is cut off at the timing T7 in FIG. 6A, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 immediately transition from the H level to the L level to cause an abnormal situation. Indicates occurrence. The main control unit 21 and the payout control unit 24 regularly check the power supply abnormality signals ABN1 and ABN2, and immediately confirm that the power supply abnormality signals ABN1 and ABN2 have transitioned to the L level. It is supposed to start.

[Power reset unit 57]
Next, the power reset unit 57 composed of the comparator A4 will be described. As illustrated, a pull-up resistor R12 is connected to the output terminal of the comparator A4, and a series circuit of a resistor Rf and a capacitor Cf is connected between the output terminal and the plus terminal. Further, the output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminal of the comparator A4, and the comparison voltage V2 of about 2.95V is supplied to the plus terminal in the steady state. The comparison voltage V2 is generated by dividing the two types of power supply voltages Vcc and VB generated by the second power supply unit SD with resistors.

  Since the power reset unit 57 is configured as described above, it operates as follows.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the output voltage Vo of the comparison voltage unit 55 becomes Vcc−Vf−Δ corresponding to the power supply voltage Vcc whose level is rising. On the other hand, since the comparison voltage V2 is generated by dividing the power supply voltages Vcc and VB of the second power supply unit SD, it is lower than the output voltage Vo during the level increase. Therefore, in such a transient state, the system reset signal SYS output from the comparator A4 becomes L level (see FIG. 6A).

  (2) Thereafter, after the power supply voltage Vcc whose level is rising reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 is maintained at 2.5V. Further, when the power supply voltages Vcc and VB increase to near the normal level, the comparison voltage V2 approaches the steady value 2.95V. Therefore, the system reset signal SYS output from the comparator A4 transitions from the L level to the H level at an appropriate timing.

  The system reset signal SYS generated in this way is transmitted to the effect control unit 22 and the image control unit 23 via the effect interface board 27, and is provided in each control unit 22 and control unit 23. The power of the CPU and other ICs is reset via the delay circuit. Note that the series circuit of the resistor Rf and the capacitor Cf also exhibits a function of delaying the transition operation.

  FIG. 5A is a circuit diagram showing the reset circuit RST arranged in the main control unit 21 and the payout control unit 24. In this embodiment, the reset circuit RST is configured by utilizing the power supply voltage monitoring IC 1 (MB3771 Fujitsu Microelectronics) and the power supply voltage monitoring IC2 with a watchdog timer function (MB3773 Fujitsu Microelectronics).

  As shown in the equivalent circuit of FIG. 5B, the power supply voltage monitoring IC 1 includes two comparators CompA and CompB. The plus terminals of the two comparators CompA and CompB are set to about 1.24V by the built-in circuit.

  In the circuit configuration of the embodiment, since the Vsa terminal is connected to the ground via the capacitor C11, the potential of the negative terminal of the comparator CompA is divided by the built-in resistor and becomes about 1.4V. . On the other hand, since the power supply voltage VB is divided and supplied to the Vsb terminal by external voltage dividing resistors R20 and R21, the potential of the Vsb terminal is VB * R21 / (R20 + R21). A voltage stabilizing capacitor C12 is connected in parallel to the resistor R21. A delay capacitor C10 is connected to the Ct terminal.

Since the power supply voltage monitoring IC 1 has the internal circuit of FIG. 5B, when the power supply voltage Vcc rises to a predetermined level after the power is turned on (see timing T2 in FIG. 6D), it is built in. Charging of the delay capacitor C10 is started by the constant current source. Until the delay capacitor C10 is charged to a predetermined level (see T3 in FIG. 6E), the basic reset signal RS1 output from the reset terminal is maintained at the L level. The reset hold time Tpo [S] is Tpo [S] = 10 ⁵ * C10 [F] corresponding to the capacitance of the external capacitor C10.

  In this way, the basic reset signal RS1 that has become H level at the timing T3 maintains that level unless the power supply voltages Vcc and VB drop. However, the potential of the Vsb terminal is VB * R21 / (R20 + R21), and the level of the power supply voltage VB is monitored at this Vsb terminal. Similarly, the potential of the Vsa terminal is Vcc * 40 / (40 + 1001) corresponding to the built-in resistors 40 kΩ and 100 kΩ, and the level of the power supply voltage Vcc is monitored at this Vsa terminal.

  For this reason, when the voltage level of both or one of the power supply voltages Vcc and VB drops due to interruption of the AC input AC 24V or failure of the power supply units FR and SD (see timing T8 in FIG. 6D), the built-in comparators CompA, Any output terminal of CompB transitions to the H level. Then, the built-in flip-flop is set, and the basic reset signal RS1 output from the reset terminal immediately falls to the L level (see timing T8 in FIG. 6E).

  By the way, in this embodiment, a capacitor C11 is connected between the Vsa terminal and the ground, and a capacitor C12 is connected between the Vsb terminal and the ground. As is apparent from the equivalent circuit of FIG. 5B, these capacitors C11 and C12 have a function of delaying the operation of the internal circuit, and the power supply voltages Vcc and VB are reduced to, for example, 4 V or less for a short time. The basic reset signal RS1 is not output in the recovering instantaneous low state or instantaneous interruption state.

  In the present embodiment, Cll = C12 = 1000 pF is set, and in response to this, in the instantaneous interruption state or instantaneous low state where the level drop of the DC voltage (5V, 12V) recovers within 40 μS, The voltage monitoring IC 1 is configured not to react. Therefore, even if spike noise within a pulse width of 40 μS is superimposed on any of the power supply lines of the power supply voltages Vcc and VB supplied from the power supply substrate 20, the basic reset signal RS1 is not abnormally output.

  Corresponding to the power supply voltage monitoring IC 1 operating as described above, the basic reset signal RS1 is sent to the main control unit 21 and the payout control unit 24 as an I / O reset signal via the two NOT gates G1 and G2. It is supplied to the reset terminal of the mounted data input / output IC. Preferably, a basic reset signal (I / O reset signal) RS1 is supplied to a data input / output IC having a latch function. Therefore, the data of the data input / output ICs (for example, SN74273, SN74LV8155, etc.) latched at random when the power is turned on is surely cleared by the basic reset signal RS1.

  The basic reset signal RS1 bar via the NOT gate G1 is supplied to the power supply voltage monitoring IC 2 with a watchdog timer function.

  As shown in FIG. 5 (a), the power supply voltage monitoring IC 2 outputs a CPU reset signal RS2, but the delay capacitor C15 is connected to the Ct terminal of the power supply voltage monitoring IC 2, and the one-chip is connected to the CK terminal. A clear pulse is supplied from the microcomputer. As shown in the equivalent circuit of FIG. 5C, the clear pulse supplied to the CK terminal from the CPU of the main control unit or the payout control unit passes through the built-in pulse generation circuit to the built-in watchdog timer. Supplied.

  Then, the discharge operation of the delay capacitor C15 connected to the Ct terminal is switched to the charge operation in synchronization with the falling edge of the clear pulse. Thus, since the power supply voltage monitoring IC 2 has a built-in pulse generation circuit, it is not necessary to set the duty ratio of the clear pulse as low as in the conventional circuit, and the duty ratio is about 50% or more. The clear pulse can be used, and the generation of high frequency noise can be effectively suppressed.

  In addition, the Vs terminal of the power supply voltage monitoring IC 2 of this embodiment is connected to the ground via the capacitor C14, and the collector terminal and the emitter terminal of the transistor Q3 are connected in parallel to the capacitor C14. The base reset signal RS1 bar divided by the bias resistors R23 and R24 is supplied to the base terminal of the transistor Q3.

  The contentor C14 is a delay element that delays the operation of the internal circuit. As in the case of the power supply voltage monitoring IC1, by appropriately setting the capacitance of the capacitor C14, the power supply voltage monitoring IC2 may be configured not to react in an instantaneous interruption or low state of the power supply voltage Vcc. it can.

  In the power supply voltage monitoring IC 2, as shown in FIG. 5C, when the Vs terminal is in an open state, the potential of the Vs terminal is set to about 1.4V by a built-in resistor. The Vs terminal is connected to the minus terminal of the built-in comparator CompS, and a voltage of about 1.24 V is supplied to the plus terminal of the comparator CompS by the built-in circuit.

  Hereinafter, the operation of the power supply voltage monitoring IC 2 will be described. Since the basic reset signal RS1 bar is at the H level during the period from the power-on to the timing T3 (see FIG. 6F), the transistor Q3 is turned on. State. Therefore, the potential of the Vs terminal of the power supply voltage monitoring IC 2 is 0 V, and the output of the comparator CompS becomes H level.

  However, when the basic reset signal RS1 bar transits to L level and the transistor Q3 enters the OFF state at timing T3, the output of the comparator CompS transits to L level, so that the built-in flip-flop enters the reset state and delays. The charging operation to the capacitor C15 is started. Then, after the delay capacitor C15 is charged to a predetermined level (see timing T4 in FIG. 6G), the CPU reset signal RS2 changes from the L level to the H level.

  While the CPU reset signal RS2 is at the L level, the reset terminal of the one-chip microcomputer is maintained at the L level, so that the CPU core and others are surely reset. The reset hold time Tpr [mS] is Tpr [mS] = 1000 * C15 [μF] corresponding to the capacitance of the external capacitor C15.

  In this power supply voltage monitoring IC 2, the watchdog timer circuit built in the power supply voltage monitoring IC 2 starts to operate at the timing when the CPU reset signal RS 2 transitions to the H level and the one-chip microcomputer starts operating. It is configured.

  Therefore, after that, the watchdog timer function is exhibited. Specifically, when the operation of the one-chip microcomputer is started, the power supply voltage monitoring IC 2 starts the discharging operation of the delay capacitor C15, and every time the one-chip microcomputer supplies a clear pulse, the falling edge is detected. In synchronization, the discharging operation of the delay capacitor C15 is switched to the charging operation.

  However, when trouble such as program runaway occurs (see timing T5 in FIG. 6G), the discharging operation of the delay capacitor C15 is continued, and the potential at the Ct terminal passes through a predetermined abnormal viewing time Twd. Decreases to about 0.4 V, the CPU reset signal RS2 is forcibly transitioned to the L level. The abnormal watching time Twd is Twd [mS] = 100 * C15 [μF] based on the value of the delay capacitor C15.

  Then, the CPU reset signal RS2 that has transitioned to the L level returns to the H level after the elapse of a predetermined maintenance time Twr. Thus, when the CPU reset signal RS2 returns to the H level, the CPU thereafter starts executing the initial processing program similar to the power-on state. The duration Twr [mS] is Twr [mS] = 20 * C15 [μF] corresponding to the capacity of the delay capacitor C15.

  Next, the operation of the power supply voltage monitoring IC 2 when the power is shut off will be described. When the power supply voltage Vcc drops to a predetermined level (4.2 V), the CPU reset signal RS2 changes to the L level (timing T8 in FIG. 6 (g)). Thereafter, the operation of the watchdog timer circuit is prohibited.

  By the way, in this embodiment, the watchdog timer circuit built in the one-chip microcomputer is not utilized, and an external dedicated IC 2 is used. This is because when the CPU runs out of control, it is impossible to deny the possibility that some kind of abnormality has occurred in the built-in circuit of the one-chip microcomputer.

  Further, in this embodiment, the power supply voltage monitoring IC 1 and the power supply voltage monitoring IC 2 are arranged in an overlapping manner, and the power supply reset signal (CPU reset signal) RS2 output from the power supply voltage monitoring IC 2 is used only for the one-chip microcomputer. The power supply reset signal (basic reset signal) RS1 output from the power supply voltage monitoring IC 1 is supplied only to the data input / output IC other than the one-chip microcomputer. The CPU reset signal RS2 generated by the watchdog timer function of the power supply voltage monitoring IC 2 is supplied only to the one-chip microcomputer. The reason for adopting such a configuration is as follows.

  First, since the ball game machine of the present embodiment has a power backup function, the game before the power interruption (before the previous day or before a power failure) may be resumed when the power is turned on. Therefore, when the power is turned on, in particular, it is necessary to reliably reset the data input / output IC having a latch function. However, since the reset hold time is short enough, the power supply reset signal (basic reset signal) RS1 is generated using the power supply voltage monitoring IC1.

  On the other hand, for the one-chip microcomputer, a sufficient reset hold time is required after the power supply voltages Vcc and VB are stabilized. For the reason described above, it is preferable to provide a watchdog timer circuit externally, and a desired reset hold time is required for the CPU reset signal RS2 by the watchdog timer. Therefore, in this embodiment, the power supply voltage monitoring IC 1 and the power supply voltage monitoring IC 2 are connected in series to generate a power reset signal (CPU reset signal) RS2 having an optimal reset hold time (= Tpo + Tpr). At the same time, the CPU reset signal RS2 when an abnormality occurs is generated using the power supply voltage monitoring IC2. The reset hold time is set to an optimum value in the main control unit 20 and the payout control unit 24 in consideration of the initial processing time after the CPU reset. Therefore, for example, the control command is not transmitted during the initial processing operation of the payout control unit 24. However, if the main control unit 20 is clearly longer than the payout control unit in the initial processing time, it is sufficient that the reset hold time is set to be the same.

  When an abnormality occurs due to program runaway or the like, the basic reset signal RS1 is not generated, so the data input / output IC is not reset. However, unlike when the power is turned on, random data is not latched in the data input / output IC at the time of abnormal reset, and at the time of abnormal reset, the RAM clear process is executed and the game operation is resumed. There is no problem in not resetting the data input / output IC.

  On the other hand, if the power supply voltage (VB, Vccc) continues for a short time but cannot be absorbed by the capacitors Cll, C12, a basic reset with a short pulse width is started from the power supply voltage monitoring 1Cl. Signal RSl is output. The basic reset signal RS1 turns on the transistor Q3 for a short time. However, by setting the ON resistance of the transistor Q3 to an appropriate value and setting the capacitor C14 connected in parallel to the transistor Q3 to an appropriate capacitance, it is possible to avoid the output of the CPU reset signal RS2.

  In such a case, only the data input / output IC is reset. In particular, this reset operation is performed when the power supply voltage VB (12 V) used for generating a switch signal such as a symbol start port is This is effective in that only the data input / output IC is cleared when it falls into a momentary low state.

  Next, an outline of a program of the main control unit 21 that controls the game operation in an integrated manner will be described. 7 to 8 are flowcharts showing a control program of the main control unit 21. The control program of the main control unit 21 includes a system reset process (FIG. 7) that is activated based on the restoration or input of the power supply voltage, and a maskable timer interrupt process (FIG. 8 (FIG. 8) that is activated every predetermined time (2 mS). a)). The operation content of the payout control unit 24 is also common in the basic configuration of the system reset process and the timer interrupt process.

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process is started when the initialization switch SW is turned off and the power is turned on, such as when recovering from a power failure, and when the game hall is opened, the initialization switch SW is turned on. There is a case where the power source is turned on by being operated. Note that when the control program runs away, the watchdog timer function of the power supply voltage monitoring IC 2 is exhibited and the CPU may be forcibly reset.

  In any case, the Z80 CPU first sets itself to the interrupt disabled state (ST1) and sets to the interrupt mode 2 (ST2). Further, the value of the stack pointer SP in the CPU is initialized to the final address of the stack area (ST3), and the values of internal registers including each part of the one-chip microcomputer are initialized (ST4).

  Subsequently, standby processing is executed until the initial setting operation in the downstream control board, in particular, the image control unit 23 is completed (ST5). The standby time is appropriately determined based on the program configuration and circuit configuration of the one-chip microcomputer or VDP mounted on the image control unit 23. In this embodiment, for example, a time of about 2 seconds is secured.

  FIG. 9 shows a specific configuration of the standby process (ST5), in which 4000H is initialized in the BC register of the Z80 CPU (ST50). H is a subscript indicating a hexadecimal number, and the number of repetitions (= 64) of steps ST51 to ST59 is initialized in the B register, and the C register is cleared to zero.

  Next, a counter value corresponding to a predetermined delay time τ is initialized in the DE register (ST51), and the decrement process is repeated until the DE register becomes zero (ST52 to ST53). Therefore, after the process of step ST51 is executed, the delay time τ is consumed until the DE register becomes zero.

  Next, 01H is stored in the accumulator ACC, and the XOR operation of the C register is executed. The ACC value after the XOR operation is stored in the C register (ST56), and the ACC value is output from a predetermined output port (ST57). In this embodiment, the least significant bit of this output port is connected to the CK terminal of the power supply voltage monitoring IC 2, and the clear pulse is output to the watchdog timer via the least significant bit of the output port. become. As described above, the discharging operation of the delay capacitor C15 is switched to the charging operation in synchronization with the falling edge of the clear pulse.

  As is clear from the above description, the reason why 01H is stored in ACC in the process of step ST54 is that the clear pulse supplied to the watchdog timer is generated by the least significant bit of ACC. In addition, the C register is set to zero in the initial state (ST50), the XOR operation is performed with the ACC, and the value after the operation is stored in the C register. This is for switching alternately from 0 → 1 → 0 →.

  In this way, when the output process of step ST57 is completed, the value of the B register is decremented, and the processes of steps ST51 to ST59 are repeated until it becomes zero. Therefore, according to the standby process shown in FIG. 9, a clear pulse having a duty ratio of 50% is continuously output repeatedly for a predetermined standby time (≈64 * τ). Here, the pulse period of the clear pulse (≈2 * τ) is set sufficiently smaller than the watchdog timer abnormality watching time Twd (Twd [mS] = 100 * C15 [μF]) (2 * τ << Twd), no matter how long the waiting time for the initial setting process of the downstream side control unit is, the CPU is not forcibly reset.

  Therefore, according to the present embodiment, it is possible to secure a sufficient time for the initial setting operation of the downstream side control unit without setting the abnormal watching time Twd to be dark. Although the abnormal watching time Twd can be set to be longer than the standby time (≈64 * τ), if such a configuration is adopted, it is not possible to quickly respond to the abnormal situation after the start of the game operation.

  The standby process (ST5) has been described with reference to FIG. 9, and the subsequent process will be described with reference to FIG. When the standby process in step ST5 is completed, the power supply abnormality signal ABN1 is acquired from the input port, and the same process is repeated until it changes to a normal level (ST6 to ST7). However, since sufficient time is secured in the standby process, the processes of steps ST6 to ST7 are not repeated in practice.

  Although the power supply voltage Vcc may not drop completely even after the processing of ST41 in FIG. 8B is completed when the power is shut off, in this embodiment, standby processing (ST5) and power monitoring processing (ST6 to ST6) are performed. Since ST7) is provided, no trouble occurs. That is, even if the watchdog timer function is exhibited and the CPU is reset at the timing when the power supply monitoring process in FIG. 8B is finished and the infinite loop process is repeated, after that, in step ST5 The standby state is entered, and at worst, the standby state is entered at step ST7.

  If such processing (ST5 to ST7) is not provided, the RAM data (basic data of checksum calculation and the backup flag BFL updated in ST33) is rewritten by the steady processing that has progressed after step ST8. The data will be saved even after the power is turned off. In such a case, in the next day determination, the backup flag BFL = 0, or the checksum value backed up on the previous day (ST38) does not match the checksum value calculated after powering on the next day. Precious backup processing (ST37 to ST38) is wasted.

  Further, the processing of steps ST5 to ST7 works effectively even in a momentary power interruption state in which the supply of the AC input voltage is stopped for a moment by cooperating with the watchdog timer function of the power supply voltage monitoring IC 2. That is, as described with reference to FIG. 5, the power supply abnormality signals ABN1 and ABN2 are supplied to the main control unit 21 and the payout control unit 24 even in the instantaneous power failure state. May be started. Depending on the pulse widths of the power supply abnormality signals ABN1 and ABN2, there is a possibility that the processing of steps ST36 to ST40 is finished and the processing proceeds to an infinite loop processing. However, even in such a case, after that, the CPU is reset by the watchdog timer function, and then the game operation up to that point can be resumed by passing through the processing of steps ST5 to ST7.

  Even in such a case, if it is confirmed in step ST7 that the power supply abnormality signal ABN1 is at a normal level, the RAM clear signal CLR is subsequently acquired from the input port (ST8). As described above, the RAM clear signal CLR is a signal for determining whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer, and the ON / OFF state of the initialization switch SW operated by the attendant It has a value corresponding to.

  Next, the level of the RAM clear signal is determined (ST9). If it is assumed that the RAM clear signal is in the ON state, the entire area of the built-in RAM is cleared to zero (ST13). Therefore, the value of the backup flag BFL set in the process of step ST37 in FIG. 8B becomes zero together with other checksum values.

  Next, a power-on command for notifying that the RAM area has been cleared to zero is output (ST14), and the CTC that outputs the interrupt signal INT for starting the timer interrupt operation (FIG. 8A) is initialized ( ST15). Then, with the CPU set to the interrupt disabled state (ST16), update processing is executed for various counters (ST17), and then the CPU is returned to the interrupt enabled state and returns to step ST16. The counter updated in step ST17 includes an out symbol counter. This out symbol counter is out of the result of the big hit lottery process in the special symbol processing (ST27) of FIG. 8A. It is a counter for deciding what kind of out-of-game to produce when it becomes a state.

  Returning to the determination process in step ST9, the RAM clear signal is OFF when the CPU is forcibly reset by the watchdog timer or when recovering from the power failure state. In such a case, following the determination in step ST9, the content of the backup flag BFL is determined (ST10). The backup flag BFL is data indicating that the operation of the power supply monitoring process of FIG. 8B has been executed. In this embodiment, the backup flag BFL is set to 5AH in the process of step ST37 when the power is turned off. It is cleared to zero in the process of step ST33 after the power is restored.

  When the power is turned on or when recovering from a power failure, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, if BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST10 to step ST13 to return the operation of the gaming machine to the initial state.

  On the other hand, if the backup flag BFL = 5AH, a checksum calculation for calculating a checksum value is executed (ST11). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST12).

  In the SUM address, the checksum value by the same checksum calculation is stored in the power supply monitoring process (FIG. 8B) executed when the voltage drops (ST38). The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST12.

  However, if the checksum calculation (ST38) cannot be executed when the power is turned off, or if it can be executed, the data in the work area will be damaged after that until the checksum calculation (ST11) of the main process is executed. In such a case, the determination result in step ST12 is inconsistent. If data corruption is detected due to a discrepancy between the determination results, the process proceeds to step ST13 to execute a RAM clear process, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST10 that the checksum value obtained by the checksum calculation (ST11) matches the stored value at the SUM address, the process proceeds to step ST15.

  Next, a timer interrupt processing program (FIG. 8A) that is started every 2 mS while interrupting the main processing described above will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST15.

  In the power supply monitoring process (ST20), the level of the power supply abnormality signal supplied from the power supply board 20 is determined. The specific processing content will be described later. When the power supply monitoring process (ST20) is completed, the winning counter RG used in the lottery operation in the normal symbol process (ST26) and the random number RND for jackpot determination used in the lottery operation in the special symbol process (ST27) Is updated (ST21).

  When the updating process (ST21) of the two counters RG and RND is completed, a timer subtraction process is performed for the timer managing the time of each gaming operation (ST22). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times.

  Subsequently, a clear pulse is output to the CK terminal of the power supply voltage monitoring IC 2, and ON / OFF signals of various switches including a winning detection switch of the symbol start opening 15 and the big winning opening 16 are input, and the work area is turned ON. The / OFF signal level and its rising state are stored (ST23). The duty ratio of the clear pulse is 50% as in step ST5, but the pulse period is twice the timer interrupt period (= 4 mS).

  Next, error management processing is performed (ST24). The error management process includes a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged.

  Next, after performing the management process based on the detection signal from the symbol start opening, the big prize winning opening, etc. (ST25), the normal symbol processing is performed (ST26). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined in the switch input process in step ST23 that the game ball has passed through the gate, the winning counter RG updated in the random number update process (ST21) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. In addition, if it is a hit, processing for the operation of a normal electric accessory such as an electric tulip is performed.

  Subsequently, special symbol processing is performed (ST27). The special symbol process is a determination as to whether or not a special electric accessory such as the big prize opening 16 is to be operated. When it is determined in the switch input process of step ST23 that a game ball has won a symbol start port. Then, the big hit lottery process is executed using the random number value RND updated in the random number update process (ST21) (ST66). Although not shown in the drawing, if the lottery result is a winning state, the operation mode is changed to a big hit operation mode. In addition, if it is a big hit, processing for the operation of special electric accessories such as a big prize opening is performed.

  After such special symbol processing (ST27), the lighting operation of the LEDs managed by the main control unit 21 is advanced (ST28), and the solenoid drive processing for realizing the opening / closing operation of the electric tulip, the big prize opening, etc. is executed. Later (ST29), the CPU is returned to the interrupt permission state EI and the timer interrupt is finished (ST30). As a result, the process returns from the interrupt process routine to the infinite loop process (FIG. 7) of the main process, and the process of step ST17 is executed.

  Next, the power supply monitoring process (ST20) shown in FIG. 8B will be described. In the power supply monitoring process (ST20), first, a power supply abnormality signal ABN1 supplied from the power supply board 20 is acquired through an input port (not shown) (ST31), and it is determined whether or not it is an abnormal level (ST32). If it is not an abnormal level, the abnormal number counter and the backup flag BFL are cleared to zero and the process is terminated (ST33).

  On the other hand, if the power supply abnormality signal ABN1 is at the abnormal level, the abnormality number counter is incremented (+1) (ST34), and it is determined whether the counting result exceeds the upper limit value MAX (ST35). This is because the data acquired from the input port may be garbled due to the influence of noise or the like, and the abnormal level is continuously set for a predetermined number of times (for example, upper limit MAX = 2). In the case of maintaining, it is determined that the AC power source is actually shut off.

  As described above, in this embodiment, the subsequent backup processing is not started immediately even when the power is turned off, and the operation start timing is delayed by MAX × 2 mS. However, (1) The power supply drop signal is not a drop in the DC power supply voltage, but a drop in the AC DC voltage is detected. (2) The DC power supply voltage is maintained for a while after the AC power supply is shut off by a large-capacitance capacitor. (3) The power supply monitoring process is repeated at a high speed (every 2 ms), and (4) the backup process is extremely simple and finishes quickly, so there is virtually no adverse effect.

  By the way, as a result of the determination in step ST35, if the count value of the abnormal number counter coincides with the upper limit value MAX, the abnormal number counter is cleared to zero (ST36), and then 5AH is set to the backup flag BFL (ST37). Next, the same calculation as in step ST7 of the main routine is executed for the same work area (work area), and the calculation result is stored (ST38). The operation to be executed is typically an 8-bit addition operation.

  Thereafter, the one-chip microcomputer is set to a RAM access prohibited state (ST39), and output data of all output ports is cleared (ST40). When the above backup process is completed, the generation of the interrupt signal INT is prohibited by the setting process for the CTC, and the DC power supply voltage is lowered while repeating the infinite loop process (ST41). At this timing, the CPU is originally in an interrupt disabled state (see ST30). However, in this embodiment, an interrupt signal from the CTC is used to eliminate as much as possible the possibility of malfunction due to a drop in power supply voltage. INT output is also prohibited.

  By the way, as described above, the process of step ST20 is quickly started within 2 mS after the AC power supply is shut off (see timing T7 in FIG. 6) and is quickly ended. On the other hand, the drop in power supply voltage Vcc to a predetermined level is considerably delayed due to the influence of a smoothing capacitor arranged in a power supply circuit or the like (see timing T8 in FIG. 6).

  As long as the power supply voltage Vcc does not drop to a predetermined level, the watchdog timer of the power supply voltage monitoring IC 2 continues to function. Therefore, there is a possibility that the CPU is abnormally reset by the watchdog timer during the infinite loop process after the process of step ST20 is started and all processes are completed. However, as described above, in this embodiment, the standby process of steps ST5 to ST6 is provided, so that the backup process is not wasted. Note that the entire processing time of the power supply monitoring process from ST31 → ST32 → ST34 → ST35 → ST36 →... ST41 is set shorter than the output period (2 mS) of the clear pulse, The dog timer will not start.

  Although the embodiments of the present invention have been specifically described above, the specific description content is not intended to limit the present invention, and various modifications can be made. For example, in the embodiment, the main control unit 21 and the payout control unit 24 have a backup function, but it is needless to say that the main control unit 21 and the payout control unit 24 may be limited to only the main control unit 21.

  When the main control unit 21 and the payout control unit 24 are provided with a reset circuit RST and a watchdog timer, the payout control unit 24 does not need to be provided with a standby process (ST5). However, the check process (ST6 to ST7) of the power supply abnormality signal ABN is preferably provided also in the payout control unit 24. In the present invention, the configuration in which only the main control unit 21 is provided with the reset circuit RST and the watchdog timer is not prohibited at all.

  In the embodiment, the backup power supply is generated by the power supply board and supplied to the main control board 21 and the payout control board 24. However, the backup power supply is supplied to the main control board 21 and / or the payout control board 24. Of course, it may be provided.

GM gaming machine 21 main control unit 23 sub control unit 20 power supply unit ST5 standby processing

Claims (10)

A gaming machine that executes a lottery process due to a detection signal indicating the occurrence of a predetermined gaming action and determines whether or not to generate a gaming state advantageous to the player,
A main control unit that centrally controls gaming operations, a sub-control unit that executes control operations based on control commands output from the main control unit, and a DC voltage generated from an AC voltage to each control unit A power supply unit to supply,
The main control unit is provided with a backup function that retains the stored contents of the RAM even after power-off, and a watchdog timer circuit that forcibly resets the CPU unless it receives a clear pulse periodically.
The CPU of the main control unit operates by executing a control program having a system reset process activated based on the supply of the DC voltage and a timer interrupt process activated at regular intervals,
By repeatedly outputting the clear pulse to the watchdog timer circuit until the initial process executed in the system reset process and executed by the sub-control unit based on the start of supply of the DC voltage is completed. A gaming machine characterized by providing a standby process that does not shift to subsequent processes.   The gaming machine according to claim 1, wherein the standby process is executed in a state where interruption of the timer interrupt process is prohibited.   The gaming machine according to claim 1, wherein the clear pulse output in the standby process has a duty ratio of 40 to 60%.   The gaming machine according to claim 1, wherein the main control unit is provided with a reset circuit that detects an abnormal level of the DC voltage supplied from the power supply unit and resets the CPU.   The gaming machine according to claim 4, wherein the reset circuit includes the watchdog timer circuit. The power supply unit is configured to detect that the AC voltage is cut off and output a power supply abnormality signal of an abnormal level,
The main control unit is provided with a determination process after the standby process that determines the level of the power supply abnormality signal and repeatedly determines the level of the power supply abnormality signal without proceeding to subsequent processing unless the level is normal. The gaming machine according to any one of claims 1 to 5. In the main control unit,
If the power supply abnormality signal is an abnormal level, the power supply abnormality signal is acquired a plurality of times in the execution cycle of the timer interrupt process, and predetermined management data is stored in the RAM on condition that this is an abnormal level continuously. The gaming machine according to claim 6, wherein a power supply monitoring process is provided for waiting for the DC voltage to become an abnormal level after being stored. After passing through the waiting process, whether or not the management data is appropriate is determined,
The gaming machine according to claim 7, wherein the stored contents of the RAM held by the backup power source are used on condition that this is a predetermined value. In the timer interrupt processing, a clear pulse is supplied to the watchdog timer circuit,
The power supply monitoring process is configured to repeat the infinite loop process after setting all the processes and setting the CPU to the timer interrupt disabled state,
The gaming machine according to claim 7 or 8, wherein a maximum time from the start of operation of the power supply monitoring process to the start of the infinite loop process is set shorter than the timer interrupt cycle.   The gaming machine according to claim 1, wherein the standby time of the standby process is set longer than an operation time of an initial setting process executed by an image control unit that controls the display device.