JP5005776B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a ball game machine or a slot machine that generates a big hit state by a lottery process resulting from a gaming operation, and more particularly to a gaming machine that can effectively eliminate illegal games.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  However, in actuality, whether or not the big hit state is determined in advance by the big hit lottery process executed based on the winning of the game ball, and the symbol display section performs the symbol variation operation exclusively to revitalize the player. Is going. In the jackpot lottery process, for example, the output value of a hardware-configured random number generation circuit is used as a random number value RND for jackpot determination, and it is determined whether or not it is a jackpot state by comparing this with a jackpot winning value Hit. The

  Here, since the counters and latches constituting the random number generation circuit are forcibly reset when the power is turned on, there is a concern about illegal games exploiting this point. That is, since the frequency of the count clock Φ supplied to the counter and the value of the big hit winning value Hit are made clear by obtaining and investigating the gaming machine, the gaming machine is brought into a power reset state by some method, and the counter If an illegal winning switch signal is input from the connector unit aiming at the timing when the counted value coincides with the value of the jackpot winning value Hit, the jackpot state can be intentionally generated.

  The same applies to the slot machine that acquires the random value RND for jackpot determination at the start lever operation timing, and the illegal start lever from the connector section is aimed at the timing that matches the value of the jackpot winning value Hit. There are concerns about illegal provision of signals.

  Therefore, the applicant has proposed a configuration of a gaming machine in which the power reset timing is changed for each gaming machine even when the power is reset. Specifically, the power reset operation is randomized by utilizing variations in the characteristics of the passive elements and active elements that generate the power reset signal.

JP 2008-295492 A

  However, even in the case of adopting the above configuration, the characteristics of individual gaming machines, that is, the characteristics of the power reset operation, will be clarified by repeated illegal actions several times. I can't say that.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine that can reliably eliminate an illegal act of misusing a power reset operation.

  In order to achieve the above object, the present invention executes a lottery process based on a detection signal indicating the occurrence of a predetermined gaming operation, and determines whether or not to generate a gaming state advantageous to the player The lottery process is executed by acquiring a counter value of a counter capable of prohibiting the counting operation and comparing the acquired value with the winning value, and the counting operation of the counter is prohibited after the power is turned on. The time is configured to be set based on random information stored in a memory circuit operable even after the power is shut off.

  Preferably, the counter is configured to execute a counting operation in synchronization with a counting clock unless the operation prohibiting signal is at a prohibiting level, and receives a holding command, a latch circuit that stores the counter value of the counter, and a read command And an output circuit for outputting the counter value stored in the latch circuit is provided on the rear stage side of the counter.

  The time during which the counting operation of the counter is prohibited is preferably defined by the capacitor charging time in the charging circuit composed of the capacitor and the resistor.

  Further, the present invention provides a starting circuit that defines a time during which the counting operation of the counter is prohibited, and the starting circuit includes N capacitors arranged corresponding to N-bit random information, and N capacitors It is preferable to have N switch circuits connected in series to each of the capacitors and a power supply unit that supplies a DC voltage to the N switch circuits.

  Also, the storage circuit is preferably configured to acquire and store the count clock and / or the carry signal of the counter based on the fact that the AC power supply is cut off, or It is preferable that a part of the counter value is acquired and stored based on the acquisition of the counter value of the counter.

  Here, it is preferable for crime prevention that the counter is reset without receiving a reset signal from another circuit board when the power is turned on.

  Typically, the holding command is output based on a game medium having won a predetermined winning opening, or is output based on a player's gaming operation. In any case, it is preferable that the hold command is waveform-shaped so as to be synchronized with one edge of the counting clock, and the counter is preferably updated in synchronization with the other edge of the counting clock.

  According to the present invention described above, illegal acts that abuse the power reset operation can be reliably eliminated.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit diagram which shows the circuit structure of a power supply board. It is a circuit diagram of the reset circuit of a main control part and a payout control part. It is a timing chart which shows operation | movement of a power supply monitoring part and a reset circuit. It is a circuit diagram which shows the circuit example of a random number generation circuit. It is a timing chart explaining operation | movement of a counter circuit. It is a circuit diagram which shows the internal circuit of counter IC. It is a flowchart explaining the system reset process of a main control part. It is a flowchart explaining the timer interruption process of a main control part. It is a circuit diagram which shows the modification circuit example of a random number generation circuit. FIG. 8 is a circuit diagram illustrating a circuit example in which the random number generation circuit of FIG. 7 is improved. 14 is a timing chart for explaining the circuit operation of FIG. 13.

  Examples of the present invention will be described in detail below. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display is provided at the approximate center of the game area 5a inside. A display device DISP is arranged. In addition, at a suitable place in the game area 5a, a symbol start opening 15, a big winning opening 16, a plurality of normal winning openings 17 (four on the right and left of the large winning opening 16), and a gate 18 serving as a passing opening are arranged. Yes. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The display device DISP variably displays a specific symbol related to the big hit state and also displays a background image, various characters, and the like in an animated manner. This display device DISP has a special symbol display part Da to Dc in the center and a normal symbol display part 19 in the upper right part. And, in the special symbol display parts Da to Dc, a reach effect that expects the invitation of a big hit state is executed, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success or failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, the symbol start port 15 is opened and closed. The claw 15a is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM mainly receives a 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DISP, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is the main board relay board. It is transmitted to the payout control board 24 via 28.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Thus, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the image control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display device DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the power supply abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V received from the power supply board 20 to the main control unit 21 as they are. On the other hand, the power relay board 30 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the image control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been turned on to the power supply board 20, and the one-chip microcomputer of the effect control unit 22 and the image control unit 23 by this power supply reset signal. The power is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The effect control unit 22 and the image control unit 23 execute the effect operation in a dependent manner based on the control command from the main control unit 21, so that the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS output from is used.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  The power supply abnormality signals ABN1 and ABN2 received from the power supply board 20 by the main control unit 21 and the payout control unit 24 are signals indicating that the AC input power supply AC24V starts to drop, and receive the power supply abnormality signals ABN1 and ABN2. Thus, the control units 21 and 24 start necessary termination processing prior to a power failure or business termination. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 25 via the main board relay board 28, while the payout control unit 25 indicates a game ball payout operation. A prize ball counting signal and a status signal CON related to an abnormality in the payout operation are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with a power supply voltage VB (12 V) supplied from the main control unit 21. Each switch signal indicating a winning state to the symbol starting port 15 is converted to a TTL level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). Then, the data is transmitted to the main control unit 21.

  FIG. 4 is a circuit diagram showing a power supply circuit of the power supply board 20. This power supply circuit includes a second power supply unit SD that generates a DC voltage supplied to the production interface board 27, and a first power supply unit FR that generates a DC voltage supplied to the main control unit 21 and the payout control unit 24. A power monitoring unit MNT that monitors power-on and power-off, and a power-cut-off unit CUT that cuts off the ground line when an excessive AC voltage is received. Note that illustration of other DC voltages (DC 32 V) supplied to the payout control unit 24 and other DC voltages (DC 32 V, DC 15 V) supplied to the production interface board 27 is omitted.

<Second power supply unit SD>
The second power supply unit SD includes a full-wave rectifier circuit including diodes D1 to D4, a smoothing capacitor C1, a DC-DC converter that generates a DC voltage VB (12V), and a DC-DC that generates a DC voltage Vcc (5V). The converter includes smoothing capacitors C2 and C3. Each of the two DC-DC converters is a chopper type, and operates in common with the smoothing capacitor C1. The direct-current voltage generated by the second power supply unit SD is transmitted to the effect interface board 27 and then stepped down as appropriate to be used by the effect interface board 27, the effect control board 22, and the image control board 23. Is done.

<First power supply FR>
The first power supply unit FR generates a full-wave rectifier circuit using diodes D1, D2, D5, and D6, a smoothing capacitor C4, a DC-DC converter that generates a DC voltage VB (12V), and a DC voltage Vcc (5V). The power storage unit BK is configured by a DC-DC converter, smoothing capacitors C5 and C6, a diode D7, and a capacitor Cb. These two DC-DC converters are also of a chopper type and operate in common with the smoothing capacitor C4. The DC voltage generated by the power storage unit BK serves as a backup power supply BAK that holds data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24.

  The DC voltage VB and the DC voltage Vcc generated by the first power supply unit FR are supplied only to the main control unit 21 and the payout control unit 24, and the DC voltage transmitted to the effect interface board 27 is on the wiring. It is distinguished. Therefore, the main control unit 21 and the payout control unit 24 are not connected to the other sub-control units 22 and 23 via the power line, and transmission of high-frequency noise and the like is prevented.

  The total current in the main control unit 21 and the payout control unit 24 does not exceed 600 mA on the power supply voltage VB line and does not exceed 300 mA on the power supply voltage Vcc line. The voltage drop of the VB and Vcc power supply lines is not a problem at all.

<Power cutoff unit CUT>
The power cut-off unit CUT corresponds to the rectifying unit 51 that generates a DC voltage of a predetermined level from the AC voltage AC24V, the AC monitoring unit 52 that is turned on when the AC power supply lines LN1 and LN2 are overvoltage, and the AC monitoring unit 52 that is turned on. And a switch circuit 53 that performs an OFF operation.

  The rectifier 51 includes a diode D12 that receives an AC voltage from the AC power supply line LN2, a current limiting resistor R1, and a parallel circuit of a capacitor C8 and a Zener diode ZD2, which are connected in series. During normal operation, the voltage across the capacitor C8 is constant at the breakdown voltage of the Zener diode ZD2.

  The switch circuit 53 includes a MOS transistor Q2 having a large current capacity and a bias resistor R5 connected in parallel to the capacitor C8. Here, the transistor Q2 is in an ON state as long as the voltage across the capacitor C8 is at a predetermined level, and connects the ground line of all the circuits of the gaming machine and the frame ground FG.

  The AC monitoring unit 52 includes two diodes D8 and D9 connected to the AC power supply lines LN1 and LN2, a Zener diode ZD1 connected to the connection point of the diodes D8 and D9, a bias resistor R2 and R3, and a capacitor C7 in parallel. The circuit includes a transistor Q1 that is turned on when the voltage across the bias resistor R3 increases, and a current limiting resistor R4 of the transistor Q1.

  Zener diode ZD1 is normally in an OFF state, but when an excessive AC voltage (for example, AC 100V) is applied to AC power supply lines LN1 and LN2, it enters a breakdown state. In this breakdown state, the voltage at both ends of the bias resistor R3 increases and the transistor Q1 is turned on, so that the voltage at both ends of the capacitor C8 decreases.

  Then, the transistor Q2 that has been in the ON state until then is turned OFF, whereby the circuit ground and the frame ground FG are disconnected, and all the power supply voltages of all the gaming machines are cut off. The operation content of the power cut-off unit CUT is as described above. When the voltage across the AC power supply lines LN1 and LN2 exceeds the limit value, the power cut-off unit CUT functions to cut off all the power supply voltages of all the gaming machines at once.

<Power supply monitoring unit MNT>
Next, the power supply monitoring unit MNT will be described. The power supply monitoring unit MNT includes a power supply monitoring unit 54 that monitors the voltage levels of the AC power supply lines LN1 and LN2, a comparison voltage unit 55 that receives the power supply voltage Vcc and outputs a comparison reference voltage Vo, and a power supply monitoring unit 54. An abnormality detection unit 56 that detects a power supply abnormality by comparing output voltages of the unit 55 and a power supply reset unit 57 that generates a system reset signal SYS are configured.

[Power supply monitoring unit 54]
The power supply monitoring unit 54 includes two diodes D10 and D11 connected to the AC power supply lines LN1 and LN2, a series circuit of a resistor R6 and a Zener diode ZD3 connected to a connection point of the diodes D10 and D11, and a Zener diode ZD3. A series circuit of a diode D13 and a smoothing capacitor C9 connected in parallel, a series circuit of resistors R7 and R8 connected in parallel to the smoothing capacitor C9, and a comparator A3 that short-circuits the resistor R8 are configured.

  In this embodiment, the breakdown voltage of the Zener diode ZD3 is about 5.1V, and the Zener diode ZD3 receives the AC voltage AC24V through the current limiting resistor R6. For this reason, when the AC input power supply is in a power supply state, the voltage across the smoothing capacitor C9 is a constant value of about 4.5V. Since the resistance values of the two resistors R7 and R8 are set to R8 >> R7, the both-ends voltage Vs of the resistor R8 is about 4.5V corresponding to the normal level AC voltage AC24V. However, if the output of the comparator A3 is at L level, the voltage Vs across the resistor R8 is substantially 0V correspondingly. The resistor R7 functions as a current limiting resistor for the comparator A3 when the L level is output.

  The comparator A3 is composed of a QUAD comparator (NJM2901) together with other comparators A1 to A4. This QUAD comparator includes four comparators A1 to A4, but each of the comparators A1 to A4 is an open collector type (see FIG. 6 (i)).

  The output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminal of the comparator A3, and the comparison voltage V1 of about 2.8V is supplied to the plus terminal in the steady state. The comparison voltage V1 is generated by dividing the two types of power supply voltages Vcc and VB generated by the first power supply unit FR with resistors.

  As will be described later, when the power is turned on, the output voltage Vo of the comparison voltage unit 55 becomes a level corresponding to the power supply voltage Vcc whose level is rising (Vo = Vcc−Vf−Δ). Vf and Δ are voltage drops in the diodes D14 and D15 and the resistor R9.

  On the other hand, since the comparison voltage V1 is generated by dividing the power supply voltages Vcc and VB, immediately after the power is turned on, it is lower than the output voltage Vo of the comparison voltage unit 55. Therefore, in a transient state immediately after the power is turned on, the output of the comparator A3 becomes L level to short-circuit the resistor R8. As a result, the output voltage Vs of the power supply monitoring unit 54 becomes almost 0V.

  On the other hand, in a steady state in which the power supply voltages Vcc and VB have reached a predetermined level, the comparison voltage V1 is about 2.8V, while the output voltage Vo of the comparison voltage unit 55 is kept constant at about 2.5V. That is, the comparator A3 has a magnitude relationship of [input voltage to the plus input]> [input voltage to the minus terminal], but the output part of the comparator A3 is an open collector (see FIG. 6 (i)). As shown in FIG. 4, since the output terminal is not pulled up, the output section of the comparator A3 is opened and does not affect other circuits.

The operation of the power supply monitoring unit 54 described above is organized as follows.
(1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the resistor R8 is short-circuited by the output part of the comparator A3, so that the voltage Vs across the resistor R8 becomes approximately 0V.
(2) Thereafter, when the power supply voltage Vcc increases to near the normal level, the output part of the comparator A3 is opened, so that the voltage Vs across the resistor R8 is approximately 4.5 V corresponding to the voltage across the Zener diode ZD3. It becomes.
(3) When the AC voltage AC24V is cut off, the voltage Vs across the resistor R8 quickly drops to 0V. However, even if the AC voltage AC24V is cut off, the power supply voltages Vcc and VB maintain a predetermined level for a while, so that the output unit of the comparator A3 maintains the open state as it is.

[Comparison voltage unit 55]
The comparison voltage unit 55 includes diodes D14 and D15 that receive two power supply voltages Vcc and Vcc generated separately by the first power supply unit FR and the second power supply unit SD at respective anode terminals, and cathodes of the diodes D14 and D15. A current limiting resistor R9 connected to the terminal and the voltage generator GN are connected in series. In this embodiment, a shunt regulator (HA17431: RENESAS) is used as the voltage generator GN.

  This shunt regulator has an anode terminal A, a cathode terminal K, and a comparison terminal REF. In the state shown in the figure, in which the anode terminal A and the cathode terminal K are connected, the shunt regulator functions in the same manner as a Zener diode. A constant reference voltage Vo (2.5 V) is output between the anode and cathode terminals (see FIG. 6H). On the other hand, during the non-breakdown operation, the internal circuit is turned OFF, and the anode and cathode terminals are opened.

  Therefore, when the power is turned on, until the power supply voltage Vcc reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 (voltage generation unit GN) corresponds to the power supply voltage Vcc whose level is rising, Vo = Vcc−Vf. −Δ. On the other hand, when the power supply voltage Vcc reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 becomes a constant comparison reference voltage (2.5 V).

[Abnormality detection unit 56]
The abnormality detection unit 56 includes a comparator A1 that generates a power supply abnormality signal ABN1 to the main control unit 21, a comparator A2 that generates a power supply abnormality signal ABN2 to the payout control unit 24, and pull-up resistors R10 of the comparators A1 and A2. , R11 and a capacitor Cs connected between the input terminals of the comparators A1, A2. The output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminals of the comparators A1 and A2, and the voltage Vs across the resistor R8 is supplied to the plus terminal. The comparators A1 and A2 are built in the QUAD comparator (NJM2901) described above.

  Although not shown, power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 are supplied to input ports of the main control unit 21 and the payout control unit 24. An appropriate capacitor is connected between the input terminal of each input port and the ground, and each input port receives a power supply abnormality signal via an appropriate resistor to ensure noise resistance. . Further, the influence of spike noise is eliminated by appropriate software processing (ST34 to ST35 in FIG. 8).

  Since the power supply monitoring unit 54 operates as described above in (1) to (3), the abnormality detection unit 56 operates as follows in response to this.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the voltage Vs across the resistor R8 is almost 0V, while the output voltage Vo of the comparison voltage unit 55 corresponds to the power supply voltage Vcc whose level is rising. Vcc−Vf−Δ. Therefore, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 stably maintain the L level without changing the level. Timings T0 to T1 in FIG. 6C show a stable L level state when the power is turned on.

  (2) Thereafter, after the power supply voltage Vcc whose level is rising exceeds a predetermined level, the output voltage Vo of the comparison voltage unit 55 is maintained at 2.5V. Further, when the power supply voltage Vcc increases to near the normal level, the output part of the comparator A3 is opened, so that the voltage Vs across the resistor R8 becomes approximately 4.5V corresponding to the voltage across the Zener diode ZD3.

  Therefore, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 transition to the H level, and thereafter the H level indicating the normal state is constantly maintained. After timing T1 in FIG. 6C, normal level power supply abnormality signals ABN1, ABN2 are shown.

  (3) Thereafter, when the AC voltage AC24V is cut off for some reason, the voltage Vs across the resistor R8 quickly drops to 0V. However, since the power supply voltages Vcc and VB are maintained at a predetermined level for a while, the comparator A3 and the comparison voltage unit 55 maintain the operation so far.

  Therefore, when the AC voltage AC24V is cut off at the timing T7 in FIG. 6A, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 immediately transition from the H level to the L level to cause an abnormal situation. Indicates occurrence. The main control unit 21 and the payout control unit 24 regularly check the power supply abnormality signals ABN1 and ABN2, and immediately confirm that the power supply abnormality signals ABN1 and ABN2 have transitioned to the L level. It is supposed to start.

[Power reset unit 57]
Next, the power reset unit 57 composed of the comparator A4 will be described. As illustrated, a pull-up resistor R12 is connected to the output terminal of the comparator A4, and a series circuit of a resistor Rf and a capacitor Cf is connected between the output terminal and the plus terminal. Further, the output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminal of the comparator A4, and the comparison voltage V2 of about 2.95V is supplied to the plus terminal in the steady state. The comparison voltage V2 is generated by dividing the two types of power supply voltages Vcc and VB generated by the second power supply unit SD with resistors.

  Since the power reset unit 57 is configured as described above, it operates as follows.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the output voltage Vo of the comparison voltage unit 55 becomes Vcc−Vf−Δ corresponding to the power supply voltage Vcc whose level is rising. On the other hand, since the comparison voltage V2 is generated by dividing the power supply voltages Vcc and VB of the second power supply unit SD, it is lower than the output voltage Vo during the level increase. Therefore, in such a transient state, the system reset signal SYS output from the comparator A4 becomes L level (see FIG. 6A).

  (2) Thereafter, after the power supply voltage Vcc whose level is rising reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 is maintained at 2.5V. Further, when the power supply voltages Vcc and VB increase to near the normal level, the comparison voltage V2 approaches the steady value 2.95V. Therefore, the system reset signal SYS output from the comparator A4 transitions from the L level to the H level at an appropriate timing.

  The system reset signal SYS generated in this way is transmitted to the effect control unit 22 and the image control unit 23 via the effect interface board 27, and is provided in each control unit 22 and control unit 23. The power of the CPU and other ICs is reset via the delay circuit. Note that the series circuit of the resistor Rf and the capacitor Cf also exhibits a function of delaying the transition operation.

  FIG. 5A is a circuit diagram showing the reset circuit RST arranged in the main control unit 21 and the payout control unit 24. In this embodiment, the reset circuit RST is configured by utilizing the power supply voltage monitoring IC 1 (MB3771 Fujitsu Microelectronics) and the power supply voltage monitoring IC2 with a watchdog timer function (MB3773 Fujitsu Microelectronics).

  As shown in the equivalent circuit of FIG. 5B, the power supply voltage monitoring IC 1 includes two comparators CompA and CompB. The plus terminals of the two comparators CompA and CompB are set to about 1.24V by the built-in circuit.

  In the circuit configuration of the embodiment, since the Vsa terminal is connected to the ground via the capacitor C11, the potential of the negative terminal of the comparator CompA is divided by the built-in resistor and becomes about 1.4V. . On the other hand, since the power supply voltage VB is divided and supplied to the Vsb terminal by external voltage dividing resistors R20 and R21, the potential of the Vsb terminal is VB * R21 / (R20 + R21). A voltage stabilizing capacitor C12 is connected in parallel to the resistor R21. A delay capacitor C10 is connected to the Ct terminal.

Since the power supply voltage monitoring IC 1 has the internal circuit of FIG. 5B, when the power supply voltage Vcc rises to a predetermined level after the power is turned on (see timing T2 in FIG. 6D), it is built in. Charging of the delay capacitor C10 is started by the constant current source. Until the delay capacitor C10 is charged to a predetermined level (see T3 in FIG. 6E), the basic reset signal RS1 output from the reset terminal is maintained at the L level. The reset hold time Tpo [S] is Tpo [S] = 10 ⁵ * C10 [F] corresponding to the capacitance of the external capacitor C10.

  In this way, the basic reset signal RS1 that has become H level at the timing T3 maintains that level unless the power supply voltages Vcc and VB drop. However, the potential of the Vsb terminal is VB * R21 / (R20 + R21), and the level of the power supply voltage VB is monitored at this Vsb terminal. Similarly, the potential of the Vsa terminal is Vcc * 40 / (40 + 1001) corresponding to the built-in resistors 40 kΩ and 100 kΩ, and the level of the power supply voltage Vcc is monitored at this Vsa terminal.

  For this reason, when the voltage level of both or one of the power supply voltages Vcc and VB drops due to interruption of the AC input AC 24V or failure of the power supply units FR and SD (see timing T8 in FIG. 6D), the built-in comparators CompA, Any output terminal of CompB transitions to the H level. Then, the built-in flip-flop is set, and the basic reset signal RS1 output from the reset terminal immediately falls to the L level (see timing T8 in FIG. 6E).

  By the way, in this embodiment, a capacitor C11 is connected between the Vsa terminal and the ground, and a capacitor C12 is connected between the Vsb terminal and the ground. As is apparent from the equivalent circuit of FIG. 5B, these capacitors C11 and C12 have a function of delaying the operation of the internal circuit, and the power supply voltages Vcc and VB are reduced to, for example, 4 V or less for a short time. The basic reset signal RS1 is not output in the recovering instantaneous low state or instantaneous interruption state.

  In the present embodiment, Cll = C12 = 1000 pF is set, and in response to this, in the instantaneous interruption state or instantaneous low state where the level drop of the DC voltage (5V, 12V) recovers within 40 μS, The voltage monitoring IC 1 is configured not to react. Therefore, even if spike noise within a pulse width of 40 μS is superimposed on any of the power supply lines of the power supply voltages Vcc and VB supplied from the power supply substrate 20, the basic reset signal RS1 is not abnormally output.

  Corresponding to the power supply voltage monitoring IC 1 operating as described above, the basic reset signal RS1 is sent to the main control unit 21 and the payout control unit 24 as an I / O reset signal via the two NOT gates G1 and G2. It is supplied to the reset terminal of the mounted data input / output IC. Preferably, a basic reset signal (I / O reset signal) RS1 is supplied to a data input / output IC having a latch function. Therefore, the data of the data input / output ICs (for example, SN74273, SN74LV8155, etc.) latched at random when the power is turned on is surely cleared by the basic reset signal RS1.

  The basic reset signal RS1 bar via the NOT gate G1 is supplied to the power supply voltage monitoring IC 2 with a watchdog timer function. As shown in the figure, the power supply voltage monitoring IC 2 outputs a CPU reset signal RS2, but a delay capacitor C15 is connected to the Ct terminal of the power supply voltage monitoring IC 2, and a clear pulse is sent from the one-chip microcomputer to the CK terminal. Configured to be supplied.

  The Vs terminal of the power supply voltage monitoring IC 2 is connected to the ground via the capacitor C14, and the collector terminal and the emitter terminal of the transistor Q3 are connected in parallel to the capacitor C14. The base reset signal RS1 bar divided by the bias resistors R23 and R24 is supplied to the base terminal of the transistor Q3.

  The contentor C14 is a delay element that delays the operation of the internal circuit. As in the case of the power supply voltage monitoring IC1, by appropriately setting the capacitance of the capacitor C14, the power supply voltage monitoring IC2 may be configured not to react in an instantaneous interruption or low state of the power supply voltage Vcc. it can.

  The power supply voltage monitoring IC 2 has the internal circuit of FIG. 5C, and when the Vs terminal is in an open state, the potential of the Vs terminal is set to about 1.4 V by a built-in resistor. The Vs terminal is connected to the minus terminal of the built-in comparator CompS, and a voltage of about 1.24 V is supplied to the plus terminal of the comparator CompS by the built-in circuit.

  Hereinafter, the operation of the power supply voltage monitoring IC 2 will be described. Since the basic reset signal RS1 bar is at the H level during the period from the power-on to the timing T3 (see FIG. 6F), the transistor Q3 is turned on. State. Therefore, the potential of the Vs terminal of the power supply voltage monitoring IC 2 is 0 V, and the output of the comparator CompS becomes H level.

  However, when the basic reset signal RS1 bar transits to L level and the transistor Q3 enters the OFF state at timing T3, the output of the comparator CompS transits to L level, so that the built-in flip-flop enters the reset state and delays. The charging operation to the capacitor C15 is started. Then, after the delay capacitor C15 is charged to a predetermined level (see timing T4 in FIG. 6G), the CPU reset signal RS2 changes from the L level to the H level.

  While the CPU reset signal RS2 is at the L level, the reset terminal of the one-chip microcomputer is maintained at the L level, so that the CPU core and others are surely reset. The reset hold time Tpr [mS] is Tpr [mS] = 1000 * C15 [μF] corresponding to the capacitance of the external capacitor C15.

  In this power supply voltage monitoring IC 2, the watchdog timer circuit built in the power supply voltage monitoring IC 2 starts to operate at the timing when the CPU reset signal RS 2 transitions to the H level and the one-chip microcomputer starts operating. It is configured.

  Therefore, after that, the watchdog timer function is exhibited. Specifically, when the operation of the one-chip microcomputer is started, the power supply voltage monitoring IC 2 starts the discharge operation of the delay capacitor C15. Every time the one-chip microcomputer supplies a clear pulse, the discharge of the delay capacitor C15 is started. The operation switches to the charging operation.

  However, when trouble such as program runaway occurs (see timing T5 in FIG. 6G), the discharging operation of the delay capacitor C15 is continued, and when the potential of the Ct terminal drops to about 0.4 V, the CPU The reset signal RS2 is forcibly transitioned to the L level. Thereafter, the CPU reset signal RS2 is maintained at the L level. However, when the CPU reset signal RS2 returns to the H level after the elapse of the predetermined maintenance time Twr, the CPU executes an initial processing program similar to that in the power-on state. To start. The duration Twr [mS] is Twr [mS] = 20 * C15 [μF] corresponding to the capacity of the delay capacitor C15.

  Next, the operation of the power supply voltage monitoring IC 2 when the power is shut off will be described. When the power supply voltage Vcc drops to a predetermined level (4.2 V), the CPU reset signal RS2 changes to the L level (timing T8 in FIG. 6 (g)). Thereafter, the operation of the watchdog timer circuit is prohibited.

  By the way, in this embodiment, the watchdog timer circuit built in the one-chip microcomputer is not utilized, and an external dedicated IC 2 is used. This is because when the CPU runs out of control, it is impossible to deny the possibility that some kind of abnormality has occurred in the built-in circuit of the one-chip microcomputer.

  Further, in this embodiment, the power supply voltage monitoring IC 1 and the power supply voltage monitoring IC 2 are arranged in an overlapping manner, and the power supply reset signal (CPU reset signal) RS2 output from the power supply voltage monitoring IC 2 is used only for the one-chip microcomputer. The power reset signal (basic reset signal) RS1 output from the power supply voltage monitoring IC 1 is supplied to a data input / output IC other than the one-chip microcomputer and a random number generation circuit. The CPU reset signal RS2 generated by the watchdog timer function of the power supply voltage monitoring IC 2 is supplied only to the one-chip microcomputer. The reason for adopting such a configuration is as follows.

  First, since the ball game machine of the present embodiment has a power backup function, the game before the power interruption (before the previous day or before a power failure) may be resumed when the power is turned on. Therefore, when the power is turned on, in particular, it is necessary to reliably reset the data input / output IC having a latch function. However, since the reset hold time is short enough, the power supply reset signal (basic reset signal) RS1 is generated using the power supply voltage monitoring IC1.

  On the other hand, for the one-chip microcomputer, a sufficient reset hold time is required after the power supply voltages Vcc and VB are stabilized. For the reason described above, it is preferable to provide a watchdog timer circuit externally, and a desired reset hold time is required for the CPU reset signal RS2 by the watchdog timer. Therefore, in this embodiment, the power supply voltage monitoring IC 1 and the power supply voltage monitoring IC 2 are connected in series to generate a power reset signal (CPU reset signal) RS2 having an optimal reset hold time (= Tpo + Tpr). At the same time, the CPU reset signal RS2 when an abnormality occurs is generated using the power supply voltage monitoring IC2. The reset hold time is set to an optimum value in the main control unit 20 and the payout control unit 24 in consideration of the initial processing time after the CPU reset. Therefore, for example, the control command is not transmitted during the initial processing operation of the payout control unit 24. However, if the main control unit 20 is clearly longer than the payout control unit in the initial processing time, it is sufficient that the reset hold time is set to be the same.

  When an abnormality occurs due to program runaway or the like, the basic reset signal RS1 is not generated, so the data input / output IC is not reset. However, unlike when the power is turned on, random data is not latched in the data input / output IC at the time of abnormal reset, and at the time of abnormal reset, the RAM clear process is executed and the game operation is resumed. There is no problem in not resetting the data input / output IC.

  On the other hand, if the power supply voltage (VB, Vccc) continues for a short time but cannot be absorbed by the capacitors Cll, C12, a basic reset with a short pulse width is started from the power supply voltage monitoring 1Cl. Signal RSl is output. The basic reset signal RS1 turns on the transistor Q3 for a short time. However, by setting the ON resistance of the transistor Q3 to an appropriate value and setting the capacitor C14 connected in parallel to the transistor Q3 to an appropriate capacitance, it is possible to avoid the output of the CPU reset signal RS2.

  In such a case, only the data input / output IC is reset. In particular, this reset operation is performed when the power supply voltage VB (12 V) used for generating a switch signal such as a symbol start port is This is effective in that only the data input / output IC is cleared when it falls into a momentary low state.

  FIG. 7 is a circuit diagram showing a connection relationship between the one-chip microcomputer 21A of the main control unit 21 and the random number generation circuit. This random number generation circuit is a circuit for generating a random value RND used in the big hit lottery process (ST27 in FIG. 11) executed based on the winning of a game ball to the symbol start port 15.

  As shown in FIG. 7, the random number generation circuit includes an oscillation circuit 40 that generates a counting clock Φ having a frequency of about 8 MHz, a holding circuit 41 that holds a winning switch signal Hon indicating a game ball winning to the symbol start port 15, and 2 A counter circuit 42 formed by cascading two 8-bit counters CNT1 and CNT2, a storage circuit 43 that acquires random information D1 to D3 when the power is turned off and maintains it after the power is turned off, and a random start-up charging operation when the power is turned on And a starting circuit 44 to be realized.

  The counter circuit 42 is connected to the data bus of the one-chip microcomputer 21A, and a 16-bit random number value RND is acquired every 8 bits. Further, input ports P1 and P2 are connected to the one-chip microcomputer 21A, and a winning switch signal Hon, a power supply abnormality signal ABN1, a RAM clear signal CLR, and the like can be acquired at appropriate timing.

<Holding circuit 41>
The holding circuit 41 is configured by connecting two D-type flip-flops FF1 and FF2 in series, and the count clock Φ of the oscillation circuit 40 is supplied to each clock terminal CLK. Although the D-type flip-flop is not particularly limited, in this embodiment, SN74HC74 (TI) is used, and data at the D input terminal is output to the Q output terminal at the rising edge of the count clock Φ. Therefore, as shown in FIGS. 8A to 8D, the winning switch signal Hon generated in response to the gaming operation is adjusted in pulse width in the flip-flop FF1 in synchronization with the count clock Φ. (Hon '), and further delayed by one count clock (Hon ") and output from the flip-flop FF2.

  The clear terminals CLR of the two flip-flops FF1 and FF2 are supplied with a power supply reset signal (basic reset signal) RS1 output from the power supply voltage monitoring IC1, and reset the power supply together with other data input / output ICs. Is done. The power reset signal RS1 is also supplied to the clear terminals CCLR of the two 8-bit counters CNT1 and CNT2, and the power is reset at the same timing.

  As described above, in this embodiment, a configuration in which the power supply reset signal is generated by the main control unit 21 or the payout control unit 24 and is supplied from another circuit board is not employed. Therefore, an illegal player cannot accurately grasp the reset timing of the random number generation circuit, which is effective for crime prevention. Contrary to this configuration, for example, when a configuration for receiving a power supply reset signal from the power supply board 20 is adopted, an illegal board is interposed in a connector connected to the power supply board 20 so that the reset timing of the random number generation circuit can be accurately set by the illegal board. It is possible to accurately grasp the big hit timing.

<Counter circuit 42>
The counter circuit 42 of this embodiment is composed of two SN74HC590A (8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS: TI) CNT1 and CNT2. As shown the equivalent circuit in FIG. 9, each 8-bit counter, and 2 ^octal counter CT, and 8-bit latch La, and the 8-bit output register Ro is incorporated. Then, the rising edge of the count clock supplied to a clock terminal CCLK, the counter value of 2 ^octal counter CT is updated.

In this embodiment, the clock terminal CCLK of the first counter CNT1, counting the clock Φ is counting clocks Φ bar is phase-inverted is supplied to the internal 2 ^octal counter CT of the carry signals (ripple carry) RCO is a 2 is supplied to the clock terminal CCLK of the counter CNT2. Therefore, the counter circuit 42 of this embodiment, as a ^whole, functions as a ^{two hexadecimal} counter, circulating in the numerical range of 0000h to FFFFh (H indicates a hexadecimal number).

However, the voltage of the operation inhibition terminal CCKEN of each counter CNT1, CNT2 is when is H level, the counting operation is prohibited, regardless of the voltage change of the clock terminal ^CCLK, the counter value of ^{2 hexadecimal} counter CT is not changed. FIG. 8 (f) and FIG. 8 (g) show this relationship. In the section where the voltage of the operation inhibition terminal CCKEN is at the H level, the counter value remains N + 1 regardless of the supply of the count clock Φbar. Indicates no change.

Further, the counter value of 2 ^octal counter CT, at the rising edge of the latch signal of the latch clock terminal RCLK, is held in the 8-bit latch La, 8 output values of bit latches La, the control signal is L level at the control terminal OE On the condition that it is output from the output register Ro. When the control signal of the control terminal OE is at the H level, the output terminal of the output register Ro is in a high impedance state (HiZ).

In this embodiment, the output (Hon ″) of the flip-flop FF2 is supplied to each latch clock terminal RCLK of the first counter CNT1 and the first counter CNT2. Therefore, at the rising edge of the winning switch signal Hon ″, counter value one of 2 ^octal counter CT is respectively held in the two 8-bit latches La. FIG. 8D and FIG. 8G illustrate the relationship, and the counter value (16-bit length) M incremented from M−1 is the output Hon ″ of the D-type flip-flop FF2. It indicates that the 8-bit latch La of the first counter CNT1 and the second counter CNT2 is acquired at the rising edge.

In the present invention, the winning switch signal Hon to the ON state at a random timing, in synchronization while shaping the waveform to count clocks [Phi, in synchronization with the count clock [Phi the count clock [Phi bar is phase-inverted 2 ^hex The counter is updated. Therefore, the counter value of each 2 ^octal counter CT is the timing latched by the 8-bit latch La, counter update operation has been completed reliably, for example, of being updated to M-1 → M not There is no possibility that a stable counter value is latched. If the counter is updated in synchronization with the count clock Φ, an unreasonable counter value during the update may be latched.

<Storage circuit 43>
The memory circuit 43 is mainly configured by an emitter follower circuit including a transistor Q5 and an emitter resistor R30, a NOT gate G6 that receives the output of the emitter follower circuit, and five D-type flip-flops FF3 to FF7. Here, the power supply abnormality signal ABN1 is supplied to the base terminal of the transistor Q5, and the NOT gate G6 is pulled down by the termination resistor R31. In this embodiment, SN74HC74 (TI) is used as the D-type flip-flops FF3 to FF7.

  The three flip-flops FF3 to FF5 function as a latch circuit that holds data at the D input terminal in synchronization with the rising edge of the signal at the clock terminal CLK. On the other hand, the other two flip-flops FF6 to FF7 have their Q-bar output terminals connected to the D input terminal, and T-type flip-flops whose Q outputs are inverted in synchronization with the rising edge of the signal at the clock terminal. Is functioning as

  A carry signal (ripple carry) RCO1 of the first counter CNT1 is supplied to the clock terminal CLK of the flip-flop FF6, and a carry signal (ripple carry) of the second counter CNT1 is supplied to the clock terminal CLK of the flip-flop FF7. ) RCO2 is supplied.

  Here, the carry signal RCO1 is output every time the 256th count clock Φbar is supplied to the counter circuit 42, and the carry signal RCO2 is output from the 256 * 256th count clock Φbar to the counter circuit 42. Is output each time the signal is supplied to (see FIG. 9). On the other hand, the flip-flops FF6 and FF7 receive the carry signals RCO1 and RCO2 and execute a toggle operation. Therefore, the Q output of the flip-flop FF6 maintains the L level while receiving 256 count clocks Φbar, and maintains the H level while receiving the next 256 count clocks Φbar. Similarly, the Q output of the flip-flop FF7 maintains the L level while receiving 256 * 256 count clocks Φbar, and maintains the H level while receiving the next 256 * 256 count clocks Φbar. .

  Next, the D-type flip-flops FF3 to FF5 will be described. As shown in the figure, the output of the NOT gate G6 is commonly supplied to the clock terminals CLK of the flip-flops FF3 to FF5. The D input terminal of the flip-flop FF3 receives the count clock Φbar while being pulled down by the termination resistor R32. On the other hand, the D input terminals of the flip-flops FF4 and FF5 receive the Q outputs of the flip-flops FF6 and FF7 while being pulled down by the termination resistors R33 and R34.

  In this embodiment, the backup power supply BAK is supplied to the clear terminal CLR and the power supply terminal Vcc of the flip-flops FF3 to FF5, respectively. Therefore, the flip-flops FF3 to FF5 continue to normally maintain the latch function even after the power is shut off, and the Q output is not cleared when the power is restored. Note that the clock terminals CLK and D input terminals of the flip-flops FF3 to FF5 are pulled down via the resistors R31 to R34, respectively, so that the flip-flops FF3 to FF5 operate abnormally when the power is shut off or when the power is restored. I don't have to.

  As described with reference to FIG. 6, at the timing (T7) when the AC power supply is turned off, only the power supply abnormality signal ABN1 quickly drops to the L level while the DC voltage Vcc is maintained at a normal value. Accordingly, since the output of the NOT gate G6 rises correspondingly, the three flip-flops FF3 to FF5 each have the count clock Φ bar (D1) and the Q output (D2) of the flip-flop FF6 at that timing, respectively. The Q output (D3) of the flip-flop FF7 is acquired and stored.

Here, assuming that the duty ratio of the count clock Φ is 50% and the frequency is 8 MHz, the voltage level D1 of the count clock Φ bar is equal to 1 / (2 * 8 * 10 ⁶ ) [seconds]. The L level and the H level are repeated with the width. In this case, the Q output D2 of the flip-flop FF6 repeats the L level and the H level with a uniform time width of 256 / (8 * 10 ⁶ ) [seconds], and the Q output D3 of the flip-flop FF7 is 256. * L level and H level are repeated with a uniform time width of 256 / (8 * 10 ⁶ ) [seconds].

Therefore, when the 3-bit data D3～D1 (Random information D3～D1), were evaluated in a relatively long duration ^(e.g., about 0.5 second ^{to 2 hexadecimal} counter value is circulated 30 times), the data D3 ~ D1 is an equal probability of 1/8 and takes any value from 000 to 111. The random 3-bit data D3 to D1 are held in the flip-flops FF3 to FF5 in a nonvolatile manner in synchronization with the rising edge of the output of the NOT gate G6. As described above, since the output of the NOT gate G6 rises at the timing (T7) when the AC power supply is turned off, the three flip-flops FF3 to FF5 store the random information D1 to D3 at that moment.

<Starting circuit 44>
The starting circuit 44 is connected in common between the analog switches AS1 to AS3 that perform ON / OFF operations corresponding to the 3-bit data D1 to D3, and one side terminals of the analog switches AS1 to AS3 and the power supply voltage Vcc. Between the pull-up resistor R35, capacitors C30 to C32 individually connected between the other terminals of the analog switches AS1 to AS3 and the ground, the N-channel MOS transistor Q6, the drain terminal of the transistor Q6 and the power supply voltage Vcc And a load resistor R36 connected to the.

  As illustrated, the gate terminal of the transistor Q6 is commonly connected to one side terminals of the analog switches AS1 to AS3, and the source terminal is connected to the ground. Note that, as the analog switches AS1 to AS3, elements that operate with a single power source are suitably employed, and for example, TS5A3159A (TI Corporation) is used. The analog switches AS1 to AS3 are turned on when the voltage at the control terminal is at the H level, but random information D1 to D3 is supplied to each control terminal.

  The three capacitors C30 to C32 have a capacitance of several μF or more, and the capacitance values are set to C31 = 2 * C30 and C32 = 4 * C30. Therefore, when the analog switches AS1 to AS3 are turned on, the capacitors C30 to C32 connected to the analog switches in the ON state are connected in parallel to each other, and these capacitors are positively connected via the pull-up resistor R35. Charged in the direction.

  In this embodiment, the capacitance values are set to C31 = 2 * C30 and C32 = 4 * C30. Therefore, corresponding to the 3-bit random information D3 to D1 supplied to the control terminals of the analog switches AS1 to AS3. The combined capacitance value changes linearly. Specifically, the combined capacitance values are 0, C30, 2 * C30, 3 * C30,... 7 * C30 corresponding to D3 to D1 = 000,001,010,011,. It becomes.

  Therefore, the time constant of the charging circuit constituted by the pull-up resistor R35 and the combined capacitance is a straight line such as 0, τ, 2τ, 3τ,... 7τ corresponding to the 3-bit random information D3 to D1. Changes. This charging circuit functions when the power supply voltage Vcc starts to be supplied, and increases the gate terminal of the transistor Q6 from 0 volts to a logic H level voltage level after a charging time corresponding to a time constant of 0 to 7τ. .

  Then, when an H level voltage is supplied to the gate terminal of the transistor Q6, the transistor Q6 changes to the ON state, so that the drain terminal becomes 0 level. Since the drain terminal of the transistor Q6 is connected to the operation prohibiting terminal CCKEN of the counter circuit 42, the counting operation of the counter circuit 42 is permitted after the drain terminal of the transistor Q6 becomes 0 level. At the time of starting the power supply until the terminal drops to 0 level, the counting operation of the counter circuit 42 is prohibited.

  Since the time during which the counting operation is prohibited is random corresponding to the 3-bit random information D3 to D1, the illegal player cannot know the timing of the big hit state according to the elapsed time since the power is turned on. . That is, even if the elapsed time from the time of power-on is the same, the operation prohibition period in which the operation prohibition terminal CCKEN of the counter circuit 42 maintains the H level is different for each gaming machine and for each business day. Unauthorized gaming cannot be successful.

The operation prohibition period is set as appropriate, but may be set to about 0.1 seconds, 0.2 seconds,..., 0.7 seconds, for example, corresponding to the 3-bit random information D3 to D1. . For such a design, the difference between the differences only 0.1 second least significant digit D1 random information is generated, during the 0.1 second, since 2 ¹⁶ binary counter value to circulate about 6 times, unauthorized It is thought that gaming can be surely prevented. In addition, the operation prohibition period can be further subtly randomized by using low-precision parts as C31, C32, and C30.

  Next, an outline of a program of the main control unit 21 that controls the game operation in an integrated manner will be described. 10 to 11 are flowcharts showing a control program of the main control unit 21. The control program of the main control unit 21 includes a system reset process (FIG. 10) that is activated based on the restoration or input of the power supply voltage, and a maskable timer interrupt process (FIG. 11 (FIG. 11) that is activated every predetermined time (2 mS). a)). The operation content of the payout control unit 24 is also common in the basic configuration of the system reset process and the timer interrupt process.

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process is started when the initialization switch SW is turned off and the power is turned on, such as when recovering from a power failure, and when the game hall is opened, the initialization switch SW is turned on. There is a case where the power source is turned on by being operated. Note that when the control program runs away, the watchdog timer function of the power supply voltage monitoring IC 2 is exhibited and the CPU may be forcibly reset.

  In any case, the Z80 CPU first sets itself to the interrupt disabled state (ST1) and sets to the interrupt mode 2 (ST2). Further, the value of the stack pointer SP in the CPU is initialized to the final address of the stack area (ST3), and the values of internal registers including each part of the one-chip microcomputer are initialized (ST4).

  Subsequently, the power supply abnormality signal ABN1 is acquired from the input port, and the same processing is repeated until it changes to a normal level (ST5 to ST6). This takes into consideration that the power supply voltage Vcc may not drop down even after the processing of ST41 in FIG. That is, even if the watchdog timer function is exhibited and the CPU is reset at the timing when the power monitoring process of FIG. There is no progress after ST7.

  If such standby processing (ST5 to ST6) is not provided, the RAM data (the basic data of the checksum calculation and the backup flag BFL updated in ST33) is rewritten by the steady processing that has proceeded from step ST5. The data will be saved even after the power is turned off. In such a case, in the next day determination, the backup flag BFL = 0, or the checksum value backed up on the previous day (ST38) does not match the checksum value calculated after powering on the next day. Precious backup processing (ST37 to ST38) is wasted.

  In addition, the processes in steps ST5 to ST6 function effectively even in a momentary power interruption state in which the supply of the AC input voltage is stopped for a moment by cooperating with the watchdog timer function of the power supply voltage monitoring IC 2. That is, as described with reference to FIG. 5, the power supply abnormality signals ABN1 and ABN2 are supplied to the main control unit 21 and the payout control unit 24 even in the instantaneous power failure state. May be started. Depending on the pulse widths of the power supply abnormality signals ABN1 and ABN2, there is a possibility that the processing of steps ST36 to ST40 is finished and the processing proceeds to an infinite loop processing. However, even in such a case, after that, the CPU is reset by the watchdog timer function, and then the game operation up to that point can be resumed by passing through the processing of steps ST5 to ST6.

  Including the above case, if it is confirmed in step ST6 that the power supply abnormality signal ABN1 is at a normal level, the RAM clear signal CLR is subsequently acquired from the input port P2 (FIG. 7) (ST7). As described above, the RAM clear signal CLR is a signal for determining whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer, and the ON / OFF state of the initialization switch SW operated by the attendant It has a value corresponding to.

  Next, the level of the RAM clear signal is determined (ST8). Assuming that the RAM clear signal is in the ON state, the entire area of the built-in RAM is cleared to zero (ST12). Therefore, the value of the backup flag BFL set in the process of step ST37 in FIG. 11B becomes zero together with other checksum values.

  Next, a power-on command for notifying that the RAM area has been cleared to zero is output (ST13), and the CTC that outputs the interrupt signal INT for starting the timer interrupt operation (FIG. 11A) is initialized ( ST14). Then, with the CPU set to the interrupt disabled state (ST15), update processing is executed for various counters (ST16), and then the CPU is returned to the interrupt enabled state and returns to step ST15. The counter updated in step ST16 includes a miss symbol counter, but this miss symbol counter is out of the result of the big hit lottery process in the special symbol process (ST27) of FIG. It is a counter for deciding what kind of out-of-game to produce when it becomes a state.

  Returning to the determination process in step ST8, the RAM clear signal is OFF when the CPU is forcibly reset by the watchdog timer or when recovering from the power failure state. In such a case, following the determination in step ST8, the content of the backup flag BFL is determined (ST9). The backup flag BFL is data indicating that the operation of the power supply monitoring process of FIG. 11 (b) has been executed. In this embodiment, the backup flag BFL is set to 5AH in the process of step ST37 when the power is turned off. It is cleared to zero in the process of step ST33 after the power is restored.

  When the power is turned on or when recovering from a power failure, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST9 to step ST12 to return the operation of the gaming machine to the initial state.

  On the other hand, if backup flag BFL = 5AH, checksum calculation for calculating the checksum value is executed (ST10). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST11).

  In the SUM address, the checksum value by the same checksum calculation is stored in the power supply monitoring process (FIG. 11B) executed when the voltage drops (ST38). The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST11.

  However, if the checksum calculation (ST38) cannot be executed when the power is turned off, or if it can be executed, the data in the work area will be damaged until the checksum calculation (ST10) of the main process is executed. In such a case, the determination result in step ST11 is inconsistent. If data corruption is detected due to a discrepancy between the determination results, the process proceeds to step ST12 to execute a RAM clear process, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST9 that the checksum value obtained by the checksum calculation (ST10) matches the stored value at the SUM address, the process proceeds to step ST14.

  Next, a timer interrupt processing program (FIG. 11 (a)) that is started every 2 mS while interrupting the main processing described above will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST15.

  In the power supply monitoring process (ST20), the level of the power supply abnormality signal supplied from the power supply board 20 is determined. The specific processing content will be described later. When the power supply monitoring process (ST20) ends, the winning counter RG used in the lottery operation in the normal symbol process (ST26) is updated (ST21). The jackpot determination random number RND used in the lottery operation in the special symbol processing (ST27) is automatically updated at a high speed (1/8 MHz time interval) in the random number generation circuit shown in FIG. .

  When the counter RG update process (ST21) is completed, a timer subtraction process is performed for the timer managing the time of each gaming operation (ST22). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times.

  Subsequently, a clear pulse is output to the CK terminal of the power supply voltage monitoring IC 2, and ON / OFF signals of various switches including a winning detection switch of the symbol start opening 15 and the big winning opening 16 are input, and the work area is turned ON. The / OFF signal level and its rising state are stored (ST23). The winning switch signal Hon indicating whether or not the game ball has won the symbol start port 15 is acquired via the input port P1 shown in FIG. Next, error management processing is performed (ST24). The error management process includes a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged.

  Subsequently, after executing a management process based on detection signals from the symbol start opening and the big winning opening (ST25), a normal symbol process is performed (ST26). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined in the switch input process in step ST23 that the game ball has passed through the gate, the winning counter RG updated in the random number update process (ST21) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. In addition, if it is a hit, processing for the operation of a normal electric accessory such as an electric tulip is performed.

  Subsequently, special symbol processing is performed (ST27). The special symbol process is a determination as to whether or not a special electric accessory such as the big prize opening 16 is to be operated. When it is determined in the switch input process of step ST23 that a game ball has won a symbol start port. The 16-bit random number value RND is acquired every 8 bits from the counter circuit 42 of the random number generation circuit. As shown in FIG. 7, lower 8 bit data is acquired in synchronization with the chip select signal (negative logic) CS3, and lower 8 bit data is acquired in synchronization with the chip select signal CS4 (negative logic).

  Then, the jackpot lottery process is executed using the acquired random number value RND (ST66). Although not shown in the drawing, if the lottery result is a winning state, the operation mode is changed to a big hit mode. In addition, if it is a big hit, processing for the operation of special electric accessories such as a big prize opening is performed.

  After such special symbol processing (ST27), the lighting operation of the LEDs managed by the main control unit 21 is advanced (ST28), and the solenoid drive processing for realizing the opening / closing operation of the electric tulip, the big prize opening, etc. is executed. Later (ST29), the CPU is returned to the interrupt permission state EI and the timer interrupt is finished (ST30). As a result, the process returns from the interrupt process routine to the infinite loop process (FIG. 10) of the main process, and the process of step ST17 is executed.

  Then, the power supply monitoring process (ST20) shown in FIG.11 (b) is demonstrated. In the power supply monitoring process (ST20), first, a power supply abnormality signal ABN1 supplied from the power supply board 20 is acquired through the input port P2 (FIG. 7) (ST31), and it is determined whether or not it is an abnormal level (ST32). If it is not an abnormal level, the abnormal number counter and the backup flag BFL are cleared to zero and the process is terminated (ST33).

  On the other hand, if the power supply abnormality signal ABN1 is at the abnormal level, the abnormality number counter is incremented (+1) (ST34), and it is determined whether the counting result exceeds the upper limit value MAX (ST35). This is because the data acquired from the input port may be garbled due to the influence of noise or the like, and the abnormal level is continuously set for a predetermined number of times (for example, upper limit MAX = 2). In the case of maintaining, it is determined that the AC power source is actually shut off.

  As described above, in this embodiment, the subsequent backup processing is not started immediately even when the power is turned off, and the operation start timing is delayed by MAX × 2 mS. However, (1) The power supply drop signal is not a drop in the DC power supply voltage, but a drop in the AC DC voltage is detected. (2) The DC power supply voltage is maintained for a while after the AC power supply is shut off by a large capacity capacitor. (3) The power supply monitoring process is repeated at a high speed (every 2 ms), and (4) the backup process is extremely simple and finishes quickly, so there is virtually no adverse effect.

  By the way, as a result of the determination in step ST35, if the count value of the abnormal number counter coincides with the upper limit value MAX, the abnormal number counter is cleared to zero (ST36), and then 5AH is set to the backup flag BFL (ST37). Next, the same calculation as in step ST7 of the main routine is executed for the same work area (work area), and the calculation result is stored (ST38). The operation to be executed is typically an 8-bit addition operation.

  Thereafter, the one-chip microcomputer is set to a RAM access prohibited state (ST39), and output data of all output ports is cleared (ST40). When the above backup process is completed, the generation of the interrupt signal INT is prohibited by the setting process for the CTC, and the DC power supply voltage is lowered while repeating the infinite loop process (ST41). At this timing, the CPU is originally in an interrupt disabled state (see ST30). However, in this embodiment, an interrupt signal from the CTC is used to eliminate as much as possible the possibility of malfunction due to a drop in power supply voltage. INT output is also prohibited.

  By the way, as described above, the process of step ST20 is quickly started within 2 mS after the AC power supply is shut off (see timing T7 in FIG. 6) and is quickly ended. On the other hand, the drop in power supply voltage Vcc to a predetermined level is considerably delayed due to the influence of a smoothing capacitor arranged in a power supply circuit or the like (see timing T8 in FIG. 6).

  As long as the power supply voltage Vcc does not drop to a predetermined level, the watchdog timer of the power supply voltage monitoring IC 2 continues to function. Therefore, there is a possibility that the CPU is abnormally reset by the watchdog timer during the infinite loop process after the process of step ST20 is started and all processes are completed. However, as described above, in this embodiment, the standby process of steps ST5 to ST6 is provided, so that the backup process is not wasted. Note that the entire processing time of the power supply monitoring process from ST31 → ST32 → ST34 → ST35 → ST36 →... ST41 is set shorter than the output period (2 mS) of the clear pulse, The dog timer will not start.

  Although the embodiments of the present invention have been specifically described above, the specific description content is not intended to limit the present invention, and various modifications can be made. For example, in the embodiments, only the ball ball game machine has been described, but it is needless to say that the present invention can be applied to other game machines such as a slot machine.

  Also, the circuit configuration of FIG. 7 is not particularly limited, and can be changed as appropriate. In particular, for the memory circuit 43, the count clock Φ bar and the double carry signal RCO are used in the present embodiment, but the present invention is not limited thereto. For simplicity, the count clock Φ bar and the double carry signal RCO may be directly supplied to the D input terminals of the flip-flops FF3 to FF5 without providing the flip-flops FF6 and FF7.

  FIG. 12A illustrates a first modification of the memory circuit 43. Here, the chip select signal CS3 supplied from the one-chip microcomputer 21A to the counter circuit 42 is commonly supplied to the clock terminals CLK of the three D-type flip-flops FF3 to FF5. The chip select signal CS3 is connected to the backup power supply BAK through the pull-up resistor Rp.

  In the first modification, the lower 3 bits Bit0 to Bit3 of the counter circuit 42 are supplied to the D input terminals of the flip-flops FF3 to FF5. Therefore, the 3-bit data Bit0 to Bit3 are stored in the flip-flops FF3 to FF5 at the rising edge of the chip select signal CS3 that has reached the active level. After the chip select signal CS3 rises to the H level, the 3-bit data Bit0 to Bit3 are in the HiZ state.

  The chip select signal CS3 becomes active level (L level) when the one-chip microcomputer 21A acquires the random number value RND from the counter circuit 42, and in this embodiment, the lower three of the acquired random number value RND. Bits are sequentially overwritten in the flip-flops FF3 to FF5. After the power is shut off, the lower 3 bits of the finally obtained random number value RND are stored and maintained in a nonvolatile manner. Of course, the 3-bit data can be replaced with any 3 bits of Bit0 to Bit15. The random information is not necessarily 3 bits, and can be increased or decreased as appropriate.

  FIG. 12B illustrates a second modification of the memory circuit 43. Here, the two flip-flops FF6 to FF7 are operated as T-type flip-flops, and a 2-bit binary counter is configured. The count clock Φbar is supplied to the clock terminal CLK of the flip-flop FF6 and the D input terminal of the flip-flop FF3.

  Therefore, the 3-bit data D1 to D3 supplied to the three flip-flops FF3 to FF5 circulate in a numerical range of 000 to 111 in synchronization with the count clock Φbar. When the power failure occurs when the power supply abnormality signal ABN1 drops or when the random number value at which the chip select signal CS3 becomes L-active is acquired, any value from 000 to 111 is latched in the three flip-flops FF3 to FF5. This value is stored and maintained even after the power is turned off. Also in this modification, the appearance probability of the random information 000 to 111 is 1/8 each, and the starting circuit 44 can execute a random starting operation when the power is turned on.

  By the way, a circuit configuration that operates accurately even when the operation of the logic element is not stable, such as when the power is turned on, is desired. In addition, there may be an illegal action that intentionally repeats the power-off operation and the power-on operation. Therefore, preferably, the circuit configuration of FIG. 13 should be adopted instead of FIG. The random number generation circuit of FIG. 13 is obtained by improving the circuit configuration of the memory circuit 43 and the start circuit 44 shown in FIG. 7, and FIG. 14 is a timing chart for explaining the circuit operation.

  13 includes a NOT gate G6 that logically inverts the basic reset signal RS1 via the emitter follower circuits Q7 and R36, and a NOR gate G7 that receives the outputs of the NOT gate G6 and the emitter follower circuits Q5 and R30. In addition, an analog switch AS4 that performs an ON / OFF operation based on the outputs of the emitter follower circuits Q5 and R30, and transistors Q7 to Q9 that discharge the charged charges of the capacitors C30 to C32 are additionally provided.

  Transistors Q7 to Q9 composed of N-channel MOSs are turned on only when the output of NOT gate G6 is at the H level. The flip-flops FF3 to FF5 perform a latch operation at the timing when the output of the NOR gate G7 rises.

<When power is turned off>
Based on the above operation, the operation when the power is shut off will be described first. Since the NOR gate G7 operates based on the outputs of the emitter follower circuits Q5 and R30 and the NOT gate G6, the output of the NOR gate G7 is that the basic reset signal RS1 is RS1 = H and the power supply abnormality signal ABN1 is Only the timing of ABN1 = L becomes the H level (see FIG. 14D).

  Therefore, the output of the NOR gate G7 rises when the power supply abnormality signal ABN1 falls when the power supply is cut off (timing T7), and the D input values of the flops FF3 to FF5 at that time are latched and stored as random information D1 to D3. Is done. When the power is shut off (timing T7), the power supply abnormality signal ABN1 falls, so that the analog switch AS4 that has been in the ON state is turned OFF.

  Thereafter, when the DC power supply starts to drop (timing T8), the output of the NOT gate G6 becomes H level corresponding to the basic reset signal RS1 becoming L level. Therefore, after the timing T8, the transistors Q7 to Q9 are turned on, and the charged charges are discharged from the charged capacitors C30 to C32. Therefore, even if the power is turned on immediately after the power is turned off, the start operation as designed is realized.

<When power is turned on>
Next, the operation when the power is turned on will be described. When the power is turned on (timing T0), first, the power abnormality signal ABN1 rises (timing T1), and the analog switch AS4 is turned on. After that, until the timing T3 when the basic reset signal RS1 rises, the transistors Q7 to Q9 maintain the ON operation. Therefore, even if the capacitors C30 to C32 that are charged are present, the charged charges are surely discharged. Is done.

  Then, after the timing T3 when the power supply voltage rises to a normal level, the transistors Q7 to Q9 are turned off. Therefore, the capacitors C30 to C32 are charged based on the random information D1 to D3 latched in the flip-flops FF3 to FF5, and the updating operation of the counters CNT1 and CNT2 is started after a random delay time.

  When the random information D1 to D3 is 000, the counter update operation is started without delay time, as in the circuit configuration of FIG.

GM gaming machine Hon detection signal CT counter 43 memory circuit D3-D1 random information

Claims (11)

A gaming machine that executes a lottery process due to a detection signal indicating the occurrence of a predetermined gaming action and determines whether or not to generate a gaming state advantageous to the player,
The lottery process is executed by acquiring a counter value of a counter that can prohibit the counting operation and comparing the acquired value with a winning value.
A gaming machine characterized in that after the power is turned on, the time during which the counting operation of the counter is prohibited is set based on random information stored in a memory circuit operable even after the power is turned off. The counter is configured to perform a counting operation in synchronization with a counting clock unless the operation prohibiting signal is at a prohibiting level,
A latch circuit that stores a counter value of the counter when a holding command is received, and an output circuit that outputs the counter value stored in the latch circuit when a reading command is received are provided on the rear stage side of the counter. Item 1. A gaming machine according to Item 1.   The gaming machine according to claim 1 or 2, wherein the time during which the counting operation of the counter is prohibited is defined by a capacitor charging time in a charging circuit including a capacitor and a resistor. A starting circuit for defining a time during which the counting operation of the counter is prohibited;
The starting circuit includes N capacitors arranged corresponding to random information of N bits length, N switch circuits connected in series to the N capacitors, and a DC voltage to the N switch circuits. A gaming machine according to any one of claims 1 to 3, further comprising: a power feeding unit to be supplied.   5. The storage circuit according to claim 1, wherein the storage circuit is configured to acquire and store the count clock and / or a carry signal of the counter based on the fact that the AC power supply is cut off. Game machines.   The gaming machine according to claim 1, wherein the storage circuit is configured to acquire and store a part of the counter value based on the acquisition of the counter value of the counter.   The gaming machine according to claim 1, wherein the power of the counter is reset without receiving a reset signal from another circuit board when power is turned on.   The gaming machine according to claim 2, wherein the holding instruction is output based on a game medium having won a predetermined winning opening.   The gaming machine according to claim 2, wherein the holding command is output based on a game operation of the player.   The gaming machine according to claim 2, wherein the holding command is waveform-shaped so as to be synchronized with one edge of the counting clock.   The gaming machine according to claim 10, wherein the counter is updated in synchronization with the other edge of the counting clock.