JP4403386B2 - Storage device - Google Patents

Description

  The present invention relates to a memory device using a plurality of resistance change memory elements.

  Conventionally, a semiconductor device using a resistance change memory element that can be mounted on a semiconductor substrate at a high density is known as a large-capacity nonvolatile memory device. In particular, as such a resistance change memory element, a ferromagnetic spin A resistance change memory element utilizing a tunnel magnetoresistance (TMR) of a tunnel junction (MTJ: Magnetic Tunnel Junction) is known (for example, see Patent Document 1). A memory device including this resistance change memory element is called an MRAM.

  In the memory device using such a resistance change memory element, as shown in FIG. 7, one end of the memory element m formed of a ferromagnetic spin tunnel junction is connected to the bit line 100 and the other end is connected to the read control transistor 200. The read word line 300 is connected to the gate of the read control transistor 200, and data is read from the storage element using the read word line 300 and the bit line 100.

  Further, a write word line 400 is provided in the vicinity of the storage element m so as to be substantially orthogonal to the storage element m, and the magnetization in the ferromagnetic spin tunnel junction is controlled by controlling the direction of the current applied to the write word line 400. The predetermined direction data is stored in the storage element m.

  The necessary number of storage elements m are provided so as to have a required storage capacity, and each bit line 100, read word line 300 and write word line 400 connected to each storage element m are input / output. The bit line 100, the read word line 300, and the write word line 400 are controlled by this input / output control port.

As another form, as shown in FIG. 8, one end of the storage element m ′ is connected to the bit line 100 ′, and the other end of the storage element m ′ is connected to the word line 300 ′. By controlling the energization state of 'and the word line 300', data can be read from the memory element m 'and data can be written to the memory element m'.
JP 2002-208682 A

  However, in a storage device that reads or writes predetermined data using a bit line and a required word line as described above, if any one storage element is in a write state, the other storage In addition to writing data to the element, data cannot be read, and conversely, when any one of the storage elements is in a read state, data from a storage element other than the storage element is not read. Since not only reading but also writing of data cannot be performed, the switching speed of the storage element in which the writing operation or the reading operation is performed determines the operation speed of the writing operation or the reading operation, thereby improving the operation speed. There was a problem that it was extremely difficult to do.

Therefore, a storage device of the present invention, in a storage device having a plurality of resistance change memory device, a pair of bit lines and the first word line in the resistance change memory device and a plurality of pairs connected, the bit line and the first word line Are connected to different input / output control ports for each pair. Further, in a memory device having a plurality of resistance change memory elements, a plurality of second word lines that conduct electricity to change the resistance state of the resistance change memory elements are provided, and these second word lines are respectively connected to different input / output control ports. Decided to connect to. By performing control for each input / output control port, the write operation and the read operation, or the write operations or the read operations can be performed in duplicate, while the plurality of input / output control ports The address of the resistance change memory element controlled by another input / output control port between the plurality of input / output control ports so that the same resistance change memory element is not simultaneously read or written. Information is input, and each of the input / output control ports temporarily stops a read operation or a write operation to the resistance change memory element controlled by another input / output control port.

The first word line is also characterized in that it is connected to the gate of a read control transistor provided in the middle of the connection wiring that connects the bit line constituting the pair and the resistance change memory element.

According to the first aspect of the invention, the memory device having a plurality of resistance change memory device, a plurality of pairs connects the pair of bit lines and the first word line in the resistance change memory device, the bit line and the first word The lines are connected to different input / output control ports for each pair, and a plurality of second word lines are provided for energizing to change the resistance state of the resistance change memory element. By connecting to the output control port, data can be read or written for each input / output control port, so the write operation and the read operation, or the write operations, or the read operations are executed in duplicate. Therefore, the substantial operation speed can be improved. In particular, since the operation speed can be improved without improving the operation clock, an increase in power consumption accompanying the increase in the operation speed can be suppressed. Furthermore, the address information of the resistance change memory element controlled by the other input / output control port is input between the plurality of input / output control ports, and each input / output control port is controlled by the other input / output control port. Since the read operation or write operation to the resistance change storage element is temporarily stopped, it is possible to prevent a plurality of input / output control ports from simultaneously performing the read operation or write operation on the same resistance change storage element. it can.

According to the second aspect of the present invention, the first word line is connected to the gate of the read control transistor provided in the middle of the connection wiring connecting the bit line constituting the pair and the resistance change memory element, A plurality of first word lines and bit lines can be easily wired, and the wiring pattern can be prevented from becoming complicated.

  A storage device of the present invention is a storage device configured by providing a plurality of resistance change storage elements that store data according to a difference in resistance value, in order to read data stored from the resistance change storage element, or data Are provided with a plurality of pairs of bit lines and word lines for each resistance change memory element.

  The paired bit line and word line are connected to an input / output control port, and a data read operation or data write operation from a predetermined resistance change memory element is performed under the control of the input / output control port. At the same time, different pairs of bit lines and word lines are connected to different input / output control ports, and control is performed for each input / output control port. The operations can be executed in duplicate.

  Therefore, the write operation and the read operation, or the write operations or the read operations can be performed simultaneously by each input / output control port, so that the substantial operation speed can be improved.

  In particular, the word line is connected to the gate of the read control transistor provided in the middle of the connection wiring that connects the bit line constituting the pair and the resistance change storage element, and thereby each of the resistance change storage elements. A plurality of bit lines and word lines can be easily wired, and the wiring pattern can be prevented from becoming complicated, and further, the resistance change memory element itself can be prevented from being enlarged.

  In addition, when a plurality of word lines for energizing to change the resistance state of the resistance change memory element are provided and the word lines are connected to different input / output control ports, the resistance change memory elements differ depending on the input / output control port. At the same time, the data write operation can be performed, and the substantial operation speed can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram of the storage device A of this embodiment. The storage device A is provided with a storage area 30 in which resistance change storage elements are arranged in a matrix, and an input / output control port is provided around the storage area 30. In particular, in the present embodiment, the storage device A is provided with two input / output control ports, a first input / output control port 10 and a second input / output control port 20.

  The first input / output control port 10 includes a first control circuit 11, a first address decoder 12 for decoding address data input from the outside, and a first I / O buffer 13 connected to an input / output terminal (not shown). The first control circuit 11 controls the first write driver circuit 14 to write data to the resistance change memory element at the address designated by the first address decoder 12 and By controlling the first sense amplifier circuit 15 by the control circuit 11, the data stored in the resistance change memory element at the address designated by the first address decoder 12 is read out.

  The second input / output control port 20 includes a second control circuit 21, a second address decoder 22 for decoding address data input from the outside, and a second I / O buffer 23 connected to an input / output terminal (not shown). The second control circuit 21 controls the second write driver circuit 24 to write data to the resistance change memory element at the address designated by the second address decoder 22 and By controlling the second sense amplifier circuit 25 by the control circuit 21, the data stored in the resistance change memory element at the address designated by the second address decoder 22 is read out.

  FIG. 2 is a circuit diagram of one resistance change storage element M1 portion in the storage device A of the present embodiment. In the present embodiment, two bit lines of the first bit line B1 and the second bit line B2 are connected to one resistance change memory element M1, and the first read word line RW1 and the second read word line RW2 are connected. Are connected to each other, and the resistance change memory element M1 is provided with one write word line WW for energization for changing the resistance state of the resistance change memory element M1. is there.

  In particular, the resistance change memory element M1 has one end connected to the common bit line B and the other end grounded.

  A first read control transistor T1 having a gate terminal connected to the first read word line RW1 is provided in the middle of the first connection line L1 connecting the common bit line B and the first bit line B1. .

  Further, a second read control transistor T2 having a gate terminal connected to the second read word line RW2 is provided in the middle of the second connection line L2 connecting the common bit line B and the second bit line B2. .

  In this way, one common bit line B is connected to the resistance change memory element M1, and the common bit line B, the first bit line B1, and the second bit line B2 are connected via the first connection line L1 and the second connection line L2. , It is possible to facilitate the wiring of the bit lines B1 and B2 in the case where the number of bit lines, which has conventionally been one, is changed to two, the first bit line B1 and the second bit line B2.

  In addition, the first read word line RW1 is connected to the gate of the first read control transistor T1 provided in the first connection line L1, and the second read word line RW2 is provided in the second connection line L2. 2 By connecting to the gate of the read control transistor T2, the word line in the case where the single read word line is changed to the first read word line RW1 and the second read word line RW2 is used. Wiring of RW1 and RW2 can be made easier.

  The pair of first bit line B1 and first read word line RW1 connected via the first read control transistor T1 are connected to the first input / output control port 10 shown in FIG. The pair of second bit line B2 and second read word line RW2 connected via the read control transistor T2 are connected to the second input / output control port 20 shown in FIG. M1 can be read by the first input / output control port 10 and the second input / output control port 20, respectively.

  The write word line WW may be connected to one of the first input / output control port 10 and the second input / output control port 20. For example, the write word line WW is connected to the first input / output control port 10. When the connection is made, the first input / output control port 10 can perform not only the read operation of the resistance change memory element M1, but also the write operation.

  However, the first input / output control port 10 and the second input / output control port 20 are configured so that the first input / output control port 10 and the second input / output control port 20 do not perform the read operation or the write operation on the same resistance change memory element M1 at the same time. Address information of the resistance change memory element M1 controlled by the other port is input to the second input / output control port 20, and the other port uses the resistance change memory element M1. In this case, the read operation or write operation to the resistance change memory element M1 is temporarily stopped.

  As described above, by providing the two input / output control ports of the first input / output control port 10 and the second input / output control port 20, data can be written or read by parallel processing. The processing speed can be improved.

  In the above-described embodiment, there is only one write word line WW. However, as shown in FIG. 3, the first write word line that conducts electricity to change the resistance state of the resistance change memory element M1. WW1 and second write word line WW2 may be provided. For example, the first write word line WW1 is connected to the first input / output control port 10 and the second write word line WW2 is connected to the second input / output control port 20, thereby different resistance change memory elements. Since the writing operation by the first input / output control port 10 and the writing operation by the second input / output control port 20 can be simultaneously performed on M1, the processing speed in the storage device can be improved.

  The number of bit lines and read word lines is not limited to the two described above. As shown in FIG. 4, one resistance change memory element M1 includes a first bit line B1, a second bit line B2, and a third bit line. The three bit lines B3 may be connected, and the three word lines of the first read word line RW1, the second read word line RW2, and the third read word line RW3 may be connected.

  The third read word line RW3 is a third connection line L3 that connects the common bit line B and the third bit line B3 in the same manner as the first read word line RW1 and the second read word line RW2. This is connected to the gate of the third read control transistor T3 provided in the middle.

  The third bit line B3 and the third read word line RW3 are the first input / output control port 10 connecting the first bit line B1 and the first read word line RW1, and the second bit line B2 and the second bit line RW3. The first input / output control port 10 and the second input / output control are connected to a third input / output control port (not shown) different from the second input / output control port 20 to which the read word line RW2 is connected. Since the port 20 and the third input / output control port perform necessary controls, the write operation and the read operation or the read operation can be performed in duplicate, thereby further improving the processing speed of the storage processing device. Can be made.

  Further, instead of one write word line WW as shown in FIG. 4, as shown in FIG. 5, the first write word line WW1, the second write word line WW2, and the third write A write word line WW3, a first write word line WW1 connected to the first input / output control port 10, a second write word line WW2 connected to the second input / output control port 20, and a third By connecting the write word line WW3 to the third input / output control port, the write operation by the first input / output control port 10 and the second input / output control port 20 are applied to the different resistance change memory elements M1. Since the writing operation and the writing operation by the third input / output control port can be performed simultaneously, the processing speed in the storage device can be further improved.

  As another embodiment, instead of a storage device having two types of word lines, a read word line and a write word line, as shown in FIG. 6, one end of the storage element M2 is connected to the bit line and the storage element In the storage device that reads the data from the storage element M2 and writes the data to the storage element M2, by connecting the other end of M2 to the word line and controlling the energization state of the bit line and the word line, The first bit line B1 ′ is connected to one end of the storage element M2, the first word line W1 ′ is connected to the other end of the storage element M2, and the second bit line B2 ′ is connected to one end of the storage element M2. The other end of the memory element M2 is connected to the second word line W2 ′, the pair of first bit lines B1 ′ and the first word line W1 ′ are connected to the first input / output control port 10 shown in FIG. A pair of second bit line B2 'and second word line W2' are connected to the second input / output control port. It may be connected to 20.

  In this way, the pair of first bit lines B1 ′ and the first word line W1 ′ are connected to the first input / output control port 10, and the pair of second bit lines B2 ′ and the second word line W2 ′ are connected to the second. By connecting to the input / output control port 20, a write operation by the first input / output control port 10 and a read operation or write operation by the second input / output control port 20 are simultaneously performed for different resistance change memory elements M2. Therefore, the processing speed in the storage device can be improved.

1 is a schematic block diagram of a storage device according to the present invention. It is a circuit diagram of a resistance change memory element portion of one memory device according to the present invention. It is a circuit diagram of the resistance change memory element part of other embodiments. It is a circuit diagram of the resistance change memory element part of other embodiments. It is a circuit diagram of the resistance change memory element part of other embodiments. It is a circuit diagram of the resistance change memory element part of other embodiments. It is a circuit diagram of one resistance change memory element part in the conventional memory device. It is a circuit diagram of one resistance change memory element part in the conventional memory device.

Explanation of symbols

A storage device
10 1st input / output control port
11 First control circuit
12 First address decoder
13 First I / O buffer
14 First write driver circuit
15 First sense amplifier circuit
20 2nd input / output control port
21 Second control circuit
22 Second address decoder
23 Second I / O buffer
24 Second write driver circuit
25 Second sense amplifier circuit
30 storage area
M1, M2 Resistance change memory element B Common bit line
B1, B1 '1st bit line
B2, B2 'Second bit line
B3 Third bit line
RW1 First read word line
RW2 Second read word line
RW3 Third read word line
WW word line for writing
L1 first connection line
L2 Second connection line
L3 Third connection line
T1 first read control transistor
T2 Second read control transistor
T3 Third read control transistor
WW1 First write word line
WW2 Second write word line
WW3 Third write word line

Claims (2)

In a memory device having a plurality of resistance change memory elements,
Plural pairs connects the pair of bit lines and the first word line in the resistance change memory device described above, respectively connected to said first word line and the bit line to the different input and output control port for each said pair, said resistor Provide a plurality of second word lines for energizing to change the resistance state of the change memory element, and connect the second word lines to different input / output control ports to control each input / output control port. Thus, the write operation and the read operation, or the write operations or the read operations can be performed in duplicate, while the plurality of input / output control ports simultaneously perform the read operation on the same resistance change memory element. Alternatively, address information of the resistance change memory element controlled by another input / output control port is input between the plurality of input / output control ports so as not to perform a write operation, and each of the input / output controls Over TMG, storage device according to claim <br/> to pause reading operation or writing operation to the resistance change memory element other output control port is controlled. 2. The first word line is connected to a gate of a read control transistor provided in a middle portion of a connection wiring for connecting the bit line constituting the pair and the resistance change memory element. Storage device.

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